A drive protection circuit for a power semiconductor device

Abstract

The embodiment of the present application provides a kind of drive protection circuit of power semiconductor device, when capacitor under voltage, the first control signal that first control circuit transmits is high level, first power semiconductor device is turned on, second power supply charges capacitor, the second control signal that second control circuit transmits is low level, second power semiconductor device is cut off, to carry out under voltage protection to second power semiconductor device;When capacitor overvoltage, the first control signal that first control circuit transmits is low level, first power semiconductor device is cut off, second power semiconductor device is cut off, to carry out overvoltage protection to second power semiconductor device.The embodiment of the present application is in the case where capacitor voltage is too low and too high, second power semiconductor device is in cut-off state, to avoid second power semiconductor in drive voltage too low or too high, be affected by overvoltage, overcurrent, short circuit and other abnormal conditions and lead to device damage or performance decline.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a drive protection circuit for a power semiconductor device. Background Technology

[0002] Power semiconductor devices are semiconductor devices specifically designed for controlling and converting electrical energy. They are widely used in various power electronic systems, such as power management, motor drives, electric vehicles, and renewable energy generation. They can efficiently convert electrical energy from one form to another and operate under high voltage and high current conditions. Power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs), are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can lead to device damage or performance degradation. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a drive protection circuit for a power semiconductor device that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned issues, this invention discloses a drive protection circuit for a power semiconductor device, comprising a first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded and the control terminal is used to receive a first control signal;

[0005] A first control circuit is connected to the control terminal of the first power semiconductor device and is used to output the first control signal to the control terminal of the first power semiconductor device.

[0006] The second power semiconductor device has its output terminal connected to the input terminal of the first power semiconductor device, its control terminal for receiving a second control signal, and its input terminal connected to a first power supply.

[0007] The second control circuit is connected to the control terminal of the second power semiconductor device and is used to output the second control signal to the control terminal of the second power semiconductor device.

[0008] The capacitor has one end connected to the first control circuit, the second control circuit, and the second power supply, respectively, and the other end connected to the input terminal of the first power semiconductor device and the output terminal of the second power semiconductor device, respectively.

[0009] When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor. When the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off to provide undervoltage protection for the second power semiconductor device.

[0010] When the capacitor is overvoltaged, the first control signal transmitted by the first control circuit is at a low level, the first power semiconductor device is turned off, and the second power semiconductor device is turned off to provide overvoltage protection for the second power semiconductor device.

[0011] Optionally, the first control circuit includes:

[0012] A first comparator, wherein the positive input terminal of the first comparator is connected to one end of the capacitor, and the inverting input terminal of the first comparator is connected to the second power supply;

[0013] The first transistor has its emitter connected to the output of the first comparator and its collector connected to the second power supply.

[0014] The second transistor has its base connected to the base of the first transistor, its collector receiving the first pulse modulation signal, and its emitter grounded and connected to the control terminal of the first power semiconductor device; the second transistor is used to output the first control signal.

[0015] When the capacitor is undervoltage, the first comparator outputs a low level, the first transistor is turned on, and when the first pulse modulation signal is high, the second transistor is turned on, and the first control signal output by the second transistor is high.

[0016] When the capacitor is overvoltaged, the first comparator outputs a high level, the first transistor is cut off, and the first control signal output by the second transistor is low.

[0017] Optionally, the second control circuit includes:

[0018] The second comparator has its positive input connected to the second power supply and its negative input connected to both the second power supply and the capacitor.

[0019] The emitter of the third transistor is connected to the output terminal of the second comparator, and the collector of the third transistor is connected to the second power supply and the capacitor respectively.

[0020] A fourth transistor, the base of which is connected to the base of the third transistor, the collector of which is connected to the second pulse modulation signal, and the emitter of which is grounded and connected to the control terminal of the second power semiconductor device; the fourth transistor is used to output the second control signal.

[0021] When the capacitor is undervoltage, the second comparator outputs a high level, and the third transistor is cut off; the second control signal output by the fourth transistor is a low level.

[0022] Optionally, the first power semiconductor device and the second power semiconductor device are IGBTs.

[0023] Optionally, the circuit further includes a diode, the anode of which is connected to the second power supply, and the cathode of which is connected to the inverting input of the second comparator, the collector of the third transistor, and the capacitor.

[0024] Optionally, the circuit further includes:

[0025] The first resistor has one end connected to the second power supply and the other end connected to the inverting input of the first comparator.

[0026] The second resistor has one end connected to the first resistor and the inverting input of the first comparator, and the other end grounded.

[0027] Optionally, the circuit further includes:

[0028] The third resistor has one end connected to the second power supply and the other end connected to the positive input terminal of the second comparator.

[0029] The fourth resistor has one end connected to the third resistor and the positive input terminal of the second comparator, and the other end grounded.

[0030] Optionally, the circuit further includes:

[0031] The fifth resistor has one end connected to the output of the first comparator and the other end connected to the second power supply.

[0032] Optionally, the circuit further includes:

[0033] The sixth resistor has one end connected to the output terminal of the second comparator and the other end connected to the second power supply.

[0034] Optionally, the circuit further includes:

[0035] The seventh resistor has one end connected to the emitter of the second transistor and the other end connected to the control terminal of the first power semiconductor device.

[0036] Optionally, the circuit further includes:

[0037] The eighth resistor has one end connected to the emitter of the fourth transistor and the other end connected to the control terminal of the second power semiconductor device.

[0038] The embodiments of the present invention have the following advantages:

[0039] An embodiment of the present invention provides a driving protection circuit for a power semiconductor device, comprising: a first power semiconductor device, the output terminal of which is grounded, and a control terminal for receiving a first control signal; a first control circuit connected to the control terminal of the first power semiconductor device, for outputting the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, the output terminal of which is connected to the input terminal of the first power semiconductor device, the control terminal of which receives a second control signal, and the input terminal of which is connected to a first power supply; a second control circuit connected to the control terminal of the second power semiconductor device, for outputting the second control signal to the control terminal of the second power semiconductor device; and a capacitor. One end of the device is connected to the first control circuit, the second control circuit, and the second power supply, respectively. The other end is connected to the input terminal of the first power semiconductor device and the output terminal of the second power semiconductor device, respectively. When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor. The second control signal transmitted by the second control circuit is low, and the second power semiconductor device is turned off, thus providing undervoltage protection for the second power semiconductor device. When the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, thus providing overvoltage protection for the second power semiconductor device. In this embodiment of the invention, the second power semiconductor device is in a cutoff state when the capacitor voltage is too low or too high, thereby avoiding damage or performance degradation of the second power semiconductor device due to abnormal conditions such as overvoltage, overcurrent, and short circuit when the driving voltage is too low or too high. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a drive protection circuit for a power semiconductor device according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the drive protection circuit of another power semiconductor device according to an embodiment of the present invention.

[0042] Reference numerals: First power semiconductor device 10, first control circuit 20, first comparator 21, first transistor 22, second transistor 23, first pulse modulation signal 24, second power semiconductor device 30, first power supply 40, second control circuit 50, second comparator 51, third transistor 52, fourth transistor 53, second pulse modulation signal 54, capacitor 60, second power supply 70, diode 80, first resistor 90, second resistor 91, third resistor 92, fourth resistor 93, fifth resistor 94, sixth resistor 95, seventh resistor 96, eighth resistor 97. Detailed Implementation

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Power semiconductor devices are semiconductor devices specifically designed for controlling and converting electrical energy. They are widely used in various power electronic systems, such as power management, motor drives, electric vehicles, and renewable energy generation. They can efficiently convert electrical energy from one form to another and operate under high voltage and high current conditions. Power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs), are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can lead to device damage or performance degradation.

[0045] Based on the operating characteristics of IGBTs, their drive voltage should be within ±20V. When the IGBT drive voltage is below 9V, it operates in the amplification region with a large on-state voltage drop. As the drive voltage increases, the saturation on-state voltage drop decreases. Furthermore, excessively low drive voltages result in a large saturation on-state voltage drop and low efficiency. When the drive voltage is below 12V, it can cause severe overheating of the IGBT. Conversely, excessively high drive voltages result in a very short time for the IGBT to withstand short circuits and overcurrents, making protection difficult and easily causing damage. The ideal drive voltage for an IGBT is 15±1V. Therefore, the IGBT drive protection circuit is crucial to the reliability of the entire operating system.

[0046] One of the core concepts of this invention is that when the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor; when the second control circuit transmits a low control signal, the second power semiconductor device is turned off, thus providing undervoltage protection for the second power semiconductor device. When the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is also turned off, thus providing overvoltage protection for the second power semiconductor device. In this invention, the second power semiconductor device is in a cutoff state when the capacitor voltage is too low or too high, thereby preventing damage or performance degradation caused by overvoltage, overcurrent, short circuits, or other abnormal conditions when the driving voltage is too low or too high.

[0047] Reference Figure 1 The diagram illustrates a structural schematic of a drive protection circuit for a power semiconductor device according to an embodiment of the present invention, which may specifically include the following structure:

[0048] The first power semiconductor device 10 has its output terminal grounded and its control terminal used to receive the first control signal.

[0049] When the first control signal is high, the control terminal of the first power semiconductor device 10 receives a high level, and the first power semiconductor device 10 is in the on state; when the first control signal is low, the control terminal of the first power semiconductor device 10 receives a low level, and the first power semiconductor device 10 is in the off state.

[0050] The first control circuit 20 is connected to the control terminal of the first power semiconductor device 10 and is used to output a first control signal to the control terminal of the first power semiconductor device 10.

[0051] The first control circuit 20 is used to output a first control signal to the control terminal of the first power semiconductor device 10. The first control signal can be a high level or a low level.

[0052] The second power semiconductor device 30 has its output terminal connected to the input terminal of the first power semiconductor device 10, its control terminal for receiving a second control signal, and its input terminal connected to the first power supply 40.

[0053] When the second control signal is high, the control terminal of the second power semiconductor device 30 receives a high level, and when the first power semiconductor device 10 is in the on state, the second power semiconductor device 30 is in the on state; when the second control signal is low, the control terminal of the second power semiconductor device 30 receives a low level, and the second power semiconductor device 30 is in the off state.

[0054] The input terminal of the second power semiconductor device 30 is connected to the first power supply 40, which is a positive power supply voltage and can be a high voltage, such as several hundred volts.

[0055] The second control circuit 50 is connected to the control terminal of the second power semiconductor device 30 and is used to output a second control signal to the control terminal of the second power semiconductor device 30.

[0056] The second control circuit 50 is used to output a second control signal to the control terminal of the second power semiconductor device 30. The second control signal can be a high level or a low level.

[0057] One end of capacitor 60 is connected to the first control circuit 20, the second control circuit 50, and the second power supply 70, respectively, and the other end is connected to the input terminal of the first power semiconductor device 10 and the output terminal of the second power semiconductor device 30, respectively.

[0058] The voltage of the second power supply 70 can be within the range of 10-20V, and the voltage of the second power supply 70 is lower than that of the first power supply 40. When the first power semiconductor device 10 is turned on, the capacitor 60 can be charged through the second power supply 70 - capacitor 60 - first power semiconductor device 10.

[0059] When capacitor 60 is undervoltage, the first control signal transmitted by the first control circuit 20 is at a high level, the first power semiconductor device 10 is turned on, the second power supply 70 charges capacitor 60, the second control signal transmitted by the second control circuit 50 is at a low level, and the second power semiconductor device 30 is turned off to provide undervoltage protection for the second power semiconductor device 30.

[0060] When capacitor 60 is over-voltage, the first control signal transmitted by the first control circuit 20 is at a low level, the first power semiconductor device 10 is turned off, and the second power semiconductor device 30 is turned off to provide over-voltage protection for the second power semiconductor device 30.

[0061] Before capacitor 60 begins charging, its voltage is very low. The first control signal transmitted by the first control circuit 20 is high, the first power semiconductor device 10 is turned on, and the second power supply 70 charges capacitor 60. Simultaneously, the second control signal transmitted by the second control circuit 50 is low, and the second power semiconductor device 30 is turned off, providing undervoltage protection for the second power semiconductor device 30. When the second power supply 70 charges capacitor 60 to the point where the voltage of capacitor 60 is too high, the first control signal transmitted by the first control circuit 20 is low, the first power semiconductor device 10 is turned off, capacitor 60 stops charging, and the second power semiconductor device 30 is also turned off. Both the first power semiconductor device 10 and the second power semiconductor device 30 cease operation, thus achieving overvoltage protection for the devices.

[0062] An embodiment of the present invention provides a driving protection circuit for a power semiconductor device, comprising: a first power semiconductor device, the output terminal of which is grounded, and a control terminal for receiving a first control signal; a first control circuit connected to the control terminal of the first power semiconductor device, for outputting the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, the output terminal of which is connected to the input terminal of the first power semiconductor device, the control terminal of which receives a second control signal, and the input terminal of which is connected to a first power supply; a second control circuit connected to the control terminal of the second power semiconductor device, for outputting the second control signal to the control terminal of the second power semiconductor device; and a capacitor. One end of the device is connected to the first control circuit, the second control circuit, and the second power supply, respectively. The other end is connected to the input terminal of the first power semiconductor device and the output terminal of the second power semiconductor device, respectively. When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor. The second control signal transmitted by the second control circuit is low, and the second power semiconductor device is turned off, thus providing undervoltage protection for the second power semiconductor device. When the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, thus providing overvoltage protection for the second power semiconductor device. In this embodiment of the invention, the second power semiconductor device is in a cutoff state when the capacitor voltage is too low or too high, thereby avoiding damage or performance degradation of the second power semiconductor device due to abnormal conditions such as overvoltage, overcurrent, and short circuit when the driving voltage is too low or too high.

[0063] In this embodiment of the invention, the first power semiconductor device 10 and the second power semiconductor device 30 are IGBTs.

[0064] The first power semiconductor device 10 has its output terminal as the emitter, its input terminal as the collector, and its control terminal as the gate. The second power semiconductor device 30 is similar. The first power semiconductor device 10 is a lower IGBT, and the second power semiconductor device 30 is an upper IGBT. The second power semiconductor device 30 requires a capacitor of 60 to conduct normally.

[0065] IGBTs are widely used in power electronic devices due to their high efficiency and fast switching characteristics. However, in practical applications, IGBTs are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can lead to device damage or performance degradation.

[0066] Based on the operating characteristics of IGBTs, their drive voltage should be within ±20V. When the IGBT drive voltage is below 9V, it operates in the amplification region with a large on-state voltage drop. As the drive voltage increases, the saturation on-state voltage drop decreases. Furthermore, excessively low drive voltages result in a large saturation on-state voltage drop and low efficiency. When the drive voltage is below 12V, it can cause severe overheating of the IGBT. Conversely, excessively high drive voltages result in a very short time for the IGBT to withstand short circuits and overcurrents, making protection difficult and easily causing damage. The ideal drive voltage for an IGBT is 15±1V. Therefore, the IGBT drive protection circuit is crucial to the reliability of the entire operating system.

[0067] Reference Figure 2 This diagram illustrates the structure of a drive protection circuit for another power semiconductor device according to an embodiment of the present invention. The first control circuit 20 includes:

[0068] The first comparator 21 has its positive input terminal connected to one end of the capacitor 60, and its inverting input terminal connected to the second power supply 70.

[0069] When capacitor 60 is not yet charged, or when capacitor 60 has been charging for a period of time and its voltage is still very low, the voltage at the positive input terminal of the first comparator 21 is less than the voltage at the negative input terminal, and the first comparator 21 outputs a low level; when capacitor 60 is charged to the point where the voltage is too high, the voltage at the positive input terminal of the first comparator 21 is greater than the voltage at the negative input terminal, and the first comparator 21 outputs a high level.

[0070] The first transistor 22 has its emitter connected to the output of the first comparator 21, and its collector connected to the second power supply 70.

[0071] The first transistor 22 is a PNP transistor. When the voltage between pins 1 and 2 of the first transistor 22 is higher than the turn-on voltage of the first transistor 22, the first transistor 22 is turned on. Therefore, when the first comparator 21 outputs a low level, the first transistor 22 is turned on; when the first comparator 21 outputs a high level, the first transistor 22 is turned off.

[0072] The base of the second transistor 23 is connected to the base of the first transistor 22. The collector of the second transistor 23 receives the first pulse modulation signal 24. The emitter of the second transistor 23 is grounded and connected to the control terminal of the first power semiconductor device 10. The second transistor 23 is used to output the first control signal.

[0073] The second transistor 23 is an NPN transistor. When the first transistor 22 is in the on state and the first pulse modulation signal 24 received by the second transistor 23 is at a high level, the second transistor 23 is turned on, that is, the first control signal output by the second transistor 23 is at a high level, and the first power semiconductor device 10 is turned on. When the first transistor 22 is in the off state, the first pulse modulation signal 24 cannot be input to the control terminal of the first power semiconductor device 10, that is, the first control signal output by the second transistor 23 is at a low level, and the first power semiconductor device 10 is turned off.

[0074] When capacitor 60 is undervoltage, the first comparator 21 outputs a low level, the first transistor 22 is turned on, and when the first pulse modulation signal 24 is high, the second transistor 23 is turned on, and the first control signal output by the second transistor 23 is high.

[0075] When capacitor 60 is over-voltage, the first comparator 21 outputs a high level, the first transistor 22 is cut off, and the first control signal output by the second transistor 23 is low.

[0076] Capacitor 60 is a bootstrap capacitor. Initially, before capacitor 60 is charged, its voltage is very low, the first comparator 21 outputs a low level, and the first transistor 22 is turned on. When the first pulse modulation signal 24 is high, the second transistor 23 is turned on. Therefore, the VCC second power supply 70 connected to pin 1 of the first transistor 22 is output to the control terminal of the first power semiconductor device 10 through the first transistor 22. At this time, the first power semiconductor device 10 is turned on, and capacitor 60 can be charged through the VCC second power supply 70 connected to one end of capacitor 60, capacitor 60, and the first power semiconductor device 10. When capacitor 60 is charged to an excessively high voltage, the first comparator 21 outputs a high level, and the first transistor 22 is turned off. Therefore, the first pulse modulation signal 24 cannot be input to the control terminal of the first power semiconductor device 10, and capacitor 60 cannot be charged through the first power semiconductor device 10. Both the first power semiconductor device 10 and the second power semiconductor device 30 are in the off state, thus achieving bootstrap overvoltage protection for the second power semiconductor device 30.

[0077] By connecting the positive input terminal of the first comparator 21 to the capacitor 60, the output signal of the first comparator 21 can change with the voltage state of the capacitor 60. When the capacitor 60 is undervoltage, the first comparator 21 outputs a low level; when the capacitor 60 is overvoltage, the first comparator 21 outputs a high level. The output terminal of the first comparator 21 is connected to the first transistor 22, the first transistor 22 is connected to the second transistor 23, and the second transistor 23 is connected to the control terminal of the first power semiconductor device 10. This allows the change in the voltage state of the capacitor 60 to control the operating state of the first power semiconductor device 10. When the capacitor 60 is undervoltage, the first power semiconductor device 10 is turned on, and the capacitor 60 is charged. When the capacitor 60 is overvoltage, the first power semiconductor device 10 is turned off, and the second power semiconductor device 30 is turned off, thereby achieving overvoltage protection for the second power semiconductor device 30.

[0078] Since the driving voltage of the first power semiconductor device 10 is the second power supply 70 connected to pin 1 of the first transistor 22, and the second power supply 70 is a stable voltage source, the first power semiconductor device 10 will not experience overvoltage or undervoltage issues. However, the driving voltage of the second power semiconductor device 30 is the voltage of the bootstrap capacitor 60, which is not a stable voltage source. Therefore, the second power semiconductor device 30 is susceptible to overvoltage or undervoltage issues and requires overvoltage and undervoltage protection.

[0079] In this embodiment of the invention, the second control circuit 50 includes:

[0080] The second comparator 51 has its positive input terminal connected to the second power supply 70, and its inverting input terminal connected to both the second power supply 70 and the capacitor 60.

[0081] If the voltage of capacitor 60 is still too low after capacitor 60 has been charging for a period of time, the voltage at the positive input terminal of the second comparator 51 will be greater than the voltage at the negative input terminal, and the second comparator 51 will output a high level.

[0082] The emitter of the third transistor 52 is connected to the output of the second comparator 51, and the collector of the third transistor 52 is connected to the second power supply 70 and the capacitor 60 respectively.

[0083] The third transistor 52 is a PNP transistor. Its emitter, pin 2, is connected to the output of the second comparator 51. Its collector, pin 1, is connected to the second power supply 70 and the capacitor 60. When the second comparator 51 outputs a high level, the third transistor 52 is off; when it outputs a low level, it is on.

[0084] The base of the fourth transistor 53 is connected to the base of the third transistor 52. The collector of the fourth transistor 53 receives the second pulse modulation signal 54. The emitter of the fourth transistor 53 is grounded and connected to the control terminal of the second power semiconductor device 30. The fourth transistor 53 is used to output the second control signal 54.

[0085] The base of the fourth transistor 53, i.e., pin 3 of the fourth transistor 53, is connected to the base of the third transistor 52, i.e., pin 3. The collector of the fourth transistor 53, i.e., pin 1, receives the second pulse modulation signal 54. The emitter of the fourth transistor 53, i.e., pin 2, is grounded and connected to the control terminal of the second power semiconductor device 30. When the third transistor 52 is off, the second pulse modulation signal 54 cannot be input to the control terminal of the second power semiconductor device 30. Whether the second pulse modulation signal 54 is high or low, the fourth transistor 53 will not conduct, and the second power semiconductor device 30 will not conduct either.

[0086] When capacitor 60 is undervoltage, the second comparator 51 outputs a high level, the third transistor 52 is cut off, and the second control signal output by the fourth transistor 53 is low.

[0087] When capacitor 60 is undervoltage, the voltage at the positive input terminal of the second comparator 51 is greater than the voltage at the negative input terminal, and the second comparator 51 outputs a high level. The third transistor 52 is cut off. At this time, whether the second pulse modulation signal 54 is high or low, the fourth transistor 53 will not be turned on, and the second power semiconductor device 30 will not be turned on, thus realizing the function of protecting the second power semiconductor device 30 from undervoltage of the bootstrap capacitor 60.

[0088] The second power semiconductor device 30 requires a bootstrap capacitor 60 to conduct normally. The charging circuit of the bootstrap capacitor 60 consists of a diode 80 and the bootstrap capacitor 60. The driving part consists of a fourth transistor 53 and a third transistor 52. The second comparator 51 compares the voltage of the capacitor 60 to control the input signal, the second pulse modulation signal 54, of the second power semiconductor device 30. The driving part of the first power semiconductor device 10 consists of a first transistor 22 and a second transistor 23. The first comparator 21 compares the voltage of the capacitor 60 to control the input signal, the first pulse modulation signal 24, of the first power semiconductor device 10.

[0089] For example, the voltage of capacitor 60 is set to three levels: 12V, 15V, and 17V. When the voltage of capacitor 60 is lower than 12V, i.e., when the voltage of capacitor 60 is too low, the first comparator 21 outputs a low level, and the first transistor 22 is turned on. When the first pulse modulation signal 24 is high, the second transistor 23 is turned on, the first power semiconductor device 10 is turned on, and capacitor 60 is charged. At the same time, the second comparator 51 outputs a high level, and the third transistor 52 is turned off. At this time, whether the second pulse modulation signal 54 is high or low, the fourth transistor 53 will not be turned on, and the second power semiconductor device 30 will not be turned on either, thus achieving undervoltage protection for the driving voltage of the second power semiconductor device 30.

[0090] When the voltage of capacitor 60 is 15V, that is, when the voltage of capacitor 60 is at the ideal driving voltage level of the second power semiconductor device 30, the voltage at the positive input terminal of the second comparator 51 is less than the voltage at the negative input terminal, the second comparator 51 outputs a low level, the third transistor 52 is turned on, and the second pulse modulation signal 54 can be input to the control terminal of the second power semiconductor device 30 to control the working state of the second power semiconductor device 30. When the second pulse modulation signal 54 is at a high level, the fourth transistor 53 is turned on, and the second power semiconductor device 30 can be turned on.

[0091] When the voltage of capacitor 60 is 17V, that is, when the voltage of capacitor 60 is too high, the first comparator 21 outputs a high level, the first transistor 22 is cut off, and the second transistor 23 and the first power semiconductor device 10 cannot be turned on regardless of whether the first pulse modulation signal 24 is high or low. Therefore, capacitor 60 cannot be charged, and the second power semiconductor device 30 will not be turned on. Thus, overvoltage protection of the driving voltage of the second power semiconductor device 30 is achieved.

[0092] This invention employs a bootstrap capacitor voltage detection capacitor. The drive signal to the IGBT is only allowed when the bootstrap voltage reaches a certain limit, and the input signal is cut off when the bootstrap voltage is too high, effectively protecting the IGBT and bootstrap capacitor from damage. This improves the IGBT's protection performance under abnormal conditions.

[0093] In this embodiment of the invention, the circuit further includes a diode 80, the anode of which is connected to the second power supply 70, and the cathode of which is connected to the inverting input terminal of the second comparator 51, the collector of the third transistor 52, and the capacitor 60, respectively.

[0094] When the first power semiconductor device 10 is turned on, the charging circuit of capacitor 60 is: second power supply 70 - diode 80 - capacitor 60 - first power semiconductor device 10, and diode 80 is used for reverse clamping.

[0095] In this embodiment of the invention, the circuit further includes:

[0096] The first resistor 90 has one end connected to the second power supply 70 and the other end connected to the inverting input of the first comparator 21.

[0097] The second resistor 91 has one end connected to the first resistor 90 and the inverting input of the first comparator 21, and the other end grounded.

[0098] The first resistor 90 and the second resistor 91 are voltage divider resistors connected to the inverting input terminal of the first comparator 21. After voltage division, they serve as the input voltage to the inverting input terminal of the first comparator 21. By adjusting the parameters of the first resistor 90 and the second resistor 91, it is possible to make the voltage at the inverting input terminal of the first comparator 21 greater than the voltage at the non-inverting input terminal when the voltage across the capacitor 60 is lower than a certain threshold (capacitor 60 is not charged or not fully charged), so that the first comparator 21 outputs a low level when capacitor 60 is not charged or not fully charged.

[0099] In this embodiment of the invention, the circuit further includes:

[0100] The third resistor 92 has one end connected to the second power supply 70 and the other end connected to the positive input terminal of the second comparator 51.

[0101] The fourth resistor 93 has one end connected to the third resistor 92 and the positive input terminal of the second comparator 51, and the other end grounded.

[0102] The third resistor 92 and the fourth resistor 93 are voltage divider resistors connected to the positive input terminal of the second comparator 51. After voltage division, they serve as the input voltage of the positive input terminal of the second comparator 51. By adjusting the parameters of the third resistor 92 and the fourth resistor 93, it can be achieved that when the voltage across the capacitor 60 reaches the ideal driving voltage of the second power semiconductor device 30, the voltage at the inverting input terminal of the second comparator 51 is greater than the voltage at the positive input terminal, so that when the voltage across the capacitor 60 meets the ideal driving voltage of the second power semiconductor device 30, the second comparator 51 outputs a low level.

[0103] In this embodiment of the invention, the circuit further includes:

[0104] The fifth resistor 94 has one end connected to the output of the first comparator 21 and the other end connected to the second power supply 70.

[0105] The fifth resistor, 94, is a pull-up resistor. Comparators are typically open-drain output structures. This means they can only pull the output low (i.e., connect it to ground), and cannot actively pull it high. Therefore, when the comparator is not conducting, the output is in a high-impedance state, requiring external components to determine its logic level. The pull-up resistor provides a path, allowing the output to be pulled towards the power supply voltage (Vcc) when the comparator output is off, thus forming a clear high-level signal.

[0106] In this embodiment of the invention, the circuit further includes:

[0107] The sixth resistor 95 has one end connected to the output of the second comparator 51 and the other end connected to the second power supply 70.

[0108] The sixth resistor, 95 ohms, is a pull-up resistor. Comparators are typically open-drain output structures. This means they can only pull the output low (i.e., connect it to ground), and cannot actively pull it high. Therefore, when the comparator is not conducting, the output is in a high-impedance state, requiring external components to determine its logic level. The pull-up resistor provides a path, allowing the output to be pulled towards the power supply voltage (Vcc) when the comparator output is off, thus forming a clear high-level signal.

[0109] In this embodiment of the invention, the circuit further includes:

[0110] The seventh resistor 96 has one end connected to the emitter of the second transistor 23 and the other end connected to the control terminal of the first power semiconductor device 10.

[0111] The seventh resistor 96 is a current-limiting resistor, which can limit the charging current of the control terminal, i.e., the gate, of the first power semiconductor device 10 to prevent overload or damage to the drive circuit; it can also adjust the switching speed of the first power semiconductor device 10, thereby achieving a balance between switching losses and electromagnetic interference; suppressing parasitic oscillations and improving the stability of device operation; and at the same time, it can protect the gate oxide layer of the first power semiconductor device 10 from damage by voltage spikes.

[0112] In this embodiment of the invention, the circuit further includes:

[0113] The eighth resistor 97 has one end connected to the emitter of the fourth transistor 53 and the other end connected to the control terminal of the second power semiconductor device 30.

[0114] The eighth resistor 97 is a current-limiting resistor, which can limit the charging current of the control terminal, i.e., the gate, of the second power semiconductor device 30 to prevent overload or damage to the drive circuit; it can also adjust the switching speed of the second power semiconductor device 30, thereby achieving a balance between switching losses and electromagnetic interference; suppressing parasitic oscillations and improving the stability of device operation; and at the same time, it can protect the gate oxide layer of the second power semiconductor device 30 from damage by voltage spikes.

[0115] An embodiment of the present invention provides a driving protection circuit for a power semiconductor device, comprising: a first power semiconductor device, the output terminal of which is grounded, and a control terminal for receiving a first control signal; a first control circuit connected to the control terminal of the first power semiconductor device, for outputting the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, the output terminal of which is connected to the input terminal of the first power semiconductor device, the control terminal of which receives a second control signal, and the input terminal of which is connected to a first power supply; a second control circuit connected to the control terminal of the second power semiconductor device, for outputting the second control signal to the control terminal of the second power semiconductor device; and a capacitor. One end of the device is connected to the first control circuit, the second control circuit, and the second power supply, respectively. The other end is connected to the input terminal of the first power semiconductor device and the output terminal of the second power semiconductor device, respectively. When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor. The second control signal transmitted by the second control circuit is low, and the second power semiconductor device is turned off, thus providing undervoltage protection for the second power semiconductor device. When the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, thus providing overvoltage protection for the second power semiconductor device. In this embodiment of the invention, the second power semiconductor device is in a cutoff state when the capacitor voltage is too low or too high, thereby avoiding damage or performance degradation of the second power semiconductor device due to abnormal conditions such as overvoltage, overcurrent, and short circuit when the driving voltage is too low or too high.

[0116] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0118] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0121] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0122] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0123] The driving protection circuit for a power semiconductor device provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A drive protection circuit for a power semiconductor device, characterized in that, The circuit includes: A first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded and the control terminal is used to receive a first control signal; A first control circuit is connected to the control terminal of the first power semiconductor device and is used to output the first control signal to the control terminal of the first power semiconductor device. The second power semiconductor device has its output terminal connected to the input terminal of the first power semiconductor device, its control terminal for receiving a second control signal, and its input terminal connected to a first power supply. The second control circuit is connected to the control terminal of the second power semiconductor device and is used to output the second control signal to the control terminal of the second power semiconductor device. The capacitor has one end connected to the first control circuit, the second control circuit, and the second power supply, respectively, and the other end connected to the input terminal of the first power semiconductor device and the output terminal of the second power semiconductor device, respectively. When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, and the second power supply charges the capacitor. When the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off to provide undervoltage protection for the second power semiconductor device. When the capacitor is overvoltaged, the first control signal transmitted by the first control circuit is at a low level, the first power semiconductor device is turned off, and the second power semiconductor device is turned off to provide overvoltage protection for the second power semiconductor device.

2. The drive protection circuit for the power semiconductor device according to claim 1, characterized in that, The first control circuit includes: A first comparator, wherein the positive input terminal of the first comparator is connected to one end of the capacitor, and the inverting input terminal of the first comparator is connected to the second power supply; The first transistor has its emitter connected to the output of the first comparator and its collector connected to the second power supply. The second transistor has its base connected to the base of the first transistor, its collector receiving the first pulse modulation signal, and its emitter grounded and connected to the control terminal of the first power semiconductor device; the second transistor is used to output the first control signal. When the capacitor is undervoltage, the first comparator outputs a low level, and the first transistor is turned on. When the first pulse modulation signal is high, the second transistor is turned on, and the first control signal output by the second transistor is high. When the capacitor is overvoltaged, the first comparator outputs a high level, the first transistor is cut off, and the first control signal output by the second transistor is low.

3. The drive protection circuit for the power semiconductor device according to claim 1, characterized in that, The second control circuit includes: The second comparator has its positive input connected to the second power supply and its negative input connected to both the second power supply and the capacitor. The emitter of the third transistor is connected to the output terminal of the second comparator, and the collector of the third transistor is connected to the second power supply and the capacitor respectively. The fourth transistor has its base connected to the base of the third transistor, its collector receiving a second pulse modulation signal, and its emitter grounded and connected to the control terminal of the second power semiconductor device; the fourth transistor is used to output the second control signal. When the capacitor is undervoltage, the second comparator outputs a high level, and the third transistor is cut off; the second control signal output by the fourth transistor is a low level.

4. The drive protection circuit for the power semiconductor device according to claim 1, characterized in that, The first power semiconductor device and the second power semiconductor device are IGBTs.

5. The drive protection circuit for the power semiconductor device according to claim 3, characterized in that, The circuit also includes a diode, the anode of which is connected to the second power supply, and the cathode of which is connected to the inverting input of the second comparator, the collector of the third transistor, and the capacitor.

6. The drive protection circuit for the power semiconductor device according to claim 2, characterized in that, The circuit also includes: The first resistor has one end connected to the second power supply and the other end connected to the inverting input of the first comparator. The second resistor has one end connected to the first resistor and the inverting input of the first comparator, and the other end grounded.

7. The drive protection circuit for the power semiconductor device according to claim 3, characterized in that, The circuit also includes: The third resistor has one end connected to the second power supply and the other end connected to the positive input terminal of the second comparator. The fourth resistor has one end connected to the third resistor and the positive input terminal of the second comparator, and the other end grounded.

8. The drive protection circuit for the power semiconductor device according to claim 2, characterized in that, The circuit also includes: The fifth resistor has one end connected to the output of the first comparator and the other end connected to the second power supply.

9. The drive protection circuit for the power semiconductor device according to claim 3, characterized in that, The circuit also includes: The sixth resistor has one end connected to the output terminal of the second comparator and the other end connected to the second power supply.

10. The drive protection circuit for the power semiconductor device according to claim 2, characterized in that, The circuit also includes: The seventh resistor has one end connected to the emitter of the second transistor and the other end connected to the control terminal of the first power semiconductor device.

11. The drive protection circuit for the power semiconductor device according to claim 3, characterized in that, The circuit also includes: The eighth resistor has one end connected to the emitter of the fourth transistor and the other end connected to the control terminal of the second power semiconductor device.

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