Resistor-capacitor RC oscillator, clock generation circuit and electronic chip

Abstract

The invention discloses a resistor-capacitor RC oscillator, a clock generation circuit and an electronic chip, in the RC oscillator, a current generation module generates a third current and a fourth current with a first temperature coefficient and a fifth current with a second temperature coefficient based on a first current and a second current; the resistor array module receives the third current and the fourth current to generate a first reference voltage with a third temperature coefficient; and the core circuit module charges the capacitor by using the fifth current and generates an oscillation clock signal. The capacitor is charged through fifth current, so that the second temperature coefficient and the temperature coefficient of the capacitor are offset, and temperature compensation of the capacitor is achieved; the third current and the fourth current flow through the resistor array module, so that the first temperature coefficient is counteracted with the temperature coefficient of the resistor, and the temperature compensation of the resistor is realized; therefore, the influence caused by the temperature coefficient of the resistor and the capacitor is weakened, the frequency stability of the oscillation clock signal is improved, and the chip performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a resistor-capacitor (RC) oscillator, a clock generation circuit, and an electronic chip. Background Art

[0002] With the rapid development of integrated circuit technology, the performance requirements for system-on-chip (SoC) chips are becoming increasingly higher. Providing a stable, reliable, and high-precision clock module for SoCs is becoming increasingly important. On-chip clock modules typically consist of oscillators, such as LC (inductance-capacitance) oscillators, ring oscillators, and RC (resistor-capacitance) oscillators (also known as relaxation oscillators).

[0003] In practical applications, RC oscillators are suitable for medium and low frequency scenarios. Compared with LC oscillators, RC oscillators do not require on-chip inductors to generate oscillation signals and are easy to integrate. Compared with ring oscillators, the frequency offset caused by PVT (Production Validation Test) of RC oscillators is easier to eliminate through compensation and calibration. Therefore, RC oscillators are widely used in on-chip clock modules.

[0004] An RC oscillator generates an oscillating clock by delaying the charging and discharging of a capacitor. However, the resistance and capacitance in the RC oscillator are significantly affected by the operating environment temperature, causing the generated clock signal to vary dramatically with temperature. This severely affects the frequency stability of the clock signal and reduces the performance of the SoC chip. Summary of the Invention

[0005] The present invention provides a resistor-capacitor (RC) oscillator, a clock generation circuit, and an electronic chip, for solving the problem in the prior art that the frequency of an output oscillation clock signal is unstable because the resistor and capacitor in the RC oscillator are greatly affected by temperature.

[0006] In a first aspect, an embodiment of the present invention provides an RC oscillator, comprising a core circuit module, a current generating module, and a resistor array module, wherein:

[0007] The current input terminal of the core circuit module is electrically connected to the first output terminal of the current generating module, the reference voltage terminal of the core circuit module is electrically connected to the second output terminal of the current generating module and the first terminal of the resistor array module respectively, and the third output terminal of the current generating module is electrically connected to the second terminal of the resistor array module;

[0008] The current generating module is configured to generate a third current and a fourth current having a first temperature coefficient, and a fifth current having a second temperature coefficient based on the first current and the second current, wherein the first current is a current having a positive temperature coefficient, and the second current is a current associated with a reference voltage;

[0009] The resistor array module is configured to receive the third current and the fourth current respectively, so that a first reference voltage having a third temperature coefficient is generated at a first end of the resistor array module;

[0010] The core circuit module is configured to charge a capacitor in the core circuit module using the fifth current to obtain a first voltage, and generate an oscillation clock signal based on the first voltage and the first reference voltage.

[0011] In the RC oscillator provided by an embodiment of the present invention, when a fifth current is used to charge a capacitor in a core circuit module, the second temperature coefficient of the fifth current and the temperature coefficient of the capacitor cancel each other out, thereby compensating for the temperature coefficient of the capacitor. Furthermore, when a third current and a fourth current are used to flow through a resistor array module, the first temperature coefficients of the third current and the fourth current and the temperature coefficients of the resistors in the resistor array module cancel each other out, thereby compensating for the temperature coefficient of the resistors. Furthermore, the third temperature coefficient of the generated first reference voltage is determined solely by the temperature coefficient of the reference voltage associated with the second current. Since the reference voltage can achieve a lower temperature coefficient, the third temperature coefficient of the first reference voltage is also correspondingly lower. The above-described method weakens or even eliminates the influence of the temperature coefficients of the resistors and capacitors, improves the frequency stability of the oscillation clock signal generated by the RC oscillator, and thereby improves the performance of a SoC chip having an RC oscillator.

[0012] In an optional embodiment, the current generating module includes a first current generating unit and a second current generating unit, wherein:

[0013] The first input end of the first current generating unit is used to input the first current, the second input end of the first current generating unit is electrically connected to the first output end of the second current generating unit, and the output end of the first current generating unit serves as the first output end of the current generating module;

[0014] The input end of the second current generating unit is used to input the second current, the second output end of the second current generating unit serves as the second output end of the current generating module, and the third output end of the second current generating unit serves as the third output end of the current generating module;

[0015] The first current generating unit is configured to generate the fifth current according to the first current and the second current;

[0016] The second current generating unit is configured to generate the third current and the fourth current according to the second current.

[0017] In an optional embodiment, the first current generating unit includes a first current mirror, a second current mirror, a third current mirror, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein:

[0018] One end of the first resistor is electrically connected to the first end of the first current mirror and serves as the first input end of the first current generating unit, and the other end of the first resistor is electrically connected to the second end of the first current mirror and the third end of the first current mirror respectively;

[0019] The fourth end of the first current mirror is electrically connected to one end of the second resistor and the first end of the second current mirror respectively, and the fifth end of the first current mirror and the sixth end of the first current mirror are both grounded;

[0020] The other end of the second resistor is electrically connected to the second end of the second current mirror and the third end of the second current mirror respectively;

[0021] The fourth end of the second current mirror is electrically connected to one end of the third resistor, the first end of the third current mirror and one end of the fourth resistor respectively;

[0022] The other end of the third resistor is electrically connected to the second end of the third current mirror and the third end of the third current mirror respectively;

[0023] The other end of the fourth resistor serves as the second input end of the first current generating unit;

[0024] The fourth terminal of the third current mirror serves as the output terminal of the first current generating unit;

[0025] The fifth terminal of the second current mirror, the sixth terminal of the second current mirror, the fifth terminal of the third current mirror and the sixth terminal of the third current mirror are all used to receive a chip operating voltage;

[0026] The first current mirror is used to perform proportional mirror processing on the first current;

[0027] The second current mirror is configured to perform mirror processing on the current processed by the first current mirror based on a first proportional coefficient to obtain a first intermediate current;

[0028] the third current mirror is configured to generate a second intermediate current according to a difference between the current output by the first output terminal of the second current generating unit and the first intermediate current, and to perform mirroring processing on the second intermediate current based on a second proportional coefficient to obtain the fifth current;

[0029] The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

[0030] The above-mentioned RC oscillator generates a fifth current with a second temperature coefficient by performing a differential processing on the first current and the second current at different ratios, and uses the fifth current to charge the capacitor in the core circuit module so that the temperature coefficient of the fifth current and the temperature coefficient of the capacitor cancel each other out, thereby achieving coarse adjustment calibration of the frequency of the oscillation clock signal; in addition, the proportional coefficient used to generate the fifth current is set as an adjustable coefficient, that is, the fifth current is adjustable to resist process errors.

[0031] In an optional embodiment, the first current generating unit includes a third current mirror, a fourth current mirror, a third resistor, and a fifth resistor, wherein:

[0032] One end of the fifth resistor is electrically connected to the first end of the fourth current mirror and serves as the first input end of the first current generating unit, and the other end of the fifth resistor is electrically connected to the second end of the fourth current mirror and the third end of the fourth current mirror respectively;

[0033] The fourth end of the fourth current mirror is electrically connected to one end of the third resistor and the first end of the third current mirror, respectively, and serves as the second input end of the first current generating unit. The fifth end and the sixth end of the fourth current mirror are both grounded.

[0034] The other end of the third resistor is electrically connected to the second end of the third current mirror and the third end of the third current mirror respectively;

[0035] The fourth terminal of the third current mirror serves as the output terminal of the first current generating unit, and the fifth terminal of the third current mirror and the sixth terminal of the third current mirror are both used to receive the chip operating voltage;

[0036] The fourth current mirror is configured to perform mirror processing on the first current based on a first proportional coefficient to obtain a first intermediate current;

[0037] the third current mirror is configured to generate a second intermediate current according to a sum of the current output by the first output terminal of the second current generating unit and the first intermediate current, and to perform mirroring processing on the second intermediate current based on a second proportional coefficient to obtain the fifth current;

[0038] The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

[0039] The above-mentioned RC oscillator generates a fifth current with a second temperature coefficient by summing the first current and the second current in different proportions, and uses the fifth current to charge the capacitor in the core circuit module so that the temperature coefficient of the fifth current and the temperature coefficient of the capacitor cancel each other out, thereby achieving coarse adjustment calibration of the frequency of the oscillation clock signal; in addition, the proportional coefficient used to generate the fifth current is set to an adjustable coefficient, that is, the fifth current is adjustable to resist process errors.

[0040] In an optional embodiment, the second current generating unit includes a fifth current mirror, a sixth current mirror, a sixth resistor, and a seventh resistor, wherein:

[0041] One end of the sixth resistor is electrically connected to the first end of the fifth current mirror and serves as the input end of the second current generating unit, and the other end of the sixth resistor is electrically connected to the second end of the fifth current mirror and the third end of the fifth current mirror respectively;

[0042] The fourth end of the fifth current mirror serves as the first output end of the second current generating unit, the fifth end of the fifth current mirror is electrically connected to one end of the seventh resistor and the first end of the sixth current mirror, respectively, and the sixth end of the fifth current mirror, the seventh end of the fifth current mirror, and the eighth end of the fifth current mirror are all grounded;

[0043] The other end of the seventh resistor is electrically connected to the second end of the sixth current mirror and the third end of the sixth current mirror respectively;

[0044] The fourth terminal of the sixth current mirror serves as the second output terminal of the second current generating unit, the fifth terminal of the sixth current mirror serves as the third output terminal of the second current generating unit, and the sixth terminal of the sixth current mirror, the seventh terminal of the sixth current mirror, and the eighth terminal of the sixth current mirror are all used to receive the chip operating voltage;

[0045] the fifth current mirror is configured to perform proportional mirroring on the second current and to perform mirroring on the second current based on a third proportional coefficient to generate a third intermediate current that is sent to the first current generating unit;

[0046] the sixth current mirror being configured to mirror the current proportionally mirrored by the fifth current mirror based on a fourth proportional coefficient to obtain the third current, and to mirror the current proportionally mirrored by the fifth current mirror based on a fifth proportional coefficient to obtain the fourth current;

[0047] The fourth proportional coefficient is greater than the fifth proportional coefficient.

[0048] The above-mentioned RC oscillator performs mirroring processing on the second current in different proportions to obtain a third current and a fourth current, respectively, and the third current is greater than the fourth current. After the third current and the fourth current pass through the resistor array module, a first reference voltage with a third temperature coefficient is generated to compensate for the temperature coefficient of the resistors in the resistor array module, thereby achieving fine-tuning calibration of the frequency of the oscillation clock signal.

[0049] In an optional embodiment, the resistor array module includes a single-pole multi-throw switch and a plurality of eighth resistors connected in series, wherein:

[0050] One end of a first eighth resistor among the plurality of eighth resistors serves as the first end of the resistor array module, one end of each of the other eighth resistors is electrically connected to the corresponding branches of the first end of the single-pole multi-throw switch, and the other end of the last eighth resistor among the plurality of eighth resistors is grounded, wherein the other eighth resistors are resistors among the plurality of eighth resistors other than the first eighth resistor;

[0051] The second end of the single-pole multi-throw switch serves as the second end of the resistor array module;

[0052] The SPMT switch is configured to conduct a path between the second end of the SPMT switch and any branch of the first end of the SPMT switch to change the number of eighth resistors through which the fourth current flows.

[0053] In an optional embodiment, the first current is a PTAT current that is proportional to absolute temperature, and the second current is determined according to a ratio of the reference voltage to a reference resistance;

[0054] The temperature coefficient of the eighth resistor is the same as the temperature coefficient of the reference resistor.

[0055] In the above-mentioned RC oscillator, since the temperature coefficient of the eighth resistor is the same as the temperature coefficient of the reference resistor, and the temperature coefficients of the third current and the fourth current are both determined by the temperature coefficient of the reference voltage and the temperature coefficient of the reference resistor, when the third current and the fourth current flow through the eighth resistor, the first temperature coefficient of the third current and the fourth current can offset the temperature coefficient of the eighth resistor to achieve compensation for the temperature coefficient of the resistor, thereby achieving fine-tuning calibration of the frequency of the oscillation clock signal.

[0056] In an optional embodiment, the core circuit module includes a switched capacitor unit, a VAF unit, and an oscillation generation unit, wherein:

[0057] The input end of the switch capacitor unit serves as the current input end of the core circuit module, the first control end of the switch capacitor unit is electrically connected to the first output end of the oscillation generating unit, and the second control end of the switch capacitor unit is electrically connected to the second output end of the oscillation generating unit;

[0058] The first output terminal of the switched capacitor unit is electrically connected to the first input terminal of the VAF unit, the second output terminal of the switched capacitor unit is electrically connected to the first input terminal of the oscillation generating unit, and the third output terminal of the switched capacitor unit is electrically connected to the second input terminal of the oscillation generating unit;

[0059] The second input terminal of the VAF unit serves as a reference voltage terminal of the core circuit module, the output terminal of the VAF unit is electrically connected to the third input terminal of the oscillation generation unit, and the third output terminal of the oscillation generation unit is used to output the oscillation clock signal;

[0060] The switched capacitor unit is configured to periodically charge the capacitor in the switched capacitor unit using the fifth current under the control of the switch control signal to generate the first voltage;

[0061] The VAF unit is configured to generate a second voltage based on the first reference voltage and the first voltage;

[0062] The oscillation generating unit is configured to generate the switch control signal and the oscillation clock signal according to the second voltage.

[0063] In the above-mentioned RC oscillator, during the oscillation process, the average value of the first voltage approaches the first reference voltage. The second voltage output by the VAF unit is used to adjust the flip voltage of the comparator in the oscillation generation unit, thereby eliminating the influence of the comparator delay in the oscillation generation unit and improving the frequency stability of the oscillation clock signal.

[0064] In a second aspect, an embodiment of the present invention provides a clock generation circuit, comprising the RC oscillator as described in any one of the embodiments of the first aspect above.

[0065] In a third aspect, an embodiment of the present invention provides an electronic chip, comprising a bandgap reference circuit and a clock generation circuit as described in any one of the embodiments of the first aspect, wherein:

[0066] The bandgap reference circuit is used to output a first current and a second current.

[0067] For the technical effects that may be achieved by the clock generation circuit disclosed in the second aspect and the electronic chip disclosed in the third aspect, please refer to the above description of the technical effects that may be achieved by the first aspect or various possible solutions in the first aspect, and no further details will be given here.

[0068] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0070] Figure 1 A schematic diagram of the module structure of an RC oscillator provided in an embodiment of the present invention;

[0071] Figure 2 A schematic diagram of the unit structure of a core circuit module in an RC oscillator provided by an embodiment of the present invention;

[0072] Figure 3 A schematic diagram of the circuit structure of a switched capacitor unit in a core circuit module provided by an embodiment of the present invention;

[0073] Figure 4 A schematic diagram of the circuit structure of a VAF unit in a core circuit module provided by an embodiment of the present invention;

[0074] Figure 5 A schematic diagram of the circuit structure of a VAF unit in another core circuit module provided by an embodiment of the present invention;

[0075] Figure 6 A schematic diagram of the circuit structure of an oscillation generating unit in a core circuit module provided by an embodiment of the present invention;

[0076] Figure 7 A schematic diagram of the circuit structure of an oscillation generating unit in another core circuit module provided by an embodiment of the present invention;

[0077] Figure 8 A schematic diagram of the unit structure of a current generating module in an RC oscillator provided in an embodiment of the present invention;

[0078] Figure 9 A schematic diagram of the circuit structure of a first current generating unit in a current generating module provided by an embodiment of the present invention;

[0079] Figure 10A schematic diagram of the circuit structure of a first current mirror provided by an embodiment of the present invention;

[0080] Figure 11 A schematic diagram of the circuit structure of a second current mirror provided by an embodiment of the present invention;

[0081] Figure 12 A schematic diagram of the circuit structure of a first current generating unit in another current generating module provided by an embodiment of the present invention;

[0082] Figure 13 A schematic diagram of the circuit structure of a second current generating unit in a current generating module provided by an embodiment of the present invention;

[0083] Figure 14 A schematic diagram of the circuit structure of a second current generating unit in another current generating module provided by an embodiment of the present invention;

[0084] Figure 15 A schematic diagram of the circuit structure of a resistor array module in an RC oscillator provided by an embodiment of the present invention;

[0085] Figure 16 A schematic diagram of a complete circuit structure of an RC oscillator provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0086] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0087] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0088] As mentioned earlier, RC oscillators are widely used in the on-chip clock modules of SoC chips. In existing RC oscillators, the temperature sensitivity of capacitors and resistors, as well as the delay of the comparator, can affect the frequency stability of the oscillating clock signal generated by the RC oscillator. To improve the frequency stability of the oscillating clock signal generated by the RC oscillator, the voltage averaging feedback (VAF) technology was introduced to reduce the impact of the comparator delay on the frequency stability of the oscillating clock signal and suppress the frequency deviation of the oscillating clock signal.

[0089] However, the aforementioned VAF-based RC oscillator cannot eliminate the impact of the temperature-sensitive nature of capacitors and resistors on the frequency stability of the oscillating clock signal. When the SoC operates in a non-constant temperature environment, the frequency of the oscillating clock signal generated by the RC oscillator varies dramatically with temperature, severely affecting the frequency stability of the clock signal and thus degrading the performance of the SoC chip.

[0090] Based on this, an embodiment of the present invention provides a resistor-capacitor RC oscillator, a clock generation circuit, and an electronic chip to weaken the influence of the temperature coefficients of the resistors and capacitors in the RC oscillator, reduce the impact of temperature changes on the frequency of the oscillation clock signal, improve the frequency stability of the oscillation clock signal, and thereby enhance the performance of the SoC chip.

[0091] The RC oscillator provided by the present invention is specifically described below with reference to the accompanying drawings:

[0092] Figure 1 A schematic diagram of the module structure of an RC oscillator is shown in FIG. Figure 1 As shown, the RC oscillator 100 includes a core circuit module 110, a current generating module 120 and a resistor array module 130, wherein:

[0093] The current input terminal of the core circuit module 110 is electrically connected to the first output terminal of the current generating module 120. The reference voltage terminal of the core circuit module 110 is electrically connected to the second output terminal of the current generating module 120 and the first terminal of the resistor array module 130 respectively. The third output terminal of the current generating module 120 is electrically connected to the second terminal of the resistor array module 130.

[0094] The current generating module 120 is configured to generate a current based on the first current I ptat and the second current I rint , generating a third current I having a first temperature coefficient ref and the fourth current I ref_trim , and a fifth current I having a second temperature coefficient out , where the first current I ptat is a current with a positive temperature coefficient, the second current Irint With the reference voltage V BG associated current;

[0095] The resistor array module 130 is configured to receive the third current I ref and the fourth current I ref_trim , so that a first reference voltage V having a third temperature coefficient is generated at the first end of the resistor array module 130 ref ;

[0096] The core circuit module 110 is configured to utilize the fifth current I out , charging the capacitor in the core circuit module 110 to obtain a first voltage V CC , and based on the first voltage V CC and the first reference voltage V ref , generates the oscillation clock signal CLK out .

[0097] In the RC oscillator provided by the embodiment of the present invention, the current generating module 120 is based on the first current I ptat and the second current I rint , generating a fifth current I having a second temperature coefficient out , and in utilizing the fifth current I out , in the process of charging the capacitor in the core circuit module 110, the fifth current I out The second temperature coefficient of the capacitor and the temperature coefficient of the capacitor cancel each other out to achieve compensation for the temperature coefficient of the capacitor;

[0098] In addition, the current generating module 120 is based on the second current I rint Generate a third current I having a first temperature coefficient ref and the fourth current I ref_trim , using the third current I ref and the fourth current I ref_trim When the third current I flows through the resistor array module 130, ref and the fourth current I ref_trim The first temperature coefficient of the resistor and the temperature coefficient of the resistor in the resistor array module 130 cancel each other out to achieve compensation for the temperature coefficient of the resistor;

[0099] And the generated first reference voltage V ref The third temperature coefficient is determined only by the second current I rint The associated reference voltage V BG The temperature coefficient is determined by the reference voltage V BG A lower temperature coefficient can be achieved, so the first reference voltage V refThe third temperature coefficient is also correspondingly low. By the above method, the influence of the temperature coefficients of the resistors and capacitors is weakened or even eliminated, the frequency stability of the oscillation clock signal generated by the RC oscillator is improved, and the performance of the SoC chip with the RC oscillator is improved.

[0100] In one or more embodiments, the first current I ptat is the PTAT (Proportional to Absolute Temperature) current; the second current I rint Based on the reference voltage V BG and reference resistor R BG The ratio is determined.

[0101] Optionally, the second current I rint It can be expressed as: Therefore, the second current I rint The temperature coefficient of the reference voltage V BG The temperature coefficient and reference resistance R BG The temperature coefficient is determined.

[0102] In a specific implementation, the first current I can be provided to the current generating module 120 by a bandgap reference circuit. ptat and the second current I rint It should be noted that the specific circuit structure of the bandgap reference circuit should be well known to those skilled in the art and will not be described in detail here.

[0103] The core circuit module 110 in the RC oscillator 110 is described in detail below:

[0104] In an optional embodiment, as Figure 2 As shown, the core circuit module 110 includes a switched capacitor unit 1101, a VAF unit 1102 and an oscillation generation unit 1103, wherein:

[0105] The input end of the switched capacitor unit 1101 serves as the current input end of the core circuit module 110. The first control end of the switched capacitor unit 1101 is electrically connected to the first output end of the oscillation generating unit 1103. The second control end of the switched capacitor unit 1101 is electrically connected to the second output end of the oscillation generating unit 1103.

[0106] The first output terminal of the switched capacitor unit 1101 is electrically connected to the first input terminal of the VAF unit 1102, the second output terminal of the switched capacitor unit 1101 is electrically connected to the first input terminal of the oscillation generating unit 1103, and the third output terminal of the switched capacitor unit 1101 is electrically connected to the second input terminal of the oscillation generating unit 1103;

[0107] The second input terminal of the VAF unit 1102 serves as the reference voltage terminal of the core circuit module 110. The output terminal of the VAF unit 1102 is electrically connected to the third input terminal of the oscillation generation unit 1103. The third output terminal of the oscillation generation unit 1103 is used to output the oscillation clock signal CLK out ;

[0108] The switch capacitor unit 1101 is used to utilize the fifth current I under the control of the switch control signal (CKA, CKB) out , periodically charging the capacitor in the switched capacitor unit 1101 to generate a first voltage V CC ;

[0109] The VAF unit 1102 is used to generate a voltage based on the first reference voltage V ref and the first voltage V CC , generating a second voltage V ref_new ;

[0110] The oscillation generating unit 1103 is configured to generate an oscillation signal according to the second voltage V ref_new , generates switch control signals (CKA, CKB) and oscillation clock signal CLK out .

[0111] Optionally, the switch control signal (CKA, CKB) includes a first switch control sub-signal CKA and a second switch control sub-signal CKB.

[0112] In one or more embodiments, Figure 3 As shown, the switch capacitor unit 1101 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a capacitor C1 and a capacitor C2, wherein:

[0113] The control terminal of the transistor M1 is electrically connected to the control terminal of the transistor M2, serving as a first control terminal of the switch capacitor unit 1101, and is configured to receive the first switch control sub-signal CKA; the first terminal of the transistor M1 is electrically connected to the first terminal of the transistor M3, serving as an input terminal of the switch capacitor unit 1101;

[0114] The second end of the transistor M1 is electrically connected to the first end of the transistor M2, one end of the capacitor C1, the first end of the transistor M5, and the first end of the transistor M6, respectively, and serves as the second output end of the switched capacitor unit 1101, for outputting the voltage VC1 at one end of the capacitor C1;

[0115] The control terminal of the transistor M3 is electrically connected to the control terminal of the transistor M4, serving as a second control terminal of the switched capacitor unit 1101, for receiving the second switch control sub-signal CKB. The second terminal of the transistor M3 is electrically connected to the first terminal of the transistor M4, one terminal of the capacitor C2, the first terminal of the transistor M7, and the first terminal of the transistor M8, respectively, serving as a third output terminal of the switched capacitor unit 1101, for outputting a voltage VC2 at one terminal of the capacitor C2.

[0116] The control end of the transistor M5 and the control end of the transistor M8 both serve as the first control end of the switch capacitor unit 1101, for receiving the first switch control sub-signal CKA; the second end of the transistor M5 is electrically connected to the second end of the transistor M6, the second end of the transistor M7, and the second end of the transistor M8, respectively, as the first output end of the switch capacitor unit 1101, for outputting the first voltage V CC ;

[0117] The control terminal of the transistor M6 and the control terminal of the transistor M7 both serve as the second control terminal of the switch capacitor unit 1101, for receiving the second switch control sub-signal CKB;

[0118] The second end of the transistor M2 , the other end of the capacitor C1 , the second end of the transistor M4 , and the other end of the capacitor C2 are all grounded.

[0119] Optionally, the transistor M1, the transistor M3, the transistor M5 and the transistor M7 are all P-type MOS transistors (Metal-Oxide Semiconductor Field Effect Transistor); the transistor M2, the transistor M4, the transistor M6 and the transistor M8 are all N-type MOS transistors.

[0120] Optionally, at the initial moment, the voltage VC1 = 0, the voltage VC2 = 0; the first switch control sub-signal CKA is a high level (1) signal, and the second switch control sub-signal CKB is a low level (0) signal.

[0121] In a specific implementation, transistors M5 and M6 form transmission gate 1, and transistors M7 and M8 form transmission gate 2. When the first switch control sub-signal CKA is a low-level signal and the second switch control sub-signal CKB is a high-level signal, transmission gate 1 is turned on and transmission gate 2 is turned off. When the first switch control sub-signal CKA is a high-level signal and the second switch control sub-signal CKB is a low-level signal, transmission gate 1 is turned off and transmission gate 2 is turned on.

[0122] Specifically, when the first switch control sub-signal CKA is a high level signal and the second switch control sub-signal CKB is a low level signal, the transistor M3 is turned on, the transistor M1 is turned off, the transmission gate 1 is closed, and the transmission gate 2 is turned on; the fifth current I out It can be sent to the capacitor C2 through the transistor M3 to charge the capacitor C2, and the voltage VC2 at one end of the capacitor C2 is sent to the first output end of the switch capacitor unit 1101 through the transmission gate 2 for output;

[0123] When the first switch control sub-signal CKA is a low level signal and the second switch control sub-signal CKB is a high level signal, the transistor M3 is turned off, the transistor M1 is turned on, the transmission gate 1 is turned on, and the transmission gate 2 is turned off; the fifth current I out The voltage VC1 at one end of the capacitor C1 is sent to the first output end of the switch capacitor unit 1101 through the transmission gate 1 for output.

[0124] In the above manner, under the control of the first switch control sub-signal CKA and the second switch control sub-signal CKB, the capacitors C1 and C2 can be periodically and alternately charged, thereby achieving the generation of an oscillation clock signal with a fixed frequency.

[0125] In one or more embodiments, Figure 4 As shown, the VAF unit 1102 includes an operational amplifier (OperationalAmplifier) ​​OPA1, a resistor R9, and a capacitor C3, wherein:

[0126] One end of the resistor R9 serves as the first input end of the VAF unit 1102 for receiving the first voltage V CC , the other end of the resistor R9 is electrically connected to the inverting input terminal of the operational amplifier OPA1 and one end of the capacitor C3 respectively;

[0127] The positive input terminal of the operational amplifier OPA1 serves as the second input terminal of the VAF unit 1102 for receiving the first reference voltage V ref The output terminal of the operational amplifier OPA1 is electrically connected to the other end of the capacitor C3, serving as the output terminal of the VAF unit 1102 for outputting a second voltage V ref_new .

[0128] In one or more embodiments, Figure 5 As shown, the VAF unit 1102 further includes a resistor R10 and a capacitor C4, wherein:

[0129] One end of the resistor R10 is electrically connected to the output end of the operational amplifier OPA1, and the other end of the resistor R10 is electrically connected to one end of the capacitor C4, serving as the output end of the VAF unit 1102 for outputting the second voltage V ref_new ;

[0130] The other end of capacitor C4 is grounded.

[0131] In a specific implementation, the operational amplifier OPA1, the resistor R9 and the capacitor C3 form an active filter, and the resistor R10 and the capacitor C4 form an RC filter.

[0132] Specifically, through the active filter, the first voltage V CC The DC value of the oscillation waveform will be set to the first reference voltage V ref , that is, within one oscillation cycle, the first voltage V CC The integral over time should be equal to the first reference voltage V ref Therefore, no matter how much the delay of the comparator in the oscillation generating unit 1103 is, the VAF unit 1102 can control the output second voltage V ref_new , to adjust the flip voltage of the comparator in the oscillation generating unit 1103, so as to eliminate the influence caused by the delay of the comparator in the oscillation generating unit 1103.

[0133] The RC filter is used to filter out the second voltage V output of the active filter. ref_new Noise and other interference signals in the .

[0134] In the above method, the second voltage V output by the VAF unit 1102 ref_new , to adjust the flip voltage of the comparator in the oscillation generation unit 1103, thereby eliminating the influence of the delay of the comparator in the oscillation generation unit 1103 and improving the frequency stability of the oscillation clock signal.

[0135] In one or more embodiments, Figure 6 As shown, the oscillation generating unit 1103 includes a transistor M9, a start-up circuit (Start Up) 610, a first comparator COMP1, a second comparator COMP2, a first NAND gate NAND1, a second NAND gate NAND2, a first inverter INV1 and a transmission gate TG1, wherein:

[0136] The first terminal of the transistor M9 is used to receive the chip operating voltage VDD. The control terminal of the transistor M9 is electrically connected to the first terminal of the startup circuit 610. The second terminal of the transistor M9 is electrically connected to the inverting input terminal of the first comparator COMP1 and the inverting input terminal of the second comparator COMP2, respectively, and serves as the third input terminal of the oscillation generation unit 1103 for receiving the second voltage V ref_new ;

[0137] The positive input terminal of the first comparator COMP1 serves as the first input terminal of the oscillation generating unit 1103 and is used to receive the voltage VC1. The output terminal of the first comparator COMP1 is electrically connected to the second terminal of the startup circuit 610 and the first input terminal of the first NAND gate NAND1 respectively.

[0138] The positive input terminal of the second comparator COMP2 serves as the second input terminal of the oscillation generating unit 1103, and is used to receive the voltage VC2. The output terminal of the second comparator COMP2 is electrically connected to the third terminal of the startup circuit 610 and the first input terminal of the second NAND gate NAND2 respectively.

[0139] The second input terminal of the first NAND gate NAND1 is electrically connected to the output terminal of the second NAND gate NAND2, serving as the third output terminal of the oscillation generating unit 1103, for outputting the oscillation clock signal CLK out The third input terminal of the first NAND gate NAND1 and the fourth terminal of the startup circuit 610 are both used to receive the reset signal rst;

[0140] The second input terminal of the second NAND gate NAND2 is electrically connected to the output terminal of the first NAND gate NAND1, the input terminal of the first inverter INV1 and the input terminal of the transmission gate TG1 respectively, and the third input terminal of the second NAND gate NAND2 is grounded;

[0141] The positive control terminal of the transmission gate TG1 is used to receive the chip operating voltage VDD, the negative control terminal of the transmission gate TG1 is grounded, and the output terminal of the transmission gate TG1 serves as the second output terminal of the oscillation generating unit 1103, for outputting the second switch control sub-signal CKB;

[0142] The output terminal of the first inverter INV1 serves as the first output terminal of the oscillation generating unit 1103 , and is used to output the first switch control sub-signal CKA.

[0143] Optionally, the transistor M9 is a P-type MOS transistor.

[0144] In a specific implementation, the working principle of the core circuit module 110 is as follows:

[0145] At the initial moment, voltage VC1 = 0, voltage VC2 = 0; the first switch control sub-signal CKA is a high level (1) signal, and the second switch control sub-signal CKB is a low level (0) signal; at this time, transistor M3 is turned on, transistor M1 is turned off, transmission gate 1 is closed, and transmission gate 2 is turned on;

[0146] Therefore, the capacitor C1 is not charged, and the voltage VC1 at one end of the capacitor C1 is equal to 0. The fifth current I outIt can be sent to capacitor C2 through transistor M3 to charge capacitor C2. The voltage VC2 at one end of capacitor C2 is: Wherein, t1 is used to represent the charging time of capacitor C2;

[0147] The voltage VC2 is sent to the first output terminal of the switch capacitor unit 1101 through the transmission gate 2 for output, that is, the output first voltage V CC = voltage VC2; the first voltage V CC After filtering by the VAF unit 1102, a second voltage V ref_new and the second voltage V ref_new Output to the inverting input terminal of the first comparator COMP1 and the inverting input terminal of the second comparator COMP2;

[0148] At this time, the first comparator COMP1 compares the voltage VC1 with the second voltage V ref_new For comparison, since the voltage VC1=0, the first comparator COMP1 outputs a low level (0) to the first NAND gate NAND1, and the first NAND gate NAND1 outputs a high level (1) to the second NAND gate NAND2, the first inverter INV1 and the transmission gate TG1 respectively, so that the first switch control sub-signal CKA output by the first inverter INV1 becomes a low level (0) signal, and the second switch control sub-signal CKB output by the transmission gate TG1 becomes a high level (1) signal;

[0149] The second comparator COMP2 compares the voltage VC2 with the second voltage V ref_new Comparison, when the voltage VC2> the second voltage V ref_new When , the second comparator COMP2 outputs a high level (1) to the second NAND gate NAND2. At this time, both input terminals of the second NAND gate NAND2 input a high level (1), and the second NAND gate NAND2 outputs a low level (0), and the half cycle of oscillation ends.

[0150] At the next moment, since the first switch control sub-signal CKA becomes a low level (0) signal and the second switch control sub-signal CKB becomes a high level (1) signal, transistor M1 is turned on and transistor M3 is turned off, transmission gate 1 is turned on and transmission gate 2 is turned off;

[0151] At this time, the fifth current I out It can be sent to capacitor C1 through transistor M1 to charge capacitor C1. The voltage VC1 at one end of capacitor C1 is: Wherein, t2 is used to represent the charging time of the capacitor C1; the capacitor C2 is not charged, and the voltage VC2 at one end of the capacitor C2 is 0;

[0152] The voltage VC1 is sent to the first output terminal of the switch capacitor unit 1101 through the transmission gate 1 for output, that is, the output first voltage V CC = voltage VC1; and repeat the above comparison and judgment process to generate an oscillation clock signal with a fixed frequency.

[0153] By the above method, during the repeated oscillation process, the first voltage V CC The average value will approach the first reference voltage V ref The VAF unit 1102 makes the frequency of the oscillation clock signal output by the RC oscillator independent of the delay of the comparator (the first comparator COMP1 and the second comparator COMP2), that is, the temperature coefficient of the oscillation clock signal depends only on the fifth current I out , capacitor C1, capacitor C2 and the first reference voltage V ref .

[0154] In a specific implementation, the startup circuit 610 is used to start the operation of the RC oscillator. It should be noted that the specific circuit structure of the startup circuit (StartUp) 610 should be well known to those skilled in the art and will not be described in detail here.

[0155] In an optional embodiment, as Figure 7 As shown, the oscillation generating unit 1103 further includes a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and a fifth inverter INV5, wherein:

[0156] The second inverter INV2 and the third inverter INV3 are connected in series between the output of the first NAND gate NAND1 and the input of the first inverter INV1; the fourth inverter INV4 and the fifth inverter INV5 are connected in series after the output of the second NAND gate NAND2, and the output of the fifth inverter INV5 is used as the third output of the oscillation generating unit 1103 for outputting the oscillation clock signal CLK out .

[0157] By connecting two stages of inverters in series after the output end of the first NAND gate NAND1 and the output end of the second NAND gate NAND2 respectively, the driving capability of the circuit is increased.

[0158] After introducing the core circuit module 110, the current generating module 120 in the RC oscillator 110 is described in detail below:

[0159] In an optional embodiment, as Figure 8 As shown, the current generating module 120 includes a first current generating unit 1201 and a second current generating unit 1202, wherein:

[0160] The first input terminal of the first current generating unit 1201 is used to input the first current I ptat , the second input end of the first current generating unit 1201 is electrically connected to the first output end of the second current generating unit 1202, and the output end of the first current generating unit 1201 serves as the first output end of the current generating module 120;

[0161] The input terminal of the second current generating unit 1202 is used to input the second current I rint , the second output end of the second current generating unit 1202 serves as the second output end of the current generating module 120, and the third output end of the second current generating unit 1202 serves as the third output end of the current generating module 120;

[0162] The first current generating unit 1201 is used to generate a first current according to the first current I ptat and the second current I rint , generating a fifth current I out ;

[0163] The second current generating unit 1202 is used to generate a second current according to the second current I rint , generating a third current I ref and the fourth current I ref_trim .

[0164] In a specific implementation, the first current generating unit 1201 can be implemented in two ways, as follows:

[0165] Method 1:

[0166] In one or more embodiments, Figure 9 As shown, the first current generating unit 1201 includes a first current mirror CM1, a second current mirror CM2, a third current mirror CM3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, wherein:

[0167] One end of the first resistor R1 is electrically connected to the first end of the first current mirror CM1, serving as the first input end of the first current generating unit 1201, and the other end of the first resistor R1 is electrically connected to the second end of the first current mirror CM1 and the third end of the first current mirror CM1 respectively;

[0168] The fourth end of the first current mirror CM1 is electrically connected to one end of the second resistor R2 and the first end of the second current mirror CM2 respectively, and the fifth end of the first current mirror CM1 and the sixth end of the first current mirror CM1 are both grounded;

[0169] The other end of the second resistor R2 is electrically connected to the second end of the second current mirror CM2 and the third end of the second current mirror CM2 respectively;

[0170] The fourth end of the second current mirror CM2 is electrically connected to one end of the third resistor R3, the first end of the third current mirror CM3 and one end of the fourth resistor R4 respectively;

[0171] The other end of the third resistor R3 is electrically connected to the second end of the third current mirror CM3 and the third end of the third current mirror CM3 respectively;

[0172] The other end of the fourth resistor R4 serves as the second input end of the first current generating unit 1201;

[0173] The fourth terminal of the third current mirror CM3 serves as the output terminal of the first current generating unit 1201;

[0174] The fifth terminal of the second current mirror CM2, the sixth terminal of the second current mirror CM2, the fifth terminal of the third current mirror CM3 and the sixth terminal of the third current mirror CM3 are all used to receive the chip operating voltage VDD;

[0175] The first current mirror CM1 is used to ptat Perform proportional mirroring;

[0176] a second current mirror CM2, configured to mirror the current processed by the first current mirror CM1 based on a first proportional coefficient to obtain a first intermediate current;

[0177] The third current mirror CM3 is used to generate a second intermediate current according to the difference between the current output by the first output terminal of the second current generating unit 1202 and the first intermediate current, and to perform mirror processing on the second intermediate current based on the second proportional coefficient to obtain a fifth current I out ;

[0178] The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

[0179] Optionally, the first current mirror CM1 includes two symmetrically arranged current mirror branches, such as Figure 10 As shown, the left current mirror branch includes transistors M01 and M02, and the right current mirror branch includes transistors M03 and M04, wherein:

[0180] The control terminal of the transistor M01 is electrically connected to the control terminal of the transistor M03 and serves as the first terminal of the first current mirror CM1. The first terminal of the transistor M01 serves as the third terminal of the first current mirror CM1. The second terminal of the transistor M01 is electrically connected to the first terminal of the transistor M02.

[0181] The control terminal of the transistor M02 is electrically connected to the control terminal of the transistor M04 and serves as the second terminal of the first current mirror CM1 . The second terminal of the transistor M02 serves as the fifth terminal of the first current mirror CM1 .

[0182] The first end of the transistor M03 serves as the fourth end of the first current mirror CM1 , and the second end of the transistor M03 is electrically connected to the first end of the transistor M04 ;

[0183] The second terminal of the transistor M04 serves as the sixth terminal of the first current mirror CM1 .

[0184] Among them, the transistor M01 , the transistor M02 , the transistor M03 and the transistor M04 are all N-type MOS transistors.

[0185] In a specific implementation, the number of left-side current mirror branches in the first current mirror CM1 is equal to the number of right-side current mirror branches. Therefore, the first current mirror CM1 is a 1:1 replica current mirror.

[0186] Optionally, the second current mirror CM2 includes two symmetrically arranged current mirror branches, such as Figure 11 As shown, the left current mirror branch includes transistor M05 and transistor M06, and the right current mirror branch includes transistor M07 and transistor M08, wherein:

[0187] The control end of the transistor M05 is electrically connected to the control end of the transistor M07 and serves as the first end of the second current mirror CM2. The first end of the transistor M05 serves as the third end of the second current mirror CM2. The second end of the transistor M05 is electrically connected to the first end of the transistor M06.

[0188] The control terminal of the transistor M06 is electrically connected to the control terminal of the transistor M08 and serves as the second terminal of the second current mirror CM2. The second terminal of the transistor M06 serves as the fifth terminal of the second current mirror CM2.

[0189] The first end of the transistor M07 serves as the fourth end of the second current mirror CM2, and the second end of the transistor M07 is electrically connected to the first end of the transistor M08;

[0190] The second terminal of the transistor M08 serves as the sixth terminal of the second current mirror CM2 .

[0191] Among them, the transistor M05 , the transistor M06 , the transistor M07 and the transistor M08 are all P-type MOS transistors.

[0192] In a specific implementation, the number of left-side current mirror branches in the second current mirror CM2 is 1, and the number of right-side current mirror branches is i, where i is a positive integer greater than 1. Therefore, the second current mirror CM2 can achieve 1:i multiple current mirroring.

[0193] It should be noted that, in the embodiment of the present invention, the number of right-side current mirror branches of the second current mirror CM2 can be flexibly set according to actual business requirements, and the embodiment of the present invention does not impose any limitation on this.

[0194] Since the circuit structure of the third current mirror CM3 is similar to that of the second current mirror CM2, both of which are current mirrors composed of PMOS transistors, the implementation method of the third current mirror CM3 can refer to the above description of the implementation method of the second current mirror CM2 and is not repeated here.

[0195] In a specific implementation, the first intermediate current can be expressed as: adj_temp×n×I ptat Wherein, the first proportional coefficient is adj_temp×n, and adj_temp is adjustable; the current output by the first output terminal of the second current generating unit 1202 can be expressed as: m×I rint ; The second intermediate current can be expressed as: I mix =m×I rint -adj_temp×n×I ptat ;

[0196] Therefore, the fifth current I out It can be expressed as:

[0197] I out =adi_coarse×I mix =adi_coarse×(m×I rint -adj_temp×n×I ptat )

[0198] Wherein, adi_coarse is the second proportional coefficient and is adjustable.

[0199] It should be noted that m and n are fixed ratios designed according to the temperature coefficient of the oscillation clock signal to reduce the difficulty of temperature calibration and save the number of calibration bits. That is, m and n are determined according to actual business needs, and the embodiments of the present invention do not impose any restrictions on this.

[0200] Method 2:

[0201] In an optional embodiment, as Figure 12 As shown, the first current generating unit 1201 includes a third current mirror CM3, a fourth current mirror CM4, a third resistor R3 and a fifth resistor R5, wherein:

[0202] One end of the fifth resistor R5 is electrically connected to the first end of the fourth current mirror CM4, serving as the first input end of the first current generating unit 1201, and the other end of the fifth resistor R5 is electrically connected to the second end and the third end of the fourth current mirror CM4, respectively.

[0203] A fourth terminal of the fourth current mirror CM4 is electrically connected to one terminal of the third resistor R3 and the first terminal of the third current mirror CM3, respectively, and serves as the second input terminal of the first current generating unit 1201. A fifth terminal of the fourth current mirror CM4 and a sixth terminal of the fourth current mirror CM4 are both grounded.

[0204] The other end of the third resistor R3 is electrically connected to the second end of the third current mirror CM3 and the third end of the third current mirror CM3 respectively;

[0205] The fourth terminal of the third current mirror CM3 serves as the output terminal of the first current generating unit 1201 , and the fifth terminal of the third current mirror CM3 and the sixth terminal of the third current mirror CM3 are both used to receive the chip operating voltage VDD;

[0206] The fourth current mirror CM4 is configured to adjust the first current I ptat Performing mirror processing to obtain a first intermediate current;

[0207] The third current mirror CM3 is used to generate a second intermediate current according to the sum of the current output by the first output terminal of the second current generating unit 1202 and the first intermediate current, and to perform mirror processing on the second intermediate current based on the second proportional coefficient to obtain a fifth current I out ;

[0208] The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

[0209] Since the circuit structure of the fourth current mirror CM4 is similar to that of the first current mirror CM1, both of which are current mirrors composed of NMOS transistors, the implementation method of the fourth current mirror CM4 can refer to the above description of the implementation method of the first current mirror CM1 and is not repeated here.

[0210] In a specific implementation, the first intermediate current can be expressed as: adj_temp×n×I ptat Wherein, the first proportional coefficient is adj_temp×n, and adj_temp is adjustable; the current output by the first output terminal of the second current generating unit 1202 can be expressed as: m×I rint ; The second intermediate current can be expressed as: I mix =m×I rint +adj_temp×n×I ptat ;

[0211] Therefore, the fifth current I out It can be expressed as:

[0212] I out =adi_coarse×I mix =adi_coarse×(m×I rint+adj_temp×n×I ptat )

[0213] Wherein, adi_coarse is the second proportional coefficient and is adjustable.

[0214] The RC oscillator, through the first current I ptat and the second current I rint The fifth current I with the second temperature coefficient is generated by superimposing different proportions of out , and using the fifth current I out The capacitors (capacitor C1 and capacitor C2) in the core circuit module 110 are charged so that the fifth current I out The temperature coefficient of the capacitor (capacitor C1, capacitor C2) cancels each other out, thereby achieving the oscillation clock signal CLK out Coarse frequency calibration;

[0215] In addition, the fifth current I is set to generate out The proportional coefficient is an adjustable coefficient, that is, the fifth current I out Adjustable to account for process errors.

[0216] In a specific implementation, the second current generating unit 1202 can be implemented in the following manner:

[0217] In an optional embodiment, as Figure 13 and Figure 14 As shown, the second current generating unit 1202 includes a fifth current mirror CM5, a sixth current mirror CM6, a sixth resistor R6 and a seventh resistor R7, wherein:

[0218] One end of the sixth resistor R6 is electrically connected to the first end of the fifth current mirror CM5, serving as the input end of the second current generating unit 1202, and the other end of the sixth resistor R6 is electrically connected to the second end of the fifth current mirror CM5 and the third end of the fifth current mirror CM5 respectively;

[0219] A fourth terminal of the fifth current mirror CM5 serves as the first output terminal of the second current generating unit 1202. A fifth terminal of the fifth current mirror CM5 is electrically connected to one terminal of the seventh resistor R7 and a first terminal of the sixth current mirror CM6, respectively. A sixth terminal of the fifth current mirror CM5, a seventh terminal of the fifth current mirror CM5, and an eighth terminal of the fifth current mirror CM5 are all grounded.

[0220] The other end of the seventh resistor R7 is electrically connected to the second end of the sixth current mirror CM6 and the third end of the sixth current mirror CM6 respectively;

[0221] The fourth terminal of the sixth current mirror CM6 serves as the second output terminal of the second current generating unit 1202, the fifth terminal of the sixth current mirror CM6 serves as the third output terminal of the second current generating unit 1202, and the sixth terminal of the sixth current mirror CM6, the seventh terminal of the sixth current mirror CM6, and the eighth terminal of the sixth current mirror CM6 are all used to receive the chip operating voltage VDD;

[0222] The fifth current mirror CM5 is used to rint Perform proportional mirror processing, and based on the third proportional coefficient, the second current I rint Perform mirroring to generate a third intermediate current that is sent to the first current generating unit 1201;

[0223] The sixth current mirror CM6 is configured to perform mirror processing on the current obtained by the proportional mirror processing of the fifth current mirror CM5 based on the fourth proportional coefficient to obtain a third current I ref , and based on the fifth proportional coefficient, the current after the proportional mirror processing of the fifth current mirror CM5 is mirrored to obtain the fourth current I ref_trim ;

[0224] The fourth proportional coefficient is greater than the fifth proportional coefficient.

[0225] Since the circuit structure of the fifth current mirror CM5 is similar to that of the first current mirror CM1, both of which are current mirrors composed of NMOS transistors, the implementation of the fifth current mirror CM5 can refer to the above description of the implementation of the first current mirror CM1 and will not be repeated here. In addition, the circuit structure of the sixth current mirror CM6 is similar to that of the second current mirror CM2, both of which are current mirrors composed of PMOS transistors. Therefore, the implementation of the fifth current mirror CM5 can refer to the above description of the implementation of the second current mirror CM2 and will not be repeated here.

[0226] In a specific implementation, the third intermediate current can be expressed as: m×I rint , which is the current output from the first output terminal of the second current generating unit 1202; the third current I ref It can be expressed as: ref =k×I rint , where k is the fourth proportional coefficient; the fourth current I ref_trim It can be expressed as: ref_trim =q×I rint , where q is the fifth proportional coefficient, and k>q, therefore, the third current I ref >The fourth current I ref_trim .

[0227] It should be noted that k and q are fixed ratios designed according to the temperature coefficient of the oscillation clock signal, that is, k and q are determined according to actual business requirements, and the embodiment of the present invention does not impose any limitation on this.

[0228] The above RC oscillator, by the second current I rint Perform mirror processing of different proportions, respectively, the third current I ref and the fourth current I ref_trim , and the third current I ref Greater than the fourth current I ref_trim , the third current I ref and the fourth current I ref_trim After passing through the resistor array module 130, a first reference voltage V having a third temperature coefficient is generated. ref , in order to realize the compensation of the temperature coefficient of the resistors in the resistor array module 130, thereby realizing the compensation of the oscillation clock signal CLK out Fine tuning calibration of the frequency.

[0229] After introducing the core circuit module 110 and the current generating module 120, the resistor array module 130 in the RC oscillator 110 is described in detail below:

[0230] In an optional embodiment, as Figure 15 As shown, the resistor array module 130 includes a single-pole multi-throw switch K1 and a plurality of eighth resistors R8 connected in series, wherein:

[0231] One end of a first eighth resistor among the plurality of eighth resistors R8 serves as the first end of the resistor array module 130, one end of each of the other eighth resistors is electrically connected to the multiple branches of the first end of the single-pole, multi-throw switch K1, and the other end of the last eighth resistor among the plurality of eighth resistors R8 is grounded. The other eighth resistors are resistors other than the first eighth resistor among the plurality of eighth resistors R8.

[0232] The second end of the single-pole multi-throw switch K1 serves as the second end of the resistor array module;

[0233] The single-pole multi-throw switch K1 is used to conduct the path between the second end of the single-pole multi-throw switch K1 and any branch of the first end of the single-pole multi-throw switch K1 to change the fourth current I ref_trim The amount of current flowing through the eighth resistor R8.

[0234] In one or more embodiments, the temperature coefficient of the eighth resistor R8 is the same as that of the reference resistor R BG The temperature coefficient is the same.

[0235] It should be noted that, in the embodiment of the present invention, the number of the eighth resistors R8 in the resistor array module 130 can be flexibly set according to actual business needs, and the embodiment of the present invention does not impose any limitation on this.

[0236] In a specific implementation, the types of the plurality of eighth resistors R8 in the resistor array module 130 may be the same as the reference resistor R BG The type is the same, that is, the temperature coefficient of the eighth resistor R8 is the same as that of the reference resistor R BG The temperature coefficient is the same;

[0237] When the third current I ref and the fourth current I ref_trim When flowing through the resistor array module 130, the third current I ref The current flows through all the eighth resistors in the resistor array module 130 to generate a first reference voltage V ref At the same time, the fourth current I can be controlled by the single-pole multi-throw switch K1 ref_trim The number of eighth resistors flows to achieve the first reference voltage V ref Adjustment of the oscillation clock signal CLK out Fine tuning calibration of the frequency.

[0238] In the above RC oscillator, the temperature coefficient of the eighth resistor R8 is the same as that of the reference resistor R BG The temperature coefficient of the third current I ref and the fourth current I ref_trim The temperature coefficient is determined by the reference voltage V BG The temperature coefficient and reference resistance R BG The temperature coefficient determines that, therefore, when the third current I ref and the fourth current I ref_trim When flowing through the eighth resistor, the third current I ref and the fourth current I ref_trim The first temperature coefficient of the resistor can be offset by the temperature coefficient of the eighth resistor to achieve compensation for the temperature coefficient of the resistor, thereby achieving compensation for the oscillation clock signal CLK out Fine tuning calibration of the frequency.

[0239] Figure 16 The complete circuit structure diagram of the RC oscillator provided by the embodiment of the present invention is as follows: Figure 16 As shown, since the temperature coefficient of the oscillation clock signal depends only on the fifth current I out , capacitor C1, capacitor C2 and the first reference voltage V ref , the fifth current I generated by the above method out , its second temperature coefficient can offset the temperature coefficient of the capacitor (capacitor C1, capacitor C2), eliminating the influence of the capacitor temperature coefficient on the frequency stability of the oscillation clock signal; and through the second current I rint and the first reference voltage V generated by the resistor array module 130 ref, its third temperature coefficient is only related to the reference voltage V BG The temperature coefficient is related to the reference voltage V BG The temperature coefficient can be made low. Therefore, through the above method, the RC oscillator can generate an oscillation clock signal with an adjustable low temperature coefficient, that is, the frequency stability of the oscillation clock signal is improved, thereby improving the performance of the SoC chip.

[0240] Based on the same concept, an embodiment of the present invention further provides a clock generation circuit, including an RC oscillator as provided in any of the above embodiments. The principles of this clock generation circuit are similar to those of the above RC oscillators, so the implementation of this clock generation circuit can refer to the implementation of the above RC oscillators, and the repeated parts will not be repeated here.

[0241] During specific implementation, other essential components of the clock generation circuit should be understood by those skilled in the art and will not be described in detail herein and should not be construed as limiting the present invention.

[0242] Based on the same concept, an embodiment of the present invention further provides an electronic chip, comprising a bandgap reference circuit and a clock generation circuit as provided in any of the above embodiments, wherein:

[0243] The bandgap reference circuit is used to output a first current and a second current.

[0244] Since the principle of solving the problem by the electronic chip is similar to that of the aforementioned clock generation circuit, the implementation of the electronic chip can refer to the implementation of the aforementioned clock generation circuit, and the repeated parts will be omitted.

[0245] During specific implementation, other essential components of the electronic chip are well understood by those skilled in the art and will not be described in detail herein and should not be construed as limiting the present invention.

[0246] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A resistor-capacitor RC oscillator, characterized in that: It includes a core circuit module, a current generation module and a resistor array module, wherein: The current input terminal of the core circuit module is electrically connected to the first output terminal of the current generating module, the reference voltage terminal of the core circuit module is electrically connected to the second output terminal of the current generating module and the first terminal of the resistor array module respectively, and the third output terminal of the current generating module is electrically connected to the second terminal of the resistor array module; The current generating module is configured to generate a third current and a fourth current having a first temperature coefficient, and a fifth current having a second temperature coefficient based on the first current and the second current, wherein the first current is a current having a positive temperature coefficient, and the second current is a current associated with a reference voltage; The resistor array module is configured to receive the third current and the fourth current respectively, so that a first reference voltage having a third temperature coefficient is generated at a first end of the resistor array module; The core circuit module is configured to charge a capacitor in the core circuit module using the fifth current to obtain a first voltage, and generate an oscillation clock signal based on the first voltage and the first reference voltage.

2. The RC oscillator according to claim 1, wherein: The current generating module includes a first current generating unit and a second current generating unit, wherein: The first input end of the first current generating unit is used to input the first current, the second input end of the first current generating unit is electrically connected to the first output end of the second current generating unit, and the output end of the first current generating unit serves as the first output end of the current generating module; The input end of the second current generating unit is used to input the second current, the second output end of the second current generating unit serves as the second output end of the current generating module, and the third output end of the second current generating unit serves as the third output end of the current generating module; The first current generating unit is configured to generate the fifth current according to the first current and the second current; The second current generating unit is configured to generate the third current and the fourth current according to the second current.

3. The RC oscillator according to claim 2, wherein: The first current generating unit includes a first current mirror, a second current mirror, a third current mirror, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein: One end of the first resistor is electrically connected to the first end of the first current mirror and serves as the first input end of the first current generating unit, and the other end of the first resistor is electrically connected to the second end of the first current mirror and the third end of the first current mirror respectively; The fourth end of the first current mirror is electrically connected to one end of the second resistor and the first end of the second current mirror respectively, and the fifth end of the first current mirror and the sixth end of the first current mirror are both grounded; The other end of the second resistor is electrically connected to the second end of the second current mirror and the third end of the second current mirror respectively; The fourth end of the second current mirror is electrically connected to one end of the third resistor, the first end of the third current mirror and one end of the fourth resistor respectively; The other end of the third resistor is electrically connected to the second end of the third current mirror and the third end of the third current mirror respectively; The other end of the fourth resistor serves as the second input end of the first current generating unit; The fourth terminal of the third current mirror serves as the output terminal of the first current generating unit; The fifth terminal of the second current mirror, the sixth terminal of the second current mirror, the fifth terminal of the third current mirror and the sixth terminal of the third current mirror are all used to receive a chip operating voltage; The first current mirror is used to perform proportional mirror processing on the first current; The second current mirror is configured to perform mirror processing on the current processed by the first current mirror based on a first proportional coefficient to obtain a first intermediate current; the third current mirror is configured to generate a second intermediate current according to a difference between the current output by the first output terminal of the second current generating unit and the first intermediate current, and to perform mirroring processing on the second intermediate current based on a second proportional coefficient to obtain the fifth current; The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

4. The RC oscillator according to claim 2, wherein: The first current generating unit includes a third current mirror, a fourth current mirror, a third resistor and a fifth resistor, wherein: One end of the fifth resistor is electrically connected to the first end of the fourth current mirror and serves as the first input end of the first current generating unit, and the other end of the fifth resistor is electrically connected to the second end of the fourth current mirror and the third end of the fourth current mirror respectively; The fourth end of the fourth current mirror is electrically connected to one end of the third resistor and the first end of the third current mirror, respectively, and serves as the second input end of the first current generating unit. The fifth end and the sixth end of the fourth current mirror are both grounded. The other end of the third resistor is electrically connected to the second end of the third current mirror and the third end of the third current mirror respectively; The fourth terminal of the third current mirror serves as the output terminal of the first current generating unit, and the fifth terminal of the third current mirror and the sixth terminal of the third current mirror are both used to receive the chip operating voltage; The fourth current mirror is configured to perform mirror processing on the first current based on a first proportional coefficient to obtain a first intermediate current; the third current mirror is configured to generate a second intermediate current according to the sum of the current output by the first output terminal of the second current generating unit and the first intermediate current, and to perform mirroring processing on the second intermediate current based on a second proportional coefficient to obtain the fifth current; The first proportional coefficient and the second proportional coefficient are both adjustable coefficients.

5. The RC oscillator according to claim 2, wherein: The second current generating unit includes a fifth current mirror, a sixth current mirror, a sixth resistor and a seventh resistor, wherein: One end of the sixth resistor is electrically connected to the first end of the fifth current mirror and serves as the input end of the second current generating unit, and the other end of the sixth resistor is electrically connected to the second end of the fifth current mirror and the third end of the fifth current mirror respectively; The fourth end of the fifth current mirror serves as the first output end of the second current generating unit, the fifth end of the fifth current mirror is electrically connected to one end of the seventh resistor and the first end of the sixth current mirror, respectively, and the sixth end of the fifth current mirror, the seventh end of the fifth current mirror, and the eighth end of the fifth current mirror are all grounded; The other end of the seventh resistor is electrically connected to the second end of the sixth current mirror and the third end of the sixth current mirror respectively; The fourth terminal of the sixth current mirror serves as the second output terminal of the second current generating unit, the fifth terminal of the sixth current mirror serves as the third output terminal of the second current generating unit, and the sixth terminal of the sixth current mirror, the seventh terminal of the sixth current mirror, and the eighth terminal of the sixth current mirror are all used to receive the chip operating voltage; the fifth current mirror is configured to perform proportional mirroring on the second current and to perform mirroring on the second current based on a third proportional coefficient to generate a third intermediate current that is sent to the first current generating unit; the sixth current mirror being configured to mirror the current proportionally mirrored by the fifth current mirror based on a fourth proportional coefficient to obtain the third current, and to mirror the current proportionally mirrored by the fifth current mirror based on a fifth proportional coefficient to obtain the fourth current; The fourth proportional coefficient is greater than the fifth proportional coefficient.

6. The RC oscillator according to claim 1, wherein: The resistor array module includes a single-pole multi-throw switch and a plurality of eighth resistors connected in series, wherein: One end of a first eighth resistor among the plurality of eighth resistors serves as the first end of the resistor array module, one end of each of the other eighth resistors is electrically connected to the corresponding branches of the first end of the single-pole multi-throw switch, and the other end of the last eighth resistor among the plurality of eighth resistors is grounded, wherein the other eighth resistors are resistors among the plurality of eighth resistors other than the first eighth resistor; The second end of the single-pole multi-throw switch serves as the second end of the resistor array module; The SPMT switch is configured to conduct a path between the second end of the SPMT switch and any branch of the first end of the SPMT switch to change the number of eighth resistors through which the fourth current flows.

7. The RC oscillator according to claim 6, wherein: The first current is a PTAT current that is proportional to absolute temperature, and the second current is determined according to a ratio of the reference voltage to a reference resistance; The temperature coefficient of the eighth resistor is the same as the temperature coefficient of the reference resistor.

8. The RC oscillator according to any one of claims 1 to 7, wherein: The core circuit module includes a switched capacitor unit, an average voltage feedback VAF unit and an oscillation generation unit, wherein: The input end of the switch capacitor unit serves as the current input end of the core circuit module, the first control end of the switch capacitor unit is electrically connected to the first output end of the oscillation generating unit, and the second control end of the switch capacitor unit is electrically connected to the second output end of the oscillation generating unit; The first output terminal of the switch capacitor unit is electrically connected to the first input terminal of the VAF unit, the second output terminal of the switch capacitor unit is electrically connected to the first input terminal of the oscillation generating unit, and the third output terminal of the switch capacitor unit is electrically connected to the second input terminal of the oscillation generating unit; The second input terminal of the VAF unit serves as a reference voltage terminal of the core circuit module, the output terminal of the VAF unit is electrically connected to the third input terminal of the oscillation generation unit, and the third output terminal of the oscillation generation unit is used to output the oscillation clock signal; The switched capacitor unit is configured to periodically charge the capacitor in the switched capacitor unit using the fifth current under the control of the switch control signal to generate the first voltage; The VAF unit is configured to generate a second voltage based on the first reference voltage and the first voltage; The oscillation generating unit is configured to generate the switch control signal and the oscillation clock signal according to the second voltage.

9. A clock generation circuit, characterized in that: The invention comprises a resistor-capacitor RC oscillator as claimed in any one of claims 1 to 8.

10. An electronic chip, characterized in that: comprising a bandgap reference circuit and the clock generation circuit as claimed in claim 9, wherein: The bandgap reference circuit is used to output a first current and a second current.

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