Low noise high stability digitally controlled crystal oscillator circuit

Abstract

The application relates to the field of electronic circuit design, and discloses a low-noise high-stability digital controlled crystal oscillator circuit. The circuit adopts two-stage voltage regulators to suppress power supply noise, a coarse-fine capacitor array to adjust phase to realize wide-range high-precision frequency adjustment, and double-loop control through automatic detection feedback and external programming to guarantee the quality of an oscillation signal, and is provided with a special starting circuit to accelerate the starting process of the crystal oscillator. Meanwhile, the core circuit and layout in the loop are optimized, so that noise and distortion are further reduced. The application can effectively solve the problems of narrow frequency adjustment range and large phase noise existing in the prior art, realizes the characteristics of low noise, high stability and fast starting, provides an excellent frequency reference for wireless communication and high-precision timing systems, and has remarkable practical value.

Description

Technical Field

[0001] This application relates to the field of electronic circuit design, and in particular to a circuit implementation technology for a high-performance numerically controlled crystal oscillator. Background Technology

[0002] With the rapid development of wireless communication and high-precision electronic devices, the requirements for clock sources are also increasing. On the one hand, the system needs a clock source with excellent frequency stability and low phase noise to ensure the reliability of the communication link and signal quality. On the other hand, the clock source needs to have a wide-range adjustable frequency output capability to adapt to different operating modes and frequency bands. In addition, characteristics such as fast startup and low power consumption are also crucial for portable electronic devices.

[0003] Traditional crystal oscillator solutions struggle to simultaneously meet the aforementioned technical requirements. For instance, while ordinary crystal oscillators offer good frequency stability, their adjustment range is extremely limited, making it difficult to keep pace with modern communication systems. Although voltage-controlled crystal oscillators (VCXOs) can expand the frequency adjustment range to some extent, their high sensitivity to changes in control voltage and susceptibility to temperature and other factors result in inconsistent adjustment accuracy and stability, and also lead to higher power consumption.

[0004] Digitally controlled crystal oscillators (DCXOs) overcome some of the shortcomings of analog control schemes by introducing digital control mechanisms. However, existing DCXO technology still suffers from problems such as narrow frequency modulation range, high phase noise, and long startup time. This is mainly due to the less-than-ideal circuit design, which employs single-stage power supply regulation, a single LC frequency modulation network, and open-loop control. These factors collectively limit the potential for performance improvement in DCXOs.

[0005] Therefore, there is an urgent need for a new type of numerically controlled crystal oscillator circuit that can significantly reduce phase noise, speed up startup, improve power supply stability, and adapt to a wide range of operating frequencies while ensuring precise frequency adjustment, thereby fully meeting the needs of modern wireless communication equipment and high-performance electronic systems. Summary of the Invention

[0006] The purpose of this application is to provide a low-noise, high-stability numerically controlled crystal oscillator circuit to solve the problems mentioned in the background art.

[0007] This application discloses a low-noise, high-stability numerically controlled crystal oscillator circuit, comprising:

[0008] The controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generation circuit Bias. The input terminal of the first-stage voltage regulator is connected to the reference voltage Vref, the output terminal outputs the pre-stabilized voltage avdd, and the power supply terminal is connected to the power supply voltage Vin. The first input terminal of the current signal generation circuit is connected to the reference voltage, the second input terminal is connected to the digital feedback signal Df_Bias, the output terminal is connected to the crystal oscillator current control terminal XTAL_CF, and the power supply terminal is connected to the pre-stabilized voltage.

[0009] The oscillation module has an input terminal connected to the enable signal En, an output terminal connected to the crystal oscillator input terminal XTAL_I, and a power supply terminal connected to the pre-stabilized voltage.

[0010] The oscillation core module has its input terminal connected to the crystal oscillator input terminal, its output terminal connected to the crystal oscillator output terminal XTAL_O, and its power supply terminal connected to the crystal oscillator current control terminal.

[0011] The output signal driving module includes a second-stage voltage regulator LDO2, a first-stage output driving circuit Buffer1, and a second-stage output driving circuit Buffer2. The input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs the driving voltage avdd_driver, and the power supply terminal is connected to the pre-stabilized voltage. The input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs an intermediate driving signal vo1, the first power supply terminal is connected to the crystal oscillator current control terminal, and the second power supply terminal is connected to the driving voltage. The input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal OSC, and the power supply terminal is connected to the driving voltage.

[0012] The signal detection and feedback module has its input terminal connected to the crystal oscillator input terminal and its output terminal connected to the digital feedback signal.

[0013] In a preferred embodiment, it also includes:

[0014] The first voltage-stabilizing capacitor CL1 has its positive terminal connected to the pre-stabilized voltage and its negative terminal connected to ground;

[0015] The second voltage regulator capacitor CL2 has its positive terminal connected to the crystal oscillator control terminal and its negative terminal connected to ground.

[0016] The third voltage regulator capacitor CL3 has its positive terminal connected to the driving voltage and its negative terminal connected to ground.

[0017] In a preferred embodiment, the current signal generating circuit includes: an operational amplifier amp, a first MOSFET M0, a second MOSFET M1, a third MOSFET M2, and an adjustable resistor R0;

[0018] Wherein: the non-inverting input terminal of the operational amplifier is connected to the reference voltage, the inverting input terminal is connected to the feedback signal vfb_amp, the output terminal is connected to the first control node vg0, and the power supply terminal is connected to the pre-stabilized voltage; the gate of the first MOS transistor is connected to the first control node, the source is connected to the feedback signal, and the drain is connected to the second control node vbp; the source of the second MOS transistor is connected to the pre-stabilized voltage, the gate and drain are connected to the second control node; the source of the third MOS transistor is connected to the pre-stabilized voltage, the gate is connected to the second control node, and the drain is connected to the crystal oscillator current control terminal; the positive terminal of the adjustable resistor is connected to the feedback signal, and the negative terminal is grounded.

[0019] In a preferred embodiment, the oscillation module includes: a capacitor discharge circuit, a ring oscillator, and a three-state gate;

[0020] The input terminal of the capacitor discharge circuit is connected to the enable signal, the first output terminal vct_clk is connected to the input terminal of the ring oscillator, and the second output terminal En_st is connected to the control terminal of the tri-state gate; the output terminal vct_st of the ring oscillator is connected to the input terminal of the tri-state gate; and the output terminal of the tri-state gate is connected to the crystal oscillator input terminal XTAL_I.

[0021] In a preferred embodiment, the oscillation core module includes: a resonator Xtal, a fourth MOSFET M3, a fifth MOSFET M4, and a feedback resistor Rf;

[0022] Wherein: the first end of the resonator is connected to the crystal oscillator input terminal, and the second end is connected to the crystal oscillator output terminal; the gate of the fourth MOS transistor is connected to the crystal oscillator input terminal, the source is connected to the crystal oscillator control terminal, and the drain is connected to the crystal oscillator output terminal; the gate of the fifth MOS transistor is connected to the crystal oscillator input terminal, the source is grounded, and the drain is connected to the crystal oscillator output terminal; one end of the feedback resistor is connected to the crystal oscillator input terminal, and the other end is connected to the crystal oscillator output terminal.

[0023] In a preferred embodiment, it also includes:

[0024] The first load capacitor C1 has its positive or negative terminal connected to the crystal oscillator input terminal, and its negative or positive terminal grounded.

[0025] The second load capacitor C2 has its positive or negative terminal connected to the output terminal of the crystal oscillator, and its negative or positive terminal grounded.

[0026] In a preferred embodiment, both the first load capacitor and the second load capacitor include: a unit coarse adjustment capacitor array CFA and a unit fine adjustment capacitor array FFA;

[0027] Wherein: Port P of the unit coarse adjustment capacitor array is connected to Port P of the unit fine adjustment capacitor array, and Port M of the unit coarse adjustment capacitor array is connected to Port M of the unit fine adjustment capacitor array; the unit coarse adjustment capacitor array includes unit coarse adjustment capacitor units controlled by n-bit binary codes, forming 2^n different capacitor combinations, each unit coarse adjustment capacitor unit includes a unit coarse adjustment capacitor Cc and a unit coarse adjustment MOS switch M_C, the unit coarse adjustment MOS switch being controlled by a corresponding coarse adjustment control signal ct_c; the unit fine adjustment capacitor array includes unit fine adjustment capacitor units controlled by m-bit binary codes, forming 2^m different capacitor combinations, each unit fine adjustment capacitor unit includes a unit fine adjustment capacitor Cf and a unit fine adjustment MOS switch M_F, the unit fine adjustment MOS switch being controlled by a corresponding fine adjustment control signal ct_f; wherein, the capacitance value of the unit fine adjustment capacitor unit is smaller than the capacitance value of the unit coarse adjustment capacitor unit, used to achieve a combination of wide-range coarse adjustment and precise fine adjustment.

[0028] In a preferred embodiment, the fifth MOS transistor includes: a fixed amplifier transistor M4_0, a first controllable amplifier transistor M4_1, a second controllable amplifier transistor M4_2, a first connection switch M_S1, a second connection switch M_S2, a first pull-down switch M_S3, and a second pull-down switch M_S4;

[0029] Wherein: the gate of the fixed amplifier tube is connected to the input terminal of the crystal oscillator, the source is grounded, and the drain is connected to the output terminal of the crystal oscillator; the sources of both the first and second controllable amplifier tubes are grounded, and the drains of both are connected to the output terminal of the crystal oscillator; one end of the first connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

[0030] In a preferred embodiment, the first-stage output drive circuit includes: a sixth MOSFET M5, a seventh MOSFET M6, a driver Buffer1_0, and a level converter lv1;

[0031] Wherein: the gates of the sixth MOS transistor and the seventh MOS transistor are connected to the input terminal of the crystal oscillator, and their drains are connected to form a first intermediate node v1, which is connected to the input terminal of the driver; the source of the sixth MOS transistor is connected to the control terminal of the crystal oscillator and to the positive terminal of the second voltage-stabilizing capacitor; the source of the seventh MOS transistor is grounded; the power supply terminal of the driver is connected to the control terminal of the crystal oscillator, the output terminal is connected to the second intermediate node v2 and to the input terminal of the level converter; the first power supply terminal of the level converter is connected to the control terminal of the crystal oscillator, the second power supply terminal is connected to the driving voltage, and the output terminal outputs the intermediate driving signal.

[0032] This application employs a two-stage voltage regulator architecture. The first-stage voltage regulator LDO1 generates a pre-stabilized voltage avdd, and the second-stage voltage regulator LDO2 further generates a low-noise drive voltage avdd_driver, effectively improving the power supply rejection performance of the output signal. For frequency adjustment, this application uses a combination of a coarse-tuning capacitor array (CFA) and a fine-tuning capacitor array (FFA). The CFA uses an n-bit encoded signal to adjust the load capacitance at 2^n levels, achieving a wide frequency range. The FFA uses an m-bit encoded signal to adjust the load capacitance at 2^m levels, achieving high-precision frequency fine-tuning. The combination of these two approaches balances the breadth and precision of frequency adjustment. Regarding noise reduction, this application addresses both the circuitry and layout. Programmable technology is used to control operational amplifiers to mitigate additional noise introduced by process variations, and the load capacitance layout is isolated to reduce coupling noise from the substrate and surrounding environment. The oscillation signal quality is ensured by both automatic detection feedback and external control. The signal detection and feedback module samples the XTAL_I signal at the crystal oscillator input, processes it internally to obtain the sampled feedback signal D_fb, and superimposes it with the external control signal D_in containing other variables to generate a digital feedback signal Df_Bias to adjust the drive current. The oscillation startup module ensures the oscillator's rapid and stable startup. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal oscillator's resonant frequency to help the crystal oscillator start oscillating. The capacitor discharge circuit periodically shuts off the startup signal, allowing the crystal oscillator to enter a steady state.

[0033] The oscillation module ensures the oscillator starts up quickly and stably. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal's resonant frequency to help the crystal start oscillating. The capacitor discharge circuit periodically shuts off the oscillation signal, allowing the crystal to enter a steady state.

[0034] In summary, this application achieves multiple technical goals such as low noise, high stability, wide adjustment range, and fast startup through an innovative circuit architecture, providing an effective solution for high-performance clock sources.

[0035] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0036] Figure 1 This is a system block diagram of a low-noise, high-stability numerically controlled crystal oscillator circuit according to an embodiment of this application, showing the connection relationship of each functional module.

[0037] Figure 2 This is a schematic diagram of the core module of a low-noise, high-stability numerically controlled crystal oscillator circuit according to an embodiment of this application, specifically showing the internal circuit structure of the controllable reference current module, the oscillation core module, and the output signal drive module.

[0038] Figure 3 This is a circuit diagram of the oscillation module in a low-noise, high-stability numerically controlled crystal oscillator circuit according to an embodiment of this application, showing the connection method of the capacitor discharge circuit, the ring oscillator and the tri-state gate.

[0039] Figure 4 The circuit diagram shows the programmable capacitor array used for the load capacitor in the low-noise, high-stability numerically controlled crystal oscillator circuit according to an embodiment of this application, and the internal structures of the unit coarse-tuning capacitor array and the unit fine-tuning capacitor array are given respectively.

[0040] Figure 5 This is a schematic diagram of the load capacitor layout design in a low-noise, high-stability numerically controlled crystal oscillator circuit according to an embodiment of this application, illustrating noise reduction measures such as multilayer metal interleaving, upper and lower shielding layers, and surround connection.

[0041] Figure 6This is a schematic diagram of the controllable MOS transistor structure of the inverting amplifier in a low-noise, high-stability digitally controlled crystal oscillator circuit according to an embodiment of this application, showing the connection method of the fixed transistor, the controllable transistor, and the control switch.

[0042] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "avdd" and "pre-stabilized voltage avdd" refer to the same technical feature, and "XTAL_CF" and "crystal oscillator control terminal XTAL_CF" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0043] Voltage and signal:

[0044] Pre-stabilized voltage avdd;

[0045] Reference voltage Vref;

[0046] Crystal oscillator control terminal XTAL_CF;

[0047] Power supply voltage Vin;

[0048] Digital feedback signal Df_Bias;

[0049] Intermediate drive signal vo1;

[0050] Oscillator output signal OSC;

[0051] Crystal input terminal XTAL_I;

[0052] Crystal oscillator output terminal XTAL_O;

[0053] Drive voltage avdd_driver;

[0054] First control node vg0;

[0055] Second control node vbp;

[0056] Feedback signal vfb_amp;

[0057] Clock control signal vct_clk;

[0058] Enable control signal En_st;

[0059] Oscillating signal vct_st;

[0060] Reference current I_ref;

[0061] Drive current I_core;

[0062] Enable signal En;

[0063] Coarse adjustment control signal ct_c;

[0064] Fine-tune the control signal ct_f;

[0065] Controllable transistor gate voltages vg4_1 and vg4_2; pull-up control signals sela_0 and sela_1; pull-down control signals selb_0 and selb_1; first intermediate node v1;

[0066] Second intermediate node v2;

[0067] Functional modules and components:

[0068] First-stage voltage regulator LDO1;

[0069] Second-stage voltage regulator LDO2;

[0070] Bias, the current signal generation circuit;

[0071] Operational amplifier (amp);

[0072] Start-up circuit;

[0073] Core oscillation circuit;

[0074] First-stage output drive circuit Buffer1; Second-stage output drive circuit Buffer2; First MOSFET M0;

[0075] Second MOSFET M1;

[0076] Third MOSFET M2;

[0077] Fourth MOSFET M3;

[0078] Fifth MOSFET M4;

[0079] The sixth MOSFET, M5;

[0080] The seventh MOSFET, M6;

[0081] Adjustable resistor R0;

[0082] Feedback resistor Rf;

[0083] Resonator Xtal;

[0084] First voltage regulator capacitor CL1;

[0085] Second voltage regulator capacitor CL2;

[0086] Third voltage regulator capacitor CL3;

[0087] Unit coarse-adjustment capacitor array (CFA);

[0088] Fine-tuning capacitor array (FFA) of individual cells;

[0089] Signal detection feedback module Det&FB;

[0090] Fixed amplifier tube M4_0;

[0091] Controllable amplifier tubes M4_1 and M4_2;

[0092] Connect switches M_S1 and M_S2;

[0093] Pull-down switches M_S3 and M_S4;

[0094] Unit coarse adjustment capacitor Cc;

[0095] Unit coarse adjustment MOS switch M_C;

[0096] The fine-tuning capacitor Cf is used for unit adjustment.

[0097] Fine-tuning of the MOS switch M_F in the unit;

[0098] Driver Buffer1_0;

[0099] Level converter lvl;

[0100] Through-hole CT;

[0101] First connecting hole V1;

[0102] Second connecting hole V2. Detailed Implementation

[0103] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0104] Explanation of some concepts:

[0105] Digitally controlled crystal oscillator (DCXO): A crystal oscillator whose output signal can be directly adjusted via a digital interface. Compared to traditional voltage-controlled crystal oscillators (VCXO), DCXOs have stronger anti-interference capabilities and a more convenient digital control method.

[0106] Pre-stabilized voltage (avdd): The intermediate voltage generated by the first-stage voltage regulator (LDO1). Its function is to provide a preliminary stable operating power supply for each module of the system, reduce power supply noise, and ensure the safe and stable operation of other circuits.

[0107] Drive voltage (avdd_driver): A high-quality drive voltage is output from the second-stage voltage regulator (LDO2). Its function is to provide the output drive circuit with strong drive capability and a low-noise, high-stability power supply, minimizing the impact of power supply noise on the output signal.

[0108] Coarse-tuning Capacitor Array (CFA): A switched capacitor array controlled by an n-bit binary code, providing a large step size for load capacitance changes. Its function is to achieve a wide range of adjustment of the oscillator output frequency.

[0109] Fine-tuning Capacitor Array (FFA): A switched capacitor array controlled by m-bit binary encoding, providing small-step load capacitance changes. Its function is to achieve fine-tuning of the oscillator output frequency based on coarse tuning.

[0110] Crystal oscillator control terminal (XTAL_CF): A key node connecting to the output of the controllable current source. Its voltage level directly determines the excitation strength and oscillation amplitude of the crystal oscillator, making it one of the core control points of the entire oscillator.

[0111] Digital feedback signal (Df_Bias): A digital control signal generated by the signal detection and feedback module from the crystal oscillator signal. Its function is to automatically adjust the crystal oscillator excitation current and stabilize the crystal oscillation amplitude.

[0112] The following is a brief summary of some of the innovative aspects of this application:

[0113] In summary, this application addresses the technical challenge of high stability and wide frequency modulation range of clock sources required for wireless communication and high-precision electronic devices. Through in-depth technical conceptualization, it proposes a novel numerically controlled crystal oscillator circuit architecture. This architecture ingeniously integrates several innovative designs, including a controllable current source, an oscillation circuit, a combined coarse and fine capacitor array, and dual-loop feedback control. Through close collaboration among the various functional modules, it achieves simultaneous optimization and improvement of several key performance indicators.

[0114] Specifically, in terms of noise reduction, this application uniquely employs a cascaded structure of two-stage voltage regulators. The first-stage voltage regulator, LDO1, generates a pre-stabilized voltage avdd, which is then further denoised by the second-stage voltage regulator, LDO2, resulting in a stable, low-noise drive voltage avdd_driver. This two-stage architecture separates the internal power supply and drive voltage, providing sufficient drive capability while reducing noise introduction, significantly outperforming traditional single-stage LDO solutions. Simultaneously, an adjustable-size inverting amplifier is incorporated into the crystal oscillator core circuit. By altering the transistor width, noise introduced by process variations is optimized, achieving a dynamic balance between noise figure, power consumption, and gain. Furthermore, this application utilizes a staggered multilayer metal shielding and isolation design in its layout, effectively reducing the impact of substrate noise on the load capacitance and further improving the signal purity of the oscillator.

[0115] To improve the oscillator startup speed, this application ingeniously designs a novel ring oscillation circuit triggered by capacitor discharge timing. Unlike traditional delay-chain oscillation, this circuit utilizes a ring oscillator to generate an excitation signal close to the crystal oscillator's resonant frequency, and the duration of the excitation is controlled by a timing capacitor discharge circuit, effectively solving the problems of slow and unstable crystal oscillation startup. Simultaneously, the ingenious combination of the startup circuit and a digitally controlled current source ensures a constant and sufficient driving current during startup, improving the startup success rate.

[0116] To address the contradiction between frequency control accuracy and adjustment range, this application creatively proposes a hierarchical frequency modulation method combining a coarse-tuning capacitor array (CFA) and a fine-tuning capacitor array (FFA). The CFA uses binary codes to switch large-step capacitors, responsible for coarse adjustment over a wide frequency range; the FFA uses independent hot-code encoding to switch small-step capacitors, responsible for fine frequency calibration within a narrow range. Through this ingenious encoding method, ultra-wide-range, ultra-high-precision frequency control is achieved using only a few control bits, far superior to traditional single-capacitor array frequency modulation schemes, and also offers the advantages of digitalization and programmability.

[0117] Regarding adaptability, this application also designs a dual-loop feedback control method, including a digital feedback loop and an external programming loop. The digital feedback loop automatically adjusts the output of the digitally controlled current source by sampling and comparing the crystal oscillator signal amplitude with the reference level, achieving constant amplitude control. The external programming loop allows users or other control circuits to directly rewrite the control word of the digitally controlled current source, achieving a higher level of system optimization. The synergy of the two feedback loops enhances the oscillator's adaptability to variations in process, temperature, and voltage, ensuring the stability of the oscillation signal in complex application environments.

[0118] In summary, the numerically controlled crystal oscillator circuit of this application has been meticulously designed and optimized at all levels, from the system and module to the layout. It employs several unique circuit innovations, achieving a perfect integration of key performance characteristics such as low noise, high stability, wide frequency adjustment, fast startup, and adaptive compensation, resulting in significant technical benefits. This deeply customized design is not a simple combination of known technologies, but rather a highly targeted and specialized design that cleverly utilizes the inherent relationships between various functional modules, demonstrating considerable creativity and greatly improving the overall performance of the numerically controlled oscillator. It provides an excellent frequency reference solution for modern high-end wireless communication and precision electronic equipment.

[0119] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0120] The first embodiment of this application relates to a low-noise, high-stability numerically controlled crystal oscillator circuit, such as... Figure 1 As shown, it includes:

[0121] The controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generation circuit Bias. The input terminal of the first-stage voltage regulator is connected to the reference voltage Vref, the output terminal outputs the pre-stabilized voltage avdd, and the power supply terminal is connected to the power supply voltage Vin. The first input terminal of the current signal generation circuit is connected to the reference voltage, the second input terminal is connected to the digital feedback signal Df_Bias, the output terminal is connected to the crystal oscillator current control terminal XTAL_CF, and the power supply terminal is connected to the pre-stabilized voltage.

[0122] The oscillation module has an input terminal connected to the enable signal En, an output terminal connected to the crystal oscillator input terminal XTAL_I, and a power supply terminal connected to the pre-stabilized voltage.

[0123] The oscillation core module has its input terminal connected to the crystal oscillator input terminal, its output terminal connected to the crystal oscillator output terminal XTAL_O, and its power supply terminal connected to the crystal oscillator current control terminal.

[0124] The output signal driving module includes a second-stage voltage regulator LDO2, a first-stage output driving circuit Buffer1, and a second-stage output driving circuit Buffer2. The input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs the driving voltage avdd_driver, and the power supply terminal is connected to the pre-stabilized voltage. The input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs an intermediate driving signal vo1, the first power supply terminal is connected to the crystal oscillator current control terminal, and the second power supply terminal is connected to the driving voltage. The input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal OSC, and the power supply terminal is connected to the driving voltage.

[0125] The signal detection and feedback module has its input terminal connected to the crystal oscillator input terminal and its output terminal connected to the digital feedback signal.

[0126] Optional, also includes:

[0127] The first voltage-stabilizing capacitor CL1 has its positive terminal connected to the pre-stabilized voltage and its negative terminal connected to ground;

[0128] The second voltage regulator capacitor CL2 has its positive terminal connected to the crystal oscillator control terminal and its negative terminal connected to ground.

[0129] The third voltage regulator capacitor CL3 has its positive terminal connected to the driving voltage and its negative terminal connected to ground.

[0130] Optionally, the current signal generation circuit includes: an operational amplifier amp, a first MOSFET M0, a second MOSFET M1, a third MOSFET M2, and an adjustable resistor R0;

[0131] Wherein: the non-inverting input terminal of the operational amplifier is connected to the reference voltage, the inverting input terminal is connected to the feedback signal vfb_amp, the output terminal is connected to the first control node vg0, and the power supply terminal is connected to the pre-stabilized voltage; the gate of the first MOS transistor is connected to the first control node, the source is connected to the feedback signal, and the drain is connected to the second control node vbp; the source of the second MOS transistor is connected to the pre-stabilized voltage, the gate and drain are connected to the second control node; the source of the third MOS transistor is connected to the pre-stabilized voltage, the gate is connected to the second control node, and the drain is connected to the crystal oscillator current control terminal; the positive terminal of the adjustable resistor is connected to the feedback signal, and the negative terminal is grounded.

[0132] Optionally, the oscillation module includes: a capacitor discharge circuit, a ring oscillator, and a three-state gate;

[0133] The input terminal of the capacitor discharge circuit is connected to the enable signal, the first output terminal vct_clk is connected to the input terminal of the ring oscillator, and the second output terminal En_st is connected to the control terminal of the tri-state gate; the output terminal vct_st of the ring oscillator is connected to the input terminal of the tri-state gate; and the output terminal of the tri-state gate is connected to the crystal oscillator input terminal XTAL_I.

[0134] Optionally, the oscillation core module includes: a resonator Xtal, a fourth MOSFET M3, a fifth MOSFET M4, and a feedback resistor Rf;

[0135] Wherein: the first end of the resonator is connected to the crystal oscillator input terminal, and the second end is connected to the crystal oscillator output terminal; the gate of the fourth MOS transistor is connected to the crystal oscillator input terminal, the source is connected to the crystal oscillator control terminal, and the drain is connected to the crystal oscillator output terminal; the gate of the fifth MOS transistor is connected to the crystal oscillator input terminal, the source is grounded, and the drain is connected to the crystal oscillator output terminal; one end of the feedback resistor is connected to the crystal oscillator input terminal, and the other end is connected to the crystal oscillator output terminal.

[0136] Optional, also includes:

[0137] The first load capacitor C1 has its positive or negative terminal connected to the crystal oscillator input terminal, and its negative or positive terminal grounded.

[0138] The second load capacitor C2 has its positive or negative terminal connected to the output terminal of the crystal oscillator, and its negative or positive terminal grounded.

[0139] Optionally, both the first load capacitor and the second load capacitor include: a unit coarse adjustment capacitor array CFA and a unit fine adjustment capacitor array FFA;

[0140] Wherein: Port P of the unit coarse adjustment capacitor array is connected to Port P of the unit fine adjustment capacitor array, and Port M of the unit coarse adjustment capacitor array is connected to Port M of the unit fine adjustment capacitor array; the unit coarse adjustment capacitor array includes unit coarse adjustment capacitor units controlled by n-bit binary codes, forming 2^n different capacitor combinations, each unit coarse adjustment capacitor unit includes a unit coarse adjustment capacitor Cc and a unit coarse adjustment MOS switch M_C, the unit coarse adjustment MOS switch being controlled by a corresponding coarse adjustment control signal ct_c; the unit fine adjustment capacitor array includes unit fine adjustment capacitor units controlled by m-bit binary codes, forming 2^m different capacitor combinations, each unit fine adjustment capacitor unit includes a unit fine adjustment capacitor Cf and a unit fine adjustment MOS switch M_F, the unit fine adjustment MOS switch being controlled by a corresponding fine adjustment control signal ct_f; wherein, the capacitance value of the unit fine adjustment capacitor unit is smaller than the capacitance value of the unit coarse adjustment capacitor unit, used to achieve a combination of wide-range coarse adjustment and precise fine adjustment.

[0141] Optionally, the fifth MOS transistor includes: a fixed amplifier transistor M4_0, a first controllable amplifier transistor M4_1, a second controllable amplifier transistor M4_2, a first connection switch M_S1, a second connection switch M_S2, a first pull-down switch M_S3, and a second pull-down switch M_S4;

[0142] Wherein: the gate of the fixed amplifier tube is connected to the input terminal of the crystal oscillator, the source is grounded, and the drain is connected to the output terminal of the crystal oscillator; the sources of both the first and second controllable amplifier tubes are grounded, and the drains of both are connected to the output terminal of the crystal oscillator; one end of the first connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

[0143] Optionally, the first-stage output drive circuit includes: a sixth MOSFET M5, a seventh MOSFET M6, a driver Buffer1_0, and a level converter lvl;

[0144] Wherein: the gates of the sixth MOS transistor and the seventh MOS transistor are connected to the input terminal of the crystal oscillator, and their drains are connected to form a first intermediate node v1, which is connected to the input terminal of the driver; the source of the sixth MOS transistor is connected to the control terminal of the crystal oscillator and to the positive terminal of the second voltage-stabilizing capacitor; the source of the seventh MOS transistor is grounded; the power supply terminal of the driver is connected to the control terminal of the crystal oscillator, the output terminal is connected to the second intermediate node v2 and to the input terminal of the level converter; the first power supply terminal of the level converter is connected to the control terminal of the crystal oscillator, the second power supply terminal is connected to the driving voltage, and the output terminal outputs the intermediate driving signal.

[0145] More specifically, such as Figure 1 As shown, this embodiment mainly consists of five functional modules and three voltage-stabilizing capacitors, realizing a high-quality digitally controlled crystal oscillation function.

[0146] The controllable reference current module is located in Figure 1 The upper left section includes the first-stage voltage regulator LDO1 and the current signal generation circuit Bias. The first-stage voltage regulator LDO1 uses the reference voltage Vref as a reference input to convert the power supply voltage Vin into a pre-stabilized voltage avdd; the current signal generation circuit Bias receives the reference voltage Vref and the digital feedback signal Df_Bias, uses the pre-stabilized voltage avdd as a power supply, and outputs a control current to the crystal oscillator control terminal XTAL_CF.

[0147] The oscillation circuit module is located in Figure 1 The lower left section is labeled "Start". This module receives the enable signal En as an input trigger, uses the pre-stabilized voltage avdd as a power supply, and outputs to the crystal oscillator input terminal XTAL_I. The main function of the oscillation module is to provide a temporary oscillation signal during the initial startup phase of the system, helping the crystal oscillator quickly enter a stable oscillation state.

[0148] The oscillation core module is located at Figure 1 The central section, consisting of the resonator Xtal and its related circuitry, is labeled "Core". This module's input is connected to the crystal oscillator input terminal XTAL_I, its output terminal to the crystal oscillator output terminal XTAL_O, and its power supply terminal to the crystal oscillator control terminal XTAL_CF. This module is the core of the entire oscillator, responsible for generating a stable oscillation signal.

[0149] The output signal drive module is located in Figure 1 The upper right section consists of a second-stage voltage regulator LDO2, a first-stage output driver circuit Buffer1, and a second-stage output driver circuit Buffer2. The second-stage voltage regulator LDO2 further adjusts the pre-stabilized voltage avdd to a more stable driving voltage avdd_driver. The first-stage output driver circuit Buffer1 uses the crystal oscillator control terminal XTAL_CF and the driving voltage avdd_driver as power supplies, converting the signal at the crystal oscillator output terminal XTAL_O into an intermediate driving signal vo1. The second-stage output driver circuit Buffer2 uses the driving voltage avdd_driver as power supplies, further amplifying the intermediate driving signal vo1 into the final oscillator output signal OSC.

[0150] The signal detection feedback module is located in Figure 1 The lower middle section is labeled "Det&FB". This module monitors the signal at the crystal oscillator input terminal XTAL_I, generates a digital feedback signal Df_Bias, and outputs it to the second input terminal of the current signal generation circuit Bias, forming a closed-loop control.

[0151] The system also includes three voltage regulator capacitors and two load capacitors: the first voltage regulator capacitor CL1 is connected between the pre-stabilized voltage avdd and ground; the second voltage regulator capacitor CL2 is connected between the crystal oscillator control terminal XTAL_CF and ground; the third voltage regulator capacitor CL3 is connected between the drive voltage avdd_driver and ground; the first load capacitor C1 is connected between the crystal oscillator input terminal XTAL_I and ground; and the second load capacitor C2 is connected between the crystal oscillator output terminal XTAL_O and ground.

[0152] This embodiment uses a controllable reference current source to provide the current required by the crystal oscillator, and introduces auxiliary circuits such as oscillation start-up and detection feedback. Through modular design, it effectively solves the technical problems of narrow frequency modulation range and high phase noise of existing DCXO solutions, and achieves the performance characteristics of fast start-up, low noise and high stability, which is particularly suitable for application in wireless communication and high-precision electronic equipment.

[0153] like Figure 2 As shown, this embodiment provides the main circuit details of the numerically controlled crystal oscillator circuit system, including the detailed structure of the reference current generation circuit, the oscillation core circuit, and the output drive circuit.

[0154] The reference current generation circuit is located in Figure 2 The upper left section includes a first-stage voltage regulator LDO1 and a current signal generation circuit Bias composed of multiple components. The first-stage voltage regulator LDO1 converts the reference voltage Vref into a pre-stabilized voltage avdd. In the current signal generation circuit, the non-inverting input of the operational amplifier amp is connected to the reference voltage Vref, the inverting input is connected to the feedback signal vfb_amp, and the output is connected to the first control node vg0. The gate of the first MOSFET M0 is connected to the first control node vg0, the source is connected to the feedback signal vfb_amp, and the drain is connected to the second control node vbp. The second MOSFET M1 and the third MOSFET M2 form a current mirror, amplifying the reference current and outputting it to the crystal oscillator control terminal XTAL_CF. The source of the second MOSFET M1 is connected to the pre-stabilized voltage avdd, and its gate and drain are shorted and connected to the second control node vbp. The source of the third MOSFET M2 is connected to the pre-stabilized voltage avdd, its gate is connected to the second control node vbp, and its drain is connected to the crystal oscillator control terminal XTAL_CF. One end of the adjustable resistor R0 is connected to the feedback signal vfb_amp, and the other end is grounded. Through the operation amplifier amp, the feedback signal vfb_amp is locked to the reference voltage Vref value, generating a reference current across the adjustable resistor R0.

[0155] The core circuit of the oscillation is located at Figure 2The lower middle section includes a resonator Xtal, a fourth MOSFET M3, a fifth MOSFET M4, and a feedback resistor Rf. The resonator Xtal is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O. The gate of the fourth MOSFET M3 is connected to the crystal oscillator input terminal XTAL_I, its source is connected to the crystal oscillator control terminal XTAL_CF, and its drain is connected to the crystal oscillator output terminal XTAL_O. The gate of the fifth MOSFET M4 is connected to the crystal oscillator input terminal XTAL_I, its source is grounded, and its drain is connected to the crystal oscillator output terminal XTAL_O. The fourth MOSFET M3 and the fifth MOSFET M4 form an inverting amplifier, and the feedback resistor Rf is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O. The figure also shows a first load capacitor C1 and a second load capacitor C2, which are connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O and ground, respectively, to adjust the frequency of the crystal oscillator.

[0156] The output drive circuit is located at Figure 2 On the right side, there is a second-stage voltage regulator LDO2, a first-stage output driver circuit, and a second-stage output driver circuit. The second-stage voltage regulator LDO2 further adjusts the pre-stabilized voltage avdd to a low-noise, stable drive voltage avdd_driver. The first-stage output driver circuit includes a sixth MOSFET M5, a seventh MOSFET M6, a first-stage driver Buffer1_0, and a level shifter lvl. The gate of the sixth MOSFET M5 is connected to the crystal oscillator input terminal XTAL_I, the source is connected to the crystal oscillator control terminal XTAL_CF and the second voltage regulator capacitor CL2, and the drain is connected to the first intermediate node v1. The gate of the seventh MOSFET M6 is connected to the crystal oscillator input terminal XTAL_I, the source is grounded, and the drain is connected to the first intermediate node v1. The first intermediate node v1 is connected to the input terminal of the first-stage driver Buffer1_0, and its output terminal is connected to the second intermediate node v2. The input terminal of the level shifter lvl is connected to the second intermediate node v2, the first power supply terminal is connected to the crystal oscillator control terminal XTAL_CF, the second power supply terminal is connected to the drive voltage avdd_driver, and the output terminal outputs the intermediate drive signal vo1. The input of the second-stage output driver circuit Buffer2 is connected to the intermediate drive signal vo1, the power supply is connected to the drive voltage avdd_driver, and the output is the final oscillator output signal OSC.

[0157] exist Figure 2The circuit also includes a third voltage regulator capacitor, CL3, with one end connected to the driving voltage avdd_driver and the other end grounded. It primarily functions as a filter and voltage regulator, further filtering out high-frequency noise in the driving voltage. A second voltage regulator capacitor, CL2, has one end connected to the crystal oscillator control terminal avdd_xtal and the other end grounded, also primarily serving a voltage regulator function. Optionally, the actual circuit may also include a first voltage regulator capacitor, CL1, connected to the pre-stabilized voltage avdd terminal. Similar to CL3, it primarily functions as a filter and voltage regulator. The load capacitors on both sides of the resonator are used to adjust the crystal oscillation frequency. This embodiment employs a two-stage voltage regulation and two-stage output drive architecture, and by setting voltage regulator and filter capacitors at key nodes, it effectively achieves power supply noise suppression and precise frequency control, which is crucial for achieving low-noise, high-precision oscillation.

[0158] like Figure 3 As shown in the figure, this embodiment provides a detailed structure of the oscillation circuit module, which is mainly used to provide an initial oscillation signal during the system startup phase to accelerate the crystal oscillator startup process. The oscillation circuit consists of three main parts: a capacitor discharge circuit, a ring oscillator, and a tri-state gate.

[0159] The capacitor discharge circuit receives an enable signal En as input. When the enable signal En changes from low to high, the capacitor discharge circuit begins the discharge process, generating two output signals: a discharge signal vct_clk and a control signal En_st. The discharge signal vct_clk exhibits a waveform that gradually decreases from a high level, while the control signal En_st is initially high.

[0160] The ring oscillator consists of multiple inverters connected in series. Its input is connected to the discharge signal vct_clk, and its output generates an oscillation signal vct_st. When the discharge signal vct_clk is within an appropriate level range, the ring oscillator is activated and generates an oscillation signal with a frequency close to the parallel resonant frequency of the crystal.

[0161] The input of the tri-state gate is connected to the oscillation signal vct_st, the control terminal is connected to the control signal En_st, and the output terminal is connected to the crystal oscillator input terminal XTAL_I. When the control signal En_st is high, the tri-state gate is in the on state, allowing the oscillation signal vct_st to be transmitted to the crystal oscillator input terminal, providing initial oscillation excitation for the crystal oscillator.

[0162] The entire oscillation circuit operates as follows: When the system is powered on and the enable signal En goes high, the capacitor discharge circuit begins to work. The control signal En_st is set high to turn on the tri-state gate, and the discharge signal vct_clk gradually decreases from high. During this process, the oscillation signal vct_st generated by the ring oscillator is transmitted to the crystal oscillator input through the tri-state gate, helping the crystal oscillator to quickly establish oscillation. When the capacitor discharges to a certain extent and the discharge signal vct_clk drops below a certain threshold, the ring oscillator stops working, and the control signal En_st is set low to turn off the tri-state gate. At this point, the crystal oscillator has established self-sustaining oscillation and no longer requires external excitation. The discharge time of the capacitor discharge circuit is designed to be longer than the time required for the crystal oscillator to start up, ensuring that the crystal oscillator can start stably.

[0163] This oscillation circuit design effectively shortens the crystal oscillator's startup time, which is the key to achieving the fast startup characteristic in this embodiment.

[0164] like Figure 4 As shown, this embodiment provides a detailed structural design of the adjustable load capacitor, which is a key part of achieving precise frequency adjustment of the numerically controlled crystal oscillator. Figure 4 The specific implementation of the coarse-tuning capacitor array CFA and the fine-tuning capacitor array FFA inside the load capacitors C1 / C2 is shown.

[0165] The load capacitors C1 / C2 have two main ports, P and M. The unit coarse-tuning capacitor array CFA and the unit fine-tuning capacitor array FFA are connected at port P and port M, respectively. Together, they form a variable capacitor network, which achieves frequency adjustment through binary encoding control.

[0166] The coarse-adjustment capacitor array (CFA) is controlled by an n-bit binary code, providing 2^n different capacitor combinations. The CFA contains n coarse-adjustment unit capacitors, labeled Cc1, Cc2, ..., Ccn. One end of each coarse-adjustment unit capacitor is connected to port P, and the other end is connected to port M via a corresponding unit coarse-adjustment MOS switch M_C1, M_C2...M_Cn. These MOS switches are controlled by coarse-adjustment control signals ct_c0, ct_c1...ct_cn-1. When the control signal is high, the corresponding MOS switch is turned on, and the corresponding capacitor is connected to the total capacitor; when the control signal is low, the MOS switch is turned off, and the corresponding capacitor is disconnected.

[0167] The structure of the fine-tuning capacitor array (FFA) is similar to that of the coarse-tuning capacitor array, but it is controlled by m-bit binary encoding to achieve 2^m levels of load capacitance adjustment. The FFA contains m fine-tuning unit capacitors, labeled Cf1, Cf2, ..., Cfm. One end of each fine-tuning unit capacitor is connected to port P, and the other end is connected to port M through the corresponding fine-tuning MOS switches M_F1, M_F2...M_Fm. These MOS switches are controlled by fine-tuning control signals ct_f0, ct_f1...ct_fm-1, and operate on the same principle as the coarse-tuning section.

[0168] It should be noted that the capacitance value of the fine-tuning unit capacitor is smaller than that of the coarse-tuning unit capacitor. The coarse-tuning capacitor array is responsible for a wide range of frequency adjustment, while the fine-tuning capacitor array is responsible for a small range of precise frequency adjustment. This combination of coarse and fine-tuning design allows the oscillator frequency to be adjusted over a wide range while achieving high adjustment accuracy.

[0169] By controlling these two sets of capacitor arrays with external digital encoding, this embodiment achieves high-precision, wide-range digital control of the crystal oscillator frequency.

[0170] like Figure 5 As shown, this embodiment provides a layout structure design for the load capacitor, which is mainly used to reduce the impact of substrate and surrounding environmental noise on the crystal oscillator signal quality.

[0171] The layout structure comprises multiple layers from bottom to top. The bottom layer is a substrate isolation layer, used to isolate the capacitor structure from the chip substrate and reduce substrate noise coupling. Above the substrate isolation layer are, in sequence, a first metal layer M1, a second metal layer M2, and a third metal layer M3. These three metal layers are arranged alternately to form a metal-oxide-metal (MOM) capacitor structure. In some embodiments, a top layer metal may be added as a shielding layer.

[0172] The metal layers are connected by interconnecting vias: via CT connects the substrate isolation layer to the first metal layer M1, via V1 connects the first metal layer M1 to the second metal layer M2, and via V2 connects the second metal layer M2 to the third metal layer M3. These interconnecting vias not only provide electrical connections but also form a surrounding structure at the edge of the layout, enhancing the isolation from external noise.

[0173] The bottom of the layout can be shielded in two ways: one is to set a polysilicon layer, and the other is to use a P-type substrate isolation layer. A metal layer can be added to the top as a shield. The upper and lower shielding layers, together with the surrounding CT, M1, V1, M2, V2, and M3, form a complete electromagnetic shielding structure, effectively preventing external noise interference.

[0174] The key to this layout design lies in the use of multi-layer metal and vias CT, M1, V1, M2, V2, and M3 stacked in an alternating manner, combined with upper and lower shielding layers and an edge-surrounding connection structure to form a three-dimensional shield, which significantly reduces the impact of substrate noise and external interference on capacitance values, thereby improving the quality and frequency stability of the crystal oscillator signal.

[0175] This noise-resistant layout structure is an important foundation for achieving a high-performance, low-noise CNC crystal oscillator in this embodiment.

[0176] like Figure 6 As shown, this embodiment provides a controllable structure design for the fifth MOS transistor M4 in the oscillation core circuit to optimize circuit noise performance. This structure allows for dynamic adjustment of the effective size of the amplifier via digital signals to accommodate additional noise introduced by process variations.

[0177] The entire structure consists of a fixed amplifier transistor M4_0, two controllable amplifier transistors M4_1 and M4_2, and four control switches S1, S2, S3, and S4. The gate of the fixed amplifier transistor M4_0 is connected to the crystal oscillator input terminal XTAL_I, its source is grounded, and its drain is connected to the crystal oscillator output terminal XTAL_O. The sources of the controllable amplifier transistors M4_1 and M4_2 are both grounded, their drains are both connected to the crystal oscillator output terminal XTAL_O, and their gates are connected to their respective control nodes vg4_1 and vg4_2.

[0178] Of the four control switches, S1 and S2 are connection switches, and S3 and S4 are pull-down switches. S1 is connected between the crystal oscillator input XTAL_I and vg4_1, and is controlled by sela_0. S2 is connected between the crystal oscillator input XTAL_I and vg4_2, and is controlled by sela_1. S3 is connected between vg4_1 and ground, and is controlled by selb_0. S4 is connected between vg4_2 and ground, and is controlled by selb_1.

[0179] The working principle of this structure is as follows:

[0180] By controlling the opening and closing states of switches S1 to S4, controllable amplifier tubes M4_1 and M4_2 can be selectively enabled or disabled, allowing them to operate in parallel with the fixed amplifier tube M4_0 or independently, thus flexibly adjusting the effective size of the amplifier. The control signals sela_0 and selb_0 are complementary, and sela_1 and selb_1 are complementary, ensuring that each pair of switches is in opposite states and preventing invalid states.

[0181] This controllable-size MOS transistor array design is an important technical means to optimize noise performance in this embodiment. It can dynamically adjust the noise introduced by process deviations and achieve a balance between noise figure, power consumption and gain.

[0182] Working principle:

[0183] The working principle of the low-noise, high-stability numerically controlled crystal oscillator circuit of this application is as follows.

[0184] After the system is powered on, the power supply voltage Vin passes through the first-stage voltage regulator LDO1. Figure 1 The voltage is converted to a pre-stabilized voltage avdd, providing operating power to the oscillation module, current signal generation circuit Bias, etc. The oscillation module starts operating when the enable signal En changes from low to high. Figure 3 As shown, the capacitor discharge circuit in the oscillation module begins to discharge, and the discharge signal vct_clk gradually decreases from a high level. Simultaneously, the control signal En_st is set to a high level, turning on the tri-state gate. Under the control of the discharge signal vct_clk, the ring oscillator generates an oscillation signal vct_st close to the crystal resonant frequency, which is fed into the crystal oscillator input terminal XTAL_I through the tri-state gate, helping the crystal oscillator to start oscillating quickly.

[0185] As the capacitor discharges, when the discharge signal vct_clk drops below the threshold voltage, the ring oscillator stops working, the control signal En_st goes low, and the tri-state gate is turned off. At this point, the crystal oscillator has established a stable self-sustaining oscillation with the help of the oscillation module, and the oscillation signal is presented through the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O.

[0186] like Figure 2 As shown, in the current signal generation circuit Bias, the operational amplifier amp locks the feedback signal vfb_amp at a level equal to the reference voltage Vref, causing a constant current to be generated across the adjustable resistor R0. The gate of the first MOSFET M0 is connected to the op-amp output vg0, the source is connected to the feedback signal vfb_amp, and the drain is connected to the second control node vbp. The generated current is amplified by a current mirror composed of the second MOSFET M1 and the third MOSFET M2, and then flows from the drain of the third MOSFET M2 into the crystal oscillator control terminal XTAL_CF, serving as the drive current to provide energy for the crystal oscillation. The digital feedback signal Df_Bias can adjust the resistance value of the adjustable resistor R0, thereby adjusting the magnitude of the drive current.

[0187] The crystal oscillator oscillates continuously under the influence of the driving current. For example... Figure 2 As shown, in the core oscillation circuit, the fourth MOSFET M3 and the fifth MOSFET M4 constitute an inverting amplifier, with their gates connected to the crystal oscillator input terminal XTAL_I. This provides negative resistance to the crystal to offset internal losses and maintain oscillation. The feedback resistor Rf is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O, providing the necessary bias to the inverting amplifier and ensuring that the oscillation conditions are met. The first load capacitor C1 and the second load capacitor C2 are connected in parallel across the crystal oscillator, and the oscillation frequency can be adjusted by changing their values. Figure 4The structure of the unit coarse-tuning capacitor array (CFA) and the unit fine-tuning capacitor array (FFA) used for the load capacitor is demonstrated. Through n-bit coarse-tuning binary encoding and m-bit fine-tuning binary encoding, the load capacitance value can be precisely adjusted over a wide range, achieving high-precision control of the oscillation frequency. The capacitance value of the unit fine-tuning capacitor is much smaller than that of the unit coarse-tuning capacitor, which enables the system to achieve both a wide range of frequency adjustment and extremely high frequency resolution.

[0188] The oscillation signal is transmitted from the crystal oscillator output terminal XTAL_O to the driver module. For example... Figure 2 As shown, the second-stage voltage regulator LDO2 further adjusts the pre-stabilized voltage avdd to a low-noise, stable drive voltage avdd_driver. In the first-stage output drive circuit Buffer1, the sixth MOSFET M5 and the seventh MOSFET M6 have the same dimensions as M3 and M4 in the oscillation core. As a buffer stage, they can replicate the oscillation waveform of the crystal oscillator without affecting its normal oscillation. Subsequently, the first-stage driver Buffer1_0 and the level converter lvl convert the buffered signal into a suitable amplitude and DC level, forming the intermediate drive signal vo1. The second-stage output drive circuit Buffer2 further enhances the driving capability of the intermediate drive signal, ultimately providing a high-quality clock signal from the output port OSC.

[0189] The signal detection and feedback module monitors the peak-to-peak value of the signal at the crystal oscillator input terminal XTAL_I in real time, and generates a digital feedback signal Df_Bias to control the current signal generation circuit Bias, thereby achieving automatic adjustment and stabilization of the oscillation amplitude.

[0190] Various noise reduction and stabilization measures are adopted in each module of this application, such as two-stage voltage regulation, two-stage drive, and multi-layer shielded layout of load capacitors. Figure 5 Adjustable size amplifier tube array Figure 6 These features effectively suppress power supply noise, floor noise, and environmental interference, ensuring high purity and frequency stability of the oscillation signal. The first voltage-stabilizing capacitor CL1, the second voltage-stabilizing capacitor CL2, and the third voltage-stabilizing capacitor CL3 are connected between the pre-stabilized voltage avdd, the crystal oscillator control terminal XTAL_CF, the drive voltage avdd_driver, and ground, respectively, forming a multi-stage filtering network. This network works collaboratively to suppress high-frequency noise and ripple in each stage of the power supply, further improving the system's anti-interference capability and signal purity.

[0191] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0192] This example presents a low-noise, high-stability digitally controlled crystal oscillator circuit, such as... Figure 1 As shown, it includes a controllable reference current module, an oscillation module, an oscillation core module, an output signal drive module, a signal detection feedback module, and three voltage stabilizing capacitors.

[0193] The controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generation circuit Bias. The input terminals of the first-stage voltage regulator LDO1 are connected to the reference voltage Vref, the output terminal outputs the pre-stabilized voltage avdd, and the power supply terminal is connected to the power supply voltage Vin. The first input terminal of the current signal generation circuit Bias is connected to the reference voltage Vref, the second input terminal is connected to the digital feedback signal Df_Bias, the output terminal is connected to the crystal oscillator control terminal XTAL_CF, and the power supply terminal is connected to the pre-stabilized voltage avdd.

[0194] The current signal generation circuit bias includes: an operational amplifier amp, whose positive terminal is connected to the reference voltage Vref, its negative terminal is connected to the feedback node vfb_amp, its output terminal is connected to the control node vg0, and its power supply terminal is connected to the pre-stabilized voltage avdd; three MOSFETs: the source of the first MOSFET M0 is connected to the feedback node vfb_amp, its gate is connected to the control node vg0, and its drain is connected to the bias node vbp; the source of the second MOSFET M1 is connected to the pre-stabilized voltage avdd, its gate is connected to the drain and to the bias node vbp; the source of the third MOSFET M2 is connected to the pre-stabilized voltage avdd, its gate is connected to the bias node vbp, and its drain is connected to the crystal oscillator control terminal XTAL_CF; and an adjustable resistor R0, whose positive terminal is connected to the feedback node vfb_amp and its negative terminal is connected to ground. This circuit uses the operational amplifier amp to lock the voltage of the feedback node vfb_amp to the reference voltage Vref, generating an adjustable reference current across the adjustable resistor. The reference current flows simultaneously through the first MOSFET M0 and the second MOSFET M1, and is amplified by a current mirror formed by the second MOSFET M1 and the third MOSFET M2 at a ratio of 1:n. It then flows from the drain of the third MOSFET M2 into the crystal oscillator control terminal XTAL_CF, providing energy for the oscillation core module.

[0195] The input terminal of the oscillation module is connected to the enable signal En, the output terminal is connected to the crystal oscillator input terminal XTAL_I, and the power supply terminal is connected to the pre-stabilized voltage avdd. Its structure is as follows: Figure 3 As shown, it includes a capacitor discharge circuit and a series ring oscillator circuit. During the startup phase, the output signal of the oscillation module is connected to the crystal oscillator input terminal XTAL_I, providing an initial oscillation signal for the slow-starting crystal oscillator, helping the crystal oscillate quickly and remain stable.

[0196] The input terminal of the oscillation core module is connected to the crystal oscillator input terminal XTAL_I, the output terminal is connected to the crystal oscillator output terminal XTAL_O, and the power supply terminal is connected to the crystal oscillator control terminal XTAL_CF. This module includes an external resonator Xtal, whose two ends are connected to the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O, respectively. An RLC network is formed inside Xtal. The gates of the fourth MOSFET M3 and the fifth MOSFET M4 are connected to the crystal oscillator input terminal XTAL_I, and their drains are connected to the crystal oscillator output terminal XTAL_O. The source of the fourth MOSFET M3 is connected to the crystal oscillator control terminal XTAL_CF, and the source of the fifth MOSFET M4 is connected to ground, forming an inverting amplifier to provide sufficient phase for the loop. A feedback resistor Rf is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O to provide the necessary bias for the inverting amplifier.

[0197] The output signal driving module includes a second-stage voltage regulator LDO2, a first-stage output driving circuit Buffer1, and a second-stage output driving circuit Buffer2. The input terminal of the second-stage voltage regulator LDO2 is connected to the reference voltage Vref, the output terminal outputs the driving voltage avdd_driver, and the power supply terminal is connected to the pre-stabilized voltage avdd. The input terminal of the first-stage output driving circuit Buffer1 is connected to the crystal oscillator output terminal XTAL_O, the output terminal is connected to the intermediate driving signal vo1, the first power supply terminal is connected to the crystal oscillator control terminal XTAL_CF, and the second power supply terminal is connected to the driving voltage avdd_driver. The input terminal of the second-stage output driving circuit Buffer2 is connected to the intermediate driving signal vo1, the output terminal is connected to the oscillator output signal OSC, and the power supply terminal is connected to the driving voltage avdd_driver. This module adjusts the pre-processed voltage avdd from the first-stage voltage regulator to the more stable and less noisy voltage avdd_driver. The first-stage driving circuit uses the crystal oscillator control terminal XTAL_CF as the power supply voltage to adjust the crystal oscillator output signal XTAL_O to the voltage domain of the driving voltage avdd_driver. Then, the second-stage driving circuit enhances the intermediate driving signal vo1 into the oscillator output signal OSC with stronger driving capability.

[0198] The input terminal of the signal detection feedback module is connected to the crystal oscillator input terminal XTAL_I, and the output terminal is connected to the digital feedback signal Df_Bias. This module calculates and generates a series of digital signals to control the reference current of the current signal generation circuit Bias by acquiring the peak-to-peak value of the crystal oscillator input terminal XTAL_I.

[0199] In addition, the circuit includes three voltage-regulating capacitors: the first voltage-regulating capacitor CL1, whose positive terminal is connected to the pre-stabilized voltage avdd and whose negative terminal is connected to ground; the second voltage-regulating capacitor CL2, whose positive terminal is connected to the crystal oscillator control terminal XTAL_CF and whose negative terminal is connected to ground; and the third voltage-regulating capacitor CL3, whose positive terminal is connected to the drive voltage avdd_driver and whose negative terminal is connected to ground.

[0200] It should be noted that this example uses two sets of programmable capacitor arrays, which increases the adjustable frequency range while adjusting the frequency accuracy; improves the output signal quality by starting with the power supply and its own structure; uses automatic detection plus external phase control to control the oscillation amplitude of the crystal oscillator to ensure signal quality; and introduces a simple structure to accelerate the crystal oscillation and achieve the goal of fast and stable operation.

[0201] More specifically, such as Figure 1 As shown, the circuit system in this example includes: a reference current generation circuit for generating a pre-stabilized voltage avdd and a drive current I_core; an oscillation circuit for generating an oscillation signal with a series resonant frequency comparable to that of the crystal oscillator during the startup phase; an oscillation core circuit for generating a stable, high-quality oscillation signal; an output signal drive circuit for adjusting the periodic signal generated by the crystal oscillator to the required peak-to-peak value and drive capability; and a sampling feedback circuit for sampling the oscillation signal of the crystal oscillator and processing it to generate a series of digital signals containing information about the crystal oscillation signal. The driving current generation circuit proposed in this example includes: a first-stage pre-stabilized voltage regulator LDO1, whose input is connected to Vref, the power supply voltage Vin, and the output voltage avdd; a driving current generation circuit Bias, whose input is connected to Vref and the input control terminal is connected to Df_bias; an oscillation circuit, whose input is the enable signal En and whose output terminal is connected to XTAL_I; an oscillation core circuit, whose one end is connected to XTAL_I and the other end is connected to XTAL_O; and an output signal driving circuit, which includes: a second-stage low-noise voltage regulator LDO2, whose input is connected to Vref, the power supply voltage avdd, and the output voltage avdd_driver; a first-stage driving circuit, whose input signal is XTAL_O with XTAL_CF as the highest peak value and whose output signal is vo1 with avdd_driver as the highest peak value; a second-stage driving circuit, whose input signal is vo1 and whose output signal is OSC with avdd_driver as the highest peak value; and a sampling feedback circuit, whose input signal is XTAL_I and whose output signal is Df_Bias. The output voltage regulator capacitors CL1, CL2, and CL3 are connected to avdd, XTAL_CF, and avdd_driver, respectively.

[0202] The driving current generation circuit mentioned in this example, such as Figure 2As shown, its operation is as follows: The first-stage pre-stabilized voltage regulator stabilizes the power supply voltage to avdd with the reference voltage Vref as a reference. The reference current generation circuit uses the pre-stabilized voltage avdd as the power supply. The operational amplifier amp, MOSFET M0, and adjustable resistor R0 form a negative feedback loop. The virtual short characteristic of the operational amplifier is used to force the voltage vfb_amp at the positive terminal of resistor R1 to be equal to the reference voltage Vref. According to Ohm's law, the current flowing through resistor R1 is the reference current I_ref. This reference current also flows through MOSFETs M0 and M1. The current mirror structure formed by MOSFETs M1 and M2 has a size ratio of 1:n, which can amplify the reference current I_ref by n times to obtain the drive current I_core.

[0203] The oscillation circuit mentioned in this example, such as Figure 3 As shown, its structure includes: a capacitor discharge circuit, a ring oscillator circuit, and a tri-state gate. The connection method is as follows: the input of the capacitor discharge circuit is connected to the enable signal En, output one is connected to vct_clk, and output two is connected to En_st; the input of the ring oscillator is connected to vct_clk, and the output is connected to vct_st; the input of the tri-state gate is connected to vct_st, the output is connected to Start_core, and the control terminal is connected to En_st. Its operation is as follows: when the enable signal En changes from a high level, the capacitor discharge circuit begins to discharge, vct_clk gradually decreases from a high level, and En_st becomes high. At this time, the tri-state gate opens, and the ring oscillator begins to oscillate at a parallel resonant frequency close to that of the crystal oscillator, outputting vct_st, which is then output through the tri-state gate to accelerate the crystal oscillator's startup; when the output vct_clk of the capacitor discharge circuit falls below a certain threshold, the ring oscillator stops oscillating, and the output signal En_st is set to zero, closing the tri-state gate. At this time, the crystal oscillator operates under its own feedback and oscillates stably. The discharge time of the capacitor discharge circuit should be greater than the crystal oscillator's startup time.

[0204] The oscillation core circuit mentioned in this example, such as Figure 2As shown, its operation is as follows: The resonator Xtal utilizes the piezoelectric effect to convert voltage and stress to each other. Internally, it is equivalent to an RLC network. Providing Xtal with an initial periodic voltage allows it to automatically generate a periodic voltage signal. To enable Xtal to stably and automatically generate a periodic signal, an inverting amplifier, consisting of M3 and M4, is introduced. This forms a feedback loop and provides a phase greater than 180 degrees. A feedback resistor Rf is introduced to provide the bias required for stable operation of the inverting amplifier. Thus, the feedback loop is formed, and the crystal oscillator can continuously output an oscillation signal. Due to the influence of temperature, manufacturing process, aging, etc., the frequency of the output signal is not accurate at this time. Therefore, a set of crystal load capacitors C1 and C2 are connected across the crystal oscillator. The positive terminal of C1 is connected to XTAL_I, and the negative terminal is connected to ground. The positive terminal of C2 is connected to XTAL_O, and the negative terminal is connected to ground.

[0205] In this example, the adjustable capacitor networks C1 and C2 for the crystal oscillator load are two identical circuits. The circuit structure of C1 / C2 is as follows: Figure 4 As shown, its structure includes a coarse-tuning capacitor network (CFA) and a fine-tuning capacitor network (FFA). The connection method is as follows: the positive terminal of the CFA is connected to the positive terminal of the FFA, and the positive and negative terminals of the CFA are connected to the negative terminal of the FFA. Its operation is as follows: This circuit is a typical variation of a Pierce oscillator, primarily, but not limited to, generating clock sources for digital circuits. Its parallel resonant frequency is: f0 p ≈f s (1+C1 / 2(C0+C L )), where f s The series resonant frequency is: We can precisely control the oscillation frequency by adjusting the load capacitor CL. In order to ensure that the adjustable frequency range is wide and precise enough, this example uses a combination of a coarse-frequency array (CFA) and a fine-frequency array (FFA). The specific digital encoding sequence to be adjusted is controlled by external sampling and encoding feedback of the output signal OSC. The coarse adjustment capacitor array mentioned in this example is connected as follows: the positive terminal of coarse adjustment capacitor Cc1 is connected to port P, the negative terminal is connected to the drain of MOS switch M_C1, the source of M_C1 is connected to ground, and the gate is connected to the control potential ct_c0; the positive terminal of coarse adjustment capacitor Cc2 is connected to port P, the negative terminal is connected to the drain of MOS switch M_C2, the source of M_C2 is connected to ground, and the gate is connected to the control potential ct_c1; the positive terminal of coarse adjustment capacitor Cc3 is connected to port P, the negative terminal is connected to the drain of MOS switch M_C3, the source of M_C3 is connected to ground, and the gate is connected to the control potential ct_c2; the positive terminal of coarse adjustment capacitor Ccn is connected to port P, the negative terminal is connected to the drain of MOS switch M_Cn, the source of M_Cn is connected to ground, and the gate is connected to the control potential ct_c(n-1). Its working principle is as follows: Cc is the unit capacitor of the coarse adjustment capacitor, and M_C is the MOS switch of the coarse adjustment capacitor. When the control signal ct_c is low, the M_C switch is not turned on, and the capacitor is disconnected. When the control signal ct_c is high, the M_C switch is turned on, and the negative terminal of the capacitor is shorted to port M. Cc1 and M_C1 are connected in series by one unit capacitor and one MOS switch to form a group. Cc2 and M_C2 are connected in parallel by two groups. Cc3 and M_C3 are connected in parallel by three groups. Cc2^n and M_Cn are connected in parallel by n groups. Thus, the binary code has 2^n different combinations for control. The unit fine adjustment capacitor array mentioned in this example has the same connection relationship and working principle as the unit coarse adjustment capacitor array. The difference is that this capacitor array is controlled by m-bit binary code, which can have 2^m different capacitor combinations. In addition, the fine adjustment unit capacitor is much smaller than the coarse adjustment unit capacitor, and the smallest unit fine adjustment capacitor determines the accuracy of the final adjustable oscillation frequency.

[0206] The adjustable capacitor network C1 and C2 mentioned in this example are designed to handle substrate noise in the chip application environment, especially since substrate noise significantly impacts the signal quality of the crystal oscillator. Therefore, the patent mentions methods for handling substrate noise in the layout, such as... Figure 5As shown, its structure includes: the bottommost substrate isolation layer, the first metal layer, the second metal layer, the third metal layer, the topmost top metal layer (which may be present), and vias CT, the connection hole V1 between the first metal layer and the second metal layer, and the connection hole V2 between the second metal layer and the third metal layer. The principle is as follows: the staggered stacked metals M1, M2, and M3 form a mom capacitor, and a shielding layer is added around it to isolate noise sources from the surrounding environment. A layer of polysilicon or active doping is added at the bottom.

[0207] In this example, the noise in the core oscillation circuit comes not only from the coupling of the adjustable capacitor to ambient noise, but also from the feedback resistor and the inverting amplifier circuit. We know that resistor noise originates from thermal noise. With flicker noise The simplest way to optimize resistor noise is to select resistors with low and stable noise, while increasing the resistor size can suppress high-frequency resistor thermal noise. For inverting amplifier noise, MOS noise sources include thermal noise. flicker noise High-frequency gate-induced noise This demonstrates that a suitable MOSFET size is crucial for noise optimization, so adding a MOSFET array can optimize noise caused by process and bias.

[0208] The above MOS array uses NMOS as an example, such as... Figure 6As shown, its structure includes: a properly sized fixed MOSFET M4_0, two gate-controlled MOSFETs M4_1 and M4_2, two connection switches S1 and S2, and two pull-down switches S3 and S4. The connection method is as follows: the source of M4_0 is grounded, its gate is connected to XTAL_I, and its drain is connected to XTAL_O; the source of M4_1 is grounded, its gate is connected to vg4_1, and its drain is connected to XTAL_O; the source of M4_2 is grounded, its gate is connected to vg4_2, and its drain is connected to XTAL_O; the positive terminal of switch S1 is connected to XTAL_I, its negative terminal is connected to vg4_1, and its control terminal is connected to sela_0; the positive terminal of switch S2 is connected to XTAL_I, its negative terminal is connected to vg4_2, and its control terminal is connected to sela_1; the positive terminal of switch S3 is connected to vg4_1, its negative terminal is grounded, and its control terminal is connected to selb_0; the positive terminal of switch S4 is connected to vg4_2, its negative terminal is grounded, and its control terminal is connected to selb_1. The operation is as follows: MOSFETs M4_0, M4_1, and M4_2 act as amplifying transistors in the inverting amplifier, maintaining the same size. The number of each transistor is set according to the required adjustable range. Normally, either M4_1 or M4_2 is open. When the size needs to be increased, the control switches S1 and S2 are both open, while S3 and S4 are both closed. When the size needs to be decreased, S1 and S2 are both closed, while S3 and S4 are both open. S1 and S2 are connection switches. When closed, they short-circuit the gate vg4_1 of M4_1 to XTAL_I, and short-circuit the gate vg4_2 of M4_2 to XTAL_I. When open, the corresponding branch is open. S3 and S4 are pull-down switches. When closed, they short-circuit the gate vg4_1 of M4_1 to ground, and short-circuit the gate vg4_2 of M4_2 to ground. When open, the corresponding branch is open. The control signals sela_0 and selb_0 are a pair of inverted signals, and sela_0, selb_0, sela_1, and selb_1 can be controlled by off-chip encoding.

[0209] The output signal driving circuit proposed in this example is, for example... Figure 2As shown, its structure includes: a second-stage voltage regulator LDO2, a first-stage voltage drive circuit Buffer1, and a second-stage voltage drive circuit Buffer2. The second-stage voltage regulator LDO2 proposed in this example is connected as follows: the input reference voltage is connected to Vref, the power supply is connected to avdd, and the output is connected to avdd_driver and a large load capacitor C3. LDO2 needs to have low output noise and high PSR. The first-stage voltage drive circuit Buffer1 proposed in this example consists of M5 and M6 as buffer stages, buffer1_0 driver, and voltage converter lvl. The connection is as follows: the gates of M5 and M6 are connected to XTAL_I, and their drains are connected as the output, outputting v1. The sources of M5 and M3 are connected to the positive terminal of CL2, the source of M6 is connected to ground, the input of ffer1_0 is connected to v1, and the output is v2. The power supply voltage is connected to XTAL_CF, the input of lvl is connected to v2, the output is connected to vo1, and the power supply is connected to XTAL_CF and avdd_driver. The principle is as follows: M5 and M3 are exactly the same size, and M6 and M4 are exactly the same size. Buffer1_0 is used to drive lvl, and lvl is used to convert the amplitude from the XTAL_CF voltage domain to the avdd_driver voltage threshold. The second-stage voltage driver Buffer2 proposed in this example is connected as follows: the input is connected to vo1, the output is OSC, and the power supply is connected to avdd_driver. This stage of driving provides sufficient driving capability to the output while keeping the noise introduction sufficiently small.

[0210] The sampling feedback circuit proposed in this example, such as Figure 1 As shown, the connection method is as follows: input is connected to XTAL_I, output is connected to D_fb, and the output signal D_fb is superimposed with the externally programmable signal D_in to output Df_Bias. Its operation is as follows: the circuit samples the oscillation amplitude of the crystal oscillator, compares it with a reference value, and then processes it using digital logic to obtain a series of binary codes (D_fb), used to dynamically control the drive current I_core. The user can provide external control programming code D_in as needed to better control the drive current I_core. The adjustment principle is as follows: when the signal acquired by the sampling circuit (which can be approximated as the voltage value of XTAL_CF) is compared with a suitable reference voltage, the comparison result is encoded into a multi-bit binary code D_f by the logic circuit. This encoded signal is superimposed with the external encoded signal D_in to obtain a new encoded signal Df_Bias (where D_in can be defined by the user, such as for detecting output signals, detecting temperature, etc.). If the detected signal is lower than the expected reference voltage, this new encoded signal will be adjusted. Figure 2The R0 resistor in the middle is reduced to increase the reference current I_ref, thereby increasing the drive current I_core to stabilize the voltage at XTAL_CF and enable the crystal oscillator to oscillate stably.

[0211] The above embodiments have the following technical effects:

[0212] The above embodiment employs a two-stage voltage regulator architecture. The first-stage voltage regulator LDO1 generates a pre-stabilized voltage avdd, and the second-stage voltage regulator LDO2 further generates a low-noise drive voltage avdd_driver, effectively improving the power supply rejection performance of the output signal. Regarding frequency adjustment, the above embodiment uses a combination of a coarse-tuning capacitor array (CFA) and a fine-tuning capacitor array (FFA). The CFA uses an n-bit encoded signal to achieve 2^n levels of load capacitance adjustment, realizing a wide frequency range. The FFA uses an m-bit encoded signal to achieve 2^m levels of load capacitance adjustment, realizing high-precision frequency fine-tuning. The combination of the two balances the width and precision of frequency adjustment. In terms of noise reduction, the above embodiment addresses both the circuitry and layout. Programmable technology is used to control operational amplifiers to adjust additional noise introduced by process variations, and the load capacitance layout is isolated to reduce coupling noise from the substrate and surrounding environment. The oscillation signal quality is ensured by automatic detection feedback and external control. The signal detection and feedback module samples the XTAL_I signal at the crystal oscillator input, processes it internally to obtain the sampled feedback signal D_fb, and superimposes it with the external control signal D_in containing other variables to generate a digital feedback signal Df_Bias to adjust the drive current. The oscillation startup module ensures the oscillator's rapid and stable startup. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal oscillator's resonant frequency to help the crystal oscillator start oscillating. The capacitor discharge circuit periodically shuts off the startup signal, allowing the crystal oscillator to enter a steady state.

[0213] The oscillation module ensures the oscillator starts up quickly and stably. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal's resonant frequency to help the crystal start oscillating. The capacitor discharge circuit periodically shuts off the oscillation signal, allowing the crystal to enter a steady state.

[0214] In summary, the above embodiments achieve multiple technical goals such as low noise, high stability, wide adjustment range, and fast startup through innovative circuit architecture, providing an effective solution for high-performance clock sources.

[0215] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0216] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low-noise, high-stability numerically controlled crystal oscillator circuit, characterized in that, include: The controllable reference current module includes a first-stage voltage regulator (LDO1) and a current signal generation circuit (Bias). The input terminal of the first-stage voltage regulator is connected to a reference voltage (Vref), the output terminal outputs a pre-stabilized voltage (avdd), and the power supply terminal is connected to the power supply voltage (Vin). The first input terminal of the current signal generation circuit is connected to the reference voltage, the second input terminal is connected to a digital feedback signal (Df_Bias), the output terminal is connected to the crystal oscillator current control terminal (XTAL_CF), and the power supply terminal is connected to the pre-stabilized voltage. The oscillation module has an input terminal connected to an enable signal (En), an output terminal connected to a crystal oscillator input terminal (XTAL_I), and a power supply terminal connected to the pre-stabilized voltage. The oscillation core module has its input terminal connected to the crystal oscillator input terminal, its output terminal connected to the crystal oscillator output terminal (XTAL_O), and its power supply terminal connected to the crystal oscillator current control terminal. The core oscillation module includes: a resonator (Xtal), a fourth MOSFET (M3), a fifth MOSFET (M4), and a feedback resistor (Rf); wherein: the first terminal of the resonator is connected to the input terminal of the crystal oscillator, and the second terminal is connected to the output terminal of the crystal oscillator; the gate of the fourth MOSFET is connected to the input terminal of the crystal oscillator, the source is connected to the current control terminal of the crystal oscillator, and the drain is connected to the output terminal of the crystal oscillator; the gate of the fifth MOSFET is connected to the input terminal of the crystal oscillator, the source is grounded, and the drain is connected to the output terminal of the crystal oscillator; one end of the feedback resistor is connected to the input terminal of the crystal oscillator, and the other end is connected to the output terminal of the crystal oscillator. The output signal driving module includes a second-stage voltage regulator (LDO2), a first-stage output driving circuit (Buffer1), and a second-stage output driving circuit (Buffer2). The input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs the driving voltage (avdd_driver), and the power supply terminal is connected to the pre-stabilized voltage. The input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs an intermediate driving signal (vo1), the first power supply terminal is connected to the crystal oscillator current control terminal, and the second power supply terminal is connected to the driving voltage. The first-stage output driving circuit includes a sixth MOSFET (M5), a seventh MOSFET (M6), a driver (Buffer1_0), and a level shifter (LV1). The gates of the sixth MOSFET and the seventh MOSFET are connected and... The first intermediate node (v1) is connected to the input terminal of the crystal oscillator and its drain is connected to form the first intermediate node (v1), which is also connected to the input terminal of the driver. The source of the sixth MOS transistor is connected to the crystal oscillator current control terminal. The source of the seventh MOS transistor is grounded. The power supply terminal of the driver is connected to the crystal oscillator current control terminal, and its output terminal is connected to the second intermediate node (v2) and the input terminal of the level converter. The first power supply terminal of the level converter is connected to the crystal oscillator current control terminal, the second power supply terminal is connected to the driving voltage, and the output terminal outputs the intermediate driving signal. The sixth MOS transistor has the same size as the fourth MOS transistor, and the seventh MOS transistor has the same size as the fifth MOS transistor. The input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal (OSC), and the power supply terminal is connected to the driving voltage. The signal detection feedback module has its input terminal connected to the crystal oscillator input terminal. It is used to sample the oscillation signal of the crystal oscillator input terminal and generate a sampling feedback signal (D_fb). The sampling feedback signal is superimposed with an external programmable control signal (D_in) to form the digital feedback signal. The first voltage regulator capacitor (CL1) has its positive terminal connected to the pre-stabilized voltage and its negative terminal connected to ground. The positive terminal of the second voltage-regulating capacitor (CL2) is connected to the current control terminal of the crystal oscillator, and the negative terminal is connected to ground. The third voltage regulator capacitor (CL3) has its positive terminal connected to the driving voltage and its negative terminal connected to ground.

2. The numerically controlled crystal oscillator circuit according to claim 1, characterized in that, The current signal generation circuit includes: an operational amplifier (amp), a first MOSFET (M0), a second MOSFET (M1), a third MOSFET (M2), and an adjustable resistor (R0); Wherein: the non-inverting input terminal of the operational amplifier is connected to the reference voltage, the inverting input terminal is connected to the feedback signal (vfb_amp), the output terminal is connected to the first control node (vg0), and the power supply terminal is connected to the pre-stabilized voltage; the gate of the first MOS transistor is connected to the first control node, the source is connected to the feedback signal, and the drain is connected to the second control node (vbp); the source of the second MOS transistor is connected to the pre-stabilized voltage, and its gate and drain are connected to the second control node; the source of the third MOS transistor is connected to the pre-stabilized voltage, its gate is connected to the second control node, and its drain is connected to the crystal oscillator current control terminal; the positive terminal of the adjustable resistor is connected to the feedback signal, and the negative terminal is grounded.

3. The numerically controlled crystal oscillator circuit according to claim 1, characterized in that, The oscillation module includes: a capacitor discharge circuit, a ring oscillator, and a three-state gate; The input terminal of the capacitor discharge circuit is connected to the enable signal, the first output terminal (vct_clk) is connected to the input terminal of the ring oscillator, and the second output terminal (En_st) is connected to the control terminal of the tri-state gate; the output terminal (vct_st) of the ring oscillator is connected to the input terminal of the tri-state gate; and the output terminal of the tri-state gate is connected to the crystal oscillator input terminal (XTAL_I).

4. The numerically controlled crystal oscillator circuit according to claim 1, characterized in that, Also includes: The first load capacitor (C1) has its positive or negative terminal connected to the input terminal of the crystal oscillator, and its negative or positive terminal grounded. The second load capacitor (C2) has its positive or negative terminal connected to the output terminal of the crystal oscillator, and its negative or positive terminal grounded.

5. The numerically controlled crystal oscillator circuit according to claim 4, characterized in that, Both the first load capacitor and the second load capacitor include: a unit coarse adjustment capacitor array (CFA) and a unit fine adjustment capacitor array (FFA); Wherein: port P of the unit coarse adjustment capacitor array is connected to port P of the unit fine adjustment capacitor array, and port M of the unit coarse adjustment capacitor array is connected to port M of the unit fine adjustment capacitor array; the unit coarse adjustment capacitor array includes unit coarse adjustment capacitor units controlled by n-bit binary codes, forming Different capacitor combinations are used. Each unit coarse adjustment capacitor includes a unit coarse adjustment capacitor (Cc) and a unit coarse adjustment MOS switch (M_C), wherein the unit coarse adjustment MOS switch is controlled by a corresponding coarse adjustment control signal (ct_c); the unit fine adjustment capacitor array includes unit fine adjustment capacitors controlled by m-bit binary codes, forming... Different capacitor combinations are used, and each fine-tuning capacitor unit includes a fine-tuning capacitor (Cf) and a fine-tuning MOS switch (M_F). The fine-tuning MOS switch is controlled by a corresponding fine-tuning control signal (ct_f). The capacitance value of the fine-tuning capacitor unit is smaller than that of the coarse-tuning capacitor unit, which is used to achieve a combination of wide-range coarse-tuning and precise fine-tuning.

6. The numerically controlled crystal oscillator circuit according to claim 1, characterized in that, The fifth MOS transistor includes: a fixed amplifier transistor (M4_0), a first controllable amplifier transistor (M4_1), a second controllable amplifier transistor (M4_2), a first connection switch (M_S1), a second connection switch (M_S2), a first pull-down switch (M_S3), and a second pull-down switch (M_S4); Wherein: the gate of the fixed amplifier tube is connected to the input terminal of the crystal oscillator, the source is grounded, and the drain is connected to the output terminal of the crystal oscillator; the sources of both the first and second controllable amplifier tubes are grounded, and the drains of both are connected to the output terminal of the crystal oscillator; one end of the first connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the input terminal of the crystal oscillator, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

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