Method for determining noise power in phase-locked loop in technical system

Abstract

The invention relates to a method (100) for determining a noise power (5) in a phase-locked loop (2) in a technical system (1), comprising the following steps: providing (101) at least one resonator (3) in the phase-locked loop (2), configuring (102) the at least one resonator (3) in terms of center frequency, bandwidth and / or integration time, the integration time being specific to the following time period, the noise power (5) is determined for the time period, and the noise power (5) in the phase-locked loop (2) is determined (103) by the at least one resonator (3) on the basis of a sum of energy of a phase error (11) of the phase-locked loop (2) for a configured integration time. The invention further relates to a computer program, a device and a storage medium for this purpose.

Description

Technical Field

[0001] The invention relates to a method for determining the noise power in a phase-locked loop (PLL) in a technical system. The invention also relates to a computer program, a device and a storage medium for this purpose. Background Art

[0002] A phase-locked loop (PLL) is a control system that stabilizes the output frequency by synchronizing it with a reference frequency. This is achieved by continuously adjusting the phase of an oscillator to align it with the phase of a reference signal. PLLs are widely used in communications technology, such as frequency synthesis, modulation, and demodulation.

[0003] Noise is a major disruptive factor in PLL systems. It can cause phase jitter, which affects the PLL's accuracy and stability. For example, phase noise occurs when the oscillator's phase randomly varies due to thermal noise or other external interference. This degrades signal quality and can cause serious problems in critical applications such as high-speed data transmission. Therefore, managing and minimizing noise is a core aspect of PLL system design.

[0004] For example, document DE 11 2018 007 419 T5 describes a technique for reducing or attenuating phase noise in a digital phase-locked loop.

[0005] Document DE 10 2013 005 054 A1 discloses a phase-locked loop for generating an output signal. Summary of the Invention

[0006] The present invention relates to a method, a computer program, a device, and a computer-readable storage medium for determining noise power in a phase-locked loop in a technical system. Further features and details of the invention can be derived from the following description and the accompanying drawings. Features and details relating to the method also apply to the computer program, device, and computer-readable storage medium, and vice versa, so that the disclosures concerning the various inventive aspects are mutually referenced.

[0007] The subject matter of the present invention is, in particular, a method for determining the noise power in a phase-locked loop in a technical system, comprising the following steps, wherein these steps can be performed repeatedly and / or sequentially:

[0008] providing at least one resonator in a phase locked loop,

[0009] configuring the at least one resonator with respect to center frequency, bandwidth and / or integration time, wherein the integration time is specific to the time period for determining the noise power,

[0010] Noise power in the phase-locked loop is determined by the at least one resonator based on summing phase error energy of the phase-locked loop over a configured integration time.

[0011] The phase-locked loop (PLL) is preferably a digital phase-locked loop. The phase error can be provided by a phase detector of the phase-locked loop. The technical system can be a radar system. The phase error can be summed by determining the phase error within a specific time interval using the phase detector. The energy obtained from the determined phase error can then be added to the current sum. Temporally, the addition or summation is preferably performed within the duration of a configured integration time. The method advantageously allows monitoring of the noise power within a resulting frequency range of the at least one resonator, where the resulting frequency range is derived from the configured center frequency and bandwidth. This allows the quality of the phase-locked loop or an oscillator within the phase-locked loop to be evaluated and monitored. The method can also monitor the phase noise in the phase-locked loop based on the determined noise power, particularly in a synthesizer within the phase-locked loop. This can be performed in both open-loop mode (oscillator only) and closed-loop mode. Thus, a technical system including a phase-locked loop can advantageously check the basic noise characteristics of the oscillator after startup before performing potentially sensitive measurements. During the measurement, the phase noise can be continuously monitored using the method according to the embodiments with very low hardware overhead.

[0012] According to another advantage, the method may further comprise the following steps:

[0013] Determine the number of resonators to provide.

[0014] Based on the available resonators, you can select several frequency ranges relevant to the application in question to determine the noise power. For a given number of resonators, you can individually configure the center frequency, bandwidth, and integration time.

[0015] Advantageously, the present invention can provide that the phase error is summed up by a squaring circuit of the at least one resonator. A squaring circuit is an electronic circuit that generates the square of an input signal so that the output signal is proportional to the square of the input signal. For this purpose, an analog multiplier can be used to multiply the input signal by itself. The result of the summation after the squaring circuit can be divided by the number of samples used and then corresponds in particular to the noise power in the configured resonator bandwidth. As an alternative to squaring, the magnitude of the phase error can also be formed and subsequently summed up with the aid of a corresponding magnitude forming circuit (Betragsbildungsschaltung) as a simplified measure of error processing.

[0016] It is contemplated that the method further comprises the following steps:

[0017] Define at least one noise power threshold,

[0018] comparing the determined noise power with the at least one threshold value,

[0019] At least one action is performed based on the comparison result.

[0020] The threshold value can be individually defined depending on the application scenario and, for example, based on empirical values. Furthermore, the threshold value can be specified by or derived from the safety requirements of the phase-locked loop. The comparison result indicates, in particular, whether the noise power exceeds a defined threshold value. By defining at least one threshold value, it is advantageously possible to determine when an impact on the phase-locked loop or a technical system containing a phase-locked loop is likely to occur. Accordingly, such an impact can be countered or prevented by at least one measure. It is also conceivable that, when the noise power exceeds a defined threshold value, a restart, a repetition of the calibration process, or the activation of an "emergency state" (safety state) is triggered.

[0021] Advantageously, within the scope of the present invention, it can be provided that the at least one measure is to initiate the output of at least one warning message or the current state of the noise power. The output can be carried out via an output unit (such as a display or a loudspeaker) so as to be presented visually or acoustically.

[0022] In addition, the method may further comprise the following steps:

[0023] The phase error is scaled based on a defined scaling factor to provide flexibility in determining the noise power.

[0024] Thus, the at least one resonator can advantageously be used for different phase amplitudes.

[0025] In another possibility, the method may further include the following steps:

[0026] Changing the configured center frequency, bandwidth and / or integration time and / or the periodicity of the determination of the noise power in the phase locked loop.

[0027] The changes can be made with a defined periodicity relative to the duration of the respective configuration of the at least one resonator. For example, the configuration can be switched first every minute for a duration of five minutes and then every two minutes for a duration of ten minutes. It is also conceivable that the changes are initiated by a trigger condition, for example, when the noise power exceeds a defined threshold or falls below a defined threshold for a defined duration.

[0028] The subject of the invention is also a computer program, in particular a computer program product, comprising instructions which, when executed by a computer, cause the computer to carry out the method of the invention.

[0029] The present invention also includes a data processing device configured to implement the method according to the present invention. For example, a computer that executes the computer program according to the present invention may be provided as the device. The computer may include at least one processor for executing the computer program. Furthermore, a non-volatile data memory may be provided in which the computer program is stored and from which the processor can read the computer program for execution.

[0030] The present invention may also be directed to a computer-readable storage medium containing the computer program of the present invention and / or instructions that, when executed by a computer, cause the computer to perform the method of the present invention. The storage medium may be a data storage device such as a hard disk, non-volatile memory, or memory card. The storage medium may be integrated into the computer.

[0031] Furthermore, the method of the present invention may also be implemented as a computer-implemented method.

[0032] Further advantages, features and details of the invention can be gathered from the following description, in which exemplary embodiments of the invention are described in detail with reference to the accompanying drawings. The features mentioned in the claims and the description may be essential to the invention individually or in any combination. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings show:

[0034] Figure 1 Schematic visualization showing methods, technical systems, devices, storage media, and computer programs according to embodiments of the present invention,

[0035] Figure 2 Shown is a schematic representation of a phase locked loop with a resonator according to an embodiment of the invention. DETAILED DESCRIPTION

[0036] exist Figure 1 In FIG. 1 , a method 100 , a technical system 1 , an apparatus 10 , a storage medium 15 and a computer program 20 according to an embodiment of the present invention are schematically illustrated.

[0037] Figure 1 In particular, an embodiment of a method 100 for determining a noise power 5 in a phase-locked loop 2 in a technical system 1 is shown. In a first step 101, at least one resonator 3 is provided in the phase-locked loop 2. In a second step 102, the at least one resonator 3 is configured with respect to a center frequency, a bandwidth, and / or an integration time, wherein the integration time is specific to a time period for determining the noise power 5. In a third step 103, the noise power 5 is determined by the at least one resonator 3 based on summing the energy of the phase error 11 of the phase-locked loop 2 over the configured integration time.

[0038] The method according to the embodiment allows, in particular, monitoring of the phase noise in the phase-locked loop 2 in both open-loop (oscillator-only) and closed-loop modes. Thus, a technical system 1 including the phase-locked loop 2 can advantageously check the basic noise characteristics of the oscillator after startup before making potentially sensitive measurements. During the measurement, the phase noise can be continuously monitored using the method according to the embodiment with very little hardware overhead.

[0039] In the digital PLL 2, the instantaneous phase error 11 is available in particular at the output of the digital phase detector 8 based on the comparison of the reference phase 6 with the measured phase 7 (see Figure 2 According to an embodiment, one or more digital resonators 3 with configurable spectral sensitivity can be used to monitor a configurable range of the spectrum. Thus, when a problem is identified (i.e., in particular, a noise power 5 exceeding a defined threshold), an error can be advantageously reported.

[0040] Figure 2 An embodiment of a phase-locked loop 2 with resonators 3 is shown. The available measured phase error 11 is preferably input to at least one, or a series of, programmable resonators 3 to obtain their spectral power within a configurable frequency band. The theory describing the center frequency and bandwidth of such structures is known in the art and can be described analytically. The resonator 3 structure shown preferably places two zeros within the unit circle in the complex z-plane, with the following center frequency f ctr and the quality factor Q. The two gain coefficients G1 and G2 preferably jointly determine the center frequency f of the resonator. ctr and quality factor Q. Z -1 In particular, it represents the frequency f clk A delay of one clock cycle.

[0041] ω0=2×π×f ctr / f clk

[0042]

[0043] where f clk Describes the clock frequency of the input data.

[0044] If the effective bandwidth is properly considered, other higher-order resonator structures can also be used. After passing through the resonator structure 3, the filtered sampled values ​​are preferably squared and summed by means of a square circuit 4. Then, according to Figure 2 In step 12 of , this result is in particular divided by the number of samples used, N, and corresponds to the noise power 5 in the given resonator bandwidth. Figure 2 The phase noise monitor 9 of the embodiment thus comprises the resonator 3 , the squaring circuit 4 and the division by the number of samples used N according to step 12 .

[0045] Before the synthesizer of the phase-locked loop 2 is put into operation, the noise power 5 of the oscillator can be advantageously measured independently according to the method of the embodiment. After the phase-locked loop 2 is closed, the noise power 5 of the oscillator can be measured using Figure 2 The phase noise monitor 9 or the method for determining the noise power 5 according to an embodiment of the present invention is used to compare the phase noise spectrum of the closed phase-locked loop 2 with the expected deviation of the open-loop phase-locked loop 2. During operation of the synthesizer, even when modulation is running, the phase noise monitor 9 or the method for determining the noise power 5 according to an embodiment of the present invention can be used to monitor a certain frequency range continuously or in a "polling" manner.

[0046] The above explanations of the embodiments describe the present invention in the context of examples. Of course, the features of the various embodiments can be freely combined as long as it is technically reasonable without departing from the scope of the present invention.

Claims

1. A method (100) for determining noise power (5) in a phase-locked loop (2) in a technical system (1), the method comprising the following steps: providing (101) at least one resonator (3) in the phase-locked loop (2), Configuring (102) the at least one resonator (3) in terms of center frequency, bandwidth and / or integration time, wherein the integration time is specific to the time period for which the noise power (5) is determined, The noise power (5) in the phase locked loop (2) is determined (103) based on summing the energy of the phase error (11) of the phase locked loop (2) over a configured integration time via the at least one resonator (3).

2. The method (100) according to claim 1, characterized in that The method (100) further comprises the following steps: The number of resonators (3) to be provided is determined.

3. The method (100) according to any one of the preceding claims, characterized in that The summation of the phase error (11) is performed by a square circuit (4) of the at least one resonator (3).

4. The method (100) according to any one of the preceding claims, characterized in that The method (100) further comprises the following steps: defining a threshold value for at least one of said noise powers (5), comparing the determined noise power (5) with the at least one threshold value, At least one action is performed based on the comparison result.

5. The method (100) according to claim 4, characterized in that The at least one measure is the initiation of the output of at least one warning message or the output of the current state of the noise power (5).

6. The method (100) according to any one of the preceding claims, characterized in that The method (100) further comprises the following steps: The phase error (11) is scaled based on a defined scaling factor to provide flexibility in determining the noise power (5).

7. The method (100) according to any one of the preceding claims, characterized in that The method (100) further comprises the following steps: The configured center frequency, the configured bandwidth, and / or the configured integration time, and / or the periodicity of the determination of the noise power (5) in the phase locked loop (2) are varied.

8. A computer program (20) comprising instructions which, when executed by a computer (10), cause the computer to carry out the method (100) according to any one of the preceding claims.

9. A device (10) for data processing, the device being configured to carry out the method (100) according to any one of claims 1 to 7.

10. A computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause the computer to perform the steps of the method (100) according to any one of claims 1 to 7.

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