An adaptive noise shaping phase detector

Abstract

The application belongs to the technical field of integrated circuits, and specifically discloses a phase detector with adaptive noise shaping, which comprises a variable delay unit, a two-way selector, an integral phase detector, a comparison and quantization module and an adaptive noise shaping control module; the integral phase detector is used for converting the time difference between a reference signal or a delay signal and a frequency division signal into an integral voltage and outputting, so as to realize linear transformation of the time difference and the integral voltage; the input end of the comparison and quantization module is connected with the integral voltage, and the comparison and quantization module is used for converting the integral voltage into an error signal output; the adaptive noise shaping control module suppresses in-band noise and optimizes delay parameters through a delay feedback control path and a noise shaping control path, so as to realize noise suppression; the adaptive noise shaping control module is used for suppressing in-band noise and optimizing delay parameters, so that noise suppression can be realized without an additional analog-to-digital converter or a complex algorithm, the circuit power consumption is greatly reduced, and the design complexity is low.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a phase detector with adaptive noise shaping. Background Art

[0002] In high-frequency wireless systems such as 5G communications and millimeter-wave radar, the phase noise and jitter performance of the local oscillator (LO) directly determine the bit error rate (BER) and modulation accuracy of the communication link. As the core architecture of the local oscillator (LO) signal generator, the performance of its phase detector is crucial. The Bang-Bang phase-locked loop (BBPLL), utilizing a 1-bit Bang-Bang phase detector (BBPD) and a time-to-digital converter (TDC), offers advantages such as simple structure and low power consumption, making it widely used in high-frequency integrated designs.

[0003] However, the strong nonlinear characteristics of BBPD introduce non-negligible quantization noise, resulting in increased PLL output jitter, making it difficult to meet the stringent requirements of next-generation communication standards for ultra-low jitter (such as 5G requiring integrated root mean square jitter <90 fs).

[0004] Current noise suppression technologies mainly adopt three solutions. The first is to improve the TDC resolution. By increasing the TDC quantization level (such as using a multi-bit TDC), the quantization noise can be reduced, but it will lead to an increase in circuit area and power consumption. In advanced processes, the design complexity of high-precision TDC increases significantly. The second is to use fixed-parameter noise shaping. Noise shaping is achieved by using fixed-delay Delta modulation feedback (such as first-order high-pass filtering). However, changes in process, voltage and temperature (PVT) will cause the delay parameters to deviate from the optimal value, and the noise suppression effect will be greatly reduced. The third is to adjust the noise shaping parameters through a complex digital calibration loop, but this requires additional analog-to-digital converters or complex algorithms, which increases circuit power consumption and design complexity. Summary of the Invention

[0005] In view of the deficiencies mentioned in the background art, the present invention provides a phase detector with adaptive noise shaping, which is used to solve the technical problem that the noise suppression technology in the prior art cannot meet the requirements of low power consumption while ensuring the noise suppression effect.

[0006] The present invention provides a phase detector with adaptive noise shaping, which includes: a variable delay unit, a two-choice selector, an integral phase detector, a comparison and quantization module, and an adaptive noise shaping control module;

[0007] The input end of the integral phase detector is connected to the frequency-divided signal and the output end of the two-or-one selector; the input end of the variable delay unit is connected to the reference signal, and the output end thereof outputs the delayed signal; the input end of the two-or-one selector is connected to the reference signal and the delayed signal, and the reference signal or the delayed signal is selected by the two-or-one selector and output to the integral phase detector;

[0008] The integral phase detector is used to convert the time difference between the reference signal or the delayed signal and the frequency-divided signal into an integral voltage and output it, thereby realizing a linear transformation between the time difference and the integral voltage;

[0009] The input end of the comparison and quantization module is connected to the integration voltage, which is used to convert the integration voltage into an error signal output;

[0010] The input end of the adaptive noise shaping control module is connected to the error signal, and the output end thereof respectively outputs a selection signal and a delay adjustment signal; the delay adjustment signal is used to control the variable delay unit to output the delayed signal, and the selection signal is used to control the two-or-one selector to select and output the reference signal or the delayed signal; the adaptive noise shaping control module suppresses in-band noise and optimizes delay parameters through a delay feedback control path and a noise shaping control path to achieve noise suppression.

[0011] Furthermore, the integrating phase detector includes a first inverter, a second inverter, and a slope control circuit;

[0012] The input end of the first inverter is connected to the frequency-divided signal, and the output end thereof outputs an inverted signal of the frequency-divided signal to the slope control circuit;

[0013] The input end of the second inverter is connected to the output end of the two-to-one selector; when the selection signal is at a high level, the two-to-one selector selects the delayed signal output, and when the selection signal is at a low level, the two-to-one selector selects the reference signal output; the output end of the second inverter outputs the inverted signal of the delayed signal or the inverted signal of the reference signal to the slope control circuit.

[0014] Furthermore, the integrating phase detector further comprises a first pulse generator, a second pulse generator, a first capacitor, a discharge switch, a second capacitor and a transmission gate;

[0015] The slope control circuit includes a first PMOS transistor, a second PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor;

[0016] The gate of the first PMOS transistor is connected to an inverted signal of a divided signal, and the source of the first PMOS transistor is connected to a voltage signal; the gate of the second PMOS transistor is connected to a delay signal or a reference signal, and the source of the second PMOS transistor is connected to the drain of the first PMOS transistor; the gate of the sixth NMOS transistor is connected to an inverted signal of a reference signal or an inverted signal of a delay signal, and the drain of the sixth NMOS transistor is connected to the drain of the second PMOS transistor; the gate of the seventh NMOS transistor is connected to an inverted signal of a divided signal, and the drain of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor is connected to ground; the drain of the sixth NMOS transistor and the drain of the second PMOS transistor are connected to the first capacitor; a time difference between the reference signal or the delay signal and the divided signal is converted into a phase error voltage output by a slope control circuit, and the phase error voltage is stored in the first capacitor;

[0017] The input ends of the first pulse generator and the second pulse generator are connected to a delay signal or a reference signal; the output end of the first pulse generator is connected to the input end of a transmission gate; the transmission gate is used for controlling the conduction between the first capacitor and the second capacitor; the output end of the second pulse generator is connected to the discharge switch, which is used for controlling the closing of the discharge switch, and the first capacitor and the discharge switch are connected in parallel, and one end of the first capacitor and one end of the discharge switch are connected to ground;

[0018] The first capacitor and the second capacitor are connected in series with the transmission gate, and the first capacitor and the second capacitor are connected in parallel, and one end of the second capacitor is connected to ground.

[0019] Further, the transmission gate comprises a fifth PMOS transistor, a sixth PMOS transistor and a third inverter;

[0020] The input end of the third inverter is connected to the output end of the first pulse generator, the gate of the third PMOS transistor is connected to the output end of the third inverter, the gate of the eighth NMOS transistor is connected to the output end of the first pulse generator, the source of the third PMOS transistor is connected to the source of the eighth NMOS transistor and the other end of the first capacitor, and the drain of the third PMOS transistor is connected to the drain of the eighth NMOS transistor and the other end of the second capacitor;

[0021] When the delay signal or the reference signal triggers the first pulse generator, the pulse signal generated by the first pulse generator turns on the transmission gate, the first capacitor and the second capacitor are connected, the phase error voltage stored in the first capacitor is distributed in the second capacitor, and the voltage stored in the second capacitor is an integral voltage;

[0022] When the delay signal or the reference signal triggers the second pulse generator, the pulse signal generated by the second pulse generator closes the discharge switch, and the first capacitor releases the phase error voltage stored in the previous cycle to prepare for the storage of the first capacitor in the next cycle.

[0023] Furthermore, the comparison and quantization module includes a 1-bit comparator and a trigger;

[0024] The clock terminal of the 1-bit comparator and the clock terminal of the trigger are both connected to the inverted signal of the frequency-divided signal;

[0025] The positive input terminal of the 1-bit comparator is connected to the integrated voltage, the negative input terminal thereof is connected to the voltage, the output terminal of the 1-bit comparator is connected to the trigger terminal of the trigger, and the output terminal of the trigger outputs an error signal;

[0026] The 1-bit comparator is used to compare the input integrated voltage and convert it into a 1-bit error signal for output, and synchronize the output 1-bit error signal with the clock signal through the trigger.

[0027] Further, the 1-bit comparator includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;

[0028] The source of the fifth NMOS transistor is grounded, and its gate is connected to the clock signal. The drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor and the fourth NMOS transistor; the gate of the third NMOS transistor is the positive input terminal of the 1-bit comparator, the gate of the fourth NMOS transistor is the negative input terminal of the 1-bit comparator, the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the source of the seventh PMOS transistor; the drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor and the source of the twelfth PMOS transistor; the drain of the first NMOS transistor is connected to the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, the gate of the second NMOS transistor and the gate of the tenth PMOS transistor, and the drain of the second NMOS transistor is connected to the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, the gate of the second NMOS transistor and the gate of the tenth PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the tenth PMOS transistor; the drain of the second NMOS transistor is connected to the source of the tenth PMOS transistor, the source of the eleventh PMOS transistor, the gate of the first NMOS transistor and the gate of the ninth PMOS transistor, and is the output end of the 1-bit comparator; the gate of the first NMOS transistor is connected to the gate of the ninth PMOS transistor; the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and is connected to a clock signal, and the gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor and is connected to a clock signal; the drains of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor and the twelfth PMOS transistor are all connected to a voltage.

[0029] Further, the adaptive noise shaping control module includes a delayed feedback control path and a noise shaping control path;

[0030] The delay feedback control path includes an AND logic gate, wherein the input end of the AND logic gate is connected to the error signal of the previous cycle and the delay feedback control signal, and the output end of the AND logic gate outputs a selection signal to the two-choice selector; the two-choice selector is controlled by the selection signal to select the output of the reference signal or the delay signal, when the polarity of the error signal of the previous cycle is +1, the selection signal is high, and the two-choice selector selects the delay signal for output; when the polarity of the error signal of the previous cycle is -1, the selection signal is low, and the two-choice selector selects the reference signal for output;

[0031] The noise shaping control path includes a shift register, a multiplier, and an accumulator; the input end of the shift register is connected to the error signal, the input end of the multiplier is connected to the output end of the shift register and the error signal, the input end of the accumulator is connected to the output end of the multiplier, and the output end of the accumulator outputs a delay adjustment signal to the variable delay unit.

[0032] Furthermore, the shift register is used to store the error signal of the current cycle and the error signal of the previous cycle, and the multiplier is used to multiply the error signal of the current cycle and the error signal of the previous cycle to obtain a first-order autocorrelation function The accumulator is used to calculate the first-order autocorrelation function Accumulate and sum the values ​​to obtain a delay adjustment signal, and adjust the delay of the variable delay unit according to the delay adjustment signal.

[0033] Furthermore, in the process of adjusting the delay of the variable delay unit by the delay adjustment signal, when the first-order autocorrelation function >0, the output of the accumulator increases, increasing the delay of the variable delay unit; when the first-order autocorrelation function <0, the output of the accumulator decreases, reducing the delay of the variable delay unit; when the first-order autocorrelation function When it approaches 0, the accumulator locks the current output value.

[0034] The present invention has the following beneficial effects:

[0035] The present invention forms a first-order noise shaping system model through a noise shaping control path, making the quantization noise exhibit high-pass characteristics, avoiding the "spectrum regrowth" problem of the traditional Bang-Bang phase detector, while the out-of-band noise can be effectively suppressed by the low-pass filter in the phase-locked loop, with significant noise suppression capabilities;

[0036] The adaptive noise shaping control module (ASC) of the present invention dynamically tracks the optimal value of the autocorrelation function and the optimal delay, enabling the phase detector to have adaptive PVT compensation capabilities. Even when process variations cause the output jitter standard deviation to vary by 50%, the input equivalent quantization noise can still be controlled within ±3% of the optimal value. The pole frequency deviation of the capacitor network composed of the first capacitor C1 and the second capacitor C2 can be indirectly compensated by the adaptive noise shaping control module (ASC).

[0037] The adaptive noise shaping control module (ASC) of the present invention includes digital circuit components such as an accumulator, a shift register, and an AND logic gate, and has the advantage of low power consumption. At the same time, based on a standard cell design, the adaptive noise shaping control module (ASC) is standardized, making the adaptive noise shaping control module (ASC) highly portable and providing technical support for the cross-platform adaptive use of the adaptive noise shaping control module (ASC). BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of a phase detector with adaptive noise shaping provided by the present invention;

[0040] Figure 2 This is a circuit schematic diagram of a phase detector with adaptive noise shaping provided by the present invention;

[0041] Figure 3 This is a circuit diagram of a 1-bit comparator provided by the present invention;

[0042] Figure 4 The present invention provides a loop model of a phase detector with adaptive noise shaping. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] like Figures 1-4 As shown, an embodiment of the present invention provides a phase detector with adaptive noise shaping, comprising: a variable delay unit, a two-choice selector, an integral phase detector, a comparison and quantization module, and an adaptive noise shaping control module;

[0045] The input of the integral phase detector is connected to the frequency division signal div and the output of the two-choice selector; the input of the variable delay unit is connected to the reference signal ref, and its output outputs the delayed signal ref d The input of the selector is connected to the reference signal ref and the delayed signal ref d, select the reference signal ref or the delayed signal ref through the two-choice selector d Output to the integral phase detector; the integral phase detector is used to convert the reference signal ref or the delayed signal ref d The time difference with the frequency-divided signal div is converted into an integral voltage V2 and output, realizing a linear transformation between the time difference and the integral voltage V2; the input end of the comparison quantization module is connected to the integral voltage V2, which is used to convert the integral voltage V2 into an error signal e[k] and output it; the input end of the adaptive noise shaping control module is connected to the error signal e[k], and its output end outputs a selection signal and a delay adjustment signal respectively; the delay adjustment signal is used to control the variable delay unit to output a delay signal ref d The selection signal is used to control the two-choice selector to select the output reference signal ref or the delay signal ref d The adaptive noise shaping control module suppresses in-band noise and optimizes delay parameters through a delayed feedback control path and a noise shaping control path to achieve noise suppression.

[0046] In some embodiments of the present invention, the integrating phase detector adopts a sampling phase detector, which converts the edge of the frequency division signal div into a voltage slope through a slope control circuit, and then converts the voltage slope into a reference signal ref or a delayed signal ref. d The rising edge of the signal is sampled to the first capacitor C1, and the switch capacitor network composed of the first capacitor C1 and the second capacitor C2 realizes an approximately ideal integration behavior; the comparison and quantization module is based on a dynamic latch comparator structure, combined with pre-charging technology to reduce dynamic offset and maximize the phase-lock gain; the delay feedback control path in the adaptive noise shaping control module is based on the error signal e[k] output by the 1-bit comparator in the comparison and quantization module, which converts the reference signal ref or the delayed signal ref d Feedback is sent to the integrating phase detector to construct a first-order modulation loop, making the quantization noise q[k] high-pass, thereby suppressing in-band noise; the noise shaping control path simultaneously uses a shift register and a multiplier to calculate the first-order autocorrelation function of the error signal , the delay adjustment signal is generated by the accumulator to drive the variable delay unit, according to the first-order autocorrelation function Dynamically adjust the delay Δtq of the variable delay unit ( >0, increase Δtq, <0, reduce Δtq), to achieve delay parameters and jitter standard deviation Real-time matching, noise suppression and low PVT sensitivity.

[0047] like Figure 2As shown, the integral phase detector includes a first inverter, a second inverter, a slope control circuit, a first pulse generator, a second pulse generator, a first capacitor C1, a discharge switch, a second capacitor C2 and a transmission gate; the input end of the first inverter is connected to the frequency division signal div, and the output end thereof outputs the inverted signal div of the frequency division signal n To the slope control circuit; the input end of the second inverter is connected to the output end of the two-choose-one selector; when the selection signal is high, the two-choose-one selector selects the delay signal ref d Output, when the selection signal is low, the two-selector selects the reference signal ref output; the output end of the second inverter outputs the inverted signal ref of the delayed signal dn Or the inverted signal of the reference signal ref n to the slope control circuit.

[0048] In some embodiments of the present invention, an inverter is a circuit element that can invert an input signal. When the input signal is high, the inverter outputs a low level; conversely, when the input signal is low, the inverter outputs a high level.

[0049] Specifically, the slope control circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a sixth NMOS transistor N6 and a seventh NMOS transistor P7; the gate of the first PMOS transistor P1 is connected to the inverted signal div n , whose source is connected to the voltage signal; the gate of the second PMOS transistor P2 is connected to the delay signal ref d Or reference signal ref, its source is connected to the drain of the first PMOS transistor P1; the gate of the sixth NMOS transistor N6 is connected to the inverted signal ref of the reference signal n Or the inverted signal of the delayed signal ref dn , whose drain is connected to the drain of the second PMOS transistor P2; the gate of the seventh NMOS transistor N7 is connected to the inverted signal div n , its drain is connected to the source of the sixth NMOS transistor N6, and the source of the seventh NMOS transistor N7 is grounded; the drain of the sixth NMOS transistor N6 and the drain of the second PMOS transistor P2 are connected to the first capacitor C1; the frequency division signal div is connected to the reference signal ref or the delayed signal ref through the slope control circuit d The time difference between them is converted into a phase error voltage V1 and outputted, and the phase error voltage V1 is stored in the first capacitor C1;

[0050] In some embodiments of the present invention, the reference signal ref and the delayed signal ref thereof after passing through the variable delay unit are d , selected by a two-to-one selector output; delayed signal ref dThe rising edge of the reference signal ref and the frequency division signal div triggers the first PMOS transistor P1, the second PMOS transistor P2, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 of the slope control circuit to close, and the voltage ramp generated by the slope control circuit is sampled to the first capacitor C1, the reference signal ref or the delayed signal ref d The time difference between the divided frequency signal div is proportional to the phase error voltage V1.

[0051] The input terminals of the first pulse generator and the second pulse generator are both connected to the delay signal ref d or reference signal ref; the output end of the first pulse generator is connected to the input end of the transmission gate; the transmission gate is used to control the conduction between the first capacitor C1 and the second capacitor C2; the output end of the second pulse generator is connected to the discharge switch, which is used to control the closing of the discharge switch, the first capacitor C1 is connected in parallel with the discharge switch, and one end of the first capacitor C1 and the discharge switch are both grounded; the first capacitor C1 and the second capacitor C2 are both connected in series with the transmission gate, the first capacitor C1 is connected in parallel with the second capacitor C2, and one end of the second capacitor C2 is grounded; the transmission gate includes a third PMOS transistor P3, an eighth NMOS transistor N8 and a third inverter; the input end of the third inverter is connected to the output end of the first pulse generator, the gate of the third PMOS transistor P3 is connected to the output end of the third inverter, the gate of the eighth NMOS transistor N8 is connected to the output end of the first pulse generator, the source of the third PMOS transistor P3 is connected to the source of the eighth NMOS transistor N8 and the other end of the first capacitor C1, and the drain of the third PMOS transistor P3 is connected to the drain of the eighth NMOS transistor N8 and the other end of the second capacitor C2; when the delay signal ref d Or the reference signal ref triggers the first pulse generator, the pulse signal generated by the first pulse generator turns on the transmission gate, so that the first capacitor C1 is connected to the second capacitor C2, and the phase error voltage V1 stored in the first capacitor C1 is distributed to the second capacitor C2. The voltage stored in the second capacitor C2 is the integrated voltage V2; when the delay signal ref d Or the reference signal ref triggers the second pulse generator, and the pulse signal generated by the second pulse generator closes the discharge switch, and the first capacitor C1 releases the phase error voltage V1 stored in the previous cycle, preparing for the storage of the first capacitor C1 in the next cycle.

[0052] In some embodiments of the present invention, the first pulse generator and the second pulse generator generate two non-overlapping pulse signals. The pulse signal generated by the first pulse generator turns on the transmission gate to share charge, and the first capacitor C1 and the second capacitor C2 perform charge distribution to achieve leaky integration, generating a filtered voltage of the integrated voltage V2. The pole frequency of the equivalent low-pass filter composed of the first capacitor C1 and the second capacitor C2 is fp =1 / (2π(C1+C2)R) (R is the equivalent parallel resistance of C1 and C2). To obtain the best integration effect, the pole frequency f generated by the first capacitor C1 and the second capacitor C2 p It is 1 / 20 of the reference frequency; before the phase detection period of the next cycle, the pulse signal generated by the second pulse generator, that is, the reset signal, opens the discharge switch, discharges the first capacitor C1, and clears the phase error voltage V1 to prepare for the next sampling.

[0053] The comparison and quantization module includes a 1-bit comparator and a trigger; the clock end of the 1-bit comparator and the clock end of the trigger are both connected to the inverted signal div n ; The positive input terminal in+ of the 1-bit comparator is connected to the integrated voltage V2, its negative input terminal in- is connected to the voltage, the output terminal of the 1-bit comparator is connected to the trigger terminal of the trigger, and the output terminal of the trigger outputs the error signal e[k]; the 1-bit comparator is used to compare the input integrated voltage V2 and convert it into a 1-bit error signal e[k] output, and synchronize the output 1-bit error signal e[k] with the clock signal clk through the trigger.

[0054] In some embodiments of the present invention, a 1-bit comparator uses a dynamic latch structure to compare and output the differential input signal only on the rising edge of the input clock signal clk, avoiding invalid comparator output. The voltage connected to the negative input terminal in- of the 1-bit comparator is a fixed voltage, which is half of the power supply voltage, so that the integrated voltage V2 is sampled at half of its swing to ensure the maximum phase detection gain. The clock terminal of the 1-bit comparator is connected to the inverted signal div of the divided signal. n , the trigger clock terminal is connected to the inverted signal of the delayed frequency division signal div n , the output 1-bit error signal e[k] is synchronized with the clock signal clk through the trigger.

[0055] Specifically, such as Figure 3 As shown, the 1-bit comparator includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5;

[0056] The source of the fifth NMOS transistor N5 is grounded, and its gate is connected to the clock signal clk. The drain of the fifth NMOS transistor N5 is connected to the source of the third NMOS transistor N3 and the fourth NMOS transistor N4; the gate of the third NMOS transistor N3 is the positive input terminal in+ of the 1-bit comparator, the gate of the fourth NMOS transistor N4 is the negative input terminal in- of the 1-bit comparator, the drain of the third NMOS transistor N3 is connected to the source of the first NMOS transistor N1 and the source of the seventh PMOS transistor P7; the drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2 and the source of the twelfth PMOS transistor P12; the drain of the first NMOS transistor N1 is connected to the source of the eighth PMOS transistor P8, the source of the ninth PMOS transistor P9, the gate of the second NMOS transistor N2 and the gate of the tenth PMOS transistor P10; the drain of the second NMOS transistor N2 ... The electrode is connected to the source of the tenth PMOS transistor P10, the source of the eleventh PMOS transistor P11, the gate of the first NMOS transistor N1 and the gate of the ninth PMOS transistor P9, and is the output end of the 1-bit comparator; the gate of the first NMOS transistor N1 is connected to the gate of the ninth PMOS transistor P9, and the gate of the second NMOS transistor N2 is connected to the gate of the tenth PMOS transistor P10; the gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8, and is connected to the clock signal clk, the gate of the eleventh PMOS transistor P11 is connected to the gate of the twelfth PMOS transistor P12, and is connected to the clock signal clk; the drains of the seventh PMOS transistor P7, the eighth PMOS transistor P8, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the eleventh PMOS transistor P11, and the twelfth PMOS transistor P12 are all connected to a voltage.

[0057] The adaptive noise shaping control module includes a delay feedback control path and a noise shaping control path; the delay feedback control path includes an AND logic gate, the input end of the AND logic gate is connected to the error signal e[k-1] of the previous cycle and the delay feedback control signal, and the output end of the AND logic gate is connected to a two-choice selector; the error signal e[k-1] of the previous cycle is output after passing through the AND logic gate. The selection signal controls the two-choice selector to select the output reference signal or the delayed signal. When the polarity of the error signal e[k-1] of the previous cycle is +1, the selection signal is high, and the two-choice selector selects the delayed signal ref d Output, when the polarity of the error signal e[k-1] of the previous cycle is -1, the selection signal is low, and the two-choice selector selects the reference signal ref for output;

[0058] The noise shaping control path includes a shift register, a multiplier and an accumulator; the input of the shift register is connected to the error signal, the input of the multiplier is connected to the output of the shift register and the error signal, the input of the accumulator is connected to the output of the multiplier, and the output of the accumulator outputs a delay adjustment signal to the variable delay unit; the shift register is used to store the error signal e[k] of the current cycle and the error signal e[k-1] of the previous cycle, and the multiplier is used to multiply the error signal e[k] of the current cycle and the error signal e[k-1] of the previous cycle to obtain a first-order autocorrelation function ; The accumulator is used to calculate the first-order autocorrelation function Accumulate and sum to obtain the delay adjustment signal, and adjust the delay of the variable delay unit by the delay adjustment signal; when the first-order autocorrelation function >0, the output of the accumulator increases, increasing the delay of the variable delay unit; when the first-order autocorrelation function <0, the output of the accumulator decreases, reducing the delay of the variable delay unit; when the first-order autocorrelation function When it approaches 0, the accumulator locks the current output value.

[0059] In some embodiments of the present invention, by Figure 2 The system modeling is carried out based on the phase detector circuit schematic diagram of the adaptive noise shaping, and the Figure 4 The system model shown in the figure is a frequency division signal div and a reference signal ref or a delayed signal ref output by a two-choice selector. d The time difference Δt[k] between them is sampled and calculated by the slope control circuit to calculate the integral voltage V2. , and then quantized by a 1-bit comparator gain K Q , output error signal e[k], at this stage the 1-bit comparator will add quantization noise q[k], and the delay parameter is adjusted by the adaptive noise shaping control module Correction , fed back to the integrating phase detector to reduce the quantization noise at the output.

[0060] Among them, the reference signal ref or the delayed signal ref output by the frequency division signal div and the two-choice selector d The time difference Δt[k] between them, and the signal transfer function STF and noise transfer function NTF from the quantization noise q[k] to the output are:

[0061] ;

[0062] ;

[0063] Among them, K Q is the quantization gain of the 1-bit comparator, z is a constant in Z-domain for the delay parameter of the variable delay unit.

[0064] quantization gain K of the 1-bit comparator Q which can be calculated by the following equation:

[0065] ;

[0066] wherein: is the standard deviation of the output jitter, i.e. the optimal value of

[0067] Since the signal transfer function STF presents a low-pass characteristic and the noise transfer function NTF presents a high-pass characteristic, i.e. the time difference At[k] is low-pass filtered and the quantization noise q[k] is high-pass filtered, the Bang-Bang phase detector for noise shaping effectively suppresses the in-band part of the quantization noise.

[0068] In some embodiments of the present application, the adaptive noise shaping control module and the control flow for adjusting the variable delay unit by the delay adjustment signal are as follows:

[0069] Since there is a delay parameter value, the quantization noise q[k] of the Bang-Bang phase detector for noise shaping is minimized, but the variation of PVT (i.e. three environmental quantities of process, voltage and temperature) and the uncertainty of the circuit can cause the delay parameter value to deviate from the optimal setting, by utilizing the sensitivity of the autocorrelation function, the delay parameter value is adjusted, and since the first-order autocorrelation function has the maximum slope near the optimal value , the first-order autocorrelation function is selected as the optimal autocorrelation function of the adaptive correction loop;

[0070] According to the error signal e[k-1] of the last period and the selection signal output by the logic gate, the reference signal ref or the delayed signal ref d is selected as the next beat input of the integral phase detector; when the error signal e[k-1] of the last period is +1, the selection signal is high, the two-way selector selects the -1 end, and the delayed signal ref d is input, so that the next beat time error is adjusted in the negative direction; when the error signal e[k-1] of the last period is -1, the selection signal is low, the two-way selector selects the 1 end, and the reference signal ref is input, so that the next beat time error is adjusted in the positive direction;

[0071] The error signal e[k] of the current period and the error signal of the last period are multiplied to obtain the first-order autocorrelation function , which is accumulated by the accumulator and serves as the delay adjustment signal of the noise shaping control path; it adjusts the delay of the variable delay unit:

[0072] like , indicating the delay parameters , the accumulator output increases to increase the delay of the variable delay unit;

[0073] like , indicating the delay parameters , the accumulator output decreases to reduce the delay of the variable delay unit;

[0074] when When the delay parameter is specified , the accumulator locks the current output value and completes the adaptive optimization.

[0075] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

[0076] Furthermore, although the operations of the method of the present invention are described in a particular order in the accompanying drawings, this does not require or imply that these operations must be performed in this particular order, or that all illustrated operations must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A phase detector with adaptive noise shaping, characterized in that: The phase detector includes: a variable delay unit, a two-to-one selector, an integral phase detector, a comparison and quantization module and an adaptive noise shaping control module; The input end of the integral phase detector is connected to the frequency-divided signal and the output end of the two-or-one selector; the input end of the variable delay unit is connected to the reference signal, and the output end thereof outputs the delayed signal; the input end of the two-or-one selector is connected to the reference signal and the delayed signal, and the reference signal or the delayed signal is selected by the two-or-one selector and output to the integral phase detector; The integral phase detector is used to convert the time difference between the reference signal or the delayed signal and the frequency-divided signal into an integral voltage and output it, thereby realizing a linear transformation between the time difference and the integral voltage; The input end of the comparison and quantization module is connected to the integration voltage, which is used to convert the integration voltage into an error signal output; The input end of the adaptive noise shaping control module is connected to the error signal, and the output end thereof outputs a selection signal and a delay adjustment signal respectively; the delay adjustment signal is used to control the variable delay unit to output the delay signal, and the selection signal is used to control the selector to select the reference signal or the delay signal for output; the adaptive noise shaping control module suppresses in-band noise and optimizes delay parameters through a delay feedback control path and a noise shaping control path to achieve noise suppression; The adaptive noise shaping control module includes a delay feedback control path and a noise shaping control path; the delay feedback control path includes an AND logic gate, the input end of the AND logic gate is connected to the error signal of the previous cycle and the delay feedback control signal, and the output end of the AND logic gate outputs a selection signal to the two-selector selector; the noise shaping control path includes a shift register, a multiplier and an accumulator; the input end of the shift register is connected to the error signal, the input end of the multiplier is connected to the output end of the shift register and the error signal, the input end of the accumulator is connected to the output end of the multiplier, and the output end of the accumulator outputs a delay adjustment signal to the variable delay unit; the shift register is used to store the error signal of the current cycle and the error signal of the previous cycle, and the multiplier is used to multiply the error signal of the current cycle by the error signal of the previous cycle to obtain a first-order autocorrelation function The accumulator is used to calculate the first-order autocorrelation function Accumulate and sum the values ​​to obtain a delay adjustment signal, and adjust the delay of the variable delay unit according to the delay adjustment signal.

2. The adaptive noise shaping phase detector according to claim 1, characterized in that: The integrating phase detector includes a first inverter, a second inverter, and a slope control circuit; The input end of the first inverter is connected to the frequency-divided signal, and the output end thereof outputs an inverted signal of the frequency-divided signal to the slope control circuit; The input end of the second inverter is connected to the output end of the two-to-one selector; when the selection signal is at a high level, the two-to-one selector selects the delayed signal output, and when the selection signal is at a low level, the two-to-one selector selects the reference signal output; the output end of the second inverter outputs the inverted signal of the delayed signal or the inverted signal of the reference signal to the slope control circuit.

3. The phase detector with adaptive noise shaping according to claim 2, characterized in that: The integrating phase detector further includes a first pulse generator, a second pulse generator, a first capacitor, a discharge switch, a second capacitor and a transmission gate; The slope control circuit includes a first PMOS transistor, a second PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The gate of the first PMOS transistor is connected to the inverted signal of the frequency-divided signal, and the source of the first PMOS transistor is connected to the voltage signal; the gate of the second PMOS transistor is connected to the delayed signal or the reference signal, and the source of the second PMOS transistor is connected to the drain of the first PMOS transistor; the gate of the sixth NMOS transistor is connected to the inverted signal of the reference signal or the inverted signal of the delayed signal, and the drain of the sixth NMOS transistor is connected to the drain of the second PMOS transistor; the gate of the seventh NMOS transistor is connected to the inverted signal of the frequency-divided signal, and the drain of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor is grounded; the drain of the sixth NMOS transistor and the drain of the second PMOS transistor are connected to the first capacitor; the time difference between the reference signal or the delayed signal and the frequency-divided signal is converted into a phase error voltage output by the slope control circuit, and the phase error voltage is stored in the first capacitor; The input ends of the first pulse generator and the second pulse generator are both connected to a delayed signal or a reference signal; the output end of the first pulse generator is connected to the input end of a transmission gate; the transmission gate is used to control the conduction between the first capacitor and the second capacitor; the output end of the second pulse generator is connected to the discharge switch, which is used to control the closing of the discharge switch, the first capacitor and the discharge switch are connected in parallel, and one end of the first capacitor and the discharge switch are both grounded; The first capacitor and the second capacitor are both connected in series with the transmission gate, the first capacitor and the second capacitor are connected in parallel, and one end of the second capacitor is grounded.

4. The phase detector with adaptive noise shaping according to claim 3, characterized in that: The transmission gate includes a third PMOS transistor, an eighth NMOS transistor and a third inverter; The input terminal of the third inverter is connected to the output terminal of the first pulse generator, the gate of the third PMOS transistor is connected to the output terminal of the third inverter, the gate of the eighth NMOS transistor is connected to the output terminal of the first pulse generator, the source of the third PMOS transistor is connected to the source of the eighth NMOS transistor and the other end of the first capacitor, and the drain of the third PMOS transistor is connected to the drain of the eighth NMOS transistor and the other end of the second capacitor; When the delay signal or the reference signal triggers the first pulse generator, the pulse signal generated by the first pulse generator turns on the transmission gate, so that the first capacitor and the second capacitor are connected, and the phase error voltage stored in the first capacitor is distributed to the second capacitor. The voltage stored in the second capacitor is the integration voltage; When the delay signal or the reference signal triggers the second pulse generator, the pulse signal generated by the second pulse generator closes the discharge switch, and the first capacitor releases the phase error voltage stored in the previous cycle, preparing for the storage of the first capacitor in the next cycle.

5. The phase detector with adaptive noise shaping according to claim 2, characterized in that: The comparison and quantization module includes a 1-bit comparator and a trigger; The clock terminal of the 1-bit comparator and the clock terminal of the trigger are both connected to the inverted signal of the frequency-divided signal; The positive input terminal of the 1-bit comparator is connected to the integrated voltage, the negative input terminal thereof is connected to the voltage, the output terminal of the 1-bit comparator is connected to the trigger terminal of the trigger, and the output terminal of the trigger outputs an error signal; The 1-bit comparator is used to compare the input integrated voltage and convert it into a 1-bit error signal for output, and synchronize the output 1-bit error signal with the clock signal through the trigger.

6. The adaptive noise shaping phase detector according to claim 5, characterized in that: The 1-bit comparator includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the fifth NMOS transistor is grounded, the gate thereof is connected to the clock signal, and the drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor and the source of the fourth NMOS transistor; The gate of the third NMOS transistor is the positive input terminal of the 1-bit comparator, the gate of the fourth NMOS transistor is the negative input terminal of the 1-bit comparator, and the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the source of the seventh PMOS transistor; The drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor and the source of the twelfth PMOS transistor; the drain of the first NMOS transistor is connected to the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, the gate of the second NMOS transistor and the gate of the tenth PMOS transistor; the gate of the second NMOS transistor is connected to the gate of the tenth PMOS transistor; the drain of the second NMOS transistor is connected to the source of the tenth PMOS transistor, the source of the eleventh PMOS transistor, the gate of the first NMOS transistor and the gate of the ninth PMOS transistor, and serves as the output end of the 1-bit comparator; the gate of the first NMOS transistor is connected to the gate of the ninth PMOS transistor; the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and is connected to a clock signal, and the gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor and is connected to a clock signal; the drains of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor and the twelfth PMOS transistor are all connected to a voltage.

7. The adaptive noise shaping phase detector according to claim 1, characterized in that: The selection signal is used to control the two-to-one selector to select the output reference signal or the delayed signal. When the polarity of the error signal in the previous cycle is +1, the selection signal is high, and the two-to-one selector selects the delayed signal output. When the polarity of the error signal in the previous cycle is -1, the selection signal is low, and the two-to-one selector selects the reference signal output.

8. The phase detector with adaptive noise shaping according to claim 1, characterized in that: In the process of adjusting the delay of the variable delay unit by the delay adjustment signal, when the first-order autocorrelation function When the first-order autocorrelation function When the first-order autocorrelation function When it approaches 0, the accumulator locks the current output value.

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