SAR ADC and implementation method
By introducing a voltage adjustment circuit into the SAR ADC to adjust the output reference voltage of the capacitor array, the capacitor mismatch problem is solved, and the performance of the SAR ADC is improved without increasing design complexity and cost.
Patent Information
- Application Number
- CN202410245411.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-04
- Publication Date
- 2025-09-05
AI Technical Summary
SAR ADCs suffer from capacitance mismatch, which affects their performance. Existing technologies struggle to effectively improve their performance without increasing design complexity and cost.
A voltage adjustment circuit is introduced to adjust the output reference voltage in the capacitor array. The weights of the capacitors are adjusted by the voltage adjustment control signal to improve the performance of the SAR ADC.
Without changing the capacitor array structure, the performance of the SAR ADC is improved, avoiding increased design complexity and cost.
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Figure CN120601890A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to wireless communication technology, and in particular to a successive approximation register (SAR) analog-to-digital converter (ADC) and an implementation method thereof. Background Art
[0002] Mobile communication systems typically use the following mechanisms for information transmission: modulating a baseband digital signal to carry information; converting the modulated digital signal into an analog signal, attaching it to a high-frequency carrier signal, and transmitting it via an antenna; using an ADC to convert the analog signal into a digital signal. The ADC is located in the receiving channel, while the analog-to-digital converter (DAC) is located in the transmitting channel.
[0003] As a widely used integrated circuit, ADC is a bridge between the digital world and the analog world. Therefore, ADC is very important in the process of information transmission. Figure 1 As shown, the performance of the ADC may directly affect the performance or function realization of the receiving channel.
[0004] SAR ADCs are widely used in various scenarios due to their relatively balanced conversion rate and resolution performance, simple structure, ease of use, low power consumption, and small footprint. However, SAR ADCs can suffer from capacitor mismatch, which can affect their performance. Summary of the Invention
[0005] To solve related technical problems, the embodiments of the present application provide a SAR ADC and an implementation method thereof.
[0006] The technical solution of the embodiment of the present application is implemented as follows:
[0007] The embodiment of the present application provides a SAR ADC, comprising: a DAC and a comparison circuit, wherein the DAC includes a capacitor array; the SAR ADC further includes a voltage adjustment circuit; wherein,
[0008] The DAC is used to provide N reference voltages for the comparison circuit, where N is an integer greater than or equal to 2;
[0009] The comparison circuit is configured to convert the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively;
[0010] The voltage adjustment circuit is used to adjust the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements.
[0011] In the above SAR ADC, the voltage adjustment circuit is configured to adjust, for each of the one or more capacitors, a first reference voltage corresponding to the capacitor to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
[0012] In the above SAR ADC, the SAR ADC further includes:
[0013] The voltage stabilizing circuit is used to keep the voltage of the voltage adjustment control signal constant and output the voltage adjustment control signal with a constant voltage to the voltage adjustment circuit.
[0014] In the above SAR ADC, the voltage adjustment circuit is configured to divide or boost the first reference voltage using a voltage adjustment control signal corresponding to the capacitor to obtain the second reference voltage.
[0015] In the above SAR ADC, the type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; or a digital signal.
[0016] In the above SAR ADC, the voltage adjustment circuit includes one or more voltage adjustment sub-circuits, each voltage adjustment sub-circuit corresponds to a capacitor and is used to adjust the output reference voltage corresponding to the capacitor.
[0017] The embodiment of the present application further provides a method for implementing a SAR ADC, including:
[0018] The DAC in the SAR ADC provides N reference voltages for a comparison circuit of the SAR ADC, where N is an integer greater than or equal to 2; the DAC includes a capacitor array;
[0019] The comparison circuit converts the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively; wherein,
[0020] The voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements.
[0021] In the above solution, the voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array, including:
[0022] For each of the one or more capacitors, the voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
[0023] In the above solution, the method further includes:
[0024] The voltage stabilizing circuit of the SAR ADC keeps the voltage of the voltage adjustment control signal constant, and outputs the voltage adjustment control signal with a constant voltage to the voltage adjustment circuit.
[0025] In the above solution, the voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to the second reference voltage using the voltage adjustment control signal corresponding to the capacitor, including:
[0026] The first reference voltage is divided or boosted using a voltage adjustment control signal corresponding to the capacitor to obtain the second reference voltage.
[0027] In the above solution, the type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; a digital signal.
[0028] In the above solution, the voltage adjustment circuit includes one or more voltage adjustment sub-circuits, each voltage adjustment sub-circuit corresponds to a capacitor, and each voltage adjustment capacitor corresponds to an output reference voltage.
[0029] In the SAR ADC and implementation method provided by the embodiments of the present application, a DAC provides N reference voltages to a comparison circuit, where N is an integer greater than or equal to 2; the comparison circuit converts the analog signal into a digital signal by comparing the analog signal with the N reference voltages; and the voltage adjustment circuit adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements. The technical solution provided by the embodiments of the present application, by introducing a voltage adjustment circuit, can adjust the output reference voltage corresponding to the capacitor, thereby adjusting the weight of the capacitor so that the performance of the SAR ADC meets the requirements; that is, without adjusting the structure of the capacitor array, the weight of the mismatched capacitor is adjusted by the voltage adjustment circuit, thereby achieving the purpose of improving the performance of the SAR ADC. In this way, the performance of the SAR ADC can be guaranteed without significantly increasing the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a structural diagram of a receiving channel in the related art;
[0031] Figure 2 Schematic diagram of the structure of a SAR ADC in related technology;
[0032] Figure 3 Schematic diagram of the structure of a DAC in related art;
[0033] Figure 4 A schematic diagram of SAR ADC performance indicators under capacitor mismatch conditions;
[0034] Figure 5 This is a schematic structural diagram of the first SAR ADC according to an embodiment of the present application;
[0035] Figure 6 This is a schematic structural diagram of the second SAR ADC according to an embodiment of the present application;
[0036] Figure 7 This is a schematic structural diagram of the third SAR ADC according to an embodiment of the present application;
[0037] Figure 8 A schematic diagram of the structure of a SAR ADC used as an example in this application;
[0038] Figure 9 This is a flow chart of the method for implementing the SAR ADC in an embodiment of the present application. DETAILED DESCRIPTION
[0039] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0040] In related technologies, ADC topology architectures can include the following types: flash, SAR, pipeline, and ∑-△; among them, SAR ADC is widely used in medium-to-high precision or medium-to-high speed application scenarios.
[0041] In actual application, such as Figure 2 As shown in the figure, an n-bit SAR ADC consists of a comparator, a DAC, and a digital logic unit; among them, the MSB is the most significant bit of the SAR ADC, and the LSB is the least significant bit of the SAR ADC. At the same time, the LSB can also indicate the minimum resolution of the SAR ADC (which can be expressed as LSB = full scale (FS) / 2 n ), FS can be understood as the sampling range corresponding to the sampling frequency. Through the comparator, V IN From large to small, the reference voltage (which can be expressed as Vref) generated by the DAC is compared to determine the output bit corresponding to each bit, and then the digital logic unit accumulates the output bit to complete the output to V IN Thus, the conversion from analog signal to digital signal is realized.
[0042] In the above process, the DAC can use the switch to change the connection state of the capacitor array, so that the capacitance of each capacitor position in the capacitor array is in the idle state, sampling state, and hold comparison state in turn to generate the reference voltage corresponding to each capacitor position. Different capacitor positions correspond to different reference voltages, and the capacitance value corresponding to each capacitor position is associated with the size of the reference voltage; that is, Figure 3 As shown, from MSB to LSB, different Vrefs can be corresponded in sequence (such as Vref(FS / 2), Vref(FS / 4), ..., Vref(FS / 2 n )wait).
[0043] Here, for capacitor arrays, a collection of capacitor units is typically used to ensure that each capacitor position has a different capacitance value. Specifically, the number of capacitor units in the collection is controlled to provide capacitance values corresponding to different capacitor positions. This approach can greatly reduce design complexity, but it is necessary to consider the additional parasitic capacitance introduced by the capacitor array.
[0044] This is because the size of the capacitor array (which can be understood as the number of capacitors) increases exponentially with the increase in SAR ADC resolution. As the size of the capacitor array increases, the layout or routing of the capacitor array introduces additional parasitic capacitance or inductance, resulting in capacitor mismatch, which in turn affects the performance of the SAR ADC. Furthermore, during the production process, manufacturing errors may occur, causing a deviation in the actual capacitor value from the designed value (i.e., capacitor mismatch). This deviation can degrade the performance of the SAR ADC, resulting in deviating high-power harmonic components, reduced dynamic range, or degraded static performance.
[0045] That is to say, due to the deviation between the actual capacitance value of the capacitor array and the designed capacitance value, the SAR ADC has a capacitance mismatch problem, which in turn leads to a decrease in the performance of the SAR ADC; wherein, the performance of the SAR ADC can be represented by the ADC performance indicators. ADC performance indicators can include: dynamic indicators and static indicators; wherein, static performance includes integral nonlinearity error (INL, Integral Nonlinearity), differential nonlinearity error (DNL, DifferentialNonlinearity), offset error, gain error, etc.; dynamic performance includes signal-to-noise and distortion ratio (SINAD), signal-to-noise and distortion ratio (SNDR), effective number of bits (ENOB), etc. DNL refers to the quotient of the difference between the actual code bin width and the average code bin width and the average code bin width, which can be obtained by statistical methods; INL refers to the maximum difference between the ideal and actual code conversion values after gain and offset correction. Such as Figure 4As shown in the figure, when the capacitance of a capacitor bit deviates, the capacitor bit will correspond to a DNL. As the capacitance deviation increases, the DNL of the corresponding capacitor bit increases. When the DNL is -1LSB, it indicates that the SAR ADC is experiencing code leakage.
[0046] In response to the problem of capacitor mismatch, related technologies have proposed two solutions related to the chip design process. The first solution is to improve the performance and accuracy of the SAR ADC by modifying the design to reduce the impact of capacitor mismatch, such as introducing redundant bits to reduce the probability of error codes and missed codes due to capacitor mismatch, or introducing adaptive calibration units to directly improve the problem of capacitor mismatch; one implementation method is to introduce an input sampling buffer and an adjustable capacitor to adjust the SAR ADC. The second solution is to add adjustable units to the design and reduce the capacitance deviation caused by capacitor mismatch by debugging the adjustable units; one implementation method is to introduce a gain error calibration capacitor array to calibrate the capacitance deviation and thus adjust the ADC accuracy and performance. However, the introduction of redundant bits has limited optimization of the SAR ADC performance and increases the design complexity. Other methods will increase the design complexity and circuit area, and at the same time, increase the timing risk; that is, the above solutions cannot guarantee both the design complexity and the performance of the SAR ADC.
[0047] Related technologies also propose a solution related to the post-wafer testing phase. By using a focused ion beam (FIB) to cut the circuit of the capacitor array in the chip to make small adjustments, the final design solution is determined by testing the chip performance after different FIB operations. However, the accuracy differences of the FIB may further introduce capacitance deviations. At the same time, this testing solution greatly prolongs the chip development cycle, directly leading to an increase in chip R&D costs.
[0048] Based on this, in various embodiments of the present application, a reference voltage adjustment unit is introduced into the SAR ADC architecture to adjust the weight of the mismatched capacitors. In the above process, since there is no need to adjust the capacitor array, the performance of the SAR ADC can be improved without significantly increasing the design complexity.
[0049] The embodiment of the present application provides a SAR ADC, such as Figure 5 As shown, it includes: a DAC and a comparison circuit 501, the DAC includes a capacitor array 502; the SAR ADC also includes a voltage adjustment circuit 503; wherein,
[0050] The DAC is used to provide N reference voltages for the comparison circuit 501, where N is an integer greater than or equal to 2;
[0051] The comparison circuit 501 is configured to convert the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively;
[0052] The voltage adjustment circuit 503 is configured to adjust the output reference voltage corresponding to one or more capacitors in the capacitor array 502 so that the performance of the SAR ADC meets the requirements.
[0053] In actual application, the comparison circuit 501 may include a comparator (which can be expressed as comparator in English), and the voltage adjustment circuit 503 may be called a voltage adjustment unit, a reference voltage adjustment unit, etc. The embodiment of the present application does not limit the name of the voltage adjustment circuit 503, as long as its function is realized.
[0054] In addition, the capacitor array 502 may include one or more capacitors, each capacitor corresponding to a capacitor position. The embodiment of the present application does not limit the number of capacitors included in the capacitor array 502.
[0055] In actual application, the SAR ADC is powered so that the SAR ADC is in normal working condition. In this case, the digital signal output by the SAR ADC can be collected, and the performance of the SAR ADC can be analyzed using a correlation analysis method (such as spectrum analysis) to determine whether the SAR ADC has a capacitance mismatch problem.
[0056] For example, when the SAR ADC is in normal operation, the DAC can provide N reference voltages to the comparison circuit 501. By comparing the analog signal with the N reference voltages, the comparison circuit 501 can convert the analog signal into a digital signal and output the digital signal. Performance analysis is then performed on the digital signal output by the SAR ADC using methods such as spectrum analysis to obtain a first signal indicator. If the first signal indicator (e.g., DNL) does not meet a requirement (which can also be understood as a threshold), it can be determined that the SAR ADC has a capacitor mismatch problem.
[0057] In actual application, when there is a capacitor mismatch in the SAR ADC, one or more capacitors in the capacitor array 502 may have a deviation in capacitance value (which can also be understood as the presence of one or more mismatched capacitors); in this case, one or more capacitor positions in the capacitor array 502 can be selected as adjustment positions, and the voltage adjustment circuit 503 can be set on the adjustment position to adjust the output reference voltage corresponding to the capacitor through the voltage adjustment circuit 503.
[0058] In one embodiment, the voltage adjustment circuit 503 is configured to adjust a first reference voltage corresponding to each capacitor of the one or more capacitors to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
[0059] In practical applications, the first reference voltage can be understood as the initial reference voltage of the capacitor. The first reference voltage is associated with the first weight of the capacitor. The second weight can reflect the importance of the capacitor in the capacitor array 502. For example, for the mth capacitor position, the first weight of the corresponding capacitor can be expressed as 2 m ; The second reference voltage can be understood as the adjusted first reference voltage.
[0060] In actual application, the SAR ADC may also include an external interface pin (also referred to as an external pin), which is used to convert the debug signal into a voltage adjustment control signal; that is, for each capacitor, the voltage adjustment circuit 503 can obtain the voltage adjustment signal through the external interface pin, and under the control of the voltage adjustment control signal, adjust the first reference voltage to the second reference voltage.
[0061] In one embodiment, the type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; a digital signal.
[0062] In actual application, the voltage control signal can be referred to as a voltage control signal, the current control signal can be referred to as a current control signal, and the digital signal can be referred to as a digital control signal. This embodiment of the present application does not limit this, as long as its function is achieved. In addition, when the type of the voltage adjustment control signal includes a voltage control signal, the voltage adjustment circuit 503 can include a voltage-controlled voltage source in the related art; when the type of the voltage adjustment control signal includes a current control signal, the voltage adjustment circuit 503 can include a current-controlled voltage source in the related art; when the type of the voltage adjustment control signal includes a digital signal, the voltage adjustment circuit 503 can include a digital control voltage source in the related art.
[0063] In actual applications, for different types of voltage adjustment control signals, the voltage adjustment circuit 503 may adjust the first reference voltage in different ways to obtain the second reference voltage.
[0064] Here, in the case that the type of the voltage adjustment control signal includes a voltage control signal, the voltage adjustment circuit 503 may adjust the first reference voltage by voltage division.
[0065] Specifically, in one embodiment, the voltage adjustment circuit 503 is configured to divide or boost the first reference voltage using a voltage adjustment control signal corresponding to a capacitor to obtain the second reference voltage.
[0066] The first reference signal may be divided or boosted by resistive transformation or capacitive transformation, which is not limited in this embodiment of the present application.
[0067] In practical applications, the voltage amplitude of the voltage control signal can be gradually adjusted in steps, so that the voltage adjustment circuit 503 uses the adjusted voltage control signal to divide or boost the first reference voltage. Simultaneously, the digital signal output by the SAR ADC can be collected in real time and performance analyzed to obtain a second signal indicator (e.g., DNL). When the second signal indicator meets a preset threshold (e.g., a theoretical code value associated with DNL), the SAR ADC performance can be considered to meet the requirements. In this case, the output reference voltage of the capacitor is the second reference voltage, and the voltage amplitude of the voltage control signal can be represented as Vctrl1.
[0068] Furthermore, when the voltage adjustment control signal includes a current control signal, the current amplitude of the current control signal can be gradually adjusted in steps, so that the voltage adjustment circuit 503 adjusts the first reference voltage using the adjusted current control signal. Simultaneously, the digital signal output by the SAR ADC can be collected in real time and performance analyzed to obtain a second signal indicator. When the second signal indicator meets a preset threshold, the SAR ADC performance can be considered to meet the requirements. In this case, the output reference voltage of the capacitor is the second reference voltage, and the current amplitude of the current control signal can be represented as Vctrl2.
[0069] It should be noted that after the first reference voltage is adjusted to the second reference voltage, the second reference voltage is associated with the second weight of the capacitor, and the second weight can reflect the importance of the capacitor in the capacitor array 502. For example, for the mth capacitor position, the second weight of the corresponding capacitor can be expressed as the second reference voltage * 2 m / first reference voltage; that is, by adjusting the output reference voltage of the capacitor, the weight of the capacitor can be adjusted.
[0070] In actual application, for multiple capacitors in the capacitor array 502 , the output reference voltages corresponding to the multiple capacitors can be adjusted simultaneously by the voltage adjustment circuit 503 .
[0071] Specifically, in one embodiment, Figure 6As shown, the voltage adjustment circuit 503 includes one or more voltage adjustment sub-circuits 5031 , each voltage adjustment sub-circuit 5031 corresponds to a capacitor and is used to adjust the output reference voltage corresponding to the capacitor.
[0072] That is, for each of the multiple capacitors, the output reference voltage corresponding to the capacitor can be adjusted by multiple voltage adjustment sub-circuits 5031 , so that the performance of the SAR ADC meets higher requirements.
[0073] Exemplarily, for a first capacitor and a second capacitor among the multiple capacitors, the output reference voltages corresponding to the first capacitor and the second capacitor can be adjusted respectively by the two voltage adjustment sub-circuits 5031 in the voltage adjustment circuit 503; specifically, the first reference voltage corresponding to the first capacitor is adjusted to the second reference voltage by one voltage adjustment sub-circuit 5031, and the third reference voltage corresponding to the second capacitor is adjusted to the fourth reference voltage by the other voltage adjustment sub-circuit 5031.
[0074] In actual application, since the stability of the voltage adjustment control signal cannot be guaranteed, a voltage stabilization circuit may be provided in the SAR ADC to output a stable voltage adjustment control signal to the voltage adjustment circuit 503 .
[0075] Based on this, in one embodiment, if Figure 7 As shown, the SAR ADC may further include:
[0076] The voltage stabilizing circuit 504 is configured to maintain a constant voltage of the voltage adjustment control signal and output a constant voltage voltage adjustment control signal to the voltage adjustment circuit 503 .
[0077] In practical applications, the voltage stabilization circuit 504 may include a voltage stabilization unit known in the related art, and may be disposed within or outside the SAR ADC. The configuration of the voltage stabilization circuit 504 may be determined based on factors such as design complexity, resources, or chip area, and is not limited in this embodiment of the present application. Furthermore, maintaining the voltage of the voltage adjustment control signal constant can be understood as maintaining the voltage amplitude of the voltage adjustment control signal within a preset range, thereby ensuring that the performance of the SAR ADC meets requirements.
[0078] In the case where the voltage stabilizing circuit 504 is provided outside the SAR ADC, the voltage stabilizing circuit 504 may output a voltage adjustment control signal with a constant voltage to the voltage adjustment circuit 503 through an external interface pin.
[0079] In the SAR ADC provided in the embodiment of the present application, the DAC provides N reference voltages for the comparison circuit, where N is an integer greater than or equal to 2; the comparison circuit converts the analog signal into a digital signal by comparing the analog signal with the N reference voltages respectively; and the voltage adjustment circuit adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements. The technical solution provided in the embodiment of the present application adjusts the output reference voltage corresponding to the capacitor by introducing a voltage adjustment circuit, thereby adjusting the weight of the capacitor to achieve the purpose of improving the performance of the SAR ADC; that is, in the case of capacitor mismatch in the SAR ADC, the mismatched capacitor weight can be adjusted by the voltage adjustment circuit without changing the structure of the capacitor array. In this way, the performance of the SAR ADC can be guaranteed without significantly increasing the design complexity.
[0080] The present application is described in further detail below with reference to application examples.
[0081] In the application example of this application, a SAR ADC with capacitance deviation adjustment is proposed to solve the problem of performance degradation of SAR ADC chip due to capacitance mismatch. Figure 8 As shown, by adding a voltage adjustment unit (ie, the voltage adjustment circuit 503 mentioned above) to the relevant SAR ADC architecture, the reference voltage of some capacitors can be adjusted.
[0082] Specifically, the process of adjusting the reference voltage of an adjustment bit (for example, the mth bit) includes the following steps:
[0083] Step 1: The SAR ADC chip is powered on and enters the normal working state. At this time, the voltage adjustment unit does not work; wherein Vref1 is the initial reference voltage of the capacitor (i.e., the first reference voltage mentioned above), and the weight of the mth capacitor is 2 m .
[0084] Among them, one or more capacitor bits in the capacitor array can be selected as adjustment bits, and a voltage adjustment unit can be added. The adjustment bits can include output bits or redundant bits; at the same time, the SAR ADC chip reserves an external pin and a voltage regulator unit.
[0085] In actual application, the output signal of the SAR ADC (ie, the digital signal mentioned above) may be collected and the ADC performance may be analyzed by means of spectrum analysis or the like to obtain a first analysis result.
[0086] Step 2: During the debugging phase, a debugging voltage adjustment control signal is input through an external pin (ie, the external interface pin mentioned above), and Vref1 is adjusted through the voltage adjustment unit. The voltage adjustment control signal may include a voltage control signal (ie, the voltage control signal mentioned above).
[0087] The voltage adjustment unit can be implemented using a variety of controllable voltage transformation schemes, such as resistive voltage transformation, capacitive voltage transformation, etc., and the type of corresponding voltage adjustment control signal can be selected according to different voltage division schemes.
[0088] For example, the voltage amplitude of the voltage control signal can be gradually adjusted in steps to adjust Vref1. Simultaneously, the output signal of the SAR ADC at this time is collected and performance analysis is performed to obtain a second analysis result. By comparing the second analysis result with the first analysis result, the voltage control signal amplitude Vctrl that optimizes the quality of the SAR ADC output signal (i.e., the SAR ADC performance meets the requirements) is determined. At this time, the output voltage of the voltage adjustment unit is Vref1', i.e., the reference voltage of the m-th capacitor is Vref1' (i.e., the second reference voltage described above).
[0089] It should be noted that, when the reference voltages of the capacitors corresponding to multiple adjustment positions are adjusted simultaneously, the voltage adjustment unit may output multiple reference voltages accordingly to meet higher requirements for precision adjustment.
[0090] Step 3: Debug the voltage stabilizing unit (ie, the voltage stabilizing unit 504 mentioned above) to output a stable voltage control signal Vctrl to the voltage adjustment unit.
[0091] The voltage stabilizing unit can be built into the SAR ADC chip or used as a peripheral circuit module of the chip. If the voltage stabilizing unit is used as a peripheral circuit module of the chip, the voltage adjustment control signal output by the voltage stabilizing unit can share an external pin with the debug port.
[0092] In this application example, a SAR ADC architecture capable of adjusting capacitance mismatch is proposed. By adding a voltage adjustment unit to the existing SAR ADC architecture, the unit can adjust the reference voltage of some capacitor bits, thereby adjusting the corresponding capacitor bit weights to improve ADC performance. This architecture can effectively correct capacitance mismatch without significantly increasing the complexity of the circuit design, thereby optimizing ADC performance.
[0093] Based on the SAR ADC of the embodiment of the present application, the embodiment of the present application also provides a method for implementing the SAR ADC, such as Figure 9 As shown, the method includes:
[0094] Step 901: A DAC in a SAR ADC provides N reference voltages for a comparison circuit of the SAR ADC, where N is an integer greater than or equal to 2; the DAC includes a capacitor array;
[0095] Step 902: The comparison circuit converts the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively; wherein,
[0096] The voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements.
[0097] In one embodiment, the voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array, including:
[0098] For each of the one or more capacitors, the voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
[0099] In one embodiment, the method may further include:
[0100] The voltage stabilizing circuit of the SAR ADC keeps the voltage of the voltage adjustment control signal constant, and outputs the voltage adjustment control signal with a constant voltage to the voltage adjustment circuit.
[0101] In one embodiment, the voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to the second reference voltage using a voltage adjustment control signal corresponding to the capacitor, including:
[0102] The first reference voltage is divided or boosted using a voltage adjustment control signal corresponding to the capacitor to obtain the second reference voltage.
[0103] In one embodiment, the type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; or a digital signal.
[0104] In one embodiment, the voltage adjustment circuit includes one or more voltage adjustment sub-circuits, each voltage adjustment sub-circuit corresponds to a capacitor, and each voltage adjustment capacitor corresponds to an output reference voltage.
[0105] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0106] In addition, the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
[0107] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.
Claims
1. A successive approximation SAR analog-to-digital converter (ADC), comprising: Analog-to-digital converter DAC and comparison circuit, the DAC includes a capacitor array; it is characterized in that the SAR ADC also includes a voltage adjustment circuit; wherein, The DAC is used to provide N reference voltages for the comparison circuit, where N is an integer greater than or equal to 2; The comparison circuit is configured to convert the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively; The voltage adjustment circuit is used to adjust the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements.
2. The SAR ADC according to claim 1, wherein: The voltage adjustment circuit is used to adjust a first reference voltage corresponding to each capacitor of the one or more capacitors to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
3. The method according to claim 2, characterized in that The SAR ADC further includes: The voltage stabilizing circuit is used to keep the voltage of the voltage adjustment control signal constant and output the voltage adjustment control signal with a constant voltage to the voltage adjustment circuit.
4. The SAR ADC according to claim 2, wherein: The voltage adjustment circuit is used to divide or boost the first reference voltage using a voltage adjustment control signal corresponding to the capacitor to obtain the second reference voltage.
5. The SAR ADC according to claim 2, wherein: The type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; a digital signal.
6. The SAR ADC according to any one of claims 1 to 5, wherein: The voltage adjustment circuit includes one or more voltage adjustment sub-circuits, each voltage adjustment sub-circuit corresponds to a capacitor and is used to adjust the output reference voltage corresponding to the capacitor.
7. A method for implementing a SAR ADC, characterized in that: The method comprises: The DAC in the SAR ADC provides N reference voltages for a comparison circuit of the SAR ADC, where N is an integer greater than or equal to 2; the DAC includes a capacitor array; The comparison circuit converts the analog signal into a digital signal by comparing the analog signal with N reference voltages respectively; wherein, The voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array so that the performance of the SAR ADC meets the requirements.
8. The method according to claim 7, characterized in that The voltage adjustment circuit of the SAR ADC adjusts the output reference voltage corresponding to one or more capacitors in the capacitor array, including: For each of the one or more capacitors, the voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to a second reference voltage using a voltage adjustment control signal corresponding to the capacitor.
9. The method according to claim 8, characterized in that The method further comprises: The voltage stabilizing circuit of the SAR ADC keeps the voltage of the voltage adjustment control signal constant, and outputs the voltage adjustment control signal with a constant voltage to the voltage adjustment circuit.
10. The method according to claim 8, characterized in that The voltage adjustment circuit adjusts the first reference voltage corresponding to the capacitor to the second reference voltage using a voltage adjustment control signal corresponding to the capacitor, including: The first reference voltage is divided or boosted using a voltage adjustment control signal corresponding to the capacitor to obtain the second reference voltage.
11. The method according to claim 8, characterized in that The type of the voltage adjustment control signal includes one of the following: a voltage control signal; a current control signal; a digital signal.
12. The method according to any one of claims 7 to 11, characterized in that The voltage adjustment circuit includes one or more voltage adjustment sub-circuits, each voltage adjustment sub-circuit corresponds to a capacitor, and each voltage adjustment capacitor corresponds to an output reference voltage.