Four-level pulse amplitude modulation transceiver, chip and equipment

Abstract

The invention discloses a four-level pulse amplitude modulation transceiver, a chip and equipment, the four-level pulse amplitude modulation transceiver comprises a transmitting end and a receiving end, the transmitting end comprises an encoder and a transmitting clock generation circuit used for providing clock signals for the decoder; the encoder is used for encoding the six groups of NRZ signals and combining the six groups of NRZ signals with a preset first correlation matrix # imgabs0 # to generate four groups of four-level pulse amplitude modulation signals W0-W3, the four groups of four-level pulse amplitude modulation signals W0-W3 serve as two groups of pseudo-differential signals and are sent to the receiving end, and the receiving end comprises a decoder and a receiving clock generation circuit used for providing clock signals for the decoder. And the decoder is used for decoding six groups of NRZ signals by combining the four groups of four-level pulse amplitude modulation signals W0-W3 with a preset second correlation matrix # imgabs1 #. The invention aims to solve the problem that an existing PAM4 modulation transceiver is poor in bit error rate and energy efficiency in an ultra-short distance and high-bandwidth environment.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a four-level pulse amplitude modulation transceiver, a chip and a device. Background Art

[0002] With the increasing demand for high-bandwidth data communications, extremely short reach (XSR) serializer-deserializer (SerDes) transceivers with data rates exceeding 100Gb / s are widely used in chip-to-chip (D2D) and co-packaged optical (CPO) links. XSR communication distances typically do not exceed 50mm, which means a total insertion loss of less than 10dB at a transmission rate of 56Gbaud. However, due to the modulation method and high bandwidth, 112G extremely short reach transceivers using PAM4 modulation have poor performance in terms of bit error rate and energy efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is as follows: In response to the above-mentioned problems in the prior art, a four-level pulse amplitude modulation transceiver, chip and device are provided. The present invention aims to solve the problem that the existing PAM4 modulation transceiver performs poorly in terms of bit error rate and energy efficiency in ultra-short distance and high bandwidth environments.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A four-level pulse amplitude modulation transceiver includes a transmitting end and a receiving end, wherein the transmitting end includes an encoder and a transmission clock generating circuit for providing a clock signal for a decoder, and the encoder is used to encode six groups of NRZ signals in combination with a preset first correlation matrix. Generate 4 groups of four-level pulse amplitude modulation signals W0~W3 and send them as two groups of pseudo differential signals to the receiving end, the receiving end includes a decoder and a receiving clock generation circuit for providing a clock signal to the decoder, the decoder is used to combine the 4 groups of four-level pulse amplitude modulation signals W0~W3 with a preset second correlation matrix The decoded NRZ signals are 6 groups, each of which includes 3 groups of high-order signals MSB0 to MSB2 and 3 groups of low-order signals LSB0 to LSB2.

[0005] Optionally, the first correlation matrix and the second correlation matrix The function expression is: , .

[0006] Optionally, the encoder includes four encoding branches, the high-order signal MSB0 and the low-order signal LSB0 serve as inputs of the first encoding branch, the high-order signal MSB1 and the low-order signal LSB1 serve as inputs of the second and third encoding branches at the same time, and the high-order signal MSB2 and the low-order signal LSB2 serve as inputs of the fourth encoding branch. The encoding branch includes a 16:4 multiplexer, a 2-bit thermometer code circuit B2T, a retiming circuit, a single slip circuit and a pulse generating circuit connected in sequence, wherein the 2-bit thermometer code circuit B2T is used to convert the input 2-bit data into a 3-bit thermometer code, the retiming circuit uses a 9.5GHz clock to sample the 3-bit thermometer code signal to obtain a retiming signal, and the single slip circuit uses The single-ended retimed signal obtained by sampling is converted into a differential signal and a pulse coding signal is generated through a pulse generating circuit. The first coding branch and the second coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo differential signal composed of four-level pulse amplitude modulation signals W0 and W1. The third coding branch and the fourth coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo differential signal composed of four-level pulse amplitude modulation signals W2 and W3. The pulse generating circuit includes four parallel pulse generating units, each of which is composed of NMOS transistors Mn1 to Mn6 and PMOS transistors Mp1 to Mp8. The input data D 0 is connected to ground in sequence through the PMOS transistor Mp1, the NMOS transistor Mn1, and the PMOS transistor Mp2. The gates of the PMOS transistors Mp1, Mp2, and Mp4 are connected to the clock signal Clk180. The NMOS transistor Mn2 and the PMOS transistor Mp3 are arranged in series between the middle node of the NMOS transistor Mn1 and the PMOS transistor Mp2 and the ground, and the gates are connected to the clock signal Clk270. The source of the PMOS transistor Mp4 is connected to the middle node of the NMOS transistor Mn2 and the PMOS transistor Mp3, and the drain is grounded. The middle node of the NMOS transistor Mn2 and the PMOS transistor Mp3 is connected to the gate of the PMOS transistor Mp5 to output the positive pulse coding signal of the data D0 through the PMOS transistor Mp5. The NMOS transistor Mn 1 is connected to the gate of the PMOS transistor Mp7, the NMOS transistors Mn3, PMOS transistors Mp7, and Mp6 are sequentially connected in series between the power supply and ground, the gates of the NMOS transistors Mn3 and PMOS transistors Mp6 are connected to each other and to the gate of the NMOS transistor Mn5, the NMOS transistor Mn4 and the PMOS transistor Mp8 are arranged in series between the power supply and ground, and their gates are connected to the clock signal Clk90, the NMOS transistor Mn5 connects the node between the NMOS transistors Mn4 and PMOS transistor Mp8 to the power supply, and the NMOS transistor Mn5 also connects the node between the NMOS transistors Mn4 and PMOS transistor Mp8 to the gate of the NMOS transistor Mn6 to output the inverse pulse coding signal of the data D0 through the NMOS transistor Mn6.

[0007] Optionally, the 4:1 combiner includes six inverters with a common output end, each of the inverters is composed of an NMOS tube and a PMOS tube with connected gates in series, the input ends of the six inverters are respectively connected to the six input signals AP0, AP1, BP0, BP1, CP0, and CP1 from the two coding branches and are respectively connected to the common output end through a resistor connected in series to generate a 7-level coding signal, the output end is connected to an electrostatic protection circuit ESD, the electrostatic protection circuit ESD includes two diodes in series, the middle junction of the two diodes is connected to the output end through an inductor, and is grounded through an inductor Tcoil and a capacitor PAD.

[0008] Optionally, the 2-bit thermometer code circuit B2T includes a NAND gate, a NOR gate and an XNOR gate. The input 2-bit data includes the high-order data MSB and the low-order data LSB. The high-order data MSB and the low-order data LSB are used to generate the first-bit output data A through the NAND gate, the low-order data LSB is used to generate the second-bit output data B through the NOR gate, and the high-order data MSB and the low-order data LSB are used to generate the second-bit output data C through the XNOR gate.

[0009] Optionally, the sending clock generation circuit includes an AC coupling circuit, a four-phase clock generation circuit, a duty cycle and phase adjustment circuit, a clock rotation selection circuit, a delay module and a frequency division clock circuit. The AC coupling circuit, the four-phase clock generation circuit, the duty cycle and phase adjustment circuit, and the clock rotation selection circuit are connected in sequence. The output end of the clock rotation selection circuit is divided into two branches, each branch is connected in series with a delay module and a frequency division clock circuit, and the frequency division clock circuit of the first branch is respectively connected to the retiming circuit and the pulse generation circuit of the first and second coding branches, and the frequency division clock circuit of the second branch is respectively connected to the retiming circuit and the pulse generation circuit of the third and fourth coding branches.

[0010] Optionally, the decoder includes three decoding branches, each decoding branch includes a logic operation circuit, a driving circuit BUF, a signal amplification circuit VGA, a PAM4 decision device, a thermometer code restoration circuit T2B and a 16:4 demultiplexer, and the logic operation circuits of the first and third decoding branches are subtraction circuits SUB, and the logic operation circuit of the second decoding branch is an addition circuit ADD. The subtraction circuit SUB in the first decoding branch is used to subtract the four-level pulse amplitude modulation signals W0 and W1 and use them as the input signal of the subsequent driving circuit BUF. The subtraction circuit SUB in the third decoding branch is used to subtract the four-level pulse amplitude modulation signals W2 and W3 and use them as the input signal of the subsequent driving circuit BUF. The addition circuit ADD is used to add the four-level pulse amplitude modulation signals W0~W4 and use them as the input signal of the subsequent driving circuit BUF. The driving circuit BUF The circuit is used to drive the input signal to generate a driving signal, the signal amplification circuit VGA is used to amplify the driving signal, the PAM4 decision device is used to decode the driving signal to generate a 3-bit thermometer code, the thermometer code restoration circuit T2B is used to restore the 3-bit thermometer code to 2-bit data, and the 16:4 demultiplexer is used to demultiplex the 2-bit data to obtain two groups of NRZ signals by decoding; the subtraction circuit SUB includes two input branches, each input branch includes an inductor, a resistor, and an NMOS transistor connected in sequence, the gates of the NMOS transistors Mn7 and Mn8 of the two input branches each input a four-level pulse amplitude modulation signal, a variable resistor and a variable capacitor are connected in parallel between the sources of the NMOS transistors Mn7 and Mn8 of the two input branches for adjusting the signal zero and pole, and the drains of the NMOS transistors Mn7 and Mn8 of the two input branches serve as the output terminals V out To output the input signal of the subsequent driving circuit BUF; the adding circuit ADD includes four NMOS tubes Mn9 to Mn12, the gates of the NMOS tubes Mn9 to Mn12 are sequentially connected to the four-level pulse amplitude modulation signals W0 to W4, and the drains of the NMOS tubes Mn9 and Mn11 are connected to each other as the output terminal V out The negative electrode of the NMOS tube Mn10 and Mn12 are connected to each other as the output terminal V out A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn9 and Mn10 to adjust the signal zero poles. A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn11 and Mn112 to adjust the signal zero poles. The output terminal V out The negative and positive electrodes are connected to the power supply through resistors and inductors.

[0011] Optionally, the receiving clock generation circuit includes an AC coupling circuit, a four-phase clock generation circuit, a phase interpolator, a duty cycle and phase adjustment circuit, a delay module and a frequency-dividing clock circuit. The AC coupling circuit, the four-phase clock generation circuit, the phase interpolator, the duty cycle and phase adjustment circuit are connected in sequence, and the output end of the duty cycle and phase adjustment circuit is divided into three branches, each branch is connected in series with a delay module and a frequency-dividing clock circuit, and the output end of the frequency-dividing clock circuit on each branch is respectively connected to the PAM4 decision maker and the clock signal input end of the 16:4 demultiplexer on a corresponding decoding branch to provide a clock signal therefor.

[0012] In addition, the present invention also provides a chip comprising at least two core particles connected to each other, wherein the four-level pulse amplitude modulation transceiver is provided between the two core particles.

[0013] In addition, the present invention also provides an electronic device, comprising a processor and a memory connected to each other, wherein the processor comprises the four-level pulse amplitude modulation transceiver.

[0014] Compared with the prior art, the present invention can achieve the following beneficial effects: the four-level pulse amplitude modulation transceiver of the present invention includes a transmitting end and a receiving end, the transmitting end includes an encoder and a transmitting clock generating circuit for providing a clock signal for a decoder, the encoder is used to encode 6 groups of NRZ signals in combination with a preset first correlation matrix Generate 4 groups of four-level pulse amplitude modulation signals W0~W3 and send them to the receiving end as two groups of pseudo differential signals. The receiving end includes a decoder and a receiving clock generation circuit for providing a clock signal to the decoder. The decoder is used to combine the 4 groups of four-level pulse amplitude modulation signals W0~W3 with a preset second correlation matrix The decoded NRZ signals are 6 groups. The present invention realizes a low-complexity four-level pulse amplitude modulation transceiver equalization design, which can solve the problem of poor bit error rate and energy efficiency of existing PAM4 modulation transceivers in ultra-short distance and high bandwidth environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the principle structure of a four-level pulse amplitude modulation transceiver in an embodiment of the present invention.

[0016] Figure 2 Schematic diagram of the principle structure of the encoder in an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of the circuit principle of the pulse generating circuit in an embodiment of the present invention.

[0018] Figure 41 is a circuit schematic diagram and an output schematic diagram of a 4:1 combiner in an embodiment of the present invention, wherein (a) is a circuit schematic diagram of the 4:1 combiner, and (b) is an output code table of the 4:1 combiner outputting W0.

[0019] Figure 5 Schematic diagram of the circuit principle of the 2-bit thermometer code conversion circuit B2T in an embodiment of the present invention.

[0020] Figure 6 Schematic diagram of the principle structure of the decoder in an embodiment of the present invention.

[0021] Figure 7 Schematic diagram of the circuit principles of two subtraction circuits SUB in an embodiment of the present invention, wherein (a) and (b) are two subtraction circuits SUB with different inputs.

[0022] Figure 8 Schematic diagram of the adding circuit ADD circuit principle in an embodiment of the present invention.

[0023] Figure 9 The figure shows a comparison between a four-level pulse amplitude modulation transceiver (CPAM) according to an embodiment of the present invention and an extremely short-distance link.

[0024] Figure 10 1 and 2 are the simulation results of the energy consumption ratio of the transmitting end and the receiving end in the embodiment of the present invention, wherein (a) is the simulation result of the energy consumption ratio of the transmitting end, and (b) is the simulation result of the energy consumption ratio of the receiving end.

[0025] Figure 11 Figures 2 and 3 are eye diagrams of three groups of 38 Gb / s non-return-to-zero (NRZ) codes simulated by the first subtraction circuit SUB, the addition circuit ADD, and the second subtraction circuit SUB in an embodiment of the present invention with and without a feedforward equalizer FFE, respectively. Figures (a) to (c) are eye diagrams of three groups of 38 Gb / s non-return-to-zero (NRZ) codes simulated without the feedforward equalizer FFE, and (d) to (f) are eye diagrams of three groups of 38 Gb / s non-return-to-zero (NRZ) codes simulated with the feedforward equalizer FFE, respectively. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] like Figure 1 As shown, the four-level pulse amplitude modulation transceiver of this embodiment includes a transmitter and a receiver. The transmitter includes an encoder and a transmission clock generation circuit for providing a clock signal to the decoder. The encoder is used to encode 6 groups of NRZ signals and combine them with a preset first correlation matrix. Generate four groups of four-level pulse amplitude modulation signals (CPAM4 signals) W0~W3 and send them as two groups of pseudo differential signals to the receiving end, the receiving end including a decoder and a receiving clock generation circuit for providing a clock signal to the decoder, the decoder is used to combine the four groups of four-level pulse amplitude modulation signals W0~W3 with a preset second correlation matrix The decoded data generates six NRZ signals, including three high-order signals (MSB0-MSB2) and three low-order signals (LSB0-LSB2). In PAM4 modulation, the MSB (Most Significant Bit) refers to the most significant bit, and the LSB (Least Significant Bit) refers to the least significant bit. Therefore, the six NRZ signals are represented as three high-order signals (MSB0-MSB2) and three low-order signals (LSB0-LSB2). In this embodiment, the transmitter uses a specially designed encoder to encode the six NRZ signals into four CPAM4 signals (W0, W1, W2, and W3), which form two pseudo-differential signals for transmission. Similarly, the receiver uses a decoder.

[0028] like Figure 1 As shown, in this embodiment, the first correlation matrix and the second correlation matrix The function expression is: , .

[0029] like Figure 2As shown, the encoder of this embodiment includes four encoding branches, the high-order signal MSB0 and the low-order signal LSB0 serve as the input of the first encoding branch, the high-order signal MSB1 and the low-order signal LSB1 serve as the input of the second and third encoding branches at the same time, and the high-order signal MSB2 and the low-order signal LSB2 serve as the input of the fourth encoding branch. The encoding branch includes a 16:4 multiplexer, a 2-bit thermometer code conversion circuit B2T, a retiming circuit, a single slip circuit and a pulse generating circuit connected in sequence, wherein the 2-bit thermometer code conversion circuit B2T is used to convert the input 2-bit data into a 3-bit thermometer code, and the retiming circuit uses a 9.5GHz clock to sample the 3-bit thermometer code signal to obtain a retiming signal. Timing signal, the single-slip circuit is used to convert the sampled single-ended retiming signal into a differential signal and generate a pulse coding signal through a pulse generation circuit. The first coding branch and the second coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo-differential signal composed of four-level pulse amplitude modulation signals W0 and W1. The third coding branch and the fourth coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo-differential signal composed of four-level pulse amplitude modulation signals W2 and W3. As a result, three groups of PAM4 (72Gbps) are encoded and transmitted as two groups of pseudo-differential CPAM4 signals (114Gbp). The transmitter in this embodiment uses a hybrid architecture, including a 16:4 multiplexer (MUX), a 2-bit thermometer code converter (B2T), a retiming circuit (RETIMER), a single-slip circuit (S2D), and a pulse generator (PUL.GEN). The high-order signal MSB1 and the low-order signal LSB1 serve as inputs for the second and third encoding branches. The replicated MSB1 and LSB1 are processed at a 1 / 16 rate to ensure consistent performance for each group of encoding units. To save power, the single-slip circuit (S2D) operates at a 1 / 4 rate (9.5 GHz). See [refer to the following text]. Figure 2 For ease of simulation, this embodiment uses a 6-bit pseudo-random number generator to generate six groups of NRZ signals: three groups of high-order signals MSB0-MSB2 and three groups of low-order signals LSB0-LSB2. In actual applications, this 6-bit pseudo-random number generator is the corresponding actual data source.

[0030] like Figure 3As shown, the pulse generating circuit of this embodiment includes four parallel pulse generating units, each of which is composed of NMOS transistors Mn1 to Mn6 and PMOS transistors Mp1 to Mp8. The input data D0 is grounded in sequence through the PMOS transistor Mp1, the NMOS transistor Mn1, and the PMOS transistor Mp2. The gates of the PMOS transistors Mp1, Mp2, and Mp4 are connected to the clock signal Clk180. The NMOS transistor Mn2 and the PMOS transistor Mp3 are arranged in series between the middle node between the NMOS transistor Mn1 and the PMOS transistor Mp2 and the ground, and the gates are connected to the clock signal Clk270. The source of the PMOS transistor Mp4 is connected to the middle node between the NMOS transistor Mn2 and the PMOS transistor Mp3, and the drain is grounded. The middle node between the NMOS transistor Mn2 and the PMOS transistor Mp3 is connected to the gate of the PMOS transistor Mp5 to output the data D0 through the PMOS transistor Mp5. The positive pulse coding signal is outputted from the NMOS transistor Mn1, the gate of the NMOS transistor Mn1 is connected to the gate of the PMOS transistor Mp7, the NMOS transistors Mn3, PMOS transistors Mp7, and Mp6 are sequentially connected in series between the power supply and the ground, the gates of the NMOS transistors Mn3 and PMOS transistor Mp6 are connected to each other and to the gate of the NMOS transistor Mn5, the NMOS transistor Mn4 and the PMOS transistor Mp8 are arranged in series between the power supply and the ground, and the gates are connected to the clock signal Clk90, the NMOS transistor Mn5 connects the node between the NMOS transistors Mn4 and the PMOS transistor Mp8 to the power supply, and the NMOS transistor Mn5 also connects the node between the NMOS transistors Mn4 and the PMOS transistor Mp8 to the gate of the NMOS transistor Mn6 to output the reverse pulse coding signal of the data D0 through the NMOS transistor Mn6. Finally, the low-speed signals generated by the four pulse generating units are synthesized into a high-speed signal at the output end OUT through the circuit.

[0031] like Figure 4As shown in (a), the 4:1 combiner of this embodiment includes six inverters with a common output terminal. Each of the inverters is composed of an NMOS transistor and a PMOS transistor connected in series with their gates connected. The input terminals of the six inverters are respectively connected to the six input signals AP0, AP1, BP0, BP1, CP0, and CP1 from the two encoding branches, and are respectively connected to the common output terminal through a resistor connected in series to generate a 7-level encoding signal. The output terminal is connected to an electrostatic protection circuit ESD, which includes two diodes connected in series. The middle junction of the two diodes is connected to the output terminal through an inductor and is grounded through an inductor Tcoil and a capacitor PAD. The 4:1 combiner of this embodiment is a driver composed of NMOS and PMOS. It is a driver composed of six groups of inverter structures and six resistors. It generates a 7-level encoding signal. The gate inputs six groups of signals from the pulse generation circuit. The source and drain of each group of inverters are connected and then driven by a resistor to output, thereby serializing the encoded pulse signals to form a high-speed signal. Taking the four-level pulse amplitude modulation signal W0 as an example, the corresponding relationships between the codes L0 to L6 of W0 and the high-order signals MSB0 to MSB1 and the two groups of low-order signals LSB0 to LSB1 are as follows: Figure 4 As shown in (b) of the figure, the 4:1 combiner of this embodiment implements a combinational logic design consisting of a MUX and a combiner, which can reduce parasitic effects at the output nodes of the 4:1 combiner, thereby reducing the output signal rise time (10%-90%) by 20%, reducing circuit power consumption, and improving linearity by 10%.

[0032] like Figure 5 As shown, the 2-bit thermometer code conversion circuit B2T of this embodiment includes a NAND gate, a NOR gate and an XNOR gate. The input 2-bit data includes the upper data MSB and the lower data LSB. The upper data MSB and the lower data LSB are converted into the first output data A through the NAND gate, the lower data LSB are converted into the second output data B through the NOR gate, and the upper data MSB and the lower data LSB are converted into the second output data C through the XNOR gate.

[0033] like Figure 2As shown, the transmitting clock generation circuit of this embodiment includes an AC coupling circuit, a four-phase clock generation circuit, a duty cycle and phase adjustment circuit (capable of adjusting the duty cycle and phase of the clock), a clock rotation selection circuit, a delay module (capable of fine-tuning the clock phase), and a frequency-dividing clock circuit. The AC coupling circuit, the four-phase clock generation circuit, the duty cycle and phase adjustment circuit, and the clock rotation selection circuit are connected in sequence. The output end of the clock rotation selection circuit is divided into two branches, each of which is connected in series with a delay module and a frequency-dividing clock circuit. The frequency-dividing clock circuit of the first branch is respectively connected to the retiming circuit and the pulse generating circuit of the first and second encoding branches, and the frequency-dividing clock circuit of the second branch is respectively connected to the retiming circuit and the pulse generating circuit of the third and fourth encoding branches.

[0034] like Figure 6 As shown, the decoder of this embodiment includes three decoding branches, each of which includes a logic operation circuit, a driving circuit BUF, a signal amplification circuit VGA, a PAM4 decision device, a thermometer code restoration circuit T2B, and a 16:4 demultiplexer. The logic operation circuits of the first and third decoding branches are subtraction circuits SUB, and the logic operation circuit of the second decoding branch is an addition circuit ADD. The subtraction circuit SUB in the first decoding branch is used to subtract the four-level pulse amplitude modulation signals W0 and W1 and use the result as the input signal of the subsequent driving circuit BUF. The subtraction circuit SUB in the third decoding branch is used to convert the four-level pulse amplitude modulation signals W0 and W1 into the input signal of the subsequent driving circuit BUF. Signals W2 and W3 are subtracted and serve as the input signal for the subsequent drive circuit BUF. The adder circuit ADD is used to add the four-level pulse amplitude modulation signals W0-W4 and provide the result as the input signal for the subsequent drive circuit BUF. The drive circuit BUF drives the input signal to generate a drive signal. The signal amplifier circuit VGA is used to amplify the drive signal. The PAM4 decision device decodes the drive signal to generate a 3-bit thermometer code. The thermometer code recovery circuit T2B is used to recover the 3-bit thermometer code into 2-bit data. The 16:4 demultiplexer demultiplexes the 2-bit data to decode two sets of NRZ (non-return-to-zero) signals. In the decoder of this embodiment, the logic operation circuit, the drive circuit BUF, and the signal amplifier circuit VGA form a three-stage differential circuit, which does not generate additional power consumption. The tail current source current variation of the final stage signal amplifier circuit VGA is reduced to 4%, outputting a stable DS-PAM4 signal for subsequent PAM4 decision and decoding.

[0035] like Figure 7As shown, the subtraction circuit SUB of this embodiment is based on a traditional CTLE (continuous time linear equalizer) and includes two input branches. Each input branch includes an inductor, a resistor, and an NMOS transistor connected in sequence. The gates of the NMOS transistors Mn7 and Mn8 of the two input branches each input a four-level pulse amplitude modulation signal, for example Figure 7 (a) The input is two four-level pulse amplitude modulation signals w0 and w1, Figure 7 The input of (b) is two four-level pulse amplitude modulation signals w2 and w3. A variable resistor and a variable capacitor are connected in parallel between the sources of the two input branches of NMOS transistors Mn7 and Mn8 to adjust the signal zero and pole. The drains of the two input branches of NMOS transistors Mn7 and Mn8 serve as the output terminals V out To output the input signal of the subsequent drive circuit BUF, from the output terminal V out The original PAM4 differential signal can be decoded.

[0036] The adding circuit ADD of this embodiment is used to perform a sum operation (W0+W1-W2-W3) on the input terminals in parallel. Figure 8 As shown, the adding circuit ADD of this embodiment is based on a traditional CTLE (Continuous Time Linear Equalizer) and includes four NMOS transistors Mn9 to Mn12. The gates of the NMOS transistors Mn9 to Mn12 are sequentially connected to the four-level pulse amplitude modulation signals W0 to W4. The drains of the NMOS transistors Mn9 and Mn11 are connected to each other as the output terminal V out The negative electrode of the NMOS tube Mn10 and Mn12 are connected to each other as the output terminal V out A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn9 and Mn10 to adjust the signal zero poles. A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn11 and Mn112 to adjust the signal zero poles. The output terminal V out The negative and positive electrodes of the MOSFET are connected to the power supply through resistors and inductors. The four-level pulse amplitude modulation signals W0 and W1, and W2 and W3 are cascaded through the NMOS output (drain) to output the summed differential signal for addition decoding.

[0037] like Figure 6As shown, the receiving clock generation circuit of this embodiment includes an AC coupling circuit, a four-phase clock generation circuit, a phase interpolator, a duty cycle and phase adjustment circuit, a delay module and a frequency-dividing clock circuit. The AC coupling circuit, the four-phase clock generation circuit, the phase interpolator, the duty cycle and phase adjustment circuit are connected in sequence. The output end of the duty cycle and phase adjustment circuit is divided into three branches, each of which is connected in series with a delay module and a frequency-dividing clock circuit, and the output end of the frequency-dividing clock circuit on each branch is respectively connected to the clock signal input end of the PAM4 decision maker and the 16:4 demultiplexer on a corresponding decoding branch to provide a clock signal therefor.

[0038] The four-level pulse amplitude modulation transceiver of this embodiment is manufactured using a 28-nanometer process. After testing, the area of ​​the transmitting end is 0.083m 2 The receiving end area is 0.058m 2 The channel area between the transmitter and receiver is 0.0705m 2 , so the total area is: 0.2115m 2 . Figure 9 A comparison is made between the four-level pulse amplitude modulation transceiver (this transceiver) of this embodiment and an extremely short reach (XSR) DS-PAM4 transmission link. Although the encoding process of the four-level pulse amplitude modulation transceiver (this transceiver) of this embodiment will lose half of the amplitude (-6dB), it can reduce the Nyquist attenuation of the PAM4 signal from 14dB to 8dB, compensating for the 6dB amplitude loss. At the same time, due to the low-frequency characteristics, the pulse width of the signal unit interval is increased from 35.7ps (28GHz) to 52.6ps (19GHz), thereby improving bit error performance.

[0039] Figure 10 The following are the energy consumption ratio simulation results of the transmitter and receiver of the four-level pulse amplitude modulation transceiver in this embodiment, where (a) is the energy consumption ratio simulation result of the transmitter and (b) is the energy consumption ratio simulation result of the receiver. The total energy consumption of the transmitter is 198 mW, which is divided into the energy consumption of the data path, clock path, driver and other parts, with the proportions as follows: Figure 10 As shown in (a) in the figure, the total energy consumption of the receiving end is 161 mW, which is divided into four parts: data path, clock path, other, and SUB&ADD&Buffer&VGA. Among them, SUB&ADD&Buffer&VGA represents the logic operation circuit, drive circuit BUF, and signal amplification circuit VGA in the decoding branch, and their proportions are as follows: Figure 10As shown in (b) of the figure. The transmitter and receiver operate on two differential channels with a maximum trace length of 70 mm. The total insertion loss is 14 dB at 28 GHz (the total insertion loss for 114 G / s CPAM is 8 dB at 19 GHz). Simulation results show that at 112 Gb / s, the energy efficiency of the transmitter and receiver of this embodiment's four-level pulse amplitude modulation transceiver is 0.86 pJ / b and 0.66 pJ / b, respectively.

[0040] Figure 11 Figures 1 and 2 show three simulated 76Gb / s non-return-to-zero (NRZ) code eye diagrams for the first subtraction circuit SUB, the addition circuit ADD, and the second subtraction circuit SUB, respectively, with and without a feedforward equalizer (FFE) in an embodiment of the present invention. Figures (a) through (c) are for the three simulated 76Gb / s NRZ codes without the FFE, and (d) through (f) are for the three simulated 76Gb / s NRZ codes with the FFE. The two subtraction circuit SUB paths are essentially identical. With the FFE, the horizontal and vertical eye openings are 0.26UI and 46mV, respectively. The horizontal and vertical eye openings for the addition circuit ADD are 0.2UI and 40mV, respectively.

[0041] Table 1 shows the results of comparing the four-level pulse amplitude modulation transceiver of this embodiment with other state-of-the-art PAM4 transceivers (ISSCC' 2021 and ISSCC' 2024).

[0042] Table 1: Comparison between this embodiment and existing PAM4 transceivers

[0043] As shown in Table 1, the FoM metric is a comprehensive indicator for evaluating communication system performance, combining three key factors: energy consumption, data throughput, and signal quality. This metric allows for a more comprehensive assessment of system performance, helping to optimize design and select more efficient technical solutions. As shown in Table 1, the four-level pulse amplitude modulation transceiver of this embodiment significantly outperforms other existing PAM4 transceivers (ISSCC' 2021 and ISSCC' 2024) in both energy efficiency and FoM. At a transmission rate of 114 Gb / s, the four-level pulse amplitude modulation transceiver of this embodiment achieves a bit error rate of less than 1×10⁻¹¹ and an energy efficiency of 1.57 pJ / bit, making it suitable for short-distance transmission of less than 70 mm.

[0044] In addition, this embodiment further provides a chip, comprising at least two cores connected to each other, wherein the four-level pulse amplitude modulation transceiver is provided between the two cores.

[0045] In addition, this embodiment further provides an electronic device, including a processor and a memory connected to each other, wherein the processor includes the four-level pulse amplitude modulation transceiver.

[0046] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A four-level pulse amplitude modulation transceiver, characterized in that: The system comprises a transmitting end and a receiving end, wherein the transmitting end comprises an encoder and a transmitting clock generating circuit for providing a clock signal to a decoder, and the encoder is used to encode 6 groups of NRZ signals in combination with a preset first correlation matrix. Generate 4 groups of four-level pulse amplitude modulation signals W0~W3 and send them as two groups of pseudo differential signals to the receiving end, the receiving end includes a decoder and a receiving clock generation circuit for providing a clock signal to the decoder, the decoder is used to combine the 4 groups of four-level pulse amplitude modulation signals W0~W3 with a preset second correlation matrix The decoded NRZ signals are 6 groups, each of which includes 3 groups of high-order signals MSB0 to MSB2 and 3 groups of low-order signals LSB0 to LSB2.

2. The four-level pulse amplitude modulation transceiver according to claim 1, characterized in that The first correlation matrix and the second correlation matrix The function expression is: ， 。 3. The four-level pulse amplitude modulation transceiver according to claim 1, characterized in that: The encoder includes four encoding branches, the high-order signal MSB0 and the low-order signal LSB0 serve as the input of the first encoding branch, the high-order signal MSB1 and the low-order signal LSB1 serve as the input of the second and third encoding branches at the same time, and the high-order signal MSB2 and the low-order signal LSB2 serve as the input of the fourth encoding branch. The encoding branch includes a 16:4 multiplexer, a 2-bit thermometer code circuit B2T, a retiming circuit, a single slip circuit and a pulse generating circuit connected in sequence, wherein the 2-bit thermometer code circuit B2T is used to convert the input 2-bit data into a 3-bit thermometer code, the retiming circuit uses a 9.5GHz clock to sample the 3-bit thermometer code signal to obtain a retiming signal, and the single slip circuit is used to convert the sampled The single-ended retimed signal obtained in this way is converted into a differential signal and a pulse coding signal is generated through a pulse generating circuit. The first coding branch and the second coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo differential signal composed of generated four-level pulse amplitude modulation signals W0 and W1. The third coding branch and the fourth coding branch use two interleaved 4:1 combiners and drivers to output a 114Gbps pseudo differential signal composed of four-level pulse amplitude modulation signals W2 and W3. The pulse generating circuit includes four parallel pulse generating units, each of which is composed of NMOS transistors Mn1 to Mn6 and PMOS transistors Mp1 to Mp8. The input data D0 is output according to The gates of the PMOS transistors Mp1, Mp2, and Mp4 are connected to the clock signal Clk180. The NMOS transistor Mn2 and the PMOS transistor Mp3 are arranged in series between the middle node of the NMOS transistor Mn1 and the PMOS transistor Mp2 and the ground, and the gates are connected to the clock signal Clk270. The source of the PMOS transistor Mp4 is connected to the middle node of the NMOS transistors Mn2 and the PMOS transistor Mp3, and the drain is grounded. The middle node of the NMOS transistors Mn2 and the PMOS transistor Mp3 is connected to the gate of the PMOS transistor Mp5 to output the positive pulse coding signal of the data D0 through the PMOS transistor Mp5. The NMOS transistor Mn1 The gate of the NMOS transistor Mn4 is connected to the gate of the PMOS transistor Mp7, the NMOS transistors Mn3, PMOS transistors Mp7, and Mp6 are connected in series between the power supply and ground in sequence, the gates of the NMOS transistors Mn3 and PMOS transistors Mp6 are connected to each other and to the gate of the NMOS transistor Mn5, the NMOS transistor Mn4 and the PMOS transistor Mp8 are arranged in series between the power supply and ground and their gates are connected to the clock signal Clk90, the NMOS transistor Mn5 connects the node between the NMOS transistor Mn4 and the PMOS transistor Mp8 to the power supply, and the NMOS transistor Mn5 also connects the node between the NMOS transistor Mn4 and the PMOS transistor Mp8 to the gate of the NMOS transistor Mn6 to output the inverse pulse coding signal of the data D0 through the NMOS transistor Mn6.

4. The four-level pulse amplitude modulation transceiver according to claim 3, characterized in that: The 4:1 combiner includes six inverters with a common output end. The inverters are each composed of an NMOS transistor and a PMOS transistor connected in series with their gates connected. The input ends of the six inverters are respectively connected to six input signals AP0, AP1, BP0, BP1, CP0, and CP1 from two coding branches and are respectively connected to the common output end through a resistor connected in series to generate a 7-level coding signal. The output end is connected to an electrostatic protection circuit ESD. The electrostatic protection circuit ESD includes two diodes connected in series. The middle junction of the two diodes is connected to the output end through an inductor and is grounded through an inductor Tcoil and a capacitor PAD.

5. The four-level pulse amplitude modulation transceiver according to claim 3, characterized in that: The 2-bit thermometer code conversion circuit B2T includes a NAND gate, a NOR gate and an XNOR gate. The input 2-bit data includes the high-order data MSB and the low-order data LSB. The high-order data MSB and the low-order data LSB are generated into the first-bit output data A through the NAND gate, the low-order data LSB is generated into the second-bit output data B through the NOR gate, and the high-order data MSB and the low-order data LSB are generated into the second-bit output data C through the XNOR gate.

6. The four-level pulse amplitude modulation transceiver according to claim 3, characterized in that: The sending clock generation circuit includes an AC coupling circuit, a four-phase clock generation circuit, a duty cycle and phase adjustment circuit, a clock rotation selection circuit, a delay module and a frequency-dividing clock circuit. The AC coupling circuit, the four-phase clock generation circuit, the duty cycle and phase adjustment circuit, and the clock rotation selection circuit are connected in sequence. The output end of the clock rotation selection circuit is divided into two branches, each of which is connected in series with a delay module and a frequency-dividing clock circuit. The frequency-dividing clock circuit of the first branch is respectively connected to the retiming circuit and the pulse generating circuit of the first and second encoding branches, and the frequency-dividing clock circuit of the second branch is respectively connected to the retiming circuit and the pulse generating circuit of the third and fourth encoding branches.

7. The four-level pulse amplitude modulation transceiver according to claim 1, characterized in that: The decoder includes three decoding branches, each of which includes a logic operation circuit, a driving circuit BUF, a signal amplification circuit VGA, a PAM4 decision device, a thermometer code restoration circuit T2B and a 16:4 demultiplexer, and the logic operation circuits of the first and third decoding branches are subtraction circuits SUB, and the logic operation circuit of the second decoding branch is an addition circuit ADD. The subtraction circuit SUB in the first decoding branch is used to subtract the four-level pulse amplitude modulation signals W0 and W1 and use them as the input signal of the subsequent driving circuit BUF. The subtraction circuit SUB in the third decoding branch is used to subtract the four-level pulse amplitude modulation signals W2 and W3 and use them as the input signal of the subsequent driving circuit BUF. The addition circuit ADD is used to add the four-level pulse amplitude modulation signals W0~W4 and use them as the input signal of the subsequent driving circuit BUF. The driving circuit BUF is used The input signal is driven to generate a driving signal, the signal amplification circuit VGA is used to amplify the driving signal, the PAM4 decision device is used to decode the driving signal to generate a 3-bit thermometer code, the thermometer code restoration circuit T2B is used to restore the 3-bit thermometer code to 2-bit data, and the 16:4 demultiplexer is used to demultiplex the 2-bit data to obtain two groups of NRZ signals by decoding; the subtraction circuit SUB includes two input branches, each input branch includes an inductor, a resistor, and an NMOS transistor connected in sequence, the gates of the NMOS transistors Mn7 and Mn8 of the two input branches each input a four-level pulse amplitude modulation signal, a variable resistor and a variable capacitor are connected in parallel between the sources of the NMOS transistors Mn7 and Mn8 of the two input branches for adjusting the signal zero pole, and the drains of the NMOS transistors Mn7 and Mn8 of the two input branches serve as the output terminal V out To output the input signal of the subsequent driving circuit BUF; the adding circuit ADD includes four NMOS tubes Mn9 to Mn12, the gates of the NMOS tubes Mn9 to Mn12 are sequentially connected to the four-level pulse amplitude modulation signals W0 to W4, and the drains of the NMOS tubes Mn9 and Mn11 are connected to each other as the output terminal V out The negative electrode of the NMOS tube Mn10 and Mn12 are connected to each other as the output terminal V out A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn9 and Mn10 to adjust the signal zero poles. A variable resistor and a variable capacitor are connected in parallel between the sources of NMOS tubes Mn11 and Mn112 to adjust the signal zero poles. The output terminal V out The negative and positive electrodes are connected to the power supply through resistors and inductors.

8. The four-level pulse amplitude modulation transceiver according to claim 7, characterized in that: The receiving clock generation circuit includes an AC coupling circuit, a four-phase clock generation circuit, a phase interpolator, a duty cycle and phase adjustment circuit, a delay module, and a frequency-dividing clock circuit. The AC coupling circuit, four-phase clock generation circuit, phase interpolator, duty cycle and phase adjustment circuit are connected in sequence. The output end of the duty cycle and phase adjustment circuit branches into three branches, each of which is connected in series with a delay module and a frequency-dividing clock circuit. The output end of the frequency-dividing clock circuit on each branch is respectively connected to the clock signal input end of the PAM4 decision maker and the 16:4 demultiplexer on a corresponding decoding branch to provide a clock signal therefor.

9. A chip comprising at least two interconnected core particles, characterized in that: The four-level pulse amplitude modulation transceiver according to any one of claims 1 to 8 is disposed between the two core particles.

10. An electronic device comprising a processor and a memory connected to each other, characterized in that: The processor includes the four-level pulse amplitude modulation transceiver according to any one of claims 1 to 8.

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