Frame conflict processing method and device for power line carrier signal

Abstract

The invention discloses a frame conflict processing method and device for a power line carrier signal, and belongs to the technical field of power line carrier communication. The method comprises the following steps that: after receiving a current signal frame and transmitting data of the current signal frame to a memory module, a baseband module sets up a receiving completion signal for indicating a receiving completion state; when the receiving completion signal is in the set-up state, if the baseband module detects a frame synchronization completion signal, an overflow flag signal is set up; and according to a frame conflict processing strategy, based on the overflow flag signal, executing a frame conflict processing operation related to the current signal frame or the next signal frame. By introducing a frame conflict detection and processing mechanism based on the receiving completion signal and the overflow mark signal, frame data processing conflicts can be quickly handled in the continuous frame receiving process, data disorder or loss is avoided, and the receiving stability and data integrity of a communication system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power line carrier communication, and in particular relates to a method and device for processing frame conflicts of a power line carrier signal. Background Art

[0002] With the development of high-speed power line communication (HPLC) technology, it has gained widespread application in smart grids, smart meters, and distribution automation. These communication systems, which use power lines as the transmission medium, face complex channel environments susceptible to transient interference, narrowband interference, and background noise. To improve communication stability and data throughput, an increasing number of HPLC systems are adopting higher-bandwidth and higher-frequency signal frame transmission methods to meet the high-speed or low-latency communication requirements of real-time reporting, grid status monitoring, and control command issuance. In these systems, upper-layer software frequently exchanges data with HPLC chips for subsequent networking and channel estimation. Because signal frames are transmitted continuously with short inter-frame intervals, signal receiving devices must complete the reception, parsing, transfer, and notification processing of the previous frame within a very short timeframe to ensure smooth transition to the next frame.

[0003] However, related technologies still have obvious shortcomings when processing this type of high-density continuous frame structure: if the CPU fails to complete the reading and status clearing operations of the previous frame in time due to heavy task load or scheduling lag, the next frame may have entered synchronization and completed part of the reception process. At this time, the system will face a typical conflict state of "the previous frame has not been processed and the next frame has started", which can easily cause problems such as cache data misalignment, frame feature information overwriting, or control status confusion. Some traditional systems rely solely on interrupts to respond to conflicts through software, but the timeliness of interrupt services is limited by the current CPU load and response capabilities, and often cannot effectively guarantee data consistency under continuous frame reception. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention proposes a method and apparatus for handling frame conflicts in power line carrier signals, thereby enabling rapid identification and strategic handling of conflicts during the reception of consecutive frames, thereby improving data integrity and processing efficiency in high-speed communication scenarios.

[0005] In a first aspect, the present invention provides a method for processing frame conflicts of a power line carrier signal, the method being applied to a signal receiving device, the signal receiving device including a baseband module and a memory module; the method comprising: After the baseband module completes receiving the current signal frame and transmits the data of the current signal frame to the memory module, it sets a reception completion signal for indicating the reception completion state; During the period when the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, an overflow flag signal is set; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame; According to the frame conflict processing strategy, a frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal.

[0006] According to the frame conflict processing method of the power line carrier signal provided by the present invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, the reception completion signal is set, thereby realizing a clear division of the state between the frame reception and the processing flow, and facilitating the processing module to judge the data reading timing; during the period when the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set, and the access behavior of the next frame can be detected in time, and a flag signal is generated for alarm, thereby realizing fast and automatic recognition of the conflict state, without waiting for the processor to participate or polling judgment, and getting rid of the dependence on the interrupt response or software scheduling mechanism; furthermore, according to the frame conflict The conflict handling strategy executes the frame conflict handling operation related to the current signal frame or the next signal frame based on the overflow flag signal. The baseband module triggers the conflict strategy by itself, supports automatic frame conflict handling within the hardware, and does not require the processor to participate in the judgment and control signal initiation, thereby reducing the control path delay and improving the robustness and overall processing efficiency in high-speed receiving scenarios. In addition, by introducing configurable or dynamically selected conflict handling strategies, it supports flexible response to the conflict of retaining the current frame or receiving the next frame according to application requirements, thereby improving the system adaptability and processing efficiency, effectively reducing the risk of data loss and state disorder caused by frame conflicts, and improving the reliability and processing efficiency of the system in high-density receiving scenarios.

[0007] According to one embodiment of the present invention, performing a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy includes: When the overflow flag signal is in a set state, the baseband module generates an overflow reset signal for triggering an interrupt; In response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame of data; The baseband module resets the reception completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0008] In the above embodiment, after a conflict is detected, the baseband module actively generates an overflow reset signal, and performs cache clearing and reception termination operations based on the signal, and then synchronizes the reception completion signal and the overflow reset signal to zero, thereby achieving rapid closed-loop processing of the frame conflict state, avoiding uncontrollable delays caused by relying on CPU response, ensuring timely handling of the conflict state, and avoiding overlapping or overwriting of consecutive frames by clearing the next frame data and terminating reception, thereby ensuring the integrity of each frame of data. In addition, the entire process is independently completed by the baseband module to complete the conflict detection and processing logic, without the need for CPU participation, without response delay, and completely avoiding the problem of conflict response lag caused by software busyness or scheduling delays. It not only ensures the real-time nature of the communication process, but also maintains the continuity and stability of the CPU software tasks. Even if consecutive frames arrive closely or the CPU is under high load, it can still ensure stable operation of the system, achieving efficient and reliable data protection in frame conflict scenarios.

[0009] According to one embodiment of the present invention, the signal receiving device further includes a processing module; wherein the performing of a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy further includes: The processing module stops the reading operation of the current signal frame when detecting the overflow flag signal; The processing module sets the reception completion signal to zero to read the next signal frame.

[0010] In the above embodiment, the processing module interrupts the continued reading of the current frame to avoid extracting invalid data after the frame data is partially overwritten, thereby improving the validity of the frame data; and by actively setting the reception completion signal to zero, it helps to shorten the conflict processing time, accelerate the processing preparation of the next frame data, and improve the overall system processing rhythm.

[0011] In a second aspect, the present invention provides a frame conflict processing device, applied to a signal receiving device, the device comprising: The signal trigger module is used to set a reception completion signal indicating a reception completion status after the baseband module completes reception of the current signal frame and transmits the data of the current signal frame to the memory module; a conflict trigger module, configured to set an overflow flag signal if the baseband module detects a frame synchronization completion signal while the reception completion signal is in the set state; the overflow flag signal is used to indicate that a processing state of the current signal frame conflicts with a reception behavior of the next signal frame; The conflict processing module is used to perform a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy.

[0012] According to the frame conflict processing device provided by the present invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, the reception completion signal is set, thereby realizing a clear division of the state between the frame reception and the processing flow, and facilitating the processing module to judge the data reading timing; during the period when the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set, and the access behavior of the next frame can be detected in time, and a flag signal is generated for alarm, thereby realizing fast and automatic recognition of the conflict state, without waiting for the processor to participate or polling judgment, and getting rid of the dependence on interrupt response or software scheduling mechanism; furthermore, according to the frame conflict processing strategy The invention discloses a frame conflict handling method which is briefly described. It performs frame conflict handling operations related to the current signal frame or the next signal frame based on the overflow flag signal. The baseband module triggers the conflict strategy by itself, supports automatic frame conflict handling in the hardware, and does not require the processor to participate in the judgment and control signal initiation, thereby reducing the control path delay and improving the robustness and overall processing efficiency in high-speed receiving scenarios. In addition, by introducing a configurable or dynamically selectable conflict handling strategy, it supports flexible response to the conflict of retaining the current frame or receiving the next frame according to application requirements, thereby improving the system adaptability and processing efficiency, effectively reducing the risk of data loss and state disorder caused by frame conflicts, and improving the reliability and processing efficiency of the system in high-density receiving scenarios.

[0013] In a third aspect, the present invention provides a signal receiving device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the method for processing frame conflicts of power line carrier signals as described in the first aspect above is implemented.

[0014] In a fourth aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for processing frame conflicts of power line carrier signals as described in the first aspect above is implemented.

[0015] In a fifth aspect, the present invention provides a chip comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a computer program or instruction to implement the frame conflict processing method of the power line carrier signal as described in the first aspect above.

[0016] In a sixth aspect, the present invention provides a computer program product, comprising a computer program, which, when executed by a processor, implements the frame conflict processing method for power line carrier signals as described in the first aspect above.

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which: Figure 1 1 is a schematic diagram of an application scenario of a frame conflict processing method for a power line carrier signal provided in some embodiments of the present invention; Figure 2 is a schematic diagram of a power line carrier communication signal processing process provided in some embodiments of the present invention; Figure 3 It is a schematic diagram of the principle of underlying data interaction provided in some embodiments of the present invention; Figure 4 is a schematic diagram of signals under normal conditions provided in some embodiments of the present invention; Figure 5 is a schematic diagram of signals under a delay condition provided in some embodiments of the present invention; Figure 6 is a flow chart of a method for processing frame conflicts of a power line carrier signal provided in some embodiments of the present invention; Figure 7 is a signal diagram of a frame conflict handling strategy provided in some embodiments of the present invention; Figure 8 is a signal diagram of another frame conflict handling strategy provided in some embodiments of the present invention; Figure 9 is a schematic diagram of a process for synchronizing feature information provided in some embodiments of the present invention; Figure 10 is a signal diagram of a feature information synchronization process provided in some embodiments of the present invention; Figure 11 is an overall schematic diagram of the feature information synchronization process provided in some embodiments of the present invention; Figure 12 is a structural diagram of a frame conflict processing device provided in some embodiments of the present invention; Figure 13 It is a structural diagram of a signal receiving device provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meanings as commonly understood by those skilled in the art to which the present invention pertains. The terms used in the specification and application of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The terms "including" and "having," as well as any variations thereof, in the specification and claims of the present invention and the accompanying drawings are intended to cover non-exclusive inclusions. The terms "first," "second," etc., in the specification and claims of the present invention and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order or a primary-secondary relationship.

[0021] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "attached" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0023] The term "and / or" in this disclosure simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this disclosure generally indicates that the related objects are in an "or" relationship.

[0024] The term "multiple" used in the present invention refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple sheets" refers to more than two sheets (including two sheets).

[0025] The following describes in detail the frame conflict processing method of the power line carrier signal provided by the embodiment of the present invention through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0026] Figure 1 Schematic diagram of an application scenario of a method for processing frame conflicts of a power line carrier signal provided in some embodiments of the present invention. The method for processing frame conflicts of a power line carrier signal provided in an embodiment of the present invention can be applied to Figure 1In the application environment of the power line communication system shown in FIG. The power line communication system includes a signal transmitting device and a signal receiving device. The signal transmitting device is used to transmit power line communication signals, and the signal receiving device is used to receive communication signals and perform subsequent processing such as channel estimation.

[0027] The signal transmitting device and the signal receiving device may be, for example, a computer device, which may be a power line communication terminal, a concentrator device, a smart meter, a device with an embedded communication module, or a communication test terminal. Alternatively, the computer device may be a device or intelligent robot with computing capabilities, configured to perform signal reception, processing, and subsequent processing tasks in the present invention.

[0028] Based on the above application scenarios, the present invention can be applied to scenarios of power line carrier communication signal processing. Figure 2 FIG. 1 is a schematic diagram of a power line carrier communication signal processing process provided in some embodiments of the present invention. Figure 2 As shown, in an exemplary embodiment, the transmitter (i.e., the signal transmitting device) encodes the frame control data and payload data, then adds a preamble to the frame signal through an inverse fast Fourier transform (IFFT), a cyclic prefix, and windowing. The preamble is then transmitted to the power line channel via an analog front-end. The receiver (i.e., the signal receiving device) receives the signal through the analog front-end and performs preliminary signal alignment using automatic gain control and a clock or frame synchronization mechanism. The receiver then converts the signal to the frequency domain using a fast Fourier transform (FFT) module and performs symbol recovery through demodulation. The demodulated frame control data and payload data are then decoded to recover the frame control data and data payload. All of this is accomplished within the receiver's baseband. Furthermore, the receiver uses a buffering mechanism to temporarily store relevant frame data for the current signal frame, ensuring data consistency and system stability even when multiple frames arrive consecutively.

[0029] Figure 3 This is a schematic diagram of the principle of underlying data interaction provided in some embodiments of the present invention. Figure 3As shown, the baseband module first receives the frame data (including the preamble, frame control data, and data payload), undergoing signal demodulation and field parsing. After processing the frame data, the baseband module writes the frame control data and data payload to the memory module (i.e., system memory). Its internal hardware logic then sets the receive completion flag (rx-end-flag) at time t1, switching from its default low state to a high state, indicating that the reception and transmission of the frame data for that signal frame has been completed. After the processing module (i.e., the CPU) detects the high state of the receive completion flag, it begins reading the corresponding frame data from system memory. After reading is complete, the processing module resets the receive completion flag to zero at time t2, returning it from a high state to a low state to signal the completion of the processing. This establishes a handshake mechanism, coordinated by the baseband and processing modules, that ensures reliable setting and release of the receive completion flag, improving the reliability of frame data reading.

[0030] The following further describes the normal timing process of the above handshake mechanism when frames arrive continuously. Figure 4 Schematic diagram of signals under normal conditions provided in some embodiments of the present invention. Figure 4 As shown, in the context of a system continuously receiving multiple frames of data, after the baseband module completes reception and processing of frame 1, it writes the frame control data and data payload to the system memory at time t1 and sets the receive completion signal (rx-end-flag) to indicate that the data writing of frame 1 is complete. Subsequently, the processing module detects that the receive completion signal is in a high-level state, confirming that the current frame data is ready for reading and initiating the read operation. After the processing module completes reading frame 1 data, at time t2, the receive completion signal is reset to zero under software control, that is, it transitions from a high level to a low level, notifying the baseband module that processing of the current frame data has ended and that the next frame data reception process can begin.

[0031] exist Figure 4 In the normal data flow scenario shown, the timely setting and zeroing of the reception completion signal realizes the effective synchronization of the frame data reception status between the baseband module and the processing module, which helps to ensure the data integrity and reading timing of the system when continuously receiving multiple signal frames. However, in the actual operation process, the CPU often undertakes multiple parallel tasks at the same time, and there is a risk of response delay. Especially in scenarios with short frame intervals and high processing pressure, the zeroing operation of the reception completion signal may not be completed within the expected time window, thereby affecting the normal reception and storage of subsequent frames. In order to illustrate the potential data conflict problem caused by this type of response delay, the following shows the overwriting and misreading caused by the continuous reception of frame data when the CPU fails to promptly set the reception completion signal to zero.

[0032] Figure 5Schematic diagram of signals under time delay provided in some embodiments of the present invention. Figure 5 As shown in the figure, at time t1, the baseband module transfers frame 1 data to system memory and sets the receive completion signal (rx-end-flag). Under normal circumstances, it should be reset to zero at time t2. However, because the CPU is currently processing other tasks and cannot respond in time, the receive completion signal is not reset to zero in time at time t2 and remains high. Assume that the receive completion signal is reset to zero at time t2', and the baseband module has already started receiving frame 2 data. In this case, the data extracted by the CPU between t1 and t2' contains a mixture of frame 1 and frame 2 data, which will cause errors in upper-layer application processing. Subsequent frame 2 data will also be missing, and subsequent processing will also cause errors.

[0033] It's important to note that while system designs typically reserve frame intervals for the CPU to complete read and flag zeroing operations, the CPU response process is software-controlled, subject to inevitable latency fluctuations. Any delay in response directly impacts the accuracy of cached data, making coverage conflicts more likely to occur, especially when receiving dense, continuous frames.

[0034] This shows that the traditional approach of relying on CPU interrupts to handle receive conflicts in the intermediate buffer has an inherent timing disadvantage. This not only easily leads to conflict identification delays, but also increases CPU load, reducing overall system efficiency and stability. Furthermore, frequent interrupt triggering increases the CPU burden, affecting overall system processing efficiency.

[0035] In view of this, the present invention provides a universal frame conflict processing method applicable to a continuous signal frame structure, which realizes conflict detection and response control of the frame reception status and the new frame access behavior, significantly improving the processing stability, response speed and module decoupling capability of the signal receiving device in a high-density data flow environment, and providing a solid basic support for subsequent receiving path management and channel feature protection strategies.

[0036] An embodiment of the present invention provides a method for processing frame conflicts of power line carrier signals. The execution subject of the method can be a signal receiving device or a functional module or functional entity in the signal receiving device that can implement the method for processing frame conflicts of power line carrier signals.

[0037] The following describes a method for processing frame conflicts of a power line carrier signal provided by an embodiment of the present invention by taking a signal receiving device as an example.

[0038] Among them, the signal receiving device includes a baseband module, a memory module and a processing module. The baseband module is responsible for demodulation and preliminary processing of signal frames, and the memory module is used to store received signal frame data.

[0039] Exemplarily, a baseband module refers to a hardware or software / hardware combination that performs underlying communication operations such as wireless signal demodulation, channel estimation, field identification, and physical layer processing. For example, a baseband module can be a hardware processing unit composed of an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), or an ASIC (Application Specific Integrated Circuit).

[0040] The memory module refers to the system storage resource used to store the complete signal frame data transmitted by the baseband module. It can be on-chip RAM (Random Access Memory), DDR (Double Data Rate) memory, or an embedded cache module.

[0041] The processing module may include an embedded processor (such as an ARM (Advanced RISC Machines) core), an MCU (Microcontroller Unit), or a main control CPU (Central Processing Unit) running in conjunction with an operating system, which is used to read the frame data in the memory module and, based on the feature information, complete further upper-layer business processing, conflict decision-making, control signal issuance, and flag signal clearing operations.

[0042] Figure 6 FIG. 1 is a flow chart of a method for processing frame conflicts of power line carrier signals provided in some embodiments of the present invention. Figure 6 As shown, the method for processing frame conflicts of power line carrier signals includes: steps 610 to 630.

[0043] Step 610: After the baseband module completes receiving the current signal frame and transmits the data of the current signal frame to the memory module, it sets a reception completion signal for indicating a reception completion status.

[0044] The receive completion signal is a status indicator signal, set by the baseband module to indicate that the reception operation of the current signal frame has completed and the next processing phase can be entered. This signal helps coordinate read and write synchronization between the baseband and subsequent processing modules, preventing overlap between frames.

[0045] The baseband module receives the current signal frame (for example, frame 1) and completes data parsing and demodulation. After completing data processing, the baseband module writes the FC (Frame Control) and PL (Payload) fields of frame 1 to the memory module and asserts the receive completion signal, rx-end-flag. This signal defaults to a low level. When asserted, it indicates that the current frame has been transmitted and the system is ready for subsequent read operations.

[0046] The baseband module completes the process of receiving the current signal frame and transferring its data to the memory module. This process not only includes the direct transmission of the FC field (Frame Control Field) and PL field (Data Payload Field) in the signal frame, but also fully supports the initial receive processing flow. Specifically, when constructing a frame of power line carrier signal data, the signal transmitter typically first performs universal channel coding on the original byte data to be transmitted (for example, the hexadecimal number 0x12) to improve error resilience. The encoded result is then interleaved to mitigate the effects of burst interference or narrowband noise. The transmitter then inserts multiple preamble symbols before the encoded data. Preamble symbols typically consist of multiple synchronization training symbols or pilots, which are used by the receiver for frame synchronization and channel estimation. For example, the original data 0x12, after coding and interleaving, is mapped to "110011." A preamble sequence "010101" is then inserted, ultimately forming the complete transmitted bit string "010101110011" as a complete physical layer signal frame.

[0047] The baseband module of the signal receiving device first receives the bit stream (i.e., a composite frame consisting of the preamble, FC, and PL). Within the synchronization window, it synchronizes to the frame by detecting multiple consecutive synchronization peaks or matching the local frame preamble sequence. This triggers the generation of the corresponding frame synchronization start (sync-begin) and frame synchronization complete (frame-synced) signals. The baseband module also performs channel estimation and equalization, using the preamble symbols to calculate CE and estimate the channel response. The signal receiving device also performs deinterleaving and decoding, performing soft-decision decoding or maximum likelihood decoding on the payload portion of the FC and PL fields in the received bit stream to recover the original data bytes (e.g., 0x12). Furthermore, the receiving end performs checksums and field parsing, such as performing a CRC check on the frame control field and parsing the length / address fields. Finally, if the decoding result is valid, the baseband module writes the decoded result corresponding to the signal frame (i.e., 0x12) to the system memory module and simultaneously asserts the receive completion signal (Rx-end-flag) to notify the processing module (e.g., the CPU) that the data is readable.

[0048] Step 620: While the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0049] The overflow flag is a conflict indicator, indicating an abnormal state where the previous frame has not yet been processed but the next frame has begun entering the receive path. This signal triggers conflict management, enabling the receiving device to promptly switch between normal processing and frame conflict handling to avoid data loss or status errors.

[0050] If the baseband module detects a frame synchronization completion signal while the receive completion signal rx-end-flag is still set (high), it indicates that frame synchronization processing for the next signal frame (for example, frame 2) has completed. In this case, the communication system faces a conflict scenario, that is, the previous frame has not yet been released, and the next frame has begun to be received. In this case, the baseband module generates the overflow flag signal overflow-flag to explicitly indicate that a new receive action has occurred while the current signal frame has not yet been processed, indicating a potential data conflict.

[0051] Step 630: According to the frame conflict processing strategy, perform a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal.

[0052] The frame collision handling strategy is a predefined conflict response plan for the signal receiving device to handle overlapping frames. This strategy includes strategies for retaining and discarding frames, along with corresponding behavior control logic, state setting and clearing sequences, and other parameters. Properly setting this strategy helps ensure system processing stability in scenarios with continuous frame reception, improving overall communication quality.

[0053] When a conflict is detected and an overflow flag is generated, the baseband module performs frame conflict handling according to a pre-set frame conflict handling strategy. This strategy determines whether to retain the previous frame or the current frame based on factors such as system load and processing priority.

[0054] For example, frame conflict handling strategies may include, but are not limited to, interrupting current reception, discarding new frames, latching old frames, enabling double buffering, and clearing the next frame. The baseband module will select differentiated conflict clearing actions for the current or next frame based on the state characteristics at the time of the conflict, thereby ensuring stable system operation.

[0055] For example, in a wireless communication system based on the OFDM (Orthogonal Frequency Division Multiplexing) signal structure, the baseband module asserts a receive completion signal after receiving all symbols of frame 1 and transferring them to memory via DMA. However, since the upper-layer CPU has not yet completed data reading, if frame 2 has already begun receiving after synchronization symbol detection, the baseband module generates an overflow flag and then handles the conflict according to a pre-set frame conflict handling strategy. For example, if the system prioritizes retaining frame 1 data, the reception process of frame 2 is discarded and its buffer area is cleared. If frame 2 must be retained, the reception status of frame 1 is cleared and its read path is released for the new frame, and so on.

[0056] The frame conflict processing method of the power line carrier signal provided by the embodiment of the present invention sets the reception completion signal after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, thereby realizing a clear division of the state between the frame reception and the processing flow, and facilitating the processing module to judge the data reading timing; while the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set, and the access behavior of the next frame can be detected in time, and a flag signal is generated for alarm, thereby realizing fast and automatic recognition of the conflict state, without waiting for the processor to participate or polling judgment, and getting rid of the dependence on interrupt response or software scheduling mechanism; furthermore, according to the frame conflict The conflict handling strategy executes the frame conflict handling operation related to the current signal frame or the next signal frame based on the overflow flag signal. The baseband module triggers the conflict strategy by itself, supports automatic frame conflict handling within the hardware, and does not require the processor to participate in the judgment and control signal initiation, thereby reducing the control path delay and improving the robustness and overall processing efficiency in high-speed receiving scenarios. In addition, by introducing configurable or dynamically selected conflict handling strategies, it supports flexible response to the conflict of retaining the current frame or receiving the next frame according to application requirements, thereby improving the system adaptability and processing efficiency, effectively reducing the risk of data loss and state disorder caused by frame conflicts, and improving the reliability and processing efficiency of the system in high-density receiving scenarios.

[0057] In the actual communication process, frames may arrive continuously. The signal receiving device needs to accurately determine when to enter the next frame reception process in order to realize the pre-triggering of frame conflict identification and control.

[0058] To this end, in some embodiments, the baseband module detects a frame synchronization completion signal, including: the baseband module monitors the synchronization sequence in the input signal, and when a synchronization sequence matching a preset frame format is detected, generates a frame synchronization start signal to indicate that the frame synchronization detection of the next signal frame has been started; after completing the confirmation of the frame synchronization position, the baseband module generates a frame synchronization completion signal, and the frame synchronization completion signal is used to indicate that the synchronization process of the next signal frame currently received has been completed.

[0059] Specifically, during signal reception, the baseband module first continuously monitors the synchronization sequence in the incoming signal. For example, a sliding window can be set to perform a matching operation on the leading region of the received signal to identify whether a sequence pattern matches a preset frame structure. If a continuous correlation peak or characteristic pattern that meets the requirements is detected, a frame synchronization start signal (sync-begin) is triggered, indicating that the synchronization detection phase of the next signal frame has begun.

[0060] The baseband module then performs frame synchronization on the input signal, such as locating the boundary between the synchronization symbols SYNCP (Synchronization Pattern) and SYNCM (Synchronization Channel Midpoint) or determining the frame header position using the maximum correlation value. Once the frame synchronization position is successfully confirmed, the baseband module generates a frame synchronization complete signal (frame-synced), indicating the end of the current synchronization process and allowing the reception process to proceed to the frame control segment and data payload segment.

[0061] Taking a typical OFDM frame structure as an example, its frame header typically contains multiple preamble symbols for frame synchronization, frequency offset estimation, and channel estimation. The communication system preconfigures a preset frame format and decision threshold. At time t0, the baseband module detects the presence of three or more similar synchronization peaks in the input signal and generates a frame synchronization start signal (sync-begin), indicating that synchronization detection for frame 2 has begun. Next, the baseband module confirms the synchronization position based on a sliding window matching mechanism, for example, determining the intersection of SYNCP and SYNCM, and generates a frame synchronization completion signal (frame-synced), indicating that synchronization for frame 2 is complete and that reception of its FC and PL fields can begin. If the previous frame, frame 1, has not yet been read, the baseband module combines this frame synchronization completion signal with the reception completion signal (Rx-end-flag) to trigger the subsequent frame conflict handling process.

[0062] In the above-described embodiment, by introducing a synchronization sequence matching and frame synchronization signal generation mechanism into the baseband module, the arrival of the next frame signal can be quickly and accurately identified without CPU involvement. This helps improve the accuracy of boundary detection during frame reception and ensures that the frame conflict handling process has an accurate basis for starting judgment. Furthermore, this mechanism effectively reduces system response latency, avoids data misreading or overwriting issues caused by hardware and software asynchrony, and enhances the robustness and real-time performance of the overall communication system.

[0063] It should be noted that the frame conflict handling method for power line carrier signals provided by the present invention can be applied to communication systems with a continuous frame structure. In such a communication system, one scenario is when multiple signal frames are arranged in a continuous sequence, and the interframe interval between adjacent signal frames is less than the shortest read cycle of the processing module. In other words, when the data extraction of the previous frame has not yet been completed, the next frame has already begun to arrive and enter the synchronization phase.

[0064] This type of system is common in high-density, high-speed data communication scenarios, such as power line carrier (HPLC), OFDM systems, or point-to-point communications between specific embedded devices. Because there is no buffering time between frames, the processing period of frame 1 can easily overlap with the reception period of frame 2, leading to frame collisions. In this context, the frame collision handling strategy proposed in this invention can significantly improve system stability.

[0065] The following will respectively describe the three frame conflict processing strategies proposed in the present invention to more clearly illustrate the specific coping methods under different conflict conditions.

[0066] It should be noted that the classification and implementation of the frame conflict handling strategies are merely exemplary descriptions and do not limit the scope of protection of the present invention. Without departing from the core concept of the present invention, the processing flow of the relevant strategies can be adapted and expanded according to the actual system design.

[0067] In some embodiments, according to the frame conflict processing strategy, a frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, including: when the overflow flag signal is in the set state, the baseband module generates an overflow reset signal for triggering an interrupt; in response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame data; the baseband module sets the reception completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0068] When the baseband module detects that the data of the current signal frame has been transmitted to the memory module and the reception completion signal is in the set state, and starts to receive the next frame of data, it will set the overflow flag signal (overflow-flag) to indicate the occurrence of a frame conflict.

[0069] Under the current frame collision handling strategy, if the overflow flag is set, the baseband module automatically generates an overflow reset signal (overflow-rst). This signal serves as a trigger, initiating a reset operation based on the signal. A reset operation means that, in the event of a frame collision, the baseband module actively suspends processing of the next frame. For example, this can reset modules such as the baseband deinterleaving and decoding modules. It should be noted that a reset does not terminate processing of the next signal frame; rather, it stops the current data write operation to avoid issues such as frame aliasing, frame header misalignment, or control signal lag caused by the writing of the next frame's data. After collision handling is complete, the baseband module simultaneously resets the previously asserted receive completion signal and the overflow reset signal to zero, clearly indicating the end of the collision and re-entering the synchronized receive state.

[0070] Figure 7 FIG. 1 is a signal diagram of a frame conflict handling strategy provided in some embodiments of the present invention. Figure 7 As shown, if the baseband module's receive completion signal (rx-end-flag) is not reset to zero after processing frame 1, and during this time, the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame collision handling strategy, the baseband module also generates an overflow reset signal (overflow-rst). Furthermore, the baseband module performs a reset operation based on this overflow reset signal. As a result, the baseband module does not perform decoding or other parsing processing on frame 2 data after time t1', and therefore does not transfer frame 2 data to the memory module for writing to system memory. The current frame collision handling strategy is to discard frame 2 data. Therefore, based on the overflow flag and reset mechanism, the baseband module does not write frame data to system memory, ensuring that frame 1 data is not overwritten by frame 2 data, thus maintaining the integrity of frame 1 data.

[0071] It should be noted that when the baseband module performs frame synchronization detection, the frame 2 data consists of the frame preamble, FC field and PL field, and the frame synchronization position is in the preamble position. Therefore, when the baseband module detects the frame synchronization signal, it has not yet started to move the frame 2 data to the system memory, and there will be no data overwrite.

[0072] In the above embodiment, after a conflict is detected, the baseband module actively generates an overflow reset signal, and performs cache clearing and reception termination operations based on the signal, and then synchronizes the reception completion signal and the overflow reset signal to zero, thereby achieving rapid closed-loop processing of the frame conflict state, avoiding uncontrollable delays caused by relying on CPU response, ensuring timely handling of the conflict state, and avoiding overlapping or overwriting of consecutive frames by clearing the next frame data and terminating reception, thereby ensuring the integrity of each frame of data. In addition, the entire process is independently completed by the baseband module to complete the conflict detection and processing logic, without the need for CPU participation, without response delay, and completely avoiding the problem of conflict response lag caused by software busyness or scheduling delays. It not only ensures the real-time nature of the communication process, but also maintains the continuity and stability of the CPU software tasks. Even if consecutive frames arrive closely or the CPU is under high load, it can still ensure stable operation of the system, achieving efficient and reliable data protection in frame conflict scenarios.

[0073] In some other embodiments, the signal receiving device further includes a processing module. The following embodiments further propose a frame conflict handling strategy that is collaboratively processed by the processing module.

[0074] Accordingly, according to the frame conflict processing strategy, the frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, and also includes: when the overflow flag signal is detected, the processing module terminates the reading operation of the current signal frame; the processing module sets the receiving completion signal to zero to read the next signal frame.

[0075] When the processing module detects the overflow flag signal set by the baseband module, it determines that there is a read risk for the current signal frame and immediately terminates the read operation of the current signal frame to prevent the data being extracted from being mixed with subsequent data. At the same time, the processing module can actively reset the receive completion signal to zero, releasing the current frame state and entering the read preparation process for the next signal frame.

[0076] For example, in a scenario where a set of consecutive OFDM signal frames is being received, the baseband module detects the start of frame 2 reception, but the receive completion signal for frame 1 has not yet been reset to zero. Therefore, the overflow flag is set. The CPU, acting as the processing module, then detects this overflow flag in an interrupt response and immediately stops fetching frame 1 data from system memory to prevent the reading of frame 2. The CPU then sends a reset command to the baseband module, instructing it to reset the receive completion signal (Rx-end-flag) to zero, allowing the system to quickly proceed with processing frame 2 data and avoiding communication backlogs.

[0077] Figure 8 FIG. 1 is a signal diagram of another frame conflict handling strategy provided in some embodiments of the present invention. Figure 8As shown, if the baseband module's receive completion signal (rx-end-flag) is not reset to zero after processing frame 1, and during this time, the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame collision handling strategy, the processing module (e.g., the CPU) proactively terminates the read operation of frame 1 to avoid extracting invalid data that may have been partially overwritten. The processing module then resets the receive completion signal to zero, releasing the read flag for the current frame 1. The baseband module then continues receiving frame 2 and writes the data of frame 2 to the system memory. After the transmission of frame 2 is complete, the baseband module resets the receive completion signal at time t3 to indicate that the data for frame 2 is ready. Finally, after the CPU detects that the receive completion signal is high, it switches to reading the data for frame 2 from the system memory, completing data recovery and normal processing after the inter-frame collision. In other words, the current frame collision handling strategy discards the data of frame 1.

[0078] Compared with the baseband module handling conflicts completely, the processing module cooperates with the reading suspension and flag clearing mechanism to effectively solve the problem of misreading conflict data caused by inter-frame continuity, and enhances the accuracy and scalability of data reception while maintaining the original system architecture unchanged.

[0079] In the above embodiment, the processing module interrupts the continued reading of the current frame to avoid extracting invalid data after the frame data is partially overwritten, thereby improving the validity of the frame data; and by actively setting the reception completion signal to zero, it helps to shorten the conflict processing time, accelerate the processing preparation of the next frame data, and improve the overall system processing rhythm.

[0080] In order to further improve the signal reception reliability and data quality in the case of frame collision, based on the aforementioned frame collision processing strategy, the present invention also proposes a frame selection mechanism based on channel quality assessment, so that the signal receiving device can automatically judge and retain the frame with better quality between the two conflicting frame signals, avoid the misselection of low-quality data in the case of channel degradation, and improve the overall robustness of the system.

[0081] To this end, in some further embodiments, in accordance with the frame conflict processing strategy, frame conflict processing operations related to the current signal frame or the next signal frame are performed based on the overflow flag signal, and also include: the baseband module at least completes the reception of the leading symbol of the next signal frame to evaluate the channel quality corresponding to the next signal frame based on the leading symbol; the baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retains the signal frame with higher channel quality based on the comparison result, and discards the other signal frame.

[0082] Specifically, after detecting a subsequent signal frame that conflicts with the current signal frame, the baseband module in the signal receiving device first receives and interprets the preamble symbol in the subsequent signal frame. The preamble symbol, serving as a reference field for channel estimation, is highly stable and representative. The baseband module uses it to calculate channel characteristics for the corresponding frame, including but not limited to signal-to-noise ratio (SNR), received signal strength indicator (RSSI), and channel estimation (CE).

[0083] After obtaining the channel quality information for the next signal frame, the baseband module compares it with the channel quality of the current signal frame and determines which frame has better reception conditions based on preset criteria, such as maximum SNR priority and RSSI exceeding a threshold. Based on this judgment, the frame with higher channel quality is automatically retained for subsequent processing, while the frame with degraded channel quality is discarded to avoid invalid data interference and resource waste.

[0084] In the above embodiments, by introducing a channel quality assessment mechanism into the conflict handling strategy, the signal receiving device can effectively distinguish and prioritize frame data with better receiving conditions in high frame density or continuous communication scenarios, thereby avoiding data misuse due to fluctuations in channel conditions; at the same time, it reduces the resource burden brought by redundant data processing, thereby improving the communication reliability and robustness of the overall system.

[0085] In practical communication systems, the operational load of signal receiving devices is often affected by factors such as upper-layer processing tasks, system buffer occupancy, and external interrupt frequency. Using a fixed frame collision handling strategy under high load conditions can compromise both system real-time performance and data integrity. This paper further proposes a load-aware policy adaptation mechanism that enables signal receiving devices to dynamically adjust their frame collision handling logic, thereby flexibly balancing data retention and feature extraction strategies under varying operational loads.

[0086] To this end, in some embodiments, the above method also includes: detecting the load status; automatically selecting different frame conflict processing strategies based on the load status to retain the current signal frame or the next signal frame, and determining the reading strategy of the characteristic information of the current signal frame or the next signal frame based on the selected frame conflict processing strategy.

[0087] Specifically, the signal receiving device continuously monitors its load status during operation, and the load status may include indicators such as CPU processing occupancy, frame buffer queue depth, and task scheduling delay.

[0088] Based on these indicators, the signal receiving device determines whether the system is currently lightly loaded, medium loaded, or heavily loaded, and selects the most appropriate frame collision handling strategy from multiple preset strategies. For example, in a low-load state, the frame collision handling strategy of retaining the current signal frame and discarding the next one is preferred. In a high-load state, the frame collision handling strategy of retaining the next signal frame and discarding the current one is preferred to reduce congestion and improve processing throughput. If the load is critical or medium, a channel quality optimization strategy can be used to retain the current frame or the next frame.

[0089] In the above embodiments, by introducing a load state perception and processing strategy adaptive mechanism, the signal receiving device's ability to respond resiliently in complex operating environments is enhanced, and the overall processing efficiency and stability of the system can be improved while ensuring the integrity of frame data. It is particularly suitable for communication scenarios with dense frame arrival, high-frequency switching, or frequent interference.

[0090] Although the aforementioned frame conflict handling strategy can effectively alleviate the data coverage problem caused by continuous frame reception, in the normal data reception process, the signal receiving device still needs to extract and retain the characteristic information corresponding to each signal frame, such as channel estimation value, received signal strength indication or signal-to-noise ratio, etc. These characteristic information do not directly participate in the real-time processing of frame conflicts, but have important reference value for the upper-layer software to perform subsequent tasks such as link quality assessment, communication tuning, fault analysis, etc. Therefore, in some embodiments, the signal receiving device extracts the characteristic information of the current signal frame while completing the frame synchronization operation, and completes stable latching through the shadow register mechanism to ensure that subsequent tasks can still obtain complete and accurate channel status information under timing uncertainty conditions.

[0091] Figure 9 FIG. 1 is a flow chart of feature information synchronization provided in some embodiments of the present invention. Figure 9 As shown, after receiving the frame data (including the preamble, frame control data and data payload), the baseband module first completes the reception and field parsing of the frame data, and extracts the corresponding feature information, such as the channel estimation value, the received signal strength indicator, the signal-to-noise ratio, etc., during the period from the start of frame synchronization (sync-begin) to the completion of frame synchronization (frame-synced), and writes it into the baseband buffer of the baseband. At the same time, the frame data of the frame control data and the data payload are transferred to the memory module to be written into the system memory. Exemplarily, the baseband module first performs a synchronization detection operation on the received signal. When three synchronization peaks are detected consecutively, the baseband module generates a sync-begin signal to mark the starting point of the current frame synchronization process. After the frame synchronization process is completed, the baseband module generates a frame-synced signal corresponding to the frame synchronization completion flag.

[0092] The baseband module then asserts the receive completion signal (rx-end-flag), transitioning from a low-level signal to a high-level signal, indicating the completion of reception and transmission of the current frame data. Upon detecting the high-level signal, the processing module (i.e., the CPU) begins reading the corresponding frame data from system memory and simultaneously retrieves the signature information from the baseband cache for use by upper-layer applications in network analysis, link assessment, and other operations. This mechanism ensures the consistent temporal and structural pairing of frame data and signature information. The receive completion signal enables data synchronization and release control between the baseband and CPU, improving the accuracy of upper-layer service processing and the overall stability of the communication system.

[0093] During the continuous reception of multiple frames, the baseband module uses the frame synchronization start signal as a trigger to continuously update the feature information in the baseband cache. For example, when the baseband module completes feature extraction between sync-begin and frame-synced while receiving frame 1, the corresponding feature information for frame 1 is written to the cache. When the baseband module begins receiving frame 2 and detects the sync-begin signal for frame 2, the baseband cache begins updating the feature information corresponding to frame 2. As a result, the contents of the baseband cache are dynamically refreshed with each frame synchronization, achieving real-time maintenance of the feature data of the currently valid frame.

[0094] Figure 10 This is a signal diagram of the feature information synchronization process provided in some embodiments of the present invention. Figure 10 As shown, at time t0, the baseband module begins frame synchronization processing for frame 1. Between sync-begin and frame-synced (i.e., time t0 to t0'), it calculates frame 1's feature information and writes it to the baseband buffer. Subsequently, at time t1, writing frame 1 data to system memory is complete, and the baseband module asserts the receive completion signal (rx-end-flag), signaling to the processing module (e.g., the CPU) that the current frame data has been received. Ideally, the CPU should promptly respond to the receive completion signal at time t2 and synchronously extract frame 1 data from system memory and frame 1's feature information from the baseband buffer, ensuring a one-to-one correspondence between the frame data and the feature information. However, in some scenarios, due to processing delays in the CPU or upper-layer software, data extraction may not be completed until time t2'. Meanwhile, if the baseband module has already begun receiving frame 2 and detects frame 2's sync-begin signal at time T1, the feature information previously stored in the baseband buffer for frame 1 will be overwritten by the new feature information for frame 2.

[0095] At this point, even if the frame data extracted by the CPU is the complete content of Frame 1, its corresponding feature information has been updated to the content of Frame 2, resulting in a mismatch between the frame data and feature information. If the application processing relies on this feature information (for example, when selecting a network based on the signal-to-noise ratio), it may cause subsequent decision errors.

[0096] This shows that while relying solely on the receive completion signal can resolve frame collisions, it cannot guarantee the correct binding of frame data and feature information. Data mismatches are particularly prone to occur in high-concurrency scenarios. Therefore, based on the above-mentioned frame collision handling method for power line carrier signals, the present invention introduces a shadow register latch mechanism to further improve the synchronization reliability of feature information.

[0097] To this end, in some embodiments, the above method also includes: when a frame synchronization start signal is detected, the baseband module calculates the characteristic information of the current signal frame and writes the calculated characteristic information of the current signal frame into the baseband cache; when a frame synchronization completion signal is detected, the baseband module moves the characteristic information of the current signal frame stored in the baseband cache to a shadow register for latching for subsequent processing module reading.

[0098] When the baseband module detects the frame synchronization start signal, it starts to execute the frame feature calculation logic, extracts key features such as demodulation, energy statistics, signal-to-noise ratio estimation, received power, initial carrier frequency offset, and channel estimation of the received data corresponding to the frame, and writes these feature information into the baseband cache.

[0099] The baseband cache is a high-speed RAM area in the baseband module, which is used to temporarily store frame-level features that have not yet been latched.

[0100] When the frame synchronization completion signal is detected, indicating frame synchronization is complete, the baseband module confirms that the synchronization position of the current frame has been determined. The baseband module immediately moves the calculated feature information in the baseband cache to the shadow register and performs a latch operation. This shadow register, as a dedicated register area for feature reading, has a write protection mechanism to prevent subsequent frame information from being overwritten during CPU reading, thereby ensuring the integrity and consistency of the read data.

[0101] It's important to note that shadow register updates aren't directly controlled by the baseband module. Instead, they're automated through hardware logic, such as gates, configured within the module. Specifically, the shadow register's state is automatically triggered by control logic based on changes in the synchronization signal and overflow flag. By controlling the gate state, the shadow register can autonomously choose whether to retain the signature information of the current signal frame or update it to the signature information of the next signal frame.

[0102] When the baseband module detects the sync-begin signal for the next signal frame, the shadow register is automatically updated according to the preset synchronization strategy. This update relies on a hardware trigger mechanism that controls the write and read paths of the shadow register through gate circuits to ensure that no information conflicts or losses occur during frame data processing.

[0103] Therefore, the state change of the shadow register is completely controlled by hardware and does not require the direct intervention of the baseband module or the intervention of the external processing module, thereby improving the response efficiency of the power communication system and ensuring the efficient storage and update of feature information.

[0104] In the above embodiment, the latching mechanism of the shadow register is combined to prevent data overwriting or conflicts during the reading process, thereby improving the stability and accuracy of feature reading. The entire process is executed independently within the baseband module, without waiting for the CPU to respond, effectively improving the system's efficiency in processing frame features.

[0105] On the basis of the above-mentioned feature information synchronization and migration mechanism, the present invention further constrains the update control strategy of the shadow register in the overflow scenario to ensure that the feature information of the current signal frame is not overwritten.

[0106] To this end, in some embodiments, the above method also includes: after detecting that the next signal frame completes frame synchronization, if the overflow flag signal is in the set state, the shadow register is not updated to keep the characteristic information of the current signal frame latched; the processing module reads the characteristic information of the current signal frame in the shadow register, and sets the reception completion signal to zero to complete the processing of the current signal frame and discard the next signal frame.

[0107] When the baseband module detects that the next signal frame has completed frame synchronization (frame-synced), if the overflow flag signal (overflow_flag) is in the set state at this time, the shadow register does not update the currently stored data, thereby preventing the feature information of the current frame from being overwritten.

[0108] In this conflict state, the processing module directly extracts the characteristic information of the current signal frame from the shadow register, and sets the receive completion signal (rx-end-flag) to zero after the extraction is completed to terminate the processing flow of the current frame and discard the next frame.

[0109] In this embodiment, the update of the shadow register is controlled by the joint judgment of the overflow signal and the synchronization status. The update is allowed only when the established conditions are met, thereby ensuring that the latched feature information always corresponds one-to-one with the frame data processed by the CPU, avoiding erroneous binding.

[0110] In the above embodiment, by not updating the shadow register when the overflow flag is set, the problem of the feature information of the next signal frame incorrectly overwriting the current feature information can be effectively avoided, thereby ensuring that the system can still extract the feature information that correctly corresponds to the frame data in data conflict scenarios. This mechanism improves the stability and consistency of software processing, avoiding upper-layer application exception handling or service judgment errors caused by feature data mismatches. It is particularly suitable for scenarios with high requirements for physical layer accuracy, such as power carrier communication, smart meter reading, and communication protocol analysis.

[0111] In other embodiments, the above method also includes: after starting frame synchronization for the next signal frame, the baseband module calculates the characteristic information of the next signal frame and writes the calculated characteristic information of the next signal frame into the baseband cache; after detecting that the next signal frame completes frame synchronization, if the overflow flag signal is set, the baseband module moves the characteristic information of the next signal frame stored in the baseband cache to the shadow register for latching to overwrite the original characteristic information of the current signal frame; the processing module reads the characteristic information of the next signal frame in the shadow register and sets the reception completion signal to zero to complete the processing of the next signal frame and discard the current signal frame.

[0112] When the baseband module begins frame synchronization for the next signal frame, it simultaneously calculates the next frame's feature information and writes it to the baseband buffer. If it detects that the next signal frame has completed frame synchronization (i.e., detects the frame-synced signal), and the overflow flag (overflow_flag) is set, the baseband module performs a feature information transfer operation, writing the next feature information in the buffer to the shadow register, thereby overwriting the feature data of the original current signal frame.

[0113] The processing module then reads the latest feature information (i.e., the next feature information) in the shadow register and sets the receive completion signal (rx-end-flag) to zero after the reading is completed, thereby terminating the processing of the current frame and taking over the feature data of the next frame.

[0114] This embodiment embodies an active coverage conflict handling strategy. Under the premise that the integrity or consistency of the current frame cannot be guaranteed, the synchronization feature information of the next frame is retained and the current frame is discarded to avoid affecting subsequent tasks due to processing delays or incorrect feature binding.

[0115] In the above embodiment, by actively moving the feature information of the next frame and overwriting the original information in the overflow state, it is helpful to reduce the frame loss rate and data mismatch probability caused by synchronization conflicts, and improve the stability and processing flexibility of the system in frame conflict scenarios. It is especially suitable for high-speed communication, dense networking or bandwidth-limited power line carrier communication scenarios.

[0116] Figure 11 This is a signal diagram of the feature information synchronization process provided in some embodiments of the present invention. Figure 11 As shown in the figure, based on the existing baseband cache structure, the present invention adds a shadow register (or shadow memory) to specifically store feature information to ensure the accuracy and readability of frame feature data in conflict states or software delay scenarios. Figure 9 As shown in Figure 2, the shadow register provides a stable copy of feature information for extraction and use by the CPU or upper-level processing modules.

[0117] refer to Figure 10 In the timing sequence shown, when the baseband module detects the sync-begin signal for frame 1 (time t0), that is, when multiple synchronization peaks are detected consecutively, the baseband module begins processing such as channel estimation, calculates the feature information of frame 1, and writes it to the baseband buffer. This process continues until the frame-synced signal for frame 1 is detected, that is, time t0'. When the baseband module detects the frame-synced signal for frame 1 at time t0', it immediately controls the shadow register to read the feature information of the current frame (frame 1) from the baseband buffer and latches it. At this point, the shadow register stores the same feature information that corresponds to the frame 1 data in the system memory.

[0118] When frame 1 data is transferred to system memory (at time t1), the baseband module asserts the receive completion signal (rx-end-flag) to notify the CPU that it can read the frame data. When the baseband detects the sync-begin signal for frame 2 at time T1, the baseband module begins recalculating and updating the feature information for frame 2. If the CPU has not yet finished extracting frame 1 data at this time, there is a risk that the frame feature data will be overwritten.

[0119] In combination with the above embodiments Figure 7 A frame collision handling strategy is provided. If the overflow flag (overflow_flag) is set at time t1' (i.e., when frame 2 synchronization is complete), the baseband module disables updates to the shadow register and retains the signature information of frame 1. In this case, even if the CPU delays data reading at time t2', the signature information obtained from the shadow register remains consistent with the data in frame 1.

[0120] In combination with the above embodiments Figure 8A frame collision handling strategy is provided. If the overflow flag is set at time t1', a feature transfer operation is triggered. The baseband module controls the shadow register to update the feature information of frame 2, in accordance with the system's frame collision handling strategy of retaining frame 2 data. When the CPU subsequently completes the frame 2 data read (for example, at time t3), it can obtain the corresponding frame 2 feature information from the shadow register to ensure data consistency. This effectively solves the mismatch between frame data and feature information caused by software latency in traditional architectures, further improving data consistency and application reliability of signal receiving devices in high-concurrency scenarios.

[0121] Unlike related techniques where the CPU directly accesses the baseband cache, the CPU in this invention reads feature information from a shadow register. This ensures a one-to-one correspondence between the extracted frame data and the feature information, preventing data mismatches caused by cache overwriting. After the read is complete, the CPU or upper-layer application sets the receive completion signal (rx-end-flag) to zero, ending the current processing cycle.

[0122] The above mechanism is particularly suitable for scenarios requiring high communication reliability, complex meter networking, and large power line noise environment interference, such as the networking application of power line carrier communication chips.

[0123] The frame conflict processing method for power line carrier signals provided in the embodiment of the present invention can be executed by a frame conflict processing device. In the embodiment of the present invention, the frame conflict processing device performing the frame conflict processing method for power line carrier signals is used as an example to illustrate the frame conflict processing device provided in the embodiment of the present invention.

[0124] An embodiment of the present invention further provides a frame conflict processing device, which is applied to a signal receiving device.

[0125] Figure 12 FIG. 1 is a schematic diagram of the structure of a frame conflict processing device provided in some embodiments of the present invention. Figure 12 As shown, the frame conflict processing device includes a signal triggering module 1201, a conflict triggering module 1202 and a conflict processing module 1203. The signal trigger module 1201 is used to set a reception completion signal for indicating a reception completion status after the baseband module completes receiving the current signal frame and transmits the data of the current signal frame to the memory module.

[0126] The conflict trigger module 1202 is used to set the overflow flag signal if the baseband module detects the frame synchronization completion signal during the period when the reception completion signal is set; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame.

[0127] The conflict processing module 1203 is configured to perform a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy.

[0128] According to the frame conflict processing device provided by the embodiment of the present invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, the reception completion signal is set, thereby realizing a clear division of the state between the frame reception and the processing flow, and facilitating the processing module to judge the timing of data reading; during the period when the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, the overflow flag signal is set, and the access behavior of the next frame can be detected in time, and a flag signal is generated for alarm, thereby realizing fast and automatic recognition of the conflict state, without waiting for the processor to participate or polling judgment, and getting rid of the dependence on interrupt response or software scheduling mechanism; furthermore, according to the frame conflict processing Strategy, based on the overflow flag signal, performs frame conflict processing operations related to the current signal frame or the next signal frame, and the baseband module automatically triggers the conflict strategy, supports automatic frame conflict processing within the hardware, and does not require the processor to participate in the judgment and control signal initiation, reduces the control path delay, and improves the robustness and overall processing efficiency in high-speed receiving scenarios. In addition, by introducing configurable or dynamically selected conflict processing strategies, it supports flexible response to the conflict situation of retaining the current frame or receiving the next frame according to application requirements, improves the system adaptability and processing efficiency, and can effectively reduce the risk of data loss and state disorder caused by frame conflicts, and improves the reliability and processing efficiency of the system in high-density receiving scenarios.

[0129] In some embodiments, the conflict handling module is also used to generate an overflow reset signal for triggering an interrupt when the overflow flag signal is in the set state; perform a reset operation in response to the overflow reset signal to stop processing the next frame of data; and set the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0130] In some embodiments, the conflict handling module is further configured to terminate the reading operation of the current signal frame when an overflow flag signal is detected; and set the receiving completion signal to zero to read the next signal frame.

[0131] In some embodiments, the conflict handling module is also used to at least complete the reception of the leading symbol of the next signal frame to evaluate the channel quality corresponding to the next signal frame based on the leading symbol; compare the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retain the signal frame with higher channel quality based on the comparison result, and discard the other signal frame.

[0132] In some embodiments, the conflict trigger module is further configured to monitor the synchronization sequence in the input signal and, upon detecting a synchronization sequence that matches a preset frame format, generate a frame synchronization start signal to indicate that frame synchronization detection for the next signal frame has been initiated; and, after confirming the frame synchronization position, generate a frame synchronization completion signal to indicate that synchronization has been completed for the next signal frame currently received.

[0133] In some embodiments, the above-mentioned device also includes a frame feature synchronization module, which is used to calculate the feature information of the current signal frame when a frame synchronization start signal is detected, and write the calculated feature information of the current signal frame into the baseband cache; when a frame synchronization completion signal is detected, the feature information of the current signal frame stored in the baseband cache is moved to a shadow register for latching for reading by a subsequent processing module.

[0134] In some embodiments, the frame feature synchronization module is also used to, after detecting that the next signal frame completes frame synchronization, if the overflow flag signal is in the set state, the shadow register is not updated to keep the feature information of the current signal frame latched; read the feature information of the current signal frame in the shadow register, and set the reception completion signal to zero to complete the processing of the current signal frame and discard the next signal frame.

[0135] In some embodiments, the frame feature synchronization module is also used to calculate the feature information of the next signal frame after starting frame synchronization for the next signal frame, and write the calculated feature information of the next signal frame into the baseband cache; after detecting that the next signal frame completes frame synchronization, if the overflow flag signal is set, the feature information of the next signal frame stored in the baseband cache is moved to the shadow register for latching to overwrite the original feature information of the current signal frame; read the feature information of the next signal frame in the shadow register, and set the reception completion signal to zero to complete the processing of the next signal frame and discard the current signal frame.

[0136] In some embodiments, the above-mentioned device also includes a detection module for detecting the load status; automatically selecting different frame conflict processing strategies based on the load status to retain the current signal frame or the next signal frame, and determining the reading strategy of the characteristic information of the current signal frame or the next signal frame based on the selected frame conflict processing strategy.

[0137] The frame conflict processing device provided in the embodiment of the present invention can implement each process implemented in each method embodiment, and to avoid repetition, it will not be described here.

[0138] The frame conflict processing apparatus in the embodiment of the present invention may be a signal receiving device, or a component in the signal receiving device, such as an integrated circuit or a chip. The signal receiving device is a computer device, such as a terminal device.

[0139] An embodiment of the present invention also provides a signal receiving device. Figure 13 FIG. 1 is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. Figure 13 As shown, the signal receiving device 1300 includes a baseband module 1301, a memory module 1302 and a processing module 1303. The baseband module 1301 is configured to set a reception completion signal indicating a reception completion status after completing reception of the current signal frame and transmitting data of the current signal frame to the memory module.

[0140] The baseband module 1301 is also used to set an overflow flag signal if it detects that the next signal frame starts to be received while the reception completion signal is in the set state; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame.

[0141] The baseband module 1301 or the processing module 1303 is configured to perform a frame conflict processing operation related to the current frame or the next frame according to the frame conflict processing strategy based on the overflow flag signal.

[0142] The memory module 1302 is used to receive and store data transmitted by the baseband module for subsequent reading and processing by the processing module.

[0143] The signal receiving device provided in the embodiment of the present invention can implement each process implemented in each method embodiment, and to avoid repetition, it will not be described again here.

[0144] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the various processes of the above-mentioned frame conflict processing method embodiment of the power line carrier signal and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0145] The processor is the processor in the computer device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0146] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the above-mentioned frame conflict processing method of the power line carrier signal when executed by a processor.

[0147] The processor is the processor in the computer device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0148] An embodiment of the present invention further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned frame conflict processing method embodiment of the power line carrier signal, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0149] It should be understood that the chip mentioned in the embodiment of the present invention can also be called a system-on-chip, a system-on-chip, a chip system, or a system-on-chip chip, etc.

[0150] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0151] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is a more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the relevant art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0152] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

[0153] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0154] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0155] Unless otherwise specified, all technical features and optional technical features of the present invention can be combined with each other to form a new technical solution.

[0156] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, "the method includes steps (a) and (b)" means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, "the method may further include step (c)" means that step (c) may be added to the method in any order, for example, the method may include steps (a), (b), and (c), or may include steps (a), (c), and (b), or may include steps (c), (a), and (b), etc.

[0157] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for processing frame conflicts of a power line carrier signal, characterized in that: Applied to a signal receiving device, the signal receiving device includes a baseband module and a memory module; the method includes: After the baseband module completes receiving the current signal frame and transmits the data of the current signal frame to the memory module, it sets a reception completion signal for indicating the reception completion state; During the period when the reception completion signal is in the set state, if the baseband module detects the frame synchronization completion signal, an overflow flag signal is set; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame; According to the frame conflict processing strategy, a frame conflict processing operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal.

2. The method for processing frame conflicts of power line carrier signals according to claim 1, wherein: The performing of a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy includes: When the overflow flag signal is in a set state, the baseband module generates an overflow reset signal for triggering an interrupt; In response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame of data; The baseband module resets the reception completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

3. The method for processing frame conflicts of power line carrier signals according to claim 1, wherein: The signal receiving device further includes a processing module; the processing module further includes: performing a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy; The processing module stops the reading operation of the current signal frame when detecting the overflow flag signal; The processing module sets the reception completion signal to zero to read the next signal frame.

4. The method for processing frame conflicts of power line carrier signals according to claim 1, wherein: The step of performing a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy further includes: The baseband module at least completes reception of a leading symbol of a next signal frame, so as to evaluate a channel quality corresponding to the next signal frame based on the leading symbol; The baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retains the signal frame with higher channel quality based on the comparison result, and discards the other signal frame.

5. The method for processing frame conflicts of power line carrier signals according to claim 1, wherein: The baseband module detects a frame synchronization completion signal, including: The baseband module monitors the synchronization sequence in the input signal. When a synchronization sequence matching the preset frame format is detected, it generates a frame synchronization start signal to indicate that the frame synchronization detection of the next signal frame has started. After completing the confirmation of the frame synchronization position, the baseband module generates a frame synchronization completion signal, where the frame synchronization completion signal is used to indicate that the next signal frame currently received has completed the synchronization process.

6. The method for processing frame conflicts of power line carrier signals according to claim 1 or 5, characterized in that: The method further comprises: When a frame synchronization start signal is detected, the baseband module calculates feature information of the current signal frame and writes the calculated feature information of the current signal frame into the baseband buffer; When the frame synchronization completion signal is detected, the baseband module moves the characteristic information of the current signal frame stored in the baseband buffer to the shadow register for latching, so as to be read by the subsequent processing module.

7. The method for processing frame conflicts of power line carrier signals according to claim 6, wherein: The method further comprises: After detecting that the next signal frame completes frame synchronization, if the overflow flag signal is set, the shadow register is not updated to keep latching the characteristic information of the current signal frame; The processing module reads the characteristic information of the current signal frame in the shadow register and sets the reception completion signal to zero to complete the processing of the current signal frame and discard the next signal frame.

8. The method for processing frame conflicts of power line carrier signals according to claim 6, wherein: The method further comprises: After starting frame synchronization for the next signal frame, the baseband module calculates feature information of the next signal frame and writes the calculated feature information of the next signal frame into the baseband buffer; After detecting that the next signal frame completes frame synchronization, if the overflow flag signal is set, the baseband module moves the feature information of the next signal frame stored in the baseband buffer to the shadow register for latching to overwrite the original feature information of the current signal frame; The processing module reads the characteristic information of the next signal frame in the shadow register and sets the reception completion signal to zero to complete the processing of the next signal frame and discard the current signal frame.

9. The method for processing frame conflicts of power line carrier signals according to claim 1, wherein: The method further comprises: Detect load status; Different frame conflict processing strategies are automatically selected based on the load status to retain the current signal frame or the next signal frame, and a reading strategy for feature information of the current signal frame or the next signal frame is determined based on the selected frame conflict processing strategy.

10. A frame conflict processing device for a power line carrier signal, characterized in that: Applied to a signal receiving device, the device comprises: The signal trigger module is used to set a reception completion signal indicating a reception completion status after the baseband module completes reception of the current signal frame and transmits the data of the current signal frame to the memory module; a conflict trigger module, configured to set an overflow flag signal if the baseband module detects a frame synchronization completion signal while the reception completion signal is in the set state; the overflow flag signal is used to indicate that a processing state of the current signal frame conflicts with a reception behavior of the next signal frame; The conflict processing module is used to perform a frame conflict processing operation related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict processing strategy.

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