A pll sharing transmitting and receiving circuit for usb3 interface

Abstract

The application discloses a PLL shared transmitting and receiving circuit for USB3 interface. The circuit comprises a receiving module, a transmitting module and a phase-locked loop. The receiving module is used to receive data from a differential line and parse frequency information from the received data; then a frequency control word is generated according to the frequency information. The transmitting module is used to send data through the differential line. The phase-locked loop is used to generate a recovered clock according to the frequency control word generated by the receiving module, and the generated recovered clock is sent to the receiving module and the transmitting module. When the receiving module samples data on the differential line, the recovered clock is used to generate a sampling clock, and when the transmitting module transmits data, the recovered clock is used as a transmitting clock. The receiving module and the transmitting module share the same phase-locked loop, so the power consumption is low and the area is small. The USB3 Link layer and the Physical layer share one clock, so the design complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data transceiver circuits, and in particular to a PLL shared transceiver circuit for a USB3 interface. Background Art

[0002] According to the USB3 protocol, data transmission requires the use of SSC (Spread Spectrum Clock). The current mainstream USB3 transceiver circuit architecture uses independent receive and transmit clocks, requiring two independent PLL (Phase Lock Loop) modules as the transmit and receive clock sources, respectively. This results in high power consumption and a large area.

[0003] The common USB3 interface circuit architecture consists of a Tx PLL (Phase Lock Loop), an Rx PLL, an Rx lane, and a Tx lane. The Tx PLL generates a spread spectrum clock (SSC) and sends it to the Tx lane, while the Rx PLL generates a fixed-frequency clock without SSC and sends it to the Rx lane. The Tx lane converts data from the USB3 link layer to serial data before sending it over differential cables. The Rx lane converts data from the differential cables to parallel data before sending it to the USB3 link layer.

[0004] Disadvantages of existing technology:

[0005] 1. RxLane and TxLane independently use two PLLs as clock sources, which consumes high power and has a large area.

[0006] 2. If the TxPLL clock with SSC is sent to the RxLane module as the clock source, the SSC spread spectrum range will be doubled, which will affect the performance of the RxLane CDR (Clock Data Recovery) module. Summary of the Invention

[0007] The object of the present invention is to provide a PLL shared transceiver circuit for a USB3 interface in view of the deficiencies in the prior art.

[0008] To achieve the above object, the present invention provides a PLL shared transceiver circuit for a USB3 interface, comprising:

[0009] A receiving module, configured to receive data from the differential line and parse frequency information from the received data; and then generate a frequency control word based on the frequency information;

[0010] The sending module is used to send data through the differential line;

[0011] A phase-locked loop is used to generate a recovered clock based on the frequency control word generated by the receiving module, and send the generated recovered clock to the receiving module and the sending module, so that the receiving module generates a sampling clock based on the recovered clock when sampling data on the differential line, and the sending module uses the recovered clock as the sending clock when sending data.

[0012] Furthermore, the receiving module includes:

[0013] The data sampling module is used to sample the input data at the rising edge of the sampling clock and convert the input data into a binary 0 or 1 digital signal output;

[0014] The nonlinear phase detection module is used to detect the current phase according to the binary 0 or 1 digital signal output by the data sampling module and output the phase error;

[0015] a proportional filtering module, configured to proportionally adjust the phase error output by the nonlinear phase detection module and output a proportional adjustment result;

[0016] an integrator, configured to integrate the phase error output by the nonlinear phase detection module to obtain the frequency information, and output the frequency information;

[0017] a low-pass filter for performing low-pass filtering on the frequency information output by the integrator, generating a frequency control word, and then outputting the generated frequency control word;

[0018] a first adder, configured to perform a subtraction operation on the frequency information output by the integrator and the frequency control word output by the low-pass filter, and output an operation result;

[0019] a second adder, configured to perform an addition operation on the proportional adjustment result output by the proportional filtering module and the operation result output by the first adder, and output a phase interpolator control word;

[0020] The first phase interpolator is used to receive the recovered clock sent by the phase-locked loop and perform phase shift on the received recovered clock according to the phase interpolator control word output by the second adder to generate the sampling clock required by the data sampling module for data sampling.

[0021] Furthermore, the low-pass filter includes a first low-pass filter and a second low-pass filter connected in cascade.

[0022] Furthermore, the first low-pass filter is a second-order cascaded integrator-comb low-pass filter.

[0023] Furthermore, the second low-pass filter is an infinite impulse response low-pass filter.

[0024] Furthermore, the phase-locked loop includes:

[0025] A frequency and phase detector is used to generate high and low level signals according to the crystal oscillator and the feedback clock, and output the generated high and low level signals;

[0026] A charge pump, configured to convert the high and low level signals output by the frequency and phase detector into voltage signals, and output the converted voltage signals;

[0027] a loop filter, configured to filter the voltage signal output by the charge pump and output the filtered voltage signal;

[0028] A voltage-controlled oscillator, used to oscillate a recovered clock according to the voltage signal output by the loop filter;

[0029] a second phase interpolator, configured to perform phase shift on the recovered clock generated by the voltage-controlled oscillator according to the frequency control word output by the low-pass filter, and output the recovered clock after the phase shift;

[0030] An integer frequency divider is used to divide the phase-shifted recovered clock output by the second phase interpolator to generate a feedback clock required by the phase and frequency detector.

[0031] Beneficial effects: 1. The receiving module and the transmitting module share the same phase-locked loop, which has low power consumption and small area;

[0032] 2. Avoid the problem of excessive pressure on the double SSC spread spectrum range of the clock data recovery module of the receiving module;

[0033] 3. The spread spectrum clock from upstream to downstream is almost completely synchronized with the spread spectrum clock from downstream to upstream;

[0034] 4. When there is no input data in the phase-locked loop, the frequency control word will not change and will not affect the locking of the phase-locked loop;

[0035] 5. The USB3 Link layer and Physical layer share a clock, reducing the complexity of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a principle block diagram of a PLL shared transceiver circuit for a USB3 interface according to an embodiment of the present invention;

[0037] Figure 21 is a principle block diagram of a CDR loop of a receiving module according to an embodiment of the present invention;

[0038] Figure 3 is a principle block diagram of a phase-locked loop according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the change of the control voltage of the voltage-controlled oscillator with the frequency control word. DETAILED DESCRIPTION

[0040] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solutions of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0041] like Figures 1 to 4 As shown, an embodiment of the present invention provides a PLL shared transceiver circuit for a USB3 interface, including a receiving module 1 (Rx Lane), a transmitting module 2 (Tx Lane) and a phase-locked loop 3 (Rx PLL). The receiving module 1 and the transmitting module 2 share a phase-locked loop 3.

[0042] Receiver module 1 receives data from the differential lines and parses the frequency information from the received data; it then generates a frequency control word based on the frequency information obtained. Transmitter module 2 transmits the data via the differential lines. USB3 applications use two pairs of differential data lines, one for transmitting data and the other for receiving data. Phase-locked loop 3 generates a recovered clock based on the frequency control word generated by receiver module 1. This recovered clock is then sent to both receiver module 1 and transmitter module 2. This allows receiver module 1 to generate a sampling clock based on the recovered clock when sampling data on the differential lines, and transmitter module 2 to use the recovered clock as the transmit clock when transmitting data.

[0043] Since there is no additional differential line transmission reference clock, the CDR loop is used in the receiving module 1 to recover the sampling clock from the received serial data and sample the input data according to the sampling clock. Figure 2 , Figure 2 The diagram shows the CDR loop of receiver module 1. The CDR loop is based on a classic second-order digital CDR structure. The proportional filter path is a first-order loop, primarily responsible for tracking phase error; the integral path is a second-order loop, primarily responsible for tracking frequency error, replacing the function of the PLL in a traditional PLL-based CDR structure. The CDR loop of the present application specifically includes a data sampling module 11, a nonlinear phase detection module 12, a proportional filter module 13, an integrator 14, a low-pass filter 15, a first adder 16, a second adder 17, and a first phase interpolator 18.

[0044] The data sampling module 11 is used to sample the input data at the rising edge of the sampling clock, and output the input data as binary 0 or 1 digital signal. The non-linear phase detection module 12 is used to detect the current phase according to the binary 0 or 1 digital signal output by the data sampling module 11, and output the phase error. The proportional filter module 13 is used to proportionally adjust the phase error output by the non-linear phase detection module 12, and output the proportional adjustment result. The integrator 14 is used to integrate the phase error output by the non-linear phase detection module 12 to obtain the frequency information, and output the frequency information. The low-pass filter 15 is used to low-pass filter the frequency information output by the integrator 14, and generate the frequency control word, and then output the generated frequency control word. The first adder 16 is used to subtract the frequency information output by the integrator 14 from the frequency control word output by the low-pass filter 15, and output the operation result. The second adder 17 is used to add the proportional adjustment result output by the proportional filter module 13 and the operation result output by the first adder 16, and output the phase interpolator control word. The first phase interpolator 18 is used to receive the recovered clock sent by the phase-locked loop 3, and shift the phase of the received recovered clock according to the phase interpolator control word output by the second adder 17 to generate the sampling clock required for the data sampling of the data sampling module 11.

[0045] The low-pass filter 15 and the first adder 16 are connected in series after the integrator 14, the second-order loop is further split into a low-frequency second-order loop and a high-frequency second-order loop, the low-frequency second-order loop is responsible for tracking the SSC component in the frequency error, and the high-frequency second-order loop is responsible for tracking the high-frequency jitter component in the frequency error. The low-pass filter 15 preferably uses a two-stage digital low-pass filter cascade, the first-stage low-pass filter uses a second-order CIC (Cascade Integrator Comb) low-pass filter, and the main function is to perform anti-aliasing down-sampling on the output value of the integrator 14; the second-stage low-pass filter uses an IIR (Infinite Impulse Response) low-pass filter, and the high-frequency part output by the integrator 14 is completely filtered out in the second-stage low-pass filter. In addition, the first adder 16 realizes the function of subtracting the output of the integrator 14 from the frequency control word, that is, the high-pass filtering of the output of the integrator 14 is realized through the first adder 16, and the tracking capability of the high-frequency jitter of the second-order CDR loop is retained.

[0046] After the integer division ratio is set in the phase-locked loop 3 of the embodiment of the present invention, the output frequency f_vco of the voltage-controlled oscillator is equal to f_xtal*N, where N is the set integer division ratio. In USB3 applications, the fixed output frequency of the voltage-controlled oscillator cannot be directly used as the transmit clock of Txlane because it does not have SSC. The phase-locked loop 3 of the present application includes a phase frequency detector 31, a charge pump 32, a loop filter 33, a voltage-controlled oscillator 34, a second phase interpolator 35, and an integer divider 36.

[0047] The phase frequency detector 31 is used to generate high and low level signals based on the crystal oscillator 37 and the feedback clock, and outputs the generated high and low level signals. The charge pump 32 is used to convert the high and low level signals output by the phase frequency detector 31 into voltage signals, and output the converted voltage signals. The loop filter 33 is used to filter the voltage signal output by the charge pump 32, and output the filtered voltage signal. The voltage controlled oscillator 34 is used to oscillate a recovered clock based on the voltage signal output by the loop filter 33. The second phase interpolator 35 is used to phase shift the recovered clock generated by the voltage controlled oscillator 34 based on the frequency control word output by the low-pass filter 15, and output the phase-shifted recovered clock. The integer divider 36 is used to divide the phase-shifted recovered clock output by the second phase interpolator 35 to generate the feedback clock required by the phase frequency detector 31.

[0048] The phase-locked loop 3 used in the present invention is connected in series with a second phase interpolator 35 behind the voltage-controlled oscillator 34, and performs phase shift on the output recovery clock of the voltage-controlled oscillator 34 based on the frequency control word, thereby changing the frequency of the feedback clock. Due to the closed-loop characteristics of the phase-locked loop 3, the frequency of the recovery clock output by the voltage-controlled oscillator 34 will be controlled by the frequency control word. As mentioned above, the frequency control word comes from the low-frequency second-order loop output in the Rxlane CDR second-order loop, that is, it only contains low-frequency frequency information related to the received data SSC, but does not contain high-frequency jitter frequency information of the received data. The SSC frequency information of the received data is represented as a digital frequency control word and is finally sent to the sending module 2 through the second phase interpolator 35, the PLL closed-loop loop, and the voltage-controlled oscillator 34. In this process, both the high-frequency jitter filtering of the received data and the function of transmitting the SSC frequency information to the sending module 2 are achieved. For details, please refer to Figure 4 The CDR loop extracts the frequency control word containing only the SSC from the input signal. When the frequency control word changes with the input signal SSC, the control voltage of the voltage-controlled oscillator 34 also changes periodically within 500mV to 495mV according to the characteristics of SSC. In this way, the SSC of the input signal of the receiving module 1 is transmitted to the output of the transmitting module 2.

[0049] The above description is merely a preferred embodiment of the present invention. It should be noted that any other aspects not specifically described are considered prior art or common knowledge to those skilled in the art. Improvements and modifications may be made without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention.

Claims

1. A PLL shared transceiver circuit for a USB3 interface, characterized in that: include: A receiving module is used to receive data from the differential line and parse frequency information from the received data; Then generating a frequency control word according to the frequency information; The sending module is used to send data through the differential line; a phase-locked loop, configured to generate a recovered clock based on the frequency control word generated by the receiving module, and send the generated recovered clock to the receiving module and the sending module, so that the receiving module generates a sampling clock based on the recovered clock when sampling data on the differential line, and the sending module uses the recovered clock as the sending clock when sending data; The receiving module includes: The data sampling module is used to sample the input data at the rising edge of the sampling clock and convert the input data into a binary 0 or 1 digital signal output; The nonlinear phase detection module is used to detect the current phase according to the binary 0 or 1 digital signal output by the data sampling module and output the phase error; a proportional filtering module, configured to proportionally adjust the phase error output by the nonlinear phase detection module and output a proportional adjustment result; an integrator, configured to integrate the phase error output by the nonlinear phase detection module to obtain the frequency information, and output the frequency information; a low-pass filter for performing low-pass filtering on the frequency information output by the integrator, generating a frequency control word, and then outputting the generated frequency control word; a first adder, configured to perform a subtraction operation on the frequency information output by the integrator and the frequency control word output by the low-pass filter, and output an operation result; a second adder, configured to perform an addition operation on the proportional adjustment result output by the proportional filtering module and the operation result output by the first adder, and output a phase interpolator control word; The first phase interpolator is used to receive the recovered clock sent by the phase-locked loop and perform phase shift on the received recovered clock according to the phase interpolator control word output by the second adder to generate the sampling clock required by the data sampling module for data sampling.

2. A PLL shared transceiver circuit for a USB3 interface according to claim 1, characterized in that: The low-pass filter includes a first low-pass filter and a second low-pass filter connected in cascade.

3. A PLL shared transceiver circuit for a USB3 interface according to claim 2, characterized in that: The first low-pass filter is a second-order cascaded integrator-comb low-pass filter.

4. A PLL shared transceiver circuit for a USB3 interface according to claim 2, characterized in that: The second low-pass filter is an infinite impulse response low-pass filter.

5. A PLL shared transceiver circuit for a USB3 interface according to claim 1, characterized in that: The phase-locked loop comprises: A frequency and phase detector is used to generate high and low level signals according to the crystal oscillator and the feedback clock, and output the generated high and low level signals; A charge pump, configured to convert the high and low level signals output by the frequency and phase detector into voltage signals, and output the converted voltage signals; a loop filter, configured to filter the voltage signal output by the charge pump and output the filtered voltage signal; A voltage-controlled oscillator, used to oscillate a recovered clock according to the voltage signal output by the loop filter; a second phase interpolator, configured to perform phase shift on the recovered clock generated by the voltage-controlled oscillator according to the frequency control word output by the low-pass filter, and output the recovered clock after the phase shift; An integer frequency divider is used to divide the phase-shifted recovered clock output by the second phase interpolator to generate a feedback clock required by the phase and frequency detector.

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