Mixed-mode balanced driving FFE circuit, Serdes transmitter and chip

Abstract

The invention provides a mixed-mode balanced driving FFE circuit, a Serdes transmitter and a chip, and the FFE circuit comprises a data retiming module which is used for retiming each path of received data into two paths of data based on a clock signal, and outputting the two paths of data; the multi-tap pulse generation module is used for receiving the data output by the data retiming module and generating a front tap pulse signal, a main tap pulse signal and a rear tap pulse signal; and the multiplexing-hybrid equalization driving module comprises a voltage mode driver and a current mode driver, the voltage mode driver is used for transmitting the main tap pulse signal, and the current mode driver is used for converting the front tap pulse signal and the rear tap pulse signal into current and injecting the current into the output end of the multiplexing-hybrid equalization driving module to realize an FFE function. According to the invention, the FFE function is realized with a small number of slices, and the bottlenecks of bandwidth limitation and balanced resolution of the existing architecture are effectively overcome while low power consumption and high linearity are maintained.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a mixed-mode balanced-driven FFE (Feed Forward Equalization) circuit, a Serdes (Serializer-Deserializer) transmitter and a chip. Background Art

[0002] After several technological evolutions, the transmission architecture of interface circuits has undergone a transition from serial to parallel and then back to serial. Early serial transmission architectures suffered from technical drawbacks such as large transmission delays and severe signal attenuation. To overcome these technical drawbacks and increase transmission speeds, the industry developed parallel data transmission technology. However, due to constraints on integrated circuit pin resources and issues such as parallel signal synchronization, traditional parallel architectures have shown technical limitations when meeting modern high-speed bandwidth requirements. To combine the advantages of serial and parallel transmission while simultaneously addressing the challenges of signal integrity and clock synchronization in long-distance transmission, interface circuits have developed a serial-parallel-serial transmission method, namely the SerDes architecture.

[0003] The SerDes architecture has been widely adopted in cutting-edge fields such as data center interconnects, high-performance computing clusters, communications infrastructure, and artificial intelligence accelerators. Notably, the exponential growth of global data traffic continues to drive the evolution of SerDes technology toward ultra-high speeds. Data shows that SerDes transmission rates double every three to four years, posing significant challenges to the signal integrity and power consumption of interface circuits.

[0004] The transmitter is located at the transmitting end of the SerDes system. The transmitter first encodes the parallel data into a high-speed serial signal through the parallel-to-serial conversion module, and then transmits the signal to the channel through the driver unit. In order to offset the attenuation caused by channel loss, the transmitter usually adopts FFE compensation technology, that is, pre-distortion equalization processing of the signal before transmitting data. Its implementation method is as follows Figure 1 shown.

[0005] Transmitter drivers are typically categorized as SST (Source-Series Terminated) and CML (Current-Mode Logic). SST drivers, also known as voltage-mode drivers, offer advantages such as lower power consumption and improved linearity. However, when implementing FFE using the SST architecture, the circuit structure requires a large number of slices, and the equalization coefficient can only be adjusted discretely. Since equalization resolution is positively correlated with the number of slices, achieving high-precision equalization significantly increases parasitic capacitance at the output node, degrading output node bandwidth and significantly limiting the SST architecture's applicability in high-speed signal transmission scenarios. CML drivers, also known as current-mode drivers, utilize a current-switching topology to dynamically adjust the bias current of the differential pair transistors, achieving equivalent FFE with fewer slices. Furthermore, the equalization coefficient can be continuously adjusted. However, to achieve high-speed switching, CML drivers require maintaining a static bias current, resulting in increased power consumption. Furthermore, during signal conversion, the drain voltage of the current-tail transistor fluctuates. This dynamic impedance change affects the static bias current, ultimately manifesting as degraded linearity in the output eye diagram. Summary of the Invention

[0006] In response to the inherent technical contradictions of traditional single-mode drivers, the present invention provides a mixed-mode balanced-driven FFE circuit, SerDes transmitter and chip, which realizes the FFE function with a smaller number of slices, while maintaining low power consumption and high linearity, effectively overcoming the bandwidth limitations and equalization resolution bottlenecks of the existing architecture.

[0007] The present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a mixed-mode balanced-drive FFE circuit, comprising: A data retiming module is used to receive an external four-phase clock signal and eight channels of parallel data, and retime each channel of data into two channels of data output based on the clock signal; a multi-tap pulse generating module, configured to receive data outputted by the data retiming module and generate a front tap pulse signal, a main tap pulse signal and a rear tap pulse signal from the received data based on a four-phase clock signal; The multiplexing-hybrid balanced driving module includes a voltage mode driver and a current mode driver. The voltage mode driver is used to transmit the main tap pulse signal, and the current mode driver is used to convert the front tap pulse signal and the rear tap pulse signal into current and inject it into the output end of the multiplexing-hybrid balanced driving module to realize the FFE function.

[0008] Preferably, the data retiming module includes two circuit slices of the same structure, and the two circuit slices are respectively used to process the four highest-order signals and the four lowest-order signals in the eight-way parallel data; The multi-tap pulse generating module includes two circuit slices with the same structure. The two circuit slices of the multi-tap pulse generating module are connected to the two circuit slices of the data retiming module in a one-to-one correspondence.

[0009] Furthermore, the multiplexing-hybrid balanced driving module includes three circuit slices with the same structure, namely two MSB slices and one LSB slice; the two MSB slices are connected to the circuit slice that processes the highest bit signal in the multi-tap pulse generating module, and the LSB slice is connected to the circuit slice that processes the lowest bit signal in the multi-tap pulse generating module.

[0010] Furthermore, each circuit slice of the multi-tap pulse generating module includes three groups of unit pulse generating units, each group of unit pulse generating units includes four unit pulse generating units, and the three groups of unit pulse generating units in each circuit slice are respectively used to generate front tap pulse signals, main tap pulse signals and rear tap pulse signals.

[0011] Further, one circuit slice of the multi-tap pulse generation module includes first to twelfth unit pulse generation units, and another circuit slice includes thirteenth to twenty-fourth unit pulse generation units; one circuit slice of the data retiming module includes a first output terminal DMSB00, a second output terminal DMSB01, a third output terminal DMSB10, a fourth output terminal DMSB11, a fifth output terminal DMSB20, a sixth output terminal DMSB21, a seventh output terminal DMSB30, and an eighth output terminal DMSB31, and another circuit slice includes a ninth output terminal DLSB00, a tenth output terminal DLSB01, an eleventh output terminal DLSB10, a twelfth output terminal DLSB11, a thirteenth output terminal DLSB20, a fourteenth output terminal DLSB21, a fifteenth output terminal DLSB30, and a sixteenth output terminal DLSB31; The first input terminals of the first and fifth unit pulse generating units are connected to the first output terminal DMSB00, the first input terminals of the second and sixth unit pulse generating units are connected to the third output terminal DMSB10, the first input terminals of the third and seventh unit pulse generating units are connected to the fifth output terminal DMSB20, the first input terminals of the fourth and eighth unit pulse generating units are connected to the seventh output terminal DMSB30, and the first input terminals of the ninth, tenth, eleventh, and twelfth unit pulse generating units are connected to the second output terminal DMSB01, the fourth output terminal DMSB11, the sixth output terminal DMSB21, and the eighth output terminal DMSB31, respectively; The first input terminals of the thirteenth and seventeenth unit pulse generating units are connected to the ninth output terminal DLSB00, the first input terminals of the fourteenth and eighteenth unit pulse generating units are connected to the eleventh output terminal DLSB10, the first input terminals of the fifteenth and nineteenth unit pulse generating units are connected to the thirteenth output terminal DLSB20, the first input terminals of the sixteenth and twentieth unit pulse generating units are connected to the fifteenth output terminal DLSB30, and the first input terminals of the twenty-first, twenty-second, twenty-third and twenty-fourth unit pulse generating units are connected to the tenth output terminal DLSB01, the twelfth output terminal DLSB11, the fourteenth output terminal DLSB21 and the sixteenth output terminal DLSB31 respectively.

[0012] Furthermore, the second to fifth input terminals of the first, eighth, eleventh, thirteenth, twentieth and twenty-third unit pulse generating units are connected to the external clock signals CK1, CK2, CK3 and CK0 in sequence, the second to fifth input terminals of the second, fifth, twelfth, fourteenth, seventeenth and twenty-fourth unit pulse generating units are connected to the external clock signals CK2, CK3, CK0 and CK1 in sequence, the second to fifth input terminals of the third, sixth, ninth, fifteenth, eighteenth and twenty-first unit pulse generating units are connected to the external clock signals CK3, CK0, CK1 and CK2 in sequence, and the second to fifth input terminals of the fourth, seventh, tenth, sixteenth, nineteenth and twenty-second unit pulse generating units are connected to the external clock signals CK0, CK1, CK2 and CK3 in sequence.

[0013] Furthermore, each circuit slice of the multiplexing-hybrid balanced driving module includes: a first current mode driver, a second current mode driver, a first voltage mode driver, a second voltage mode driver, a first resistor R1 and a second resistor R2; the first current mode driver includes a first current source and first to eighth MOS transistors P1 to P8, and the second current mode driver includes a second current source and ninth to sixteenth MOS transistors P9 to P10. 16 structure; In the MSB slice: the sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, the drains are connected to the second end of the first resistor R1, and the gates are respectively connected to the second output terminals VB of the first to fourth unit pulse generating units; the sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, the drains are connected to the second end of the second resistor R2, and the gates are respectively connected to the third output terminals VC of the first to fourth unit pulse generating units; the ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, the drains are connected to the second end of the second resistor R1, and the gates are respectively connected to the third output terminals VC of the first to fourth unit pulse generating units. 12 The source of the MOS tubes P is connected to the second current source, the drain is connected to the second end of the first resistor R1, and the gate is connected to the second output end VB of the ninth to twelfth unit pulse generating units respectively; the thirteenth to sixteenth MOS tubes P 13 To P 16The source of the first voltage mode driver is connected to the second current source, the drain is connected to the second end of the second resistor R2, and the gate is respectively connected to the third output terminal VC of the ninth to twelfth unit pulse generating units; the first to fourth input terminals DP1 to DP4 of the first voltage mode driver are respectively connected to the third output terminal VC of the fifth to eighth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminal VA of the fifth to eighth unit pulse generating units, and the first output terminal DOUT of the first voltage mode driver is connected to the first end of the first resistor R1; the first to fourth input terminals DP1 to DP4 of the second voltage mode driver are respectively connected to the fourth output terminal VD of the fifth to eighth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminal VB of the fifth to eighth unit pulse generating units, and the first output terminal DOUT of the second voltage mode driver is connected to the first end of the second resistor R2; In the LSB slice: the sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, the drains are connected to the second end of the first resistor R1, and the gates are respectively connected to the second output terminals VB of the thirteenth to sixteenth unit pulse generating units; the sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, the drains are connected to the second end of the second resistor R2, and the gates are respectively connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units; the ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, the drains are connected to the second end of the second resistor R1, and the gates are respectively connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units. 12 The source of the MOS tubes P is connected to the second current source, the drain is connected to the second end of the first resistor R1, and the gate is connected to the second output end VB of the twenty-first to twenty-fourth unit pulse generating units respectively; the thirteenth to sixteenth MOS tubes P 13 To P 16 The source is connected to the second current source, the drain is connected to the second end of the second resistor R2, and the gate is respectively connected to the third output terminal VC of the twenty-first to twenty-fourth unit pulse generating units; the first to fourth input terminals DP1 to DP4 of the first voltage mode driver are respectively connected to the third output terminal VC of the seventeenth to twentieth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminal VA of the seventeenth to twentieth unit pulse generating units, and the first output terminal DOUT of the first voltage mode driver is connected to the first end of the first resistor R1; the first to fourth input terminals DP1 to DP4 of the second voltage mode driver are respectively connected to the fourth output terminal VD of the seventeenth to twentieth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminal VB of the seventeenth to twentieth unit pulse generating units, and the first output terminal DOUT of the second voltage mode driver is connected to the first end of the second resistor R2.

[0014] Furthermore, the first voltage-mode driver and the second voltage-mode driver both include: first to fourth MOS transistors M1 to M4, and fifth to eighth MOS transistors M5 to M8; the drains of the first to fourth MOS transistors M1 to M4 are connected one-to-one with the drains of the fifth to eighth MOS transistors M5 to M8, and serve as the first output terminal DOUT; the sources of the first to fourth MOS transistors M1 to M4 are connected to the power supply, and the sources of the fifth to eighth MOS transistors M5 to M8 are connected to the ground; the gates of the first to fourth MOS transistors M1 to M4 serve as the first to fourth input terminals DP1 to DP4, respectively, and the gates of the fifth to eighth MOS transistors M5 to M8 serve as the fifth to eighth input terminals DN1 to DN4, respectively.

[0015] In a second aspect, the present invention provides a mixed-mode balanced-driven SerDes transmitter comprising the FFE circuit described above.

[0016] In a third aspect, the present invention provides a chip comprising the FFE circuit as described above.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The present invention achieves the fusion of an SST driver and a CML driver through circuit structure design, and designs a multi-tap pulse generation module that can work in conjunction with them. Compared to equalization circuits using only SST or CML drivers, the present invention has the advantages of fewer slices, larger output node bandwidth, lower power consumption, and continuously adjustable equalization strength. It achieves FFE functionality with a relatively small number of slices, while maintaining low power consumption and high linearity, effectively overcoming the bandwidth limitations and equalization resolution bottlenecks of existing architectures. Specifically, unlike transmitters using SST drivers, the present invention uses CML drivers for equalization, and can achieve continuous adjustment of the equalization coefficient by adjusting the CML driver tail pipe bias voltage, avoiding the degradation of output node bandwidth caused by an excessive number of slices. Unlike transmitters using CML drivers, the present invention uses SST drivers to transmit main tap pulse signals, avoiding the linearity degradation caused by the tail pipe approaching the linear region when transmitting large swing signals. Furthermore, compared to using CML drivers to transmit main tap pulse signals, SST drivers have higher energy efficiency, which helps reduce system power consumption.

[0018] Traditional SerDes architectures typically perform the final stage of serialization before the driver, requiring multiple full-rate pre-drivers to improve signal drive capability. This introduces more full-rate signal nodes, resulting in additional power consumption. Furthermore, to increase full-rate node bandwidth to ensure signal integrity, active or passive inductor compensation technology is required, but this comes at the expense of area and power consumption. Unlike traditional SerDes architectures, the present invention places the final stage of serialization within the driver, avoiding the introduction of full-rate pre-drivers, effectively reducing the number of internal full-rate nodes, and lowering inter-symbol crosstalk introduced by parasitics in the data link, which is beneficial for improving eye diagram quality and reducing system power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 Schematic diagram of the implementation of FFE; Figure 2 1 is a structural block diagram of the FFE circuit of the mixed mode balanced drive in the present invention; Figure 3 A schematic diagram of a circuit slice of the data retiming module of the present invention; Figure 4 A signal timing diagram of a data retiming module according to an embodiment of the present invention; Figure 5 This is a structural block diagram of the multi-tap pulse generating module in the present invention; Figure 6 This is a schematic diagram of the unit pulse generation module of the present invention; Figure 7 This is a schematic diagram of the multiplexing-hybrid balanced driving module of the present invention; Figure 8 This is a schematic diagram of the 4:1 driver of the present invention; Figure 9 FIG. 1 is a signal timing diagram of a multiplexing-hybrid balanced driving module in one embodiment of the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and several specific embodiments. It should be pointed out that, without departing from the concept of the present invention, those skilled in the art can make equivalent substitutions or reasonable modifications to the following embodiments in combination with prior art knowledge, and such modifications and variations based on the technical essence of the present invention all fall within the scope of protection of the present invention. It should be understood that the embodiments described in the specification are only used to illustrate the principles and implementation methods of the present invention, and the scope of protection of the present invention shall be subject to the claims.

[0022] The accompanying drawings show schematic diagrams of the construction and operating principles of several exemplary embodiments of the present invention. It should be noted that the elements such as the proportional relationship of component sizes and relative position relationships presented in the accompanying drawings may be drawn in non-proportional manner. In particular: in order to highlight the structural features of key innovative parts, selected areas may be partially enlarged; in order to clearly demonstrate the core working principles of the technical solution, conventional structures that are not directly related to the invention may be simplified. Those skilled in the art should understand that this type of diagram processing is only a convention for expressing patent documents, does not affect the understanding of the substantive technical content of the invention, and does not constitute a limitation on the scope of protection of the invention.

[0023] The expressions "including," "comprising," and their variations used in this specification are open-ended expressions within the meaning of patent law and should be interpreted as "including but not limited to," meaning that equivalent technical elements beyond those described in the specification are permitted. Furthermore, unless otherwise specified, circuit numbers such as "first" and "second" are merely distinguishing identifiers of technical features and do not constitute absolute restrictions on the order of steps. Assuming the same technical effect, reasonable substitution of the order of steps or parallel implementation by those skilled in the art should be considered within the scope of protection of this invention.

[0024] To address the inherent technical contradictions of traditional single-mode driver architectures, this paper proposes a hybrid architecture driver that combines the advantages of voltage-mode and current-mode drivers, along with a coordinated multi-tap pulse generation module. The voltage-mode driver of this invention is specifically designed to transmit the main tap pulse signal, while the current-mode driver is configured to implement the FFE function. This avoids the reduction of output node bandwidth due to excessive circuit slicing while maintaining the linearity of the output eye diagram.

[0025] refer to Figure 2The hybrid-mode balanced drive FFE circuit of the present invention includes: a data retiming module, a multi-tap pulse generation module, and a multiplexing-hybrid balanced drive module. The data retiming module has external clock signal input terminals CK1, CK2, CK3, and CK4, and external data input terminals MSB0, MSB1, MSB2, MSB3, LSB0, LSB1, LSB2, and LSB3. The multi-tap pulse generation module has external clock signal input terminals CK1, CK2, CK3, and CK4. The multiplexing-hybrid balanced drive module has differential signal output terminals DOUTP and DOUTN connected to an external load.

[0026] The data retiming module, comprised of two circuit slices with identical circuit structures, receives eight parallel data signals and a four-phase clock signal from external input. The two circuit slices process four MSBs (most significant bit) and four LSBs (least significant bit) signals, respectively. The data retiming module retimes one data channel into two signals with a timing difference of four unit intervals, preventing timing errors during subsequent processing. A total of 16 channels of parallel data are output to the multi-tap pulse generation module. The unit interval (UI) is the reciprocal of the maximum symbol rate in this invention.

[0027] In a specific embodiment of the present invention, the four-phase clock signal provided by the external clock source is sequentially connected to the clock input terminals CK1, CK2, CK3, and CK4 of the data retiming module, and the eight-way parallel data provided by the external signal source is sequentially connected to the data input terminals MSB0, MSB1, MSB2, MSB3, LSB0, LSB1, LSB2, and LSB3 of the data retiming module. The first output terminal DMSB00, the second output terminal DMSB01, the third output terminal DMSB10, the fourth output terminal DMSB11, the fifth output terminal DMSB20, the sixth output terminal DMSB21, the seventh output terminal DMSB30, the eighth output terminal DMSB31, the ninth output terminal DLSB00, the tenth output terminal DLSB01, the eleventh output terminal DLSB10, the twelfth output terminal DLSB11, the thirteenth output terminal DLSB20, the fourteenth output terminal DLSB21, the fifteenth output terminal DLSB30, and the sixteenth output terminal DLSB31 of the data retiming module are sequentially connected to the multiple The first input terminal DMSB00, the second input terminal DMSB01, the third input terminal DMSB10, the fourth input terminal DMSB11, the fifth input terminal DMSB20, the sixth input terminal DMSB21, the seventh input terminal DMSB30, the eighth input terminal DMSB31, the ninth input terminal DLSB00, the tenth input terminal DLSB01, the eleventh input terminal DLSB10, the twelfth input terminal DLSB11, the thirteenth input terminal DLSB20, the fourteenth input terminal DLSB21, the fifteenth input terminal DLSB30 and the sixteenth input terminal DLSB31 of the tap pulse generating module are connected.

[0028] refer to Figure 3 Taking any circuit slice of the data retiming module as an example, this circuit slice consists of a tree structure of 22 D flip-flops. Labels like CK1 and CK2 in the figure represent external clocks connected to the clock inputs of the D flip-flops. Four parallel data inputs are retimed by CK1 and then pass through different delay paths to generate data outputs with different delays. Figure 4 The timing waveform diagram of the data retiming module is given. It can be found that each input data is retimed into two output data. The time interval between the two output data is 1UI, and the delay between the first data output and CK1 is 6UI to obtain sufficient timing margin.

[0029] The multi-tap pulse generation module is used to receive an external four-phase clock signal and the parallel output data from the data retiming module. Based on the multiple parallel data and clock signals of different phases, this module generates unit pulse signals for the front tap, main tap, and rear tap of different data, namely the front tap pulse signal, the main tap pulse signal, and the rear tap pulse signal. The generated signals serve as inputs to the multiplexing-hybrid equalization drive module.

[0030] refer to Figure 5 , the multi-tap pulse generation module is composed of twenty-four unit pulse generation units with the same structure. The first to fourth pulse generation units are the first group, the fifth to eighth pulse generation units are the second group, the ninth to twelfth pulse generation units are the third group, the thirteenth to sixteenth pulse generation units are the fourth group, the seventeenth to twentieth pulse generation units are the fifth group, and the twenty-first to twenty-fourth pulse generation units are the sixth group. Among them, the first, second, and third groups are the first circuit slices, which generate corresponding front tap pulse signals, main tap pulse signals, and rear tap pulse signals according to the MSB signal respectively. The fourth, fifth, and sixth groups are the second circuit slices, which generate corresponding front tap pulse signals, main tap pulse signals, and rear tap pulse signals according to the LSB signal respectively. The two circuit slices of the multi-tap pulse generation module are connected one-to-one with the two circuit slices of the data retiming module.

[0031] For a unit pulse generating unit of any circuit slice, the first input terminal D is used as a data input. IN , the second to fifth input terminals as clock input, the first output terminal VA, the second output terminal VB, the third output terminal VC and the fourth output terminal VD, where VB is the inverse signal of VA, VD is the inverse signal of VC, and the pulse width of VA, VB, VC and VD are all 1UI.

[0032] refer to Figure 6 The unit pulse generation unit includes a first NAND gate, a first NOR gate, a first MOS transistor P1, a second MOS transistor P2, a third MOS transistor P3, a fourth MOS transistor N1, a fifth MOS transistor N2, a sixth MOS transistor N3, and two pre-drivers. The sources of the first MOS transistor P1 and the third MOS transistor P3 are connected to a power supply, the sources of the fourth MOS transistor N1 and the sixth MOS transistor N3 are grounded, the drain of the first MOS transistor P1 is connected to the source of the second MOS transistor P2, the drain of the second MOS transistor P2 is connected to the drain of the fourth MOS transistor N1, the drain of the fifth MOS transistor N2 is connected to the drain of the third MOS transistor P3, and the source of the fifth MOS transistor N2 is connected to the drain of the sixth MOS transistor N3. External clocks CK1 and CK2 are connected to the first and second input terminals of the first NAND gate, respectively. The output terminal of the first NAND gate is connected to the gates of the first MOS transistor P1 and the fourth MOS transistor N1. The external clocks CK3 and CK4 are connected to the first input terminal and the second input terminal of the first NOR gate respectively. The first output terminal of the first NOR gate is connected to the gates of the third MOS transistor P3 and the sixth MOS transistor N3. The gates of the second MOS transistor P2 and the fifth MOS transistor N2 are connected and serve as the first input terminal D of the unit pulse generating unit. INThe drain of the second MOS transistor P2 and the drain of the fifth MOS transistor N2 are respectively connected to the input of a pre-driver. The pre-driver converts the single pulse input of the multi-tap pulse generation module into a differential pulse output and improves the ability of these signals to drive the load.

[0033] In order to ensure that the unit pulses from different data have the correct sequence, and to ensure that the multi-tap pulse signals from the same data have corresponding timing, the input ends of the 24 unit pulse generation units have different connection relationships with the external clock and data retiming modules.

[0034] The second to fifth input terminals of the first, eighth, eleventh, thirteenth, twentieth, and twenty-third unit pulse generating units are connected to the external clock signals CK1, CK2, CK3, and CK0, respectively. The second to fifth input terminals of the second, fifth, twelfth, fourteenth, seventeenth, and twenty-fourth unit pulse generating units are connected to the external clock signals CK2, CK3, CK0, and CK1, respectively. The second to fifth input terminals of the third, sixth, ninth, fifteenth, eighteenth, and twenty-first unit pulse generating units are connected to the external clock signals CK3, CK0, CK1, and CK2, respectively. The second to fifth input terminals of the fourth, seventh, tenth, sixteenth, nineteenth, and twenty-second unit pulse generating units are connected to the external clock signals CK0, CK1, CK2, and CK3, respectively.

[0035] The connection relationship between each pulse generation unit and the output terminal of the data retiming module is as follows: the first input terminals of the first and fifth unit pulse generation units are connected to the first output terminal DMSB00 of the data retiming module. The first input terminals of the second and sixth unit pulse generation units are connected to the third output terminal DMSB10 of the data retiming module. The first input terminals of the third and seventh unit pulse generation units are connected to the fifth output terminal DMSB20 of the data retiming module. The first input terminals of the fourth and eighth unit pulse generation units are connected to the seventh output terminal DMSB30 of the data retiming module. The first input terminals of the ninth, tenth, eleventh, and twelfth unit pulse generation units are respectively connected to the second output terminal DMSB01, the fourth output terminal DMSB11, the sixth output terminal DMSB21, and the eighth output terminal DMSB31 of the data retiming module.

[0036] The first input terminals of the thirteenth and seventeenth unit pulse generating units are connected to the ninth output terminal DLSB00 of the data retiming module. The first input terminals of the fourteenth and eighteenth unit pulse generating units are connected to the tenth output terminal DLSB10 of the data retiming module. The first input terminals of the fifteenth and nineteenth unit pulse generating units are connected to the eleventh output terminal DLSB20 of the data retiming module. The first input terminals of the sixteenth and twentieth unit pulse generating units are connected to the twelfth output terminal DLSB30 of the data retiming module. The first input terminals of the twenty-first, twenty-second, twenty-third, and twenty-fourth unit pulse generating units are respectively connected to the thirteenth, fourteenth, fifteenth, and sixteenth output terminals DLSB01, DLSB11, DLSB21, and DLSB31 of the data retiming module.

[0037] The multiplexing-hybrid equalization driving module is used to receive the output of the multi-tap pulse generating module, serialize and superimpose the multi-tap pulse signals and transmit them to the channel, and realize the FFE function to compensate for the channel insertion loss.

[0038] refer to Figure 7 The multiplexing-hybrid balanced driving module is composed of three circuit slices with the same structure, namely one LSB slice and two MSB slices. The two MSB slices process the signal from the first circuit slice of the multi-tap pulse generating module, and the LSB slice processes the signal from the second circuit slice of the multi-tap pulse generating module. The two MSB slices are connected to the circuit slice that processes the highest bit signal in the multi-tap pulse generating module of the first slice, and the LSB slice is connected to the circuit slice that processes the lowest bit signal in the multi-tap pulse generating module of the second slice. Any circuit slice of the multiplexing-hybrid balanced driving module includes: a first current source, a second current source, and first to sixteenth MOS tubes P1 to P 16 , a first voltage mode driver, a second voltage mode driver, a first resistor R1, and a second resistor R2. The multiplexing-hybrid balanced driving module uses a voltage mode driver to serialize four parallel main tap pulse signals into one serial data channel, and then uses a current mode driver to convert the front tap pulse signal and the rear tap pulse signal into current and inject it into the output end of the multiplexing-hybrid balanced driving module to achieve the FFE function.

[0039] refer to Figure 7 The first current mode driver is composed of the first current source and the first to eighth MOS tubes P1 to P8, and the second current mode driver is composed of the second current source and the ninth to sixteenth MOS tubes P9 to P 16The sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, and the drains are connected to the second end of the first resistor R1. The sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, and the drains are connected to the second end of the second resistor R2. The ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, and the drains are connected to the second end of the second resistor R1. 12 The source of the thirteenth to sixteenth MOS tubes P is connected to the second current source, and the drain is connected to the second end of the first resistor R1. 13 To P 16 The source is connected to the second current source, and the drain is connected to the second end of the second resistor R2.

[0040] refer to Figure 8 Each voltage-mode driver includes first to fourth input terminals DP1 to DP4, fifth to eighth input terminals DN1 to DN4, and a first output terminal DOUT. The driver is composed of first to fourth MOS transistors M1 to M4 and fifth to eighth MOS transistors M5 to M8. The drains of the first to fourth MOS transistors M1 to M4 are connected one-to-one with the drains of the fifth to eighth MOS transistors M5 to M8, and serve as the first output terminal DOUT of the voltage-mode driver. The sources of the first to fourth MOS transistors M1 to M4 are connected to the power supply, and the sources of the fifth to eighth MOS transistors M5 to M8 are connected to ground. The gates of the first to fourth MOS transistors M1 to M4 serve as the first to fourth input terminals DP1 to DP4, respectively, and the gates of the fifth to eighth MOS transistors M5 to M8 serve as the fifth to eighth input terminals DN1 to DN4, respectively.

[0041] The connection relationship between the two MSB slices and the multi-tap pulse generation module is the same, wherein the drains of the first to fourth MOS transistors P1 to P4 of the current mode driver serve as the first output terminal DOUTP of the multiplexing-hybrid balanced driving module, and the gates are respectively connected to the second output terminals VB of the first to fourth unit pulse generation units. The drains of the fifth to eighth MOS transistors P5 to P8 serve as the second output terminal DOUTN of the multiplexing-hybrid balanced driving module, and the gates are respectively connected to the third output terminals VC of the first to fourth unit pulse generation units. The ninth to twelfth MOS transistors P9 to P 12 The gates of the thirteenth to sixteenth MOS tubes P are connected to the second output terminals VB of the ninth to twelfth unit pulse generating units respectively. 13 To P 16The gates of the first voltage-mode driver are respectively connected to the third output terminals VC of the ninth to twelfth unit pulse generating units. The first to fourth input terminals DP1 to DP4 of the first voltage-mode driver are respectively connected to the third output terminals VC of the fifth to eighth unit pulse generating units, and the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminals VA of the fifth to eighth unit pulse generating units. The first output terminal DOUT of the first voltage-mode driver is connected to the first end of the first resistor R1. The first to fourth input terminals DP1 to DP4 of the second voltage-mode driver are respectively connected to the fourth output terminals VD of the fifth to eighth unit pulse generating units, and the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminals VB of the fifth to eighth unit pulse generating units. The first output terminal DOUT of the second voltage-mode driver is connected to the first end of the second resistor R2.

[0042] Similarly, in the LSB slice, the sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, the drains are connected to the second end of the first resistor R1, and the gates are connected to the second output terminals VB of the thirteenth to sixteenth unit pulse generating units, respectively. The sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, the drains are connected to the second end of the second resistor R2, and the gates are connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units, respectively. The ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, the drains are connected to the second end of the second resistor R1, and the gates are connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units, respectively. 12 The source of the MOS tubes P is connected to the second current source, the drain is connected to the second end of the first resistor R1, and the gate is connected to the second output end VB of the 21st to 24th unit pulse generating units respectively. 13 To P 16 The source is connected to the second current source, the drain is connected to the second end of the second resistor R2, and the gate is respectively connected to the third output terminal VC of the 21st to 24th unit pulse generating units. The first to fourth input terminals DP1 to DP4 of the first voltage mode driver are connected to the third output terminal VC of the 17th to 20th unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminals VA of the 17th to 20th unit pulse generating units, and the first output terminal DOUT of the first voltage mode driver is connected to the first end of the first resistor R1. The first to fourth input terminals DP1 to DP4 of the second voltage mode driver are connected to the fourth output terminal VD of the 17th to 20th unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminals VB of the 17th to 20th unit pulse generating units, and the first output terminal DOUT of the second voltage mode driver is connected to the first end of the second resistor R2.

[0043] refer to Figure 9 In a specific embodiment of the present invention, it is assumed that the main tap data being sent is D0 and the front tap data is D-1 , the rear tap data is D1. For the first voltage mode driver of any circuit slice of the multiplexing-hybrid balanced driving module, D0 needs to generate two signals VA and VC in the multi-tap pulse generating module. VA and VC have 1UI in every 4UI as data D0, and VA is at a low level in the remaining 3UI to turn off the fifth MOS tube M5 of the voltage mode driver, and VC is at a high level to turn off the first MOS tube M1 of the voltage mode driver, so as not to affect the transmission of other data. Similarly, for the second voltage mode driver, D0 needs to generate two signals VB and VD in the multi-tap pulse generating module. VB and VD are the inverted signals of VA and VC respectively, to generate differential data output. Similarly, the first current mode driver needs to be driven by D -1 The second current mode driver needs to be driven by the VB and VC signals generated by D1 in the multi-tap pulse generation module.

[0044] The transmitter including the FFE circuit of the present invention combines the advantages of a voltage mode driver and a current mode driver, realizes the FFE function of continuously adjusting the equalization coefficient with a smaller number of slices, and ensures the linearity of the output eye diagram and lower power consumption.

[0045] It should be understood that the embodiments disclosed herein are illustrative in nature and not restrictive. Those skilled in the art will recognize that various modifications, adjustments, or alterations may be made to the embodiments described in the specification and accompanying drawings without departing from the subject matter and spirit of the present invention as defined by the appended claims. These modifications may involve changes in structural configurations or process parameters, and all such modifications are considered to fall within the scope of protection of the present invention.

Claims

1. A mixed-mode balanced-drive FFE circuit, characterized in that: include: A data retiming module is used to receive an external four-phase clock signal and eight channels of parallel data, and retime each channel of data into two channels of data output based on the clock signal; a multi-tap pulse generating module, configured to receive data outputted by the data retiming module and generate a front tap pulse signal, a main tap pulse signal and a rear tap pulse signal from the received data based on a four-phase clock signal; The multiplexing-hybrid balanced driving module includes a voltage mode driver and a current mode driver. The voltage mode driver is used to transmit the main tap pulse signal, and the current mode driver is used to convert the front tap pulse signal and the rear tap pulse signal into current and inject it into the output end of the multiplexing-hybrid balanced driving module to realize the FFE function.

2. The mixed-mode balanced drive FFE circuit according to claim 1, characterized in that: The data retiming module includes two circuit slices with the same structure, and the two circuit slices are respectively used to process the four most significant signals and the four least significant signals in the eight parallel data channels; The multi-tap pulse generating module includes two circuit slices with the same structure. The two circuit slices of the multi-tap pulse generating module are connected to the two circuit slices of the data retiming module in a one-to-one correspondence.

3. The mixed-mode balanced drive FFE circuit according to claim 2, characterized in that: The multiplexing-hybrid balanced driving module includes three circuit slices with the same structure, namely two MSB slices and one LSB slice; the two MSB slices are connected to the circuit slice that processes the highest bit signal in the multi-tap pulse generation module, and the LSB slice is connected to the circuit slice that processes the lowest bit signal in the multi-tap pulse generation module.

4. The mixed-mode balanced-drive FFE circuit according to claim 3, characterized in that: Each circuit slice of the multi-tap pulse generating module includes three groups of unit pulse generating units, each group of unit pulse generating units includes four unit pulse generating units, and the three groups of unit pulse generating units in each circuit slice are used to generate front tap pulse signals, main tap pulse signals and rear tap pulse signals respectively.

5. The mixed-mode balanced-drive FFE circuit according to claim 4, characterized in that: One circuit slice of the multi-tap pulse generation module includes first to twelfth unit pulse generation units, and another circuit slice includes thirteenth to twenty-fourth unit pulse generation units; one circuit slice of the data retiming module includes a first output terminal DMSB00, a second output terminal DMSB01, a third output terminal DMSB10, a fourth output terminal DMSB11, a fifth output terminal DMSB20, a sixth output terminal DMSB21, a seventh output terminal DMSB30, and an eighth output terminal DMSB31, and another circuit slice includes a ninth output terminal DLSB00, a tenth output terminal DLSB01, an eleventh output terminal DLSB10, a twelfth output terminal DLSB11, a thirteenth output terminal DLSB20, a fourteenth output terminal DLSB21, a fifteenth output terminal DLSB30, and a sixteenth output terminal DLSB31; The first input terminals of the first and fifth unit pulse generating units are connected to the first output terminal DMSB00, the first input terminals of the second and sixth unit pulse generating units are connected to the third output terminal DMSB10, the first input terminals of the third and seventh unit pulse generating units are connected to the fifth output terminal DMSB20, the first input terminals of the fourth and eighth unit pulse generating units are connected to the seventh output terminal DMSB30, and the first input terminals of the ninth, tenth, eleventh, and twelfth unit pulse generating units are connected to the second output terminal DMSB01, the fourth output terminal DMSB11, the sixth output terminal DMSB21, and the eighth output terminal DMSB31, respectively; The first input terminals of the thirteenth and seventeenth unit pulse generating units are connected to the ninth output terminal DLSB00, the first input terminals of the fourteenth and eighteenth unit pulse generating units are connected to the eleventh output terminal DLSB10, the first input terminals of the fifteenth and nineteenth unit pulse generating units are connected to the thirteenth output terminal DLSB20, the first input terminals of the sixteenth and twentieth unit pulse generating units are connected to the fifteenth output terminal DLSB30, and the first input terminals of the twenty-first, twenty-second, twenty-third and twenty-fourth unit pulse generating units are connected to the tenth output terminal DLSB01, the twelfth output terminal DLSB11, the fourteenth output terminal DLSB21 and the sixteenth output terminal DLSB31 respectively.

6. The mixed-mode balanced-drive FFE circuit according to claim 5, characterized in that: The second to fifth input terminals of the first, eighth, eleventh, thirteenth, twentieth and twenty-third unit pulse generating units are connected to the external clock signals CK1, CK2, CK3 and CK0 in sequence, the second to fifth input terminals of the second, fifth, twelfth, fourteenth, seventeenth and twenty-fourth unit pulse generating units are connected to the external clock signals CK2, CK3, CK0 and CK1 in sequence, the second to fifth input terminals of the third, sixth, ninth, fifteenth, eighteenth and twenty-first unit pulse generating units are connected to the external clock signals CK3, CK0, CK1 and CK2 in sequence, and the second to fifth input terminals of the fourth, seventh, tenth, sixteenth, nineteenth and twenty-second unit pulse generating units are connected to the external clock signals CK0, CK1, CK2 and CK3 in sequence.

7. The mixed-mode balanced-drive FFE circuit according to claim 5, characterized in that: Each circuit slice of the multiplexing-hybrid balanced driving module includes: a first current mode driver, a second current mode driver, a first voltage mode driver, a second voltage mode driver, a first resistor R1 and a second resistor R2; the first current mode driver includes a first current source and first to eighth MOS transistors P1 to P8, and the second current mode driver includes a second current source and ninth to sixteenth MOS transistors P9 to P1. 16 structure; In the MSB slice: the sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, the drains are connected to the second end of the first resistor R1, and the gates are respectively connected to the second output terminals VB of the first to fourth unit pulse generating units; the sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, the drains are connected to the second end of the second resistor R2, and the gates are respectively connected to the third output terminals VC of the first to fourth unit pulse generating units; the ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, the drains are connected to the second end of the second resistor R1, and the gates are respectively connected to the third output terminals VC of the first to fourth unit pulse generating units. 12 The source of the MOS tubes P is connected to the second current source, the drain is connected to the second end of the first resistor R1, and the gate is connected to the second output end VB of the ninth to twelfth unit pulse generating units respectively; the thirteenth to sixteenth MOS tubes P 13 To P 16 The source of the first voltage mode driver is connected to the second current source, the drain is connected to the second end of the second resistor R2, and the gate is respectively connected to the third output terminal VC of the ninth to twelfth unit pulse generating units; the first to fourth input terminals DP1 to DP4 of the first voltage mode driver are respectively connected to the third output terminal VC of the fifth to eighth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminal VA of the fifth to eighth unit pulse generating units, and the first output terminal DOUT of the first voltage mode driver is connected to the first end of the first resistor R1; the first to fourth input terminals DP1 to DP4 of the second voltage mode driver are respectively connected to the fourth output terminal VD of the fifth to eighth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminal VB of the fifth to eighth unit pulse generating units, and the first output terminal DOUT of the second voltage mode driver is connected to the first end of the second resistor R2; In the LSB slice: the sources of the first to fourth MOS transistors P1 to P4 are connected to the first current source, the drains are connected to the second end of the first resistor R1, and the gates are respectively connected to the second output terminals VB of the thirteenth to sixteenth unit pulse generating units; the sources of the fifth to eighth MOS transistors P5 to P8 are connected to the first current source, the drains are connected to the second end of the second resistor R2, and the gates are respectively connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units; the ninth to twelfth MOS transistors P9 to P10 are connected to the first current source, the drains are connected to the second end of the second resistor R1, and the gates are respectively connected to the third output terminals VC of the thirteenth to sixteenth unit pulse generating units. 12 The source of the MOS tubes P is connected to the second current source, the drain is connected to the second end of the first resistor R1, and the gate is connected to the second output end VB of the twenty-first to twenty-fourth unit pulse generating units respectively; the thirteenth to sixteenth MOS tubes P 13 To P 16 The source is connected to the second current source, the drain is connected to the second end of the second resistor R2, and the gate is respectively connected to the third output terminal VC of the twenty-first to twenty-fourth unit pulse generating units; the first to fourth input terminals DP1 to DP4 of the first voltage mode driver are respectively connected to the third output terminal VC of the seventeenth to twentieth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the first output terminal VA of the seventeenth to twentieth unit pulse generating units, and the first output terminal DOUT of the first voltage mode driver is connected to the first end of the first resistor R1; the first to fourth input terminals DP1 to DP4 of the second voltage mode driver are respectively connected to the fourth output terminal VD of the seventeenth to twentieth unit pulse generating units, the fifth to eighth input terminals DN1 to DN4 are respectively connected to the second output terminal VB of the seventeenth to twentieth unit pulse generating units, and the first output terminal DOUT of the second voltage mode driver is connected to the first end of the second resistor R2.

8. The mixed-mode balanced-drive FFE circuit according to claim 7, characterized in that: The first voltage-mode driver and the second voltage-mode driver both include: first to fourth MOS transistors M1 to M4, and fifth to eighth MOS transistors M5 to M8; the drains of the first to fourth MOS transistors M1 to M4 are connected one-to-one with the drains of the fifth to eighth MOS transistors M5 to M8, and serve as the first output terminal DOUT; the sources of the first to fourth MOS transistors M1 to M4 are connected to the power supply, and the sources of the fifth to eighth MOS transistors M5 to M8 are connected to the ground; the gates of the first to fourth MOS transistors M1 to M4 serve as the first to fourth input terminals DP1 to DP4, respectively, and the gates of the fifth to eighth MOS transistors M5 to M8 serve as the fifth to eighth input terminals DN1 to DN4, respectively.

9. A mixed-mode balanced-driven SerDes transmitter, characterized in that: The FFE circuit comprises the FFE circuit according to any one of claims 1 to 8.

10. A chip, characterized in that The FFE circuit comprises the FFE circuit according to any one of claims 1 to 8.

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