JPEG image compression system and method based on FPGA double-matrix shared pipeline

Abstract

The application discloses a JPEG image compression system and method based on a double-matrix shared pipeline of FPGA, and the JPEG image compression system comprises a YUV420 preprocessing module, a double-8-row-matrix segmentation storage module, a shared pipeline timing scheduling module, a shared processing module and a merging and coding module, and the application further provides a JPEG image compression method based on the double-matrix shared pipeline of FPGA.The technical scheme of the application can break through the traditional independent module architecture, realizes efficient time-sharing multiplexing of core modules such as YUV three-component DCT transformation, quantization, ZigZag scanning and Huffman coding through double-8-row-matrix segmentation and timing alignment shared pipeline design, forms a complete and efficient JPEG coding system through optimization of data organization, processing flow and timing control, significantly reduces the calculation complexity and data carrying cost, and is particularly suitable for resource-limited embedded image compression application scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of image processing and data compression, in particular to a JPEG image compression system and method based on a FPGA double-matrix shared pipeline. BACKGROUND

[0002] The existing image compression algorithm is mainly divided into two categories, namely lossless compression and lossy compression. Lossless compression refers to not losing any information of the image, and is simply realized by coding the statistical characteristics of the data stream, but this compression is usually difficult to meet the requirement of high compression ratio. Lossy compression refers to the loss of certain redundant information or insensitive information in the compression process, which does not have too much impact on subsequent image processing, but can obtain high compression ratio. The JPEG compression algorithm is the most widely used lossy compression algorithm, which has the characteristics of high compression efficiency and simple algorithm, and is widely used in digital photography, network transmission, remote sensing communication and other fields.

[0003] At present, in the existing JPEG image compression scheme based on FPGA, the processing of YUV color space generally adopts a component independent processing architecture: the luminance component (Y) and the chrominance component (U, V) are processed through independent DCT modules, Zig-Zag scanning modules, quantization modules and Huffman coding modules. This architecture has the following significant defects:

[0004] Hardware resource redundancy: each component needs to be configured with a complete set of processing modules. Taking 8-bit image data as an example, a single DCT module needs 64 multipliers and 192 adders, and independent configuration of three components will directly multiply the resource occupation by 3, which seriously increases the consumption of FPGA logic elements (LE), storage units (RAM) and multipliers (DSP).

[0005] Coding module isolation: Huffman coding is the core link of entropy coding, and the existing scheme does not consider the statistical characteristics of YUV component code stream. Independent coding leads to repeated design of code table buffer (3 sets of independent code table need to be stored) and coding control logic, further wasting resources. SUMMARY

[0006] The main purpose of the present application is to provide a JPEG image compression system and method based on a FPGA double-matrix shared pipeline, which is aimed at image data compression processing under YUV color space, and realizes efficient time-sharing multiplexing of Y, U, V three components of discrete cosine transform (DCT), Zig-Zag scanning, quantization and Huffman coding and other core modules through double 8-row matrix division architecture and timing alignment shared pipeline design, solving the technical problem of hardware resource redundancy in the traditional scheme.

[0007] To achieve the above object, the application provides a JPEG image compression system based on FPGA double-matrix shared pipeline, which comprises:

[0008] A YUV420 preprocessing module is used for converting YUV444 format data into YUV420 format data, completely retaining Y component, 2:1 horizontal / vertical downsampling UV component, generating Y component data stream and 2:1 horizontal / vertical downsampling UV component data stream;

[0009] A double-8-row-matrix division storage module is used for alternately storing Y component data stream into Y1 and Y2 buffer areas according to rows, forming double-8-row-matrix structure, and synchronously storing UV component data stream, obtaining Y1, Y2, U and V data blocks, realizing Y1 / Y2 double-matrix division of Y component and 8-row-aligned storage of UV component;

[0010] A shared pipeline timing scheduling module is used for reading Y1, Y2, U and V data blocks from Y1 and Y2 buffer areas according to Y1→Y1→Y2→Y2→U→V sequence, generating timing control signals of shared processing pipeline, realizing pipeline continuous processing, and converting parallel multi-component data into serial data stream;

[0011] A shared processing module is used for time-division multiplexing to execute DCT transformation, quantization, ZigZag scanning, run-length encoding and Huffman encoding processing of Y1, Y2, U and V data blocks according to the timing control signals;

[0012] A merging and encoding module is used for splicing encoding output into continuous bit stream, generating output according to byte alignment, realizing format integration of encoding data, and generating compression data stream conforming to JPEG standard.

[0013] Optionally, the double-8-row-matrix division storage module alternately generates two 8x8 Y1 and Y2 data blocks by row count control and division counter every 16 rows of Y component data, and the UV component data stream is stored according to 8-row depth, and forms six 8x8 data block standard input groups with Y1 and Y2 data blocks, so as to provide standardized 8x8 data blocks for the shared pipeline.

[0014] Optionally, the shared pipeline timing scheduling module adopts a three-section state machine, and the three-section state machine comprises:

[0015] IDLE state: when the amount of UV component FIFO data is greater than or equal to 8, jumping to read enable generation state;

[0016] GEN_RD_EN state: generating read enable signals according to Y1→Y1→Y2→Y2→U→V sequence through 48-period counter;

[0017] WAIT_BACK state: listen to the back-end FIFO empty flag, to ensure that the shared pipeline has no data backlog.

[0018] Optionally, the shared processing module comprises:

[0019] The shared two-dimensional DCT transform module is configured to decompose the two-dimensional DCT into row transform and column transform by a row-column separation algorithm, to convert cosine base function floating point coefficients into 16-bit fixed point numbers by using a Loeffler algorithm, and to realize 8-point DCT calculation by a 3-stage butterfly network.

[0020] The dynamic quantization module is configured to perform non-uniform quantization on the DCT coefficients based on a timing control signal, to dynamically switch between luma / chroma quantization tables, and to preserve low-frequency information sensitive to the human eye.

[0021] The Zigzag pipeline scanning module is configured to rearrange the 8x8 quantized coefficient matrix into a one-dimensional sequence in a Zigzag path, and to perform DPCM differential encoding on the DC coefficient.

[0022] The shared run-length encoding module is configured to compress the one-dimensional sequence after Zigzag scanning, to perform zero run-length encoding, and to reduce the data volume.

[0023] The four-table shared Huffman encoding module is configured to perform variable-length encoding on the DC / AC four independent code tables of Y, U and V component data after run-length encoding, to assign different lengths of codes according to the data occurrence probability, and to realize lossless compression.

[0024] Optionally, the dynamic quantization module dynamically switches between luma / chroma quantization tables according to a 48-cycle counter, wherein:

[0025] When the counter is in the 0-31 cycle, Y1 and Y2 data blocks are processed using the luma quantization table.

[0026] When the counter is in the 32-47 cycle, U and V data blocks are processed using the chroma quantization table.

[0027] In another aspect, the present application further provides a JPEG image compression method based on a FPGA double-matrix shared pipeline, which is performed by using the above-mentioned JPEG image compression system based on a FPGA double-matrix shared pipeline.

[0028] The YUV444 format data is converted into YUV420 format to generate Y component data stream and UV component data stream subjected to 2:1 horizontal / vertical down-sampling.

[0029] The Y component data stream is alternately stored by row to Y1 and Y2 buffer areas to form a double 8-row matrix structure, and the UV component data stream is synchronously stored, Y1 / Y2 double matrix partitioning of the Y component and 8-row aligned storage of the UV component are realized, and a standardized 8x8 data block is provided for a shared pipeline;

[0030] Data blocks are read from the Y1 and Y2 buffer areas in the order of Y1→Y1→Y2→Y2→U→V, timing control signals of the shared processing pipeline are generated, and output is performed in the order of Y1→Y1→Y2→Y2→U→V, and pipeline continuous processing is realized;

[0031] Based on the timing control signals, DCT transformation, quantization, ZigZag scanning, run-length encoding and Huffman encoding processing of Y1, Y2, U and V data blocks are executed in time multiplexing;

[0032] The encoded output is spliced into a continuous bit stream, and a compressed data stream conforming to the JPEG standard is generated.

[0033] Optionally, the conversion of the YUV444 format data into YUV420 format to generate a Y component data stream and a UV component data stream subjected to 2:1 horizontal / vertical downsampling includes the following steps:

[0034] Data buffering: a 2-row deep UV component buffer is constructed to form a 2x2 pixel window matrix;

[0035] Mean value calculation: the sum of the 4 UV values in the window is calculated, and efficient average calculation is realized by right shifting 2 bits;

[0036] Data alignment output: a YUV420 format data stream is generated, the Y resolution is 2x2 times that of the UV, and the double 8-row matrix partitioning requirement is matched.

[0037] Optionally, alternately storing the Y component data stream by row to Y1 and Y2 buffer areas to form a double 8-row matrix structure includes the following steps:

[0038] Through row count control, 2 8x8 Y1 and Y2 data blocks are alternately generated every 16 rows of Y component data received;

[0039] The UV component data stream is buffered by 8 rows of depth to form a standard input group of 6 8x8 data blocks with the Y1 / Y2 data blocks.

[0040] Optionally, the DCT transformation, quantization, ZigZag scanning, run-length encoding and Huffman encoding processing of Y1, Y2, U and V data blocks based on the timing control signals includes the following steps:

[0041] Based on the 48 cycle counter value, the luminance quantization table is used when processing Y1 and Y2 data blocks in 0-31 cycles, and the chrominance quantization table is used when processing U and V data blocks in 32-47 cycles.

[0042] Based on the Y / UV component DC / AC four independent code tables, Huffman coding is performed on different component data.

[0043] Optionally, based on the timing control signal, the DCT transform of Y1, Y2, U and V data blocks is time-multiplexed, including the following steps:

[0044] Row and column separation: decompose the two-dimensional DCT into 8 one-dimensional row transform + 8 one-dimensional column transform, that is:

[0045] Wherein, f(x, y) is the spatial domain 8x8 pixel value, C i (x) and C j (y) are cosine basis functions, a one-dimensional DCT unit is called for each row of the 8x8 image block to generate an intermediate frequency domain matrix, the row transform result is interchanged in row and column dimensions through a double-port BRAM, converted into column data format, and then a one-dimensional DCT unit is called for the transposed column data to output a complete 8x8 frequency domain coefficient matrix.

[0046] Butterfly operation: Loeffler algorithm is adopted to complete 8-point DCT calculation through a 3-stage butterfly network, only 4 multiplications and 8 additions are required in each stage, and the matrix multiplication is decomposed into iteration operation of addition and subtraction + a small amount of multiplication by utilizing the symmetry of the cosine function.

[0047] Fixed-point implementation: convert the floating-point coefficients of the cosine basis function into 16-bit fixed-point numbers.

[0048] The technical scheme of the present application has the following beneficial effects: The technical scheme of the present application breaks through the traditional independent module architecture, realizes efficient time-multiplexing of core modules such as DCT transform, quantization, ZigZag scanning and Huffman coding of YUV three components through double 8-row matrix segmentation and timing alignment shared pipeline design, and has the following advantages: Compared with the traditional three-channel architecture, the logic units and DSP resources are reduced by more than 50%; The on-chip SRAM demand is reduced by 30% without simultaneously buffering the intermediate results of three components; The average power consumption is reduced by 40% and the data bus bandwidth demand is reduced by 30% due to the time-multiplexing mechanism; The data path is simplified, the FPGA / ASIC wiring difficulty is reduced, the development cycle is shortened by about 25%, and the implementation complexity is optimized; The present application forms a complete and efficient JPEG encoding system by optimizing data organization, processing flow and timing control, significantly reduces the calculation complexity and data handling overhead, and is particularly suitable for resource-limited embedded image compression application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.

[0050] Figure 1 The overall module framework structure schematic diagram of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application;

[0051] Figure 2 The partial module framework structure schematic diagram of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application;

[0052] Figure 3 The JPEG image compression running flowchart of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application;

[0053] Figure 4 The YUV data storage module flowchart of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application;

[0054] Figure 5 The flowchart of the shared pipeline timing scheduling module state machine of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application.

[0055] Figure 6 The ZigZag path diagram of a JPEG image compression system based on FPGA double-matrix shared pipeline according to an embodiment of the present application;

[0056] Figure 7 The flowchart of a JPEG image compression method based on FPGA double-matrix shared pipeline according to an embodiment of the present application.

[0057] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0058] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present application.

[0059] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indications also change accordingly.

[0060] In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope of the present application.

[0061] The present application provides a JPEG image compression system and method based on FPGA double-matrix shared pipeline.

[0062] As shown in the figure, in an embodiment of the present application, the JPEG image compression system based on FPGA double-matrix shared pipeline comprises: Figures 1 to 6 The YUV420 preprocessing module 101 is used to convert YUV444 format data into YUV420 format data, completely retains Y component, performs 2:1 horizontal / vertical downsampling on UV component, generates Y component data stream and UV component data stream which is 2:1 horizontally / vertically downsampled;

[0063] The double-8-row-matrix division storage module 102 is used to store Y component data stream alternately into Y1 and Y2 buffer areas according to rows, forms double-8-row-matrix structure, and synchronously stores UV component data stream, obtains Y1, Y2, U, V data blocks, realizes Y1 / Y2 double-matrix division of Y component and 8-row-aligned storage of UV component;

[0064] The shared pipeline timing scheduling module 103 is used to read Y1, Y2, U, V data blocks from Y1 and Y2 buffer areas in the order of Y1→Y1→Y2→Y2→U→V, generates timing control signals of shared processing pipeline, realizes pipeline type continuous processing, and converts parallel multi-component data into serial data stream;

[0065]

[0066] ​The shared processing module 104 is used to perform DCT transformation, quantization, ZigZag scanning, run-length coding and Huffman coding of the Y1, Y2, U and V data blocks in a time-division multiplexing manner according to the timing control signal;

[0067] The merge encoding module 105 is used to splice the encoded output into a continuous bit stream and generate output according to byte alignment to achieve formatted integration of the encoded data and generate a compressed data stream that complies with the JPEG standard.

[0068] The JPEG image compression system based on FPGA dual matrix shared pipeline of the present invention builds a JPEG compression architecture with dual 8-row matrix segmentation and time alignment shared pipeline as the core, and realizes efficient compression processing of YUV three-component through the collaboration of 9 major modules. The JPEG image compression process is as follows Figure 3 shown.

[0069] Specifically, the YUV420 pre-processing module 101 (dual matrix preparation) is used to implement the format conversion from YUV444 to YUV420, completely retain the Y component, perform 2:1 horizontal / vertical downsampling on the UV component, use 2×2 block mean filtering to ensure chroma smoothing, and provide pre-processed data for dual 8-row matrix segmentation. The specific implementation process steps are as follows:

[0070] (1) Data cache: Construct a UV component cache with a depth of 2 rows to form a 2×2 pixel window matrix;

[0071] (2) Mean calculation: Sum the four UV values ​​within the window and perform efficient averaging by right shifting by 2 bits (fixed-point division);

[0072] (3) Data alignment output: Generates a YUV420 format data stream with a Y resolution of 2×2 times that of UV, matching the dual 8-row matrix segmentation requirements.

[0073] Specifically, the dual 8-row matrix segmentation storage module 102 realizes the Y1 / Y2 dual matrix segmentation of the Y component and the 8-row aligned storage of the UV component through independent caching, row count judgment, write enable triggering and FIFO write control, providing standardized 8×8 data blocks for the shared pipeline, supporting the efficient operation of subsequent encoding, algorithm processing and other links. The realized flow chart is as follows: Figure 4 As shown, the specific implementation process steps are as follows:

[0074] (1) Parallel channel input: Y, U, and V component data are continuously input through independent channels. When i_de_Y is valid, i_data_Y is written into the Y buffer 8×8 sliding window row by row; similarly, data is written into the U / V buffer 8×8 sliding window through i_de_U / i_data_U and i_de_V / i_data_V.

[0075] (2) Row count and write enable control: The Y component triggers row count through the rising edge of i_de_Y, and the 3-bit counter row_cnt_Y counts 0-7 in a loop. When row_cnt_Y=7, o_de_Y==i_de_Y, and the counter automatically resets to zero to enter the next row count cycle. The UV component is the same as the Y component. When the row count reaches 7, the output is o_de_U=i_de_U and o_de_V=i_de_V.

[0076] (3) Y component double buffer division: count the falling edges of o_de_Y and use the 1-bit counter row_cnt_Y (0 / 1 cycle) to implement Y1 / Y2 switching. When row_cnt_Y=0, o_de_Y1=o_de_Y; when row_cnt_Y=1, o_de_Y2=o_de_Y, thereby writing the first 8 rows of Y and the last 8 rows of Y into the corresponding FIFO respectively, realizing the dual 8-row matrix division strategy;

[0077] (4) Data bit width and transmission cycle: The single pixel bit width is 8 bits / pixel, which complies with the YUV420 standard; the bus bit width is 64 bits (8 pixels × 8 bits / pixel), one line of data is transmitted per clock cycle, and an 8 × 8 data block is written in 8 cycles.

[0078] Specifically, the shared pipeline timing scheduling module 103 is designed to meet the YUV42016×16 matrix operation requirements in JPEG compression processing. It converts parallel multi-component data (Y1 / Y2 / U / V matrices) into a serial data stream and outputs it in the order of Y1→Y1→Y2→Y2→U→V, realizing pipeline continuous processing, eliminating data waiting bottlenecks, and ensuring orderly and efficient processing of each component data.

[0079] The specific implementation process is: use the three-state state machine (IDLE→GEN_RD_EN→WAIT_BACK) to implement the function. The state machine process is as follows: Figure 5 The specific process steps are as follows:

[0080] (1) Initial state (IDLE)

[0081] Function: Wait for data to be ready and ensure that there are 8×8 data in both UV component and Y component FIFO.

[0082] Trigger condition: Due to the YUV420 sampling characteristics, the Y component data volume is four times that of the U / V component, and the UV component is written to the FIFO slower than the Y component. Only the amount of data in the U component FIFO needs to be checked. When the U component FIFO data volume is ≥8, the state jumps to the read enable generation state (GEN_RD_EN).

[0083] (2) Read enable generation status (GEN_RD_EN)

[0084] Function: Generate each component read enable signal in the order of Y1→Y1→Y2→Y2→U→V, realize data sequence control, strictly match the 16×16 matrix processing flow in JPEG compression, ensure complete reading of each 8×8 data block, and avoid data misplacement.

[0085] Trigger condition: Single reading needs to complete 6 8×8 blocks (Y1×2+Y2×2+U×1+V×1), a total of 384 pixels. If 64-bit bus + 8 cycles / block transmission is used, 6 blocks need 48 cycles, so cnt is counted from 0 to 47. When cnt==47 (48-cycle reading is completed), the trigger state jumps to WAIT_BACK to wait for the back-end FIFO to be emptied. The specific cnt range and read enable control relationship are as follows:

[0086]

[0087] (3) Wait for the back-end FIFO to be empty (WAIT_BACK)

[0088] Function: As a flow control mechanism, prevent the back-end FIFO from overflowing, avoid data accumulation due to slow back-end processing speed, and ensure smooth operation of the pipeline.

[0089] Trigger condition: Listen to the empty flag (empty_back) of the back-end FIFO. Only when the back-end has enough space, return to the initial state to prepare for the next round of reading.

[0090] Specifically, the shared processing module 104 includes a shared two-dimensional DCT transform module 1041, a dynamic quantization module 1042, a ZigZag pipeline scanning module 1043, a shared run-length encoding module 1044, and a four-table shared Huffman encoding module 1045.

[0091] Specifically, the shared two-dimensional DCT transform module 1041 is used to implement two-dimensional discrete cosine transform (2D-DCT) of an 8×8 image block, convert spatial domain pixels into frequency domain coefficients, and realize energy concentration, parallel computing and resource optimization through row-column separation algorithm, Loeffler algorithm and fixed-point processing. The specific implementation process steps are as follows:

[0092] (1) Row-column separation algorithm: decompose two-dimensional DCT into 8 times of one-dimensional row transform + 8 times of one-dimensional column transform, that is:

[0093]

[0094] Wherein, f(x, y) is the spatial domain 8×8 pixel value, Ci(x) and Cj(y) are cosine base functions.

[0095] A one-dimensional DCT unit is called for each row of the 8*8 image block to generate an intermediate frequency domain matrix; the row transformation result is interchanged in row and column dimensions through a double-port BRAM to be converted into a column data format; then a one-dimensional DCT unit is called for the transposed column data to output a complete 8*8 frequency domain coefficient matrix;

[0096] (2) Butterfly operation: Loeffler algorithm is adopted to complete 8-point DCT calculation through a 3-stage butterfly network. Only 4 multiplications and 8 additions are required in each stage, the matrix multiplication is decomposed into an iterative operation of "addition and subtraction + a small amount of multiplication" by using the symmetry of the cosine function, the calculation amount is reduced, the characteristics of FPGA parallel flow are matched, and the processing throughput is improved;

[0097] (3) Fixed-point implementation: in order to avoid high resource consumption of floating-point operation, the floating-point coefficient of the cosine base function is converted into a 16-bit fixed-point number. For example, the floating-point coefficient C(0)=0.3536 is approximately rounded to 0xB5 (decimal 181) by 0.3536*2^9=181.0432.

[0098] Specifically, the dynamic quantization module 1042 (shared table switching) is used to perform non-uniform quantization on the DCT coefficients, and dynamically switches the luminance / chroma quantization table according to the 48-cycle counter to retain the low-frequency information sensitive to the human eye. The specific implementation process steps are as follows:

[0099] (1) Quantization table storage and reading: each quantization table uses 8*8*8-bit wide data storage, including luminance component (Y) and chroma component (U / V) quantization tables. A column-first parallel processing architecture is adopted, and one column of data (8 elements) of the quantization table is read every clock cycle, and an element-by-element fixed-point division operation (equivalent to multiplication by the inverse of the quantization table) is performed with the corresponding column of the DCT coefficient matrix, and the quantization operation of the 8*8 matrix is completed in 8 cycles;

[0100] (2) Quantization table switching mechanism: the system uses a 0-47 cycle counter as a timing reference, synchronized with the DCT module processing rhythm. Every 8 counts correspond to processing an 8*8 block, and the luminance table (Y) or the chroma table (UV) is dynamically selected according to the counter value:

[0101] Counter=0-7: process the first 8*8 block of Y1 component, use the luminance table.

[0102] Counter=8-15: process the second 8*8 block of Y1 component, use the luminance table.

[0103] Counter=16-23: process the first 8*8 block of Y2 component, use the luminance table.

[0104] Counter=24-31: process the second 8*8 block of Y2 component, use the luminance table.

[0105] Counter = 32-39: Process the first 8x8 block of U component, using the chroma table.

[0106] Counter = 40-47: Process the second 8x8 block of V component, using the chroma table.

[0107] Specifically, the Zigzag pipeline scanning module 1043 is used to implement ZigZag rearrangement of the 8x8 quantization coefficient matrix, DPCM differential encoding and data pipeline processing, convert the two-dimensional matrix into a one-dimensional sequence, reduce the inter-block redundancy, and ensure continuous data output. The specific implementation process steps are as follows:

[0108] (1) Matrix cache architecture: an 8-stage row shift register group is adopted, 8 pixels are received and stored in the first row every cycle, the subsequent rows are updated by 1 cycle through the register chain delay, and an complete 8x8 matrix is formed after 8 cycles, ensuring that the data timing is aligned when ZigZag scanning;

[0109] (2) ZigZag path decomposition: the matrix is decomposed into 8 sub-sequences according to the ZigZag path, and each sub-sequence contains 8 data; Figure 4

[0110] (3) Pipeline buffer and output

[0111] Multi-stage cache: each sub-sequence is delayed through a register to ensure timing alignment;

[0112] Timing control: the sub-sequences are selected by a counter cycle, and the complete sequence is output in 8 cycles;

[0113] Enable delay: the input enable signal is delayed by 9 registers to ensure synchronization with the data;

[0114] Data output: the processed data is written into the FIFO in sequence;

[0115] (4) FIFO control

[0116] Read enable trigger: when the remaining data amount of the FIFO reaches a threshold, the read enable is started;

[0117] Rhythm control: the read enable is controlled by a counter, 1 pixel is read every cycle to ensure continuous data output;

[0118] (5) DPCM processing

[0119] DC value latching: when the block start position is detected, the current block DC value is latched into the corresponding component register;

[0120] Difference calculation: calculate the difference between the current DC and the previous block DC;

[0121] Output control: output the DC difference at the block start position, and output the AC component at the remaining positions;​

[0122] Component switching: track block type by a counter, process 4 Y blocks, 1 U block, 1 V block in turn;

[0123] Independent management of each component DC value.

[0124] Specifically, the shared run-length coding module 1044 is used to compress the one-dimensional sequence after ZigZag scanning, and continuous zero values are represented by "zero run length + non-zero value", thereby reducing the data amount and optimizing the AC component with high-frequency zero value concentration. The specific implementation process steps are as follows:

[0125] (1) Data input: receive the one-dimensional sequence (DC difference + AC component) after DPCM processing;

[0126] (2) Zero run length counting: when 0 is encountered, the counter is incremented by 1; when non-zero is encountered, the current count value and non-zero value are output, and the counter is cleared;

[0127] (3) Encoding output: generate (run length, non-zero value) combination; output (0, 0) at the end of the block as an end-of-block (EOB) symbol;

[0128] (4) Special processing: all-zero blocks are directly output as EOB; DC difference is output separately and does not participate in zero run length counting.

[0129] Specifically, the four-table shared Huffman coding module 1045 is used to perform variable-length coding on the Y, U, and V component data after run-length coding, and different lengths of coding are allocated according to the data occurrence probability. Y component DC / AC, UV component DC / AC use independent Huffman tables respectively, and the code length (size) and binary code (code) corresponding to each symbol are output to realize lossless compression. The specific implementation process steps are as follows:

[0130] (1) Four sets of Huffman table loading: read Y-DC, Y-AC, UV-DC, and UV-AC tables from ROM, and store the mapping relationship of symbols to (code length, encoding) in the tables;

[0131] (2) Table lookup coding: select the corresponding table according to the component (Y / UV) and type (DC / AC) of the input data; DC difference is looked up according to the amplitude value, and AC (run length, non-zero value) is looked up according to the combination key to obtain the corresponding code length and binary code;

[0132] (3) Output control: output one set of (size, code) per cycle, the code length indicates the number of coding bits, and the binary code is output in left-justified format;

[0133] (4) Special symbol processing: when the end-of-block (EOB) symbol is encountered, a fixed code length and encoding (such as size = 2, code = 00) are output.

[0134] Specifically, the merging coding module 105 is used for splicing the size and code output by the Huffman coding module into a continuous bit stream and generating an output aligned by bytes, so as to realize the formatting integration of the coded data. The specific implementation process steps are as follows:

[0135] (1) Input buffer architecture design: a 32-bit deep buffer register (supporting two splicing of maximum 16-bit coding) is adopted, and a 5-bit bit counter (recording the current buffer bit number) is matched. The buffer is set to 0 and the counter is set to 0 during initialization, so as to ensure the continuity of cross-byte coding;

[0136] (2) Bit stream dynamic splicing: the coding is spliced into the buffer according to the size: the new coding is combined with the buffer after left shifting the current buffer bit number, and the buffer and the bit counter are updated. The maximum 16-bit coding (compatible with the longest code of Huffman) is supported, and the coding order is ensured through the shifting operation;

[0137] (3) Byte alignment output control: when the number of bits in the buffer is greater than or equal to 8, the high 8 bits are taken as a byte output, the buffer is updated to the remaining bits, and the counter is reduced by 8. Multi-stage register delay is adopted to ensure that the output data is synchronized with the enable signal, so as to avoid timing conflicts;

[0138] (4) Cross-byte coding processing: for the case that the coding length is more than 8 bits, the coding is dynamically divided through a state machine and conditional judgment: the complete byte is output first, and the remaining bits are reserved for the next splicing (for example, if there are 3 bits in the buffer and the new coding is 7 bits, the high 8 bits are output after splicing, and the remaining 2 bits are reserved). Different combinations of code length and remaining bits are processed using a predefined case statement to ensure that the splicing logic covers all scenarios;

[0139] (5) Block end and data statistics: when the block end flag is detected, the remaining bits in the output buffer are filled to the byte boundary to generate a block end signal. The total code length data is accumulated and counted, which is used for subsequent compression ratio analysis or state monitoring.

[0140] On the other hand, as shown in Figure 7 the application also provides a JPEG image compression method based on the FPGA double-matrix shared pipeline, which is implemented by using the JPEG image compression system based on the FPGA double-matrix shared pipeline.

[0141] S100, convert YUV444 format data into YUV420 format to generate Y component data stream and 2:1 horizontal / vertical down-sampled UV component data stream;

[0142] S200, alternately store the Y component data stream to Y1 and Y2 buffer area by row, form a double 8 row matrix structure, and synchronously store the UV component data stream, realize Y1 / Y2 double matrix partitioning of Y component and 8 row aligned storage of UV component, provide a standardized 8x8 data block for a shared pipeline;

[0143] S300, read data blocks from Y1 and Y2 buffer area in the order of Y1→Y1→Y2→Y2→U→V, generate timing control signals of a shared processing pipeline, and output in the order of Y1→Y1→Y2→Y2→U→V, realize pipeline continuous processing;

[0144] S400, based on the timing control signals, time-multiplexed execute DCT transform, quantization, ZigZag scanning, run-length encoding and Huffman encoding processing of Y1, Y2, U, V data blocks;

[0145] S500, splice the encoding output into a continuous bit stream, and generate a compressed data stream conforming to the JPEG standard.

[0146] Specifically, the conversion of YUV444 format data into YUV420 format, generating Y component data stream and 2:1 horizontal / vertical down-sampled UV component data stream includes the following steps:

[0147] Data buffering: construct a 2-row deep UV component buffer, form a 2x2 pixel window matrix;

[0148] Mean value calculation: sum the 4 UV values in the window, and realize efficient average calculation by right shifting 2 bits (fixed-point division);

[0149] Data alignment output: generate YUV420 format data stream, Y resolution is 2x2 times of UV, match the double 8 row matrix partitioning requirement.

[0150] Specifically, alternately storing the Y component data stream to Y1 and Y2 buffer area by row, forming a double 8 row matrix structure includes the following steps:

[0151] Through row count control, alternately generate 2 8x8 Y1 and Y2 data blocks every 16 rows of Y component data received;

[0152] Store the UV component data stream by 8 row depth, form a standard input group of 6 8x8 data blocks with Y1 / Y2 data blocks.

[0153] Specifically, the time-multiplexed execution of DCT transform, quantization, ZigZag scanning, run-length encoding and Huffman encoding processing of Y1, Y2, U, V data blocks based on the timing control signals includes the following steps:

[0154] Based on 48 period counter value, using brightness quantization table when processing Y1, Y2 data block in 0-31 period, using chroma quantization table when processing U, V data block in 32-47 period;

[0155] Based on Y / UV component DC / AC four sets of independent code table, different component data is executed Huffman coding.

[0156] Specifically, the time-sharing multiplexing execution Y1, Y2, U, V data block DCT transformation based on the timing control signal includes the following steps:

[0157] Row and column separation: the two-dimensional DCT is decomposed into 8 times one-dimensional row transformation + 8 times one-dimensional column transformation, that is:

[0158] Wherein, f(x,y) is the spatial domain 8*8 pixel value, C i (x), C j (y) is the cosine basis function, the one-dimensional DCT unit is called for each row of 8*8 image block, the intermediate frequency domain matrix is generated, the row and column dimensions of the row transformation result are interchanged through the double-port BRAM, and the column data format is converted, then the one-dimensional DCT unit is called for the transposed column data, and the complete 8*8 frequency domain coefficient matrix is output;

[0159] Butterfly operation: Loeffler algorithm is adopted, 8-point DCT calculation is completed through a 3-stage butterfly network, only 4 times of multiplication and 8 times of addition are required in each stage, the matrix multiplication is decomposed into iteration operation of addition and subtraction + a small amount of multiplication by utilizing the symmetry of cosine function, the calculation amount is reduced, the parallel flow characteristics of FPGA are matched, and the processing throughput is improved;

[0160] Fixed-point implementation: in order to avoid high resource consumption of floating-point operation, the floating-point coefficient of the cosine basis function is converted into 16-bit fixed-point number.

[0161] Specifically, the basic principle and process of the technical scheme of the application are as follows:

[0162] Aiming at the YUV420 data characteristics, a vertical direction matrix segmentation strategy is proposed:

[0163] (1) 16 rows of Y component data are divided into the first 8 rows of Y1 matrix and the last 8 rows of Y2 matrix, and 8 rows of U / V components are extracted to form independent matrices;

[0164] (2) the Y1 / Y2 write enable is switched by a 1-bit row counter in a cycle, and 2 8*8 Y matrices, 1 8*8 U matrix and 1 8*8 V matrix are generated after receiving 16 rows of Y data;

[0165] (3) beneficial effect: directly matching 8*8 DCT operation, eliminating the overhead of traditional row and column conversion, reducing the data cache demand by 30%.

[0166] 2. Time-aligned shared pipeline

[0167] A dedicated timing control module is designed to realize the ordered scheduling of multi-component data:

[0168] (1) A 48-cycle state machine is adopted to sequentially output 6 8x8 data blocks (Y1x2, Y2x2, Ux1, Vx1) in the order of Y1→Y1→Y2→Y2→U→V; and DCT transformation is performed on each block.

[0169] (2) Data reading is triggered based on the FIFO depth threshold of UV components to ensure the synchronization of YUV component data;

[0170] (3) Shared processing unit: only one set of DCT transformation, quantization, ZigZag scanning, RLE encoding and Huffman encoding modules are required, and different component data blocks are processed by time-sharing multiplexing.

[0171] 3. Hardware resource optimization mechanism

[0172] Resource efficient multiplexing is realized through architectural innovation:

[0173] (1) Computing circuit: compared with the traditional three-channel architecture, more than 50% of logic units and DSP resources are reduced;

[0174] (2) Storage system: without simultaneously buffering three-component intermediate results, the on-chip SRAM demand is reduced by 30%;

[0175] (3) Power consumption control: the time-sharing multiplexing mechanism reduces the average power consumption by 40%, and the data bus bandwidth demand is reduced by 30%.

[0176] 4. Complete encoding process optimization

[0177] (1) YUV444 to YUV420: 2x2 block mean filtering down-sampling, retaining Y component and compressing UV component;

[0178] (2) Two-dimensional DCT transformation: row and column separation algorithm combined with Loeffler butterfly network, 16-bit fixed-point implementation;

[0179] (3) Quantization and Huffman encoding: dynamic switching of luminance / chrominance quantization table, four independent code tables for entropy encoding.

[0180] Specifically, the present application forms a complete and efficient JPEG encoding system by optimizing data organization, processing flow and timing control, significantly reducing the computational complexity and data handling overhead, and is particularly suitable for resource-constrained embedded image compression application scenarios.

[0181] Specifically, compared with the prior art, the present application has the following advantages:

[0182] The present application realizes resource high-efficiency multiplexing by using the serial processing order of Y1→Y1→Y2→Y2→U→V:

[0183] (1) Hardware area saving: only one set of DCT / quantization / ZigZag / Huffman coding processing unit (3 sets of parallel units are required in the traditional scheme); more than 50% of the calculation circuit area is reduced; the control logic is simplified, and the timing synchronization complexity is reduced.

[0184] (2) Power consumption reduction: time-sharing multiplexing of the calculation unit, the average power consumption is reduced by about 40%; the data bus bandwidth requirement is reduced, and the storage access power consumption is reduced.

[0185] (3) Storage demand reduction: no need to simultaneously buffer the intermediate results of Y, U and V three components; the on-chip SRAM demand is reduced by about 30%.

[0186] (4) Implementation complexity optimization: data path simplification, FPGA / ASIC wiring difficulty reduction; development cycle is shortened by about 25%.

[0187] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structural transformation made under the inventive concept of the present application, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A JPEG image compression system based on FPGA dual-matrix shared pipeline, characterized in that: include: The YUV420 preprocessing module is used to convert YUV444 format data into YUV420 format data, completely retain the Y component, perform 2:1 horizontal / vertical downsampling on the UV component, and generate a Y component data stream and a 2:1 horizontal / vertical downsampling UV component data stream; A dual 8-row matrix segmentation storage module is used to store the Y component data stream alternately in the Y1 and Y2 buffer areas by row to form a dual 8-row matrix structure, and synchronously store the UV component data stream to obtain Y1, Y2, U, and V data blocks, thereby realizing Y1 / Y2 dual matrix segmentation of the Y component and 8-row aligned storage of the UV component; A shared pipeline timing scheduling module is used to read Y1, Y2, U, and V data blocks from the Y1 and Y2 buffers in the order of Y1 → Y1 → Y2 → Y2 → U → V, generate timing control signals for the shared processing pipeline, implement pipeline-type continuous processing, and convert parallel multi-component data into a serial data stream; A shared processing module is used to perform DCT transformation, quantization, ZigZag scanning, run-length coding and Huffman coding processing of Y1, Y2, U and V data blocks in a time-division multiplexing manner according to the timing control signal; as well as The merge encoding module is used to splice the encoded output into a continuous bit stream and generate output by byte alignment, so as to realize the formatted integration of the encoded data and generate a compressed data stream that conforms to the JPEG standard.

2. The JPEG image compression system based on FPGA dual-matrix shared pipeline according to claim 1, characterized in that: The dual 8-row matrix segmentation storage module uses row count control and a segmentation counter to alternately generate two 8×8 Y1 and Y2 data blocks for every 16 rows of Y component data received. The UV component data stream is cached at an 8-row depth and forms a standard input group of six 8×8 data blocks with the Y1 and Y2 data blocks, providing standardized 8×8 data blocks for the shared pipeline.

3. The JPEG image compression system based on FPGA dual-matrix shared pipeline according to claim 1, characterized in that: The shared pipeline timing scheduling module adopts a three-stage state machine, which includes: IDLE state: when the UV component FIFO data volume is detected to be ≥8, it jumps to the read enable generation state; GEN_RD_EN state: Generates the read enable signal in the order of Y1→Y1→Y2→Y2→U→V through the 48-cycle counter; WAIT_BACK state: monitors the backend FIFO empty flag to ensure that there is no data backlog in the shared pipeline.

4. The JPEG image compression system based on FPGA dual-matrix shared pipeline according to claim 1, characterized in that: The shared processing module includes: Shared 2D DCT transform module, used to decompose the 2D DCT into row transform and column transform using the row-column separation algorithm, implement 8-point DCT calculation through a 3-level butterfly network using the Loeffler algorithm, and convert the cosine basis function floating-point coefficients into 16-bit fixed-point numbers; Dynamic quantization module, which is used to perform non-uniform quantization on DCT coefficients based on timing control signals, dynamically switch the luminance / chrominance quantization table, and retain low-frequency information that is sensitive to the human eye; Zigzag pipeline scanning module, used to rearrange the quantized 8×8 quantization coefficient matrix into a one-dimensional sequence according to the ZigZag path, and perform DPCM differential coding on the DC coefficient; A shared run-length encoding module is used to compress the one-dimensional sequence after ZigZag scanning, perform zero run-length encoding, and reduce the amount of data; and The four tables share the Huffman encoding module, which is used to perform variable-length encoding on the four independent code tables of DC / AC for the Y, U, and V component data after run-length encoding, and assign codes of different lengths according to the probability of data occurrence to achieve lossless compression.

5. The JPEG image compression system based on FPGA dual-matrix shared pipeline according to claim 4, characterized in that: The dynamic quantization module dynamically switches the luminance / chrominance quantization table according to a 48-cycle counter, wherein: Counter in cycles 0-31: Process Y1 and Y2 data blocks and use the brightness quantization table; Counter in cycles 32-47: Processing U, V data blocks and using the chromaticity quantization table.

6. A JPEG image compression method based on an FPGA dual-matrix shared pipeline, performed using the JPEG image compression system based on an FPGA dual-matrix shared pipeline according to any one of claims 1 to 5, characterized in that: The JPEG image compression method comprises the following steps: Convert YUV444 format data to YUV420 format, generate Y component data stream and UV component data stream after 2:1 horizontal / vertical downsampling; The Y component data stream is alternately stored in the Y1 and Y2 buffer areas by row to form a dual 8-row matrix structure, and the UV component data stream is stored synchronously to achieve Y1 / Y2 dual matrix segmentation of the Y component and 8-row aligned storage of the UV component, providing a standardized 8×8 data block for the shared pipeline; Read data blocks from the Y1 and Y2 buffers in the order of Y1 → Y1 → Y2 → Y2 → U → V, generate timing control signals for the shared processing pipeline, and output them in the order of Y1 → Y1 → Y2 → Y2 → U → V to achieve pipeline continuous processing; Based on the timing control signal, DCT transformation, quantization, ZigZag scanning, run-length coding and Huffman coding processing of Y1, Y2, U and V data blocks are performed in a time-division multiplexing manner; The encoded output is spliced ​​into a continuous bit stream to generate a compressed data stream that conforms to the JPEG standard.

7. The JPEG image compression method based on FPGA dual-matrix shared pipeline according to claim 6, characterized in that: The conversion of YUV444 format data into YUV420 format to generate a Y component data stream and a UV component data stream that is downsampled horizontally and vertically by 2:1 includes the following steps: Data buffer: Build a UV component buffer with a depth of 2 rows, forming a 2×2 pixel window matrix; Average calculation: sum the 4 UV values ​​in the window and perform efficient average calculation by right shifting 2 bits; Data alignment output: Generates a YUV420 format data stream with a Y resolution 2×2 times that of UV, matching the dual 8-row matrix segmentation requirements.

8. The JPEG image compression method based on FPGA dual-matrix shared pipeline according to claim 6, characterized in that: Storing the Y component data stream alternately in rows into the Y1 and Y2 buffer areas to form a dual 8-row matrix structure includes the following steps: Through line count control, every time 16 lines of Y component data are received, two 8×8 Y1 and Y2 data blocks are alternately generated; The UV component data stream is buffered as 8 lines of depth and forms a standard input group of 6 8×8 data blocks with the Y1 / Y2 data blocks.

9. The JPEG image compression method based on FPGA dual-matrix shared pipeline according to claim 6, characterized in that: The method of performing DCT transformation, quantization, ZigZag scanning, run-length coding and Huffman coding of the Y1, Y2, U and V data blocks in a time-division multiplexing manner based on the timing control signal includes the following steps: Based on the 48-cycle counter value, the luminance quantization table is used when processing the Y1 and Y2 data blocks in cycles 0-31, and the chrominance quantization table is used when processing the U and V data blocks in cycles 32-47; Based on four independent code tables for Y / UV components DC / AC, Huffman encoding is performed on different component data.

10. The JPEG image compression method based on FPGA dual-matrix shared pipeline according to claim 6, characterized in that: The DCT transformation of the Y1, Y2, U, and V data blocks is performed in a time-division multiplexing manner based on the timing control signal, comprising the following steps: Row and column separation: Decompose the two-dimensional DCT into 8 one-dimensional row transforms + 8 one-dimensional column transforms, that is: Among them, f(x,y) is the 8×8 pixel value in the spatial domain, C i (x), C j (y) is a cosine basis function. A one-dimensional DCT unit is called for each row of the 8×8 image block to generate an intermediate frequency domain matrix. The row transform result is converted to column data format by swapping the row and column dimensions through a dual-port BRAM. The one-dimensional DCT unit is then called for the transposed column data to output a complete 8×8 frequency domain coefficient matrix. Butterfly operation: Using the Loeffler algorithm, a three-level butterfly network is used to complete 8-point DCT calculations. Each level requires only four multiplications and eight additions. Utilizing the symmetry of the cosine function, matrix multiplication is decomposed into iterative operations of addition, subtraction, and a small number of multiplications. Fixed-point implementation: Convert the cosine basis function floating-point coefficients to 16-bit fixed-point numbers.

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