High-speed single-slope ADC, control method thereof and CMOS image sensor

Abstract

The invention discloses a high-speed single-slope ADC, a control method thereof and a CMOS image sensor, the high-speed single-slope ADC comprises a ramp generator, a sampling hold circuit, a pre-comparator, a dynamic comparator, a control logic register and an add-subtract counter, the ramp generator is used for generating a reference voltage VRAMP and performing slope calibration; the sampling and holding circuit is connected with the ramp generator, and the sampling and holding circuit is used for stably sampling the pixel voltage VPIXEL of the CMOS image sensor; and the dynamic comparator is connected with the sampling and holding circuit and is used for comparing the reference voltage VRAMP with the pixel voltage VPIXEL after sampling and holding in real time in a formal conversion stage. According to the invention, the efficiency bottleneck of the traditional single-slope ADC in continuous multi-row signal quantization is solved, the conversion speed is obviously improved, the structure is kept simple, and the high-speed column-level analog-to-digital conversion requirement of the CMOS image sensor is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a high-speed single-slope ADC and a control method thereof, and a CMOS image sensor. Background Art

[0002] The traditional single-slope ADC corresponds to a single-slope analog-to-digital converter (Single-Slope Analog-to-Digital Converter), which includes a sample-and-hold circuit, a dynamic comparator, a counter, a register, and a ramp generator. Figure 1 As shown in FIG, the working principle is: the ramp generator generates a linearly rising V_RAMP signal, the counter starts counting from zero, and when V_RAMP exceeds the sampling voltage V_PIXEL, the comparator flips and latches the count value.

[0003] Specifically, the traditional single-slope ADC structure requires 2^N clock cycles to complete N-bit precision conversion, and the counter must be reset after each conversion, resulting in low efficiency when continuously converting multiple lines of signals. Current existing technical solutions use technologies such as segmented quantization and voltage feedback to increase speed, but none of them solves the problem of counter reset when quantizing multiple lines of signals. Especially in CMOS image sensor applications, the voltage change between adjacent pixel rows is usually very small (ΔV < 1LSB). Traditional methods still require a full counting cycle, resulting in a waste of time. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-speed single-slope ADC and a control method thereof and a CMOS image sensor, which are used to solve the efficiency bottleneck of traditional single-slope ADC and the insufficient quantization speed of continuous multi-line signals.

[0005] A first aspect of the present invention provides a high-speed single-slope ADC, comprising:

[0006] Ramp generator, sample and hold circuit, pre-comparator, dynamic comparator, control logic register and up / down counter, among which,

[0007] The ramp generator is used to generate a reference voltage V_RAMP and perform slope calibration;

[0008] The sample-and-hold circuit is connected to the ramp generator, and the sample-and-hold circuit is used to stably sample the pixel voltage V_PIXEL of the CMOS image sensor;

[0009] The dynamic comparator is connected to the sample-and-hold circuit and is used to compare the reference voltage V_RAMP with the sample-and-hold pixel voltage V_PIXEL in real time during the formal conversion phase, wherein when V_RAMP exceeds V_PIXEL, the output is flipped, triggering the add-subtract counter to stop counting;

[0010] The pre-comparator is connected to the dynamic comparator and is used to quickly determine the change direction ΔV between the current row pixel voltage signal and the previous row pixel voltage signal within one clock cycle before the formal conversion phase;

[0011] The control logic register is connected to the dynamic comparator and is used to latch the final value of the counter and output the ADC conversion result;

[0012] The add-subtract counter is connected to the control logic register and is used to dynamically adjust the counting direction of the counter based on the change direction ΔV, wherein, if ΔV=0, counting continues from the last count value; if ΔV>0, counting starts from the last count value minus the offset; if ΔV<0, counting starts from the last count value plus the offset.

[0013] In this solution, the slope calibration range of the ramp generator is (2.8V-1.2V) / 2^Nper clock, and the voltage change in each clock cycle corresponds to a least significant bit, where the voltage range is 1.2V-2.8V, N is the precision, and clock is the clock period.

[0014] In this solution, the sampling and holding circuit adopts a charge sharing structure, including a sampling switch, a sampling capacitor, a holding capacitor and an operational amplifier, wherein the sampling capacitor and the holding capacitor have the same value.

[0015] In this solution, the dynamic comparator includes a three-stage preamplifier, wherein the total gain of the three stages is 60dB.

[0016] In this solution, the pre-comparator adopts a Strong_ARM latch structure, wherein MOS transistors m1 to m4 form a cross-coupling pair, and MOS transistors m5 to m6 form a clock-controlled differential pair.

[0017] A second aspect of the present invention provides a high-speed single-slope ADC control method, comprising the following steps:

[0018] Sampling the input voltage signal to obtain a stable output voltage signal;

[0019] The reference voltage of the ramp generator is obtained and compared with the stable output voltage signal. When the reference voltage exceeds the stable output voltage signal, the counter is controlled to stop counting.

[0020] Performing a pre-comparison based on the stable output voltage signals of adjacent rows to obtain a comparison result;

[0021] The initial value of the counter is dynamically adjusted based on the comparison result, and the ADC conversion result is output after counting is stopped.

[0022] In this solution, the total time for converting multiple lines of signals is calculated as follows:

[0023]

[0024] Where T is the total conversion time, V mk is the input voltage signal of the kth conversion, n is the total number of conversions, V m1 is the input voltage signal for the first conversion, f is the clock cycle frequency, N is the ADC resolution, and the voltage range is (1.2, 2.8).

[0025] In this solution, the piecewise function for dynamically adjusting the initial value of the counter within a single conversion time is as follows:

[0026]

[0027] Where ΔV is the voltage comparison result, f is the clock cycle frequency, LSB is the least significant bit, N is the ADC resolution, and the voltage range is (1.2, 2.8).

[0028] A third aspect of the present invention provides a computer-readable storage medium, which includes a high-speed single-slope ADC control method program for a machine. When the high-speed single-slope ADC control method program is executed by a processor, the steps of a high-speed single-slope ADC control method as described in any one of the above items are implemented.

[0029] A fourth aspect of the present invention provides a CMOS image sensor, wherein an ADC manufactured by using any one of the high-speed single-slope ADCs described above is used as a column-level analog-to-digital converter of the CMOS image sensor.

[0030] The present invention discloses a high-speed single-slope ADC, a control method thereof, and a CMOS image sensor, which resolve the efficiency bottleneck of traditional single-slope ADCs when quantizing continuous multi-row signals, significantly improve the conversion speed, and maintain a simple structure, making it suitable for the high-speed column-level analog-to-digital conversion requirements of CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shows a schematic diagram of the structure of a traditional single-slope ADC;

[0032] Figure 2 A schematic structural diagram of a high-speed single-slope ADC according to the present invention is shown;

[0033] Figure 3 The present invention shows a schematic diagram of a sampling and holding circuit structure of a high-speed single-slope ADC;

[0034] Figure 4 A schematic diagram of the structure of a three-stage preamplifier in a dynamic comparator of a high-speed single-slope ADC according to the present invention is shown;

[0035] Figure 5 A schematic structural diagram of a Strong_ARM latch in a high-speed single-slope pre-comparator of the present invention is shown;

[0036] Figure 6 A schematic diagram of the steps of a high-speed single-slope ADC control method of the present invention is shown. DETAILED DESCRIPTION

[0037] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0039] Figure 2 The figure shows a schematic structural diagram of a high-speed single-slope ADC of the present application.

[0040] like Figure 2 As shown, the present application discloses a high-speed single-slope ADC, comprising:

[0041] Ramp generator, sample and hold circuit, pre-comparator, dynamic comparator, control logic register and up / down counter, among which,

[0042] The ramp generator is used to generate a reference voltage V_RAMP and perform slope calibration;

[0043] The sample-and-hold circuit is connected to the ramp generator, and the sample-and-hold circuit is used to stably sample the pixel voltage V_PIXEL of the CMOS image sensor;

[0044] The dynamic comparator is connected to the sample-and-hold circuit and is used to compare the reference voltage V_RAMP with the sample-and-hold pixel voltage V_PIXEL in real time during the formal conversion phase, wherein when V_RAMP exceeds V_PIXEL, the output is flipped, triggering the add-subtract counter to stop counting;

[0045] The pre-comparator is connected to the dynamic comparator and is used to quickly determine the change direction ΔV between the current row pixel voltage signal and the previous row pixel voltage signal within one clock cycle before the formal conversion phase;

[0046] The control logic register is connected to the dynamic comparator and is used to latch the final value of the counter and output the ADC conversion result;

[0047] The add-subtract counter is connected to the control logic register and is used to dynamically adjust the counting direction of the counter based on the change direction ΔV, wherein, if ΔV=0, counting continues from the last count value; if ΔV>0, counting starts from the last count value minus the offset; if ΔV<0, counting starts from the last count value plus the offset.

[0048] It should be noted that, in this embodiment, compared with the traditional single-slope ADC, the present invention adds a pre-comparator module on the basis of the traditional structure, and adopts an add-subtract counter to replace the traditional up-counter, which can control the initial state of the counter through the pre-comparison result, thereby avoiding starting from zero each time and saving time. Specifically, it includes a ramp generator, a sample-and-hold circuit, a pre-comparator, a dynamic comparator, a control logic register and an add-and-subtract counter. Accordingly, the ramp generator is used to generate a reference voltage V_RAMP and perform slope calibration. The sample-and-hold circuit is connected to the ramp generator, and the sample-and-hold circuit is used to stably sample the pixel voltage V_PIXEL of the CMOS image sensor.

[0049] Furthermore, the dynamic comparator is connected to the sample-and-hold circuit and is used to compare the reference voltage V_RAMP with the pixel voltage V_PIXEL after sampling and holding in real time during the formal conversion phase, wherein when V_RAMP exceeds V_PIXEL, the output is flipped, triggering the add-subtract counter to stop counting, and the pre-comparator is connected to the dynamic comparator and is used to quickly determine the change direction ΔV of the current row pixel voltage signal and the previous row pixel voltage signal within one clock cycle before the formal conversion phase, and the control logic register is connected to the dynamic comparator and is used to latch the final value of the counter and output the ADC conversion result.

[0050] Furthermore, the add-subtract counter is connected to a control logic register for dynamically adjusting the counting direction of the counter based on the change direction ΔV, wherein, if ΔV=0, counting continues from the last count value; if ΔV>0, counting starts from the last count value minus the offset; if ΔV<0, counting starts from the last count value plus the offset.

[0051] According to an embodiment of the present invention, the sample-and-hold circuit adopts a charge-sharing structure, including a sampling switch, a sampling capacitor, a holding capacitor, and an operational amplifier, wherein the sampling capacitor and the holding capacitor have the same value.

[0052] It should be noted that, in this embodiment, Figure 3 As shown, it is a schematic diagram of the sampling and holding circuit structure, which specifically includes a sampling switch, a sampling capacitor, a holding capacitor and an operational amplifier, wherein the sampling capacitor and the holding capacitor have the same value (typical value 2pF) to ensure signal stability.

[0053] According to an embodiment of the present invention, the dynamic comparator includes a three-stage preamplifier, wherein the total gain of the three stages is 60 dB.

[0054] It should be noted that, in this embodiment, Figure 4 As shown, it is a structural diagram of the three-stage preamplifier in the dynamic comparator, which specifically adopts a low-latency design of the three-stage preamplifier with a total gain of 60dB, which can ensure accuracy and speed.

[0055] According to an embodiment of the present invention, the pre-comparator adopts a Strong_ARM latch structure, wherein MOS transistors m1 to m4 form a cross-coupling pair, and MOS transistors m5 to m6 form a clock-controlled differential pair.

[0056] It should be noted that in this embodiment, the pre-comparator adopts a Strong_ARM latch structure, wherein MOS transistors m1 to m4 form a cross-coupled pair, and MOS transistors m5 and m6 form a clock-controlled differential pair. This allows the initial value of the counter to be dynamically adjusted (starting counting from near the previous result) based on the pre-comparison result (corresponding to the change direction ΔV), avoiding starting from zero each time and saving time.

[0057] Figure 6 A flow chart of a high-speed single-slope ADC control method of the present application is shown.

[0058] like Figure 6 As shown, the present application discloses a high-speed single-slope ADC control method, comprising the following steps:

[0059] S602, sampling the input voltage signal to obtain a stable output voltage signal;

[0060] S604, obtaining a reference voltage of the ramp generator and comparing it with the stable output voltage signal, and when the reference voltage exceeds the stable output voltage signal, controlling the counter to stop counting;

[0061] S606 , performing a preliminary comparison based on the stable output voltage signals of adjacent rows to obtain a comparison result;

[0062] S608 , dynamically adjusting the initial value of the counter based on the comparison result, and outputting the ADC conversion result after stopping counting.

[0063] It should be noted that in this embodiment, the input voltage signal is stably sampled, and then the obtained reference voltage is compared with the stable output voltage signal. In particular, when the reference voltage exceeds the stable output voltage signal, the counter is controlled to stop counting. Since the high-speed single-slope ADC of the present invention is provided with a pre-comparator, a pre-comparison can be performed based on the stable output voltage signals of adjacent rows to obtain a comparison result, thereby dynamically adjusting the initial value of the counter based on the comparison result, and outputting the ADC conversion result after stopping counting. Among them, a feedback loop is formed by the pre-comparator and the add-subtract counter, which dynamically shortens the conversion time. In particular, the efficiency of continuous readout can be significantly improved in CMOS image sensors (for example, the speed is increased by 37% when ΔV≈0.1LSB).

[0064] According to an embodiment of the present invention, the total time for converting multiple lines of signals is calculated as follows:

[0065]

[0066] Where T is the total conversion time, V mk is the input voltage signal of the kth conversion, n is the total number of conversions, V m1 is the input voltage signal for the first conversion, f is the clock cycle frequency, N is the ADC resolution, and the voltage range is (1.2, 2.8).

[0067] It should be noted that, in this embodiment, the total conversion time is specifically described, wherein the total conversion time Where T is the total conversion time, V mk is the input voltage signal of the kth conversion, n is the total number of conversions, V m1 is the input voltage signal for the first conversion, f is the clock cycle frequency, N is the ADC resolution, and the voltage range is (1.2, 2.8).

[0068] According to an embodiment of the present invention, a piecewise function for dynamically adjusting the initial value of a counter within a single conversion time is as follows:

[0069]

[0070] Where ΔV is the voltage comparison result, f is the clock cycle frequency, LSB is the least significant bit, N is the ADC resolution, and the voltage range is (1.2, 2.8).

[0071] It should be noted that, in this embodiment, how the pre-comparator determines the count value and the corresponding segment time when performing pre-comparison is specifically described. When |ΔV|=1.6V, the segment time is When 1LSB<|ΔV|<(2.8-1.2)V, the segment time is When |ΔV|<1LSB, the segment time is Accordingly, Here, "1.6" is the difference between the voltage ranges (1.2, 2.8).

[0072] A third aspect of the present invention provides a computer-readable storage medium, which includes a high-speed single-slope ADC control method program. When the high-speed single-slope ADC control method program is executed by a processor, the steps of a high-speed single-slope ADC control method as described in any one of the above items are implemented.

[0073] A fourth aspect of the present invention provides a CMOS image sensor, wherein an ADC manufactured by using any one of the high-speed single-slope ADCs described above is used as a column-level analog-to-digital converter of the CMOS image sensor.

[0074] The present invention discloses a high-speed single-slope ADC, a control method thereof, and a CMOS image sensor, which resolve the efficiency bottleneck of traditional single-slope ADCs when quantizing continuous multi-row signals, significantly improve the conversion speed, and maintain a simple structure, making it suitable for the high-speed column-level analog-to-digital conversion requirements of CMOS image sensors.

[0075] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0076] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0077] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0078] Those skilled in the art will appreciate that all or part of the steps of the above-mentioned method embodiments may be implemented by hardware associated with program instructions, and the aforementioned program may be stored in a computer-readable storage medium. When the program is executed, the program executes the steps of the above-mentioned method embodiments. The aforementioned storage medium includes various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0079] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

Claims

1. A high-speed single-slope ADC, characterized in that: include: Ramp generator, sample and hold circuit, pre-comparator, dynamic comparator, control logic register and up / down counter, among which, The ramp generator is used to generate a reference voltage V_RAMP and perform slope calibration; The sample-and-hold circuit is connected to the ramp generator, and the sample-and-hold circuit is used to stably sample the pixel voltage V_PIXEL of the CMOS image sensor; The dynamic comparator is connected to the sample-and-hold circuit and is used to compare the reference voltage V_RAMP with the sample-and-hold pixel voltage V_PIXEL in real time during the formal conversion phase, wherein when V_RAMP exceeds V_PIXEL, the output is flipped, triggering the add-subtract counter to stop counting; The pre-comparator is connected to the dynamic comparator and is used to quickly determine the change direction ΔV between the current row pixel voltage signal and the previous row pixel voltage signal within one clock cycle before the formal conversion phase; The control logic register is connected to the dynamic comparator and is used to latch the final value of the counter and output the ADC conversion result; The add-subtract counter is connected to the control logic register and is used to dynamically adjust the counting direction of the counter based on the change direction ΔV, wherein, if ΔV=0, counting continues from the last count value; if ΔV>0, counting starts from the last count value minus the offset; if ΔV<0, counting starts from the last count value plus the offset.

2. A high-speed single-slope ADC according to claim 1, characterized in that: The slope calibration range of the ramp generator is (2.8V-1.2V) / 2^N per clock, and the voltage change in each clock cycle corresponds to a least significant bit, where the voltage range is 1.2V-2.8V, N is the precision, and clock is the clock period.

3. A high-speed single-slope ADC according to claim 2, characterized in that: The sampling and holding circuit adopts a charge sharing structure, including a sampling switch, a sampling capacitor, a holding capacitor and an operational amplifier, wherein the sampling capacitor and the holding capacitor have the same value.

4. A high-speed single-slope ADC according to claim 3, characterized in that: The dynamic comparator includes a three-stage preamplifier, wherein the total gain of the three stages is 60 dB.

5. A high-speed single-slope ADC according to claim 4, characterized in that: The pre-comparator adopts a Strong_ARM latch structure, wherein MOS transistors m1 to m4 form a cross-coupling pair, and MOS transistors m5 to m6 form a clock-controlled differential pair.

6. A high-speed single-slope ADC control method, characterized in that: A high-speed single-slope ADC according to any one of claims 1 to 5, comprising the following steps: Sampling the input voltage signal to obtain a stable output voltage signal; obtaining a reference voltage of the ramp generator and comparing it with the stable output voltage signal, and controlling the counter to stop counting when the reference voltage exceeds the stable output voltage signal, wherein a comparison result is obtained by performing a pre-comparison based on the stable output voltage signals of adjacent rows; The initial value of the counter is dynamically adjusted based on the comparison result, and the ADC conversion result is output after counting is stopped.

7. A high-speed single-slope ADC control method according to claim 6, characterized in that: The total time for multi-line signal conversion is calculated as follows: Where T is the total conversion time, V mk is the input voltage signal of the kth conversion, n is the total number of conversions, V m1 is the input voltage signal for the first conversion, f is the clock cycle frequency, N is the ADC resolution, and the voltage range is (1.2, 2.8).

8. A high-speed single-slope ADC control method according to claim 7, characterized in that: The piecewise function for dynamically adjusting the initial value of the counter within a single conversion time is as follows: Where ΔV is the voltage comparison result, f is the clock cycle frequency, LSB is the least significant bit, N is the ADC resolution, and the voltage range is (1.2, 2.8).

9. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a high-speed single-slope ADC control method program. When the high-speed single-slope ADC control method program is executed by a processor, the steps of a high-speed single-slope ADC control method according to any one of claims 6 to 8 are implemented.

10. A CMOS image sensor, characterized in that: An ADC manufactured by using the high-speed single-slope ADC according to any one of claims 1 to 5 is used as a column-level analog-to-digital converter of a CMOS image sensor.

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