Semiconductor device and method of manufacturing the same

Abstract

Disclosed herein are a semiconductor device and a method of manufacturing the same. Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes an array structure having a plurality of memory cells. A memory cell of the plurality of memory cells includes a transistor and a capacitor stacked together. The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure. A first terminal of the transistor is in contact with a first electrode of the capacitor in a first direction. The gate structure includes a conductive film having an angled or curved end that is closer to the first terminal of the transistor than the second terminal of the transistor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a process for manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. A 3D memory device typically includes a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. The memory cells can include vertical structures. Summary of the Invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a semiconductor device comprising an array structure including a plurality of memory cells. A memory cell in the plurality of memory cells comprises a transistor and a capacitor stacked together along a first direction. The transistor comprises a transistor body, a first terminal, a second terminal, and a gate structure. The first terminal and the second terminal are located at opposite ends of the transistor body along the first direction. The gate structure extends along the first direction and is adjacent to the transistor body along a second direction perpendicular to the first direction. The first terminal of the transistor contacts a first electrode of the capacitor along the first direction. The gate structure comprises a conductive film having an angled or curved end that is closer to the first terminal of the transistor than to the second terminal of the transistor.

[0005] In some embodiments, the transistor body includes a first body and a second body contacting each other along the second direction, the second body having a higher electron mobility than the first body, and the second body being closer to the gate structure than the first body.

[0006] In some embodiments, the first body includes amorphous silicon, and the second body includes at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO).

[0007] In some embodiments, the transistor body includes at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO).

[0008] In some embodiments, the array structure includes an isolation region located between transistors of two adjacent memory cells in the plurality of memory cells, wherein the isolation region has a first end proximate to a first terminal of the transistor and a second end proximate to a second terminal of the transistor, and the first end has a smaller size than the second end.

[0009] In some embodiments, the capacitor includes a dielectric structure extending along a first direction, wherein the first electrode is located on at least one surface of the dielectric structure. The dielectric structure has a first end and a second end opposite to each other along the first direction. The first end is closer to the first terminal of the transistor than the second end, and the first end has a larger size than the second end.

[0010] In some embodiments, the capacitor further includes a second electrode and a capacitor body positioned between the first electrode and the second electrode. The first electrode surrounds the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body. The array structure includes a support structure extending along the second direction and distributed along the first direction between the first electrode and the second electrode or between the first electrodes of two adjacent capacitors.

[0011] In some embodiments, the array structure further includes a plurality of bit lines, wherein one bit line among the plurality of bit lines contacts the second terminal of the transistor, and adjacent bit lines are isolated by corresponding isolation regions.

[0012] In some embodiments, the array structure is integrated into a first die, and the semiconductor device further includes a second die. The first die includes at least one conductive interconnect, and one bit line among the plurality of bit lines is coupled to a control circuit in the second die via the at least one conductive interconnect. A surface of a capping layer located above the plurality of bit lines in the first die contacts a surface of the control circuit in the second die, and the plurality of bit lines are closer to the second die than the capacitor.

[0013] Another aspect of the present disclosure is characterized by a semiconductor device comprising an array structure including a plurality of memory cells. A memory cell in the plurality of memory cells comprises a transistor and a capacitor stacked together along a first direction. The transistor comprises a transistor body, a first terminal, a second terminal, and a gate structure. The first terminal and the second terminal are located at opposite ends of the transistor body along the first direction. The gate structure extends along the first direction and is adjacent to the transistor body along a second direction perpendicular to the first direction. The transistor body comprises at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO). The first terminal of the transistor contacts a first electrode of the capacitor along the first direction. The capacitor comprises a dielectric structure extending along the first direction, the first electrode being located on at least one surface of the dielectric structure, and the dielectric structure having a first end and a second end opposite to each other along the first direction. The first end of the dielectric structure is closer to the first terminal of the transistor than the second end of the dielectric structure, and the first end of the dielectric structure has a larger dimension along the second direction than the second end of the dielectric structure.

[0014] In some embodiments, the array structure includes an isolation region located between transistors of two adjacent memory cells in the plurality of memory cells, wherein the isolation region has a first end proximate to a first terminal of the transistor and a second end proximate to a second terminal of the transistor, and the first end has a smaller size than the second end.

[0015] In some embodiments, the gate structure includes a conductive film having an angled or curved end that is closer to a first terminal of the transistor than to a second terminal of the transistor.

[0016] In some embodiments, the capacitor further includes a second electrode and a capacitor body positioned between the first electrode and the second electrode. The first electrode surrounds the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body. The array structure includes a support structure extending along the second direction and distributed along the first direction between the first electrode and the second electrode or between the first electrodes of two adjacent capacitors.

[0017] In some embodiments, the array structure further includes a plurality of bit lines, and one of the plurality of bit lines contacts the second terminal of the transistor, and adjacent bit lines are isolated by corresponding isolation regions. The array structure is integrated into a first die, and the semiconductor device further includes a second die. The first die includes at least one conductive interconnect, and one of the plurality of bit lines is coupled to a control circuit in the second die via the at least one conductive interconnect. A surface of a cover layer located above the plurality of bit lines in the first die contacts a surface of the control circuit in the second die. The plurality of bit lines are closer to the second die than the capacitor.

[0018] Another aspect of the present disclosure features a method comprising: forming a first portion of a capacitor of a semiconductor structure on a semiconductor substrate; forming a transistor of the semiconductor structure on the first portion of the capacitor; removing the semiconductor substrate to at least partially expose the first portion of the capacitor; and forming a second portion of the capacitor by at least partially replacing at least one of a sacrificial material or a dielectric structure located between first electrodes of the capacitor. The first portion of the capacitor includes a first electrode and a dielectric structure. The first electrodes of the capacitor are separated by a sacrificial material. The second portion of the capacitor includes a second electrode and a capacitor body located between the first and second electrodes.

[0019] In some embodiments, forming a second portion of the capacitor by at least partially replacing at least one of a sacrificial material or a dielectric structure located between first electrodes of the capacitor includes at least partially removing the sacrificial material located between the first electrodes of the capacitor, depositing a dielectric material on the first electrodes to form a capacitor body of the capacitor, and depositing at least one conductive film on the dielectric material to form the second electrode of the capacitor.

[0020] In some embodiments, forming a transistor of a semiconductor structure on a first portion of a capacitor includes: forming a transistor body of the transistor, the transistor body coupled to a first electrode of the capacitor; forming a vertical gate of the transistor adjacent to the transistor body of the transistor; and forming an isolation region between two adjacent transistors. The isolation region has a first end proximate to the first electrode of the capacitor and a second end opposite the first end along a first direction, and the first end has a smaller dimension than the second end.

[0021] In some embodiments, forming a transistor of a semiconductor structure on a first portion of a capacitor includes: forming a conductive layer on the first portion of the capacitor; annealing the conductive layer so that a conductive material of the conductive layer reacts with a first electrode of the capacitor to form a composite conductive material; forming a body on the conductive layer; and forming a groove extending through the layer of composite conductive material and the body to form a first terminal of the transistor and a transistor body of the transistor, respectively.

[0022] In some embodiments, the method further includes forming a bit line on the second terminal of the transistor, forming at least a conductive interconnect layer on the bit line, and bonding the semiconductor structure to the control structure by bonding a surface of at least the conductive interconnect layer to a surface of a control circuit of the control structure.

[0023] In some embodiments, forming a first portion of a capacitor of a semiconductor structure on a semiconductor substrate includes: forming an array of holes through one or more dielectric layers in the semiconductor substrate, depositing a first conductive film on a surface of the array of holes, and filling the array of holes with a dielectric material by depositing a dielectric material on the first conductive film to form a dielectric structure of the capacitor. The dielectric structure has a first end and a second end opposite to each other. The first end is closer to the transistor than the second end, and the first end has a larger size than the second end. The dielectric layers are separated by an isolation material.

[0024] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, a capacitor in a 3D memory device may have an irregular (e.g., trapezoidal) shape in a cross-sectional view, wherein one end of the capacitor closer to the first terminal (e.g., source terminal) of the vertical transistor may be wider than the other end of the capacitor. Similarly, the vertical transistor body may also have an irregular (e.g., trapezoidal) shape in a cross-sectional view, wherein one end in contact with the first terminal (e.g., source terminal) of the vertical transistor may be wider than the other end in contact with the second terminal (e.g., drain terminal) of the vertical transistor. In this way, when the capacitor and transistor are stacked vertically, the configuration (e.g., "back-to-back trapezoidal") may improve the alignment accuracy between the vertical transistor array and the capacitor array, which is particularly advantageous in advanced technologies characterized by narrower spacing. In addition, a bit line (BL) may be formed by depositing a conductive layer on top of the second terminal (e.g., drain terminal) of the vertical transistor and patterning the conductive layer. Unlike buried BL, this process does not require consuming a portion of the vertical transistor body. Therefore, it is no longer necessary to etch the vertical transistor trench deeper than the vertical transistor body. The feasibility of using a stop layer for both BL trench etching and vertical transistor etching can also reduce process difficulty. In addition, since processes requiring high temperatures (e.g., implantation during vertical transistor formation) are performed before depositing the high-k material for the capacitor, the thermal budget is significantly improved. This range of options alleviates concerns that high temperatures may damage the high-k material.

[0025] This technology can be applied to various types of semiconductor devices, including volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase change memory (PCM) (e.g., PCRAM), spin transfer torque (STT)-magnetoresistive random access memory (MRAM), and others. This technology can also be applied to charge trapping-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (quad-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and others.

[0026] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one of ordinary skill in the art to make and use the disclosure.

[0028] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device having a pillar-type capacitor is shown.

[0029] Figure 2A-2R Cross-sectional views of an exemplary 3D semiconductor structure at various stages of a fabrication process are shown.

[0030] Figure 3 A cross-sectional view of an exemplary 3D semiconductor device having a cup-type capacitor is shown.

[0031] Figure 4A An example of a 3D vertical transistor with a single-sided gate is shown.

[0032] Figure 4B An example of a 3D vertical transistor with double-sided gates is shown.

[0033] Figure 5 is a flow chart of an exemplary process for forming a 3D semiconductor device.

[0034] Figure 6 A block diagram of an example system having one or more semiconductor devices is shown.

[0035] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0036] Current vertical transistor technology in dynamic random access memory (DRAM) involves a process of forming transistors on the front side of a substrate and then forming capacitors stacked vertically above the memory cell array. The substrate is then bonded to a carrier wafer on its front side and is then flipped over to form drain terminals and / or bit lines (BLs) on the back side of the substrate after polishing off the substrate. Due to process limitations, buried BLs are typically used, which have the disadvantages of high resistance and enhanced parasitic coupling between BLs. Buried BLs may further affect the formation of gaps between bit lines for isolation purposes. This is in part because the buried bit lines are located below the surface of the substrate. In contrast, other bit line formation techniques may involve creating bit lines on the surface. This difference in depth may affect the ease with which gaps can be formed. Furthermore, when bonding a first wafer (e.g., containing a DRAM array) to a second wafer (e.g., containing complementary metal oxide semiconductor (CMOS) control circuitry), interconnect via alignment is problematic because both bonding processes (e.g., bonding to the carrier wafer and bonding between the DRAM wafer and the CMOS wafer) generate unnecessary mechanical and thermal stresses on the wafers. This results in a narrow contact landing process window. This problem becomes even more severe for more advanced technologies with further reduced pitch. Furthermore, in some technologies, vertical transistor formation typically involves implantation at high temperatures. However, high-k materials in capacitors may not perform well at extremely high temperatures. Due to this limitation, implantation of the transistor terminals is performed before depositing the high-k material. This increases process complexity in the manufacturing process, particularly when it comes to drain implantation, as the drain may be at the bottom of the transistor body, making it challenging to effectively deliver dopants from the top of the transistor body to the drain. An alternative approach is to form the drain terminal together with the BL after the substrate is thinned or polished away. However, at this stage, the capacitor has already been formed using high-k materials, and the thermal budget for drain formation may be limited.

[0037] Embodiments of the present disclosure provide techniques for forming a 3D memory device that can address the aforementioned issues. In some embodiments, the 3D memory device is fabricated by forming a first portion of a capacitor of the 3D memory device on a semiconductor substrate, the first portion of the capacitor including a first electrode separated by a dielectric sacrificial material; forming a transistor of the 3D memory device stacked above the first portion of the capacitor; removing the semiconductor substrate to at least partially expose the first portion of the capacitor; and finally, forming a second portion of the capacitor by replacing at least a portion of the sacrificial material between the first electrodes of the capacitor, the second portion of the capacitor including a second electrode and a dielectric capacitor body located between the first and second electrodes.

[0038] In some embodiments, the vertical transistor channel includes at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO) to enhance channel performance with high electron mobility. Furthermore, the capacitor can have an irregular (e.g., trapezoidal) shape in a cross-sectional view, wherein one end of the capacitor closer to the first terminal (e.g., source terminal) of the vertical transistor can be wider than the other end of the capacitor. Similarly, the vertical transistor body can also have an irregular (e.g., trapezoidal) shape in a cross-sectional view, wherein one end in contact with the first terminal (e.g., source terminal) of the vertical transistor can be wider than the other end in contact with the second terminal (e.g., drain terminal) of the vertical transistor. Thus, when the capacitor and transistor are stacked vertically together, this configuration (e.g., a "back-to-back trapezoidal") can improve the alignment accuracy between the vertical transistor array and the capacitor array. Furthermore, at least one conductive film in the gate structure of the vertical transistor can have an angled or curved end, such as an L-shape. The first portion of the L-shaped gate extends in a lateral direction (e.g., BL direction), and the second portion of the L-shaped gate extends in a vertical direction or extends at an oblique angle relative to the vertical direction. In addition, the first portion of the L-shape extending in the BL direction may be closer to the first terminal (e.g., source terminal) of the vertical transistor than to the second terminal (e.g., drain terminal).

[0039] In some embodiments, a BL is formed by depositing a conductive layer directly on top of the second terminal (e.g., drain terminal) of the vertical transistor and patterning the conductive layer. Unlike a buried BL, this process does not require consuming a portion of the semiconductor body of the vertical transistor. As such, there is no need to etch the vertical transistor trench deeper than the vertical transistor body. In addition, the feasibility of using a stop layer for BL trench etching and vertical transistor etching also reduces process difficulty. Because processes requiring high temperatures (e.g., implantation during vertical transistor processing) are performed before depositing the high-k material for the capacitor, the thermal budget is also significantly improved.

[0040] In some embodiments, a carrier wafer is not used during the process of forming a 3D memory device. This can reduce or eliminate issues associated with the bonding process, such as alignment issues, surface contamination, thermal stress, mechanical stress, or wafer warpage. With reduced thermal or mechanical stress, interconnect via alignment is significantly improved when a first wafer (e.g., a DRAM array wafer) is bonded to a second wafer (e.g., a CMOS control circuit wafer). This expanded contact landing process window is particularly advantageous in cutting-edge technologies where pitch is further reduced.

[0041] Figure 11 shows a side view of a cross section of an exemplary 3D semiconductor device 100. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that Figure 1 This is for illustrative purposes only and does not necessarily reflect actual device structures (e.g., interconnections) in practice. In some embodiments, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be joined at a bonding interface 106 therebetween.

[0042] like Figure 1 As shown in , the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single crystal silicon (c-Si)), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include a peripheral circuit 112 located on the substrate 110. In some embodiments, the peripheral circuit 112 includes a plurality of transistors (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors) may also be formed on or in the substrate 110. In some examples, the peripheral circuit 112 is formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or a CMOS die.

[0043] In some embodiments, first semiconductor structure 102 further includes an interconnect layer 116 located above peripheral circuitry 112 to transmit electrical signals to and from peripheral circuitry 112. Interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and via contacts. Interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which interconnect lines and via contacts may be formed. In other words, interconnect layer 116 may include interconnect lines and via contacts located in multiple ILD layers. In some embodiments, peripheral circuitry 112 is coupled to one another via interconnects located in interconnect layer 116. The interconnects in interconnect layer 116 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed using dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0044] like Figure 1As shown in , the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may also include a bonding layer 118 located at the back side of the bonding interface 106 and located above the interconnect layer 116 and the peripheral circuit 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 118 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 119 and the surrounding dielectric in the bonding layer 118 may be used for hybrid bonding. Similarly, as Figure 1 As shown in , the second semiconductor structure 104 may also include a bonding layer 120 located at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric may be used for hybrid bonding. The bonding contacts 121 may be in contact with the bonding contacts 119 at the bonding interface 106. In some embodiments, as Figure 1 As shown in FIG, a bonding layer 120 includes a dielectric layer opposite a memory cell (eg, a DRAM cell) 124, with a bit line 123 positioned between the dielectric layer and the memory cell 124. The dielectric layer may include a bonding interface 106 having a bonding contact 121.

[0045] The second semiconductor structure 104 can be bonded in a face-to-face manner on top of the first semiconductor structure 102 at a bonding interface 106. In some embodiments, the bonding interface 106 is provided between the bonding layers 120 and 118 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer of a particular thickness that includes the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0046] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122, which includes bit lines 123 located above the bonding layer 120 to transmit electrical signals. The interconnect layer 122 may include multiple interconnects, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 122 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed using dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0047] In some embodiments, peripheral circuitry 112 includes a wordline driver / row decoder coupled to wordline contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bitline driver / column decoder coupled to bitlines 123 and bitline contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bitlines 123 are metal bitlines, as opposed to semiconductor bitlines (e.g., doped silicon bitlines). For example, bitlines 123 can include W, Co, Cu, Al, or any other suitable metal having a higher electrical conductivity than doped silicon. In some embodiments, the bitline contacts are ohmic contacts, as opposed to Schottky contacts.

[0048] In some embodiments, the bit line 123 is made of a conductive material (e.g., W, Co, Cu, Al, or any combination thereof). In some embodiments, the bit line 123 is made of a composite conductive material, including but not limited to WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0049] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 124 above the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 can be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 can be coupled to the strings of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and can be referred to as an array die.

[0050] In some embodiments, a semiconductor device may include multiple array dies (e.g., the second semiconductor structure 104) and CMOS dies (e.g., the first semiconductor structure 102). The multiple array dies and CMOS dies may be stacked and bonded together. The CMOS die may be coupled to each of the multiple array dies, and each of the multiple array dies may be driven separately, thereby operating in a manner similar to the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer bonded face to face. The array die may be arranged on a first wafer together with other array dies, and the CMOS die may be arranged on a second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together so that the array die on the first wafer may be bonded to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least an array die and a CMOS die bonded together. In an example, the chip is cut from the bonded wafers. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0051] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be of any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a transistor body 130 extending vertically (in the z-direction) and a gate structure 136 in contact with one side of the transistor body 130. In a single-gate vertical transistor, the transistor body 130 may have a rectangular parallelepiped shape or a cylindrical shape, and the gate structure 136 may be shaped like a rectangle in a plan view (e.g., as shown in FIG. 1 ). Figure 1 ) abuts a single side of the transistor body 130. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located in a bit line direction (e.g., in the X direction) between the gate electrode 134 and the transistor body 130. In some embodiments, the gate dielectric 132 abuts a side of the transistor body 130, and the gate electrode 134 abuts the gate dielectric 132.

[0052] In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer on a TiN layer. Figure 1As shown in FIG, the gate electrode 134 includes two layers: a first gate electrode layer 134 (a) (e.g., TiN) and a second gate electrode layer 134 (b) (e.g., W). The first gate electrode layer 134 (a) may have an angled or curved end, for example, an L-shape in the XZ plane. The L-shaped gate electrode 134 (a) includes two portions: a first portion extending along the Z axis or along an oblique angle relative to the Z axis, and a second portion extending along the X axis. In addition, the second portion of the gate electrode 134 (a) extending along the x-axis is closer to the first terminal 138 than the second terminal 139.

[0053] It should be understood that the construction of the gate structure 136 is not limited to Figure 1 , and may include any appropriate structures and configurations, such as a single-side gate structure, a double-side gate structure, a three-side gate structure, or a gate-all-around (GAA) structure.

[0054] like Figure 1 As shown in FIG, in some embodiments, the transistor body 130 has two ends ( Figure 1 134 ), and at least one end (e.g., the lower end) extends beyond the gate dielectric 132 in the vertical direction (z-direction) into the ILD layer (not shown). In some embodiments, one end (e.g., the upper end) of the transistor body 130 is flush with a corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the transistor body 130 extend beyond the gate electrode 134 in the vertical direction (z-direction) into the ILD layer (not shown). That is, the transistor body 130 can have a vertical dimension (e.g., depth) that is larger than the vertical dimension of the gate electrode 134 (e.g., in the z-direction), and neither the upper end nor the lower end of the transistor body 130 is flush with a corresponding end of the gate electrode 134. Thus, short circuits between the bit line 123 and the word line / gate electrode 134, or between the word line / gate electrode 134 and the capacitor 128, can be avoided. The vertical transistor 126 may further include a first terminal 138 and a second terminal 139, i.e., a source and a drain, respectively, disposed at both ends (upper end and lower end) of the transistor body 130 in the vertical direction (z direction). In some embodiments, the first terminal 138 (e.g., at Figure 1 ) is coupled to capacitor 128, and a second terminal 139 (e.g., at Figure 1 is coupled to the bit line 123. Figure 1 As shown in , vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite the first terminal in the negative z-direction.

[0055] In some embodiments, transistor body 130 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, indium gallium zinc oxide (IGZO) or indium gallium silicon oxide (IGSO), any other semiconductor material, or any combination thereof. Terminals 138 and 139 can be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level, or include silicon germanium (SiGe).

[0056] In some embodiments, transistor body 130 includes a first body 171 and a second body 172 that are laterally in contact with each other. In some embodiments, second body 172 has a higher electron mobility than first body 171 and is laterally disposed between first body 171 and gate dielectric 132 along the X direction (e.g., the BL direction).

[0057] In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the second terminal 139 of the vertical transistor 126 and the bitline 123 as a bitline contact, or between the first terminal 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142, thereby reducing contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric. High-k dielectrics include, but are not limited to, Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material such as, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, gate structure 136 can be a "gate oxide / gate polysilicon" gate, where gate dielectric 132 comprises silicon oxide and gate electrode 134 comprises doped polysilicon. In another example, gate structure 136 can be HKMG, where gate dielectric 132 comprises a high-k dielectric and gate electrode 134 comprises metal. High-k materials can include any material having a dielectric constant greater than or equal to a threshold value (e.g., 3.9).

[0058] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in a word line direction (e.g., Y direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each of the multiple word lines extending in the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two perpendicular lateral directions, and the transistor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word line 134 is in contact with a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, which includes but is not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, as Figure 1 As shown in FIG, word line 134 includes a plurality of conductive layers, such as a W layer on a TiN layer.

[0059] In some embodiments, as Figure 1 As shown in FIG, vertical transistor 126 extends vertically through and contacts wordline 134, and a second terminal 139 of vertical transistor 126 at its lower end contacts bitline 123 (or, if provided, a bitline contact). Accordingly, due to the vertical arrangement of vertical transistor 126, wordline 134 and bitline 123 can be arranged in different planes in the vertical direction, which simplifies the routing of wordline 134 and bitline 123. In some embodiments, bitline 123 is vertically arranged between bonding layer 120 and wordline 134, and wordline 134 is vertically arranged between bitline 123 and capacitor 128. Wordline 134 can be coupled to peripheral circuitry 112 in first semiconductor structure 102 via a wordline contact (not shown) in interconnect layer 122, bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnects in interconnect layer 116. Similarly, the bit lines 123 in the interconnect layer 122 may be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnects in the interconnect layer 116 .

[0060] In some embodiments, vertical transistors 126 may be arranged in a mirror-symmetrical manner to increase the density of DRAM cells 124 in the bit line direction (X direction). Figure 1As shown in FIG, two adjacent vertical transistors 126 in the bitline direction are mirror-imaged relative to the trench isolation region 160. That is, the second semiconductor structure 104 may include a plurality of trench isolation regions 160, each of which extends in the wordline direction (Y direction) parallel to the wordline 134 and is disposed between the transistor bodies 130 of two adjacent rows of vertical transistors 126. In some embodiments, the rows of vertical transistors 126 separated by the trench isolation region 160 are mirror-imaged relative to the trench isolation region 160. The trench isolation region 160 may be formed using a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be understood that the trench isolation region 160 may include gaps, each of which is disposed laterally between adjacent transistor bodies 130. The gaps may be formed due to the relatively small spacing of the vertical transistors 126 in the bitline direction (e.g., the X direction). On the other hand, the relatively large dielectric constant of air in the voids (e.g., approximately 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, depending on the spacing of the word lines / gate electrodes 134 in the bit line direction, voids are also formed laterally between the word lines / gate electrodes 134 (not shown). In some embodiments, rather than having voids in the trench isolation regions 160, conductive material (e.g., a metal such as W) is filled in the trench isolation regions 160 and surrounded by a dielectric material. As described in further detail below, the conductive material in the trench isolation regions 160 can be coupled out from the back side of the second semiconductor structure 104.

[0061] like Figure 1 As shown in FIG, in some embodiments, capacitor 128 includes a first electrode 144 located above first terminal 138 of vertical transistor 126 (e.g., an upper end of transistor body 130) and coupled to first terminal 138 of vertical transistor 126 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, as opposed to a Schottky contact. For example, capacitor contact 142 can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0062] In some embodiments, the capacitor 142 includes a dielectric structure 149 that can have a pillar shape. The first electrode 144 covers at least one surface of the dielectric structure 149. In some embodiments, the bottom portion of the first electrode 144 is coupled to the first terminal 138 of the corresponding vertical transistor 126 via an ohmic contact (e.g., a capacitor contact 142 made of a metal silicide material). A capacitor body 145 including a dielectric material (e.g., a high-k material) can be deposited on at least a portion of the surface of the first electrode 144, followed by deposition of the second electrode 143. In other words, the capacitor body 145 is located between the first electrode 144 and the second electrode 143, wherein the capacitor body 145 at least partially covers the first electrode 144 and the second electrode 143 at least partially covers the capacitor body 145. The second electrode 143 can include one or more metal layers stacked together. In some examples, for example, as Figure 1 As shown in FIG, the second electrode 143 is formed by depositing a first metal layer 143a (eg, TiN) on the surface of the capacitor body 145 and depositing a second metal layer 143b (eg, SiGe) on the first metal layer 143a. Figure 1 As shown in , one or more support structures 150 may extend along the X-axis and be distributed between the first electrode 144 and the second electrode 143 and / or between the first electrodes 144 of two adjacent capacitors 128 .

[0063] In some embodiments, each first electrode 144 is coupled to the first terminal 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146 coupled to a ground (e.g., a common ground). In some embodiments, capacitor 128 can have a first end in the negative z-direction and a second end (not shown) opposite the first end in the positive z-direction. In some embodiments, the first end of capacitor 128 is coupled to the first terminal 138 of vertical transistor 126 via an ohmic contact (e.g., a capacitor contact 142 made of a metal silicide material). Figure 1 As shown in , the second semiconductor structure 104 may further include a capacitor contact 147 (eg, a conductor) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. Figure 1 , a capacitor contact 147 (e.g., a conductor) extends from the dielectric layer of the bonding layer 120 in the z-direction to couple to a second end of the capacitor 128 via the common plate 146. In some embodiments, the ILD layer in which the capacitor 128 is formed has the same dielectric material as the ILD layer into which the transistor body 130 extends, such as silicon oxide.

[0064] It should be understood that the structure and construction of capacitor 128 is not limited to Figure 1 , and can include any suitable structure and construction, such as a pillar capacitor, a cup capacitor, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, capacitor body 145 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 can be a ferroelectric capacitor used in a FRAM cell, and capacitor body 145 can be replaced by a ferroelectric layer having a ferroelectric material (such as PZT or SBT). In some embodiments, the electrode includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0065] like Figure 1 As shown in FIG, vertical transistor 126 extends vertically through and contacts word line 134, a second terminal 139 of vertical transistor 126 at its lower end contacts bit line 123, and a first terminal 138 of vertical transistor 126 at its upper end is coupled to capacitor 128. That is, due to the vertical arrangement of vertical transistor 126, bit line 123 and capacitor 128 can be arranged in different planes in the vertical direction and vertically coupled to opposite ends of vertical transistor 126 of DRAM cell 124. In some embodiments, bit line 123 and capacitor 128 are arranged on opposite sides of vertical transistor 126 in the vertical direction, which simplifies the routing of bit line 123 and reduces the coupling capacitance between bit line 123 and capacitor 128, compared to DRAM cells in which the bit line and capacitor are arranged on the same side of a planar transistor.

[0066] like Figure 1 As shown in FIG, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be disposed closer to the peripheral circuit 112 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. Therefore, the interconnect layer 122 including the bit line 123 can be disposed close to the bonding interface 106 to reduce interconnect routing distance and complexity.

[0067] like Figure 1As shown in , the second semiconductor structure 104 may further include a pad output interconnect layer 156 located above the capacitor 128 and the DRAM cell 124. The pad output interconnect layer 156 may include interconnects located in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 156 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. The capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 156. In some embodiments, for example, for pad output purposes, the interconnects in the pad output interconnect layer 156 may transmit electrical signals between the 3D semiconductor device 100 and an external circuit.

[0068] In some embodiments, second semiconductor structure 104 further includes one or more contacts 152 extending through a portion of pad output interconnect layer 156 to couple pad output interconnect layer 156 to DRAM cell 124 and interconnect layer 122. Thus, peripheral circuit 112 can be coupled to DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuit 112 and DRAM cell 124 can be coupled to external circuitry via contacts 152 and pad output interconnect layer 156. Contact pads 154 and contacts 152 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, contact pads 154 can include Al, and contacts 152 can include W.

[0069] Although not shown, it should be understood that the pad output of the 3D memory device is not limited to Figure 1 1 and 124 and may be from the first semiconductor structure 102 having the peripheral circuitry 112. Although not shown, it is also understood that the gaps between the word lines 134 and / or between the transistor bodies 130 may be partially or completely filled with a dielectric. Although not shown, it is also understood that more than one array of DRAM cells 124 may be stacked on top of each other to vertically scale up the number of DRAM cells 124.

[0070] although Figure 1 1 , but it is understood that the capacitor 128 may have an irregular shape (e.g., a trapezoidal shape) in a cross-sectional view, wherein one end of the capacitor closer to the first terminal 138 (e.g., the source terminal) of the vertical transistor 126 is wider than the other end of the capacitor, for example, as described below in Figure 2RSimilarly, the vertical transistor body 130 may also have an irregular shape (e.g., a trapezoidal shape) in a cross-sectional view, wherein one end in contact with the first terminal 138 (e.g., the source terminal) of the vertical transistor 126 is wider than the other end in contact with the second terminal 139 (e.g., the drain terminal) of the vertical transistor 126, for example, as described below in Figure 2R As shown in . As such, when capacitors 128 and transistors 126 are stacked vertically together, this configuration (eg, "back-to-back trapezoidal") can enhance the alignment accuracy between the vertical transistor array and the capacitor array, which enables the formation of memory devices with narrower pitches.

[0071] Figure 2A-2R The structure of an exemplary semiconductor device at various stages of the manufacturing process is shown in top view and / or cross-sectional view. The semiconductor device can be Figure 1 The semiconductor device 100 is the same or similar to, or Figure 1 A portion of the 3D semiconductor device 100 in Figure 1 For illustration purposes, Figure 2A-2L Each of the figures includes a cross-sectional view of the corresponding structure in figure (a) and figure (b). Figure (a) shows a top view of the corresponding structure in the XY plane, while figure (b) shows a cross-sectional view of the corresponding structure in the XY plane. Figure 2A-Figure 2I Each of the figures shows a cross-sectional view in the YZ plane, or a Figure 2J-2L Each of the figures shows a cross-sectional view of the XZ plane. Figure 2M-2Q There is only one diagram showing a cross-sectional view of the XZ plane. Figure 2R A cross-sectional view along the YZ plane is shown. Y may represent the direction along which a word line (WL) extends, such as the WL direction, X may represent the direction along which a bit line (BL) extends, such as the BL direction, and Z is the vertical direction along which capacitor 128 and memory cell 124 are stacked together.

[0072] Figure 2A-2G An exemplary process for forming a first portion of a capacitor cell 214 on a substrate 201 is shown. The capacitor cell 214 may be Figure 1 The capacitors 128 in FIG. 1 are the same or similar.

[0073] Figure 2A The diagram (a) shows a top view of the XY plane, and Figure 2A The illustration (b) is a cross-sectional view in the YZ plane (e.g., in the AA plane through the hole or groove array). The same layers are also arranged in Figure 2B-2C middle.

[0074] like Figure 2AAs shown in , a first support structure 150(a) is deposited on top of a substrate 201. Subsequently, a first layer of patterned photoresist 202(a) is formed on top of the first support structure 150(a) along the Z-axis. A photolithography process is used to pattern the photoresist layer 150(a). The photoresist pattern can be an array of holes extending along the z-axis to expose at least a portion of the top surface of the underlying first support structure 150(a). In some embodiments, the first support structure 150(a) includes a dielectric material including, but not limited to, SiN, SiCN, or any combination thereof. The first support structure 150(a) can be deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof.

[0075] like Figure 2B As shown in FIG. 1 (b), a first support structure 150 (a) is partially etched on top of the substrate 201, and the first patterned photoresist 202 (a) is removed after etching. The first patterned photoresist 202 (a) is used to protect certain areas of the support structure 150 so that the etchant can be etched through the unprotected areas until the top surface of the substrate 201 is exposed. The patterned support structure 150 can be used to support a subsequently formed capacitor array. In some embodiments, one or more dry etching and / or wet etching processes are performed on the substrate 201, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, or any combination thereof.

[0076] Subsequently, a first sacrificial layer 206(a) is deposited on top of the first support structure 150(a) and fills the trenches and / or holes thereof. In some embodiments, the first sacrificial layer 206(a) comprises a dielectric material including, but not limited to, silicon dioxide (SiO2), a low-k dielectric, silicon nitride, silicon oxynitride, or any combination thereof. The first sacrificial layer 206(a) can be deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof.

[0077] After depositing the first sacrificial layer 206(a), a second layer of support structure 150(b) is deposited on top of the first sacrificial layer 206(a). In some embodiments, the second support structure 150(b) may comprise the same material as the first support structure 150(a). A second patterned photoresist 202(b) is then formed to protect certain areas of the second support structure 150(b) from a subsequent etching process (not shown here). In some embodiments, as shown in FIG. Figure 2A and Figure 2B As shown in FIG. 2 (a), the pattern of the second photoresist 202 ( b ) has the same layout as the first patterned photoresist 202 ( a ).

[0078] like Figure 2C As shown in Figure (b), repeat Figure 2A and Figure 2B Some or all of the process steps in the process of FIG. 1 produce a second patterned support structure 150(b), a top patterned support structure 150(c), and a final sacrificial layer 206(b). In some embodiments, the top patterned support structure 150(c) can have a different array pattern than the first and / or second support structures 150(a) and (b) (not shown). In some embodiments, the top patterned support structure 150(c) can comprise the same material as the first and / or second support structures 150(a) and (b). In some examples, the third support structure 150(c) comprises silicon boron nitride (SiBN).

[0079] Then, if Figure 2C As shown in FIG. 2( b ), an array of capacitor trenches 208 is formed by etching along the Z-axis through all layers of the support structure 150 and the sacrificial layer 206 until the top surface of the substrate 201 is exposed. In some embodiments, a double patterning technique is employed to produce smaller features and spacing of the array of capacitor trenches 208. In some embodiments, one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, or any combination thereof, are performed to form the capacitor trenches 208.

[0080] like Figure 2C As shown in FIG. 1( b ), multiple layers of patterned support structures 150 are stacked together in the Z direction and separated by sacrificial layers 206. For example, the first support structure 150 ( a ) is separated from the second support structure 150 ( b ) by the first sacrificial layer 206 ( a ), and the second support structure 150 ( b ) is separated from the top support structure 150 ( c ) by the last sacrificial layer 206 ( b ). Figure 2CA total of three layers of support structures 150 and two sacrificial layers 206 are shown, but it should be understood that support structures 150 can have one or more layers, and sacrificial layers 206 can also have one or more layers. In the following description, top support structure 150(c) refers to the top layer of one or more support structure layers along the positive Z direction, and is not limited to the third support structure. In other words, if there is a total of one support structure, top support structure 150(c) refers to that support structure; if there are a total of five support structures, top support structure 150(c) refers to the fifth support structure stacked above the first four support structures along the positive Z direction.

[0081] In addition, although Figure 2C Illustration (b) shows that all three support structures, such as 150(a), 150(b) and 150(c), have the same array pattern, but it should also be understood that different layers of the patterned support structure 150 can have different patterns, structural thicknesses, sizes and / or materials and be formed using the same or different process technologies.

[0082] Figure 2D The diagram (b) shows a cross-sectional view of the YZ plane, and Figure 2D Illustration (a) of FIG. 1 is a cross-sectional view in the XY plane (eg, in the CC plane through the top support structure 150 ( c ) and a row of dielectric structures 149 ).

[0083] refer to Figure 2D , first, the first capacitor electrode 144 is deposited, covering at least a portion of the inner surface of the capacitor trench 208 and at least a portion of the top surface of the support structure 150. The thickness of the first capacitor electrode 144 is less than the radius of the capacitor trench 208. In other words, the first electrode 144 material does not completely fill the capacitor trench 208, and thus, after depositing the first capacitor electrode 144, some space remains within the capacitor trench 208. In some embodiments, the electrode material of the first capacitor electrode 144 includes, but is not limited to, TiN, TaN, Al, W, Cu, Co, Cu, doped polysilicon, silicide, or any combination thereof. In some embodiments, the first capacitor electrode 144 is deposited by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), sputtering, electroplating, electroless plating, or any combination thereof.

[0084] Subsequently, a dielectric material is deposited into the capacitor trench 208, which completely or substantially fills the remaining space of the capacitor trench 208, thereby forming a dielectric structure 149 for support purposes. Figure 2DAs shown in FIG. 2 (a), the capacitor trench 208 has a dielectric structure 149 in the center of the trench laterally surrounded by the first electrode 144. In some embodiments, the dielectric structure 149 includes a dielectric material including, but not limited to, polysilicon, carbon, or any combination thereof. The dielectric structure 149 can be deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, MOCVD, sputtering, or any combination thereof. In some embodiments, as Figure 2D As shown in diagram (b) of , during the deposition of the dielectric structure 149 , a dielectric layer 202 is formed on top of the support structure 150 .

[0085] Figure 2E The diagram (a) shows a top view of the XY plane, and Figure 2E The illustration (b) is a cross-sectional view in the YZ plane (eg, in the DD plane through a row of dielectric structures 149). The same layers are also arranged in Figure 2F-2G middle.

[0086] like Figure 2D Diagram (b) and Figure 2E As shown in FIG. 2 (b), the dielectric layer 202 is etched away, and the top portion of the dielectric structure 149 is also recessed by etching. Therefore, the top surface of the recessed dielectric structure 149 after etching is lower than the top surface 151 of the first electrode 144 along the Z axis. In some embodiments, the top surface of the recessed dielectric structure 149 is flush with the top surface of the last sacrificial layer 206 (b). Although Figure 2E 1 , but it is understood that the top surface 155 of the recessed dielectric structure 149 can be higher or lower than the top surface 153 of the sacrificial layer along the Z-axis. In some embodiments, etching and recessing can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, or any combination thereof.

[0087] refer to Figure 2E and Figure 2F , depositing a layer of conductive material, such as a conductive film, to fill the recessed space of the dielectric structure 149 and form a uniform conductive layer 212 on top of the top support structure 150 (c). The conductive layer 212 may include the same conductive material as the first electrode 144. Subsequently, as Figure 2GAs shown in FIG. 2 (b), a polishing process is performed to remove the conductive layer 212 so that the top surface of the top support structure 150 (c) is exposed. As a result, each dielectric structure 149 is surrounded by the first electrode 144, thereby forming a first portion of the capacitor unit 214. In addition, each first portion of the capacitor unit 214 is isolated by the sacrificial layer 206 and the support structure 150. In other words, at this stage, there is no conductive communication path between each first portion of the capacitor unit 214. Although Figure 2G , but it is understood that the top portion of the top support structure 150(c) and the first electrode 216 can be partially polished so that they become thinner after polishing. In some embodiments, the polishing process can include, but is not limited to, chemical mechanical polishing (CMP), mechanical polishing, electrochemical polishing, ultrasonic polishing, or any combination thereof.

[0088] At this stage, the first portion of capacitor unit 214 is completed. Figure 2A-2Q , but the first portion of the capacitor unit 214 may have an irregular shape (eg, a trapezoidal shape) in the YZ plane. Figure 2R As shown in FIG. 1 (a), the dielectric structure 149 has two ends: a first capacitor end 234 in the positive z-direction and a second capacitor end 236 in the negative z-direction, wherein the second capacitor end 236 is closer to the substrate 201 than the first capacitor end 234. Figure 2R As shown in FIG. 2A , the first capacitor terminal 234 can be wider than the second capacitor terminal 236, for example due to etching from the first capacitor terminal 234 to the second capacitor terminal 236, thereby forming a trapezoidal shape in the YZ plane. The larger first capacitor terminal 234 enables an increased coverage window of the capacitor unit 214.

[0089] Figure 2H-2L An exemplary process of forming vertical transistor 126 and BL 123 on top of the first portion of capacitor cell 214 is shown.

[0090] refer to Figure 2H In some embodiments, a layer of first terminal 138 is deposited followed by deposition of body 220. First terminal 138 serves as a vertical transistor 126 (see Figure 1), for example, a source terminal, while the body 220 is used to form the semiconductor body of the vertical transistor 126. In some embodiments, the material used for the first terminal 138 may include, but is not limited to, doped Si, SiGe, GaAs with N-type or P-type dopants, or any combination thereof. N-type dopants may include, but are not limited to, phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof. P-type dopants may include, but are not limited to, boron (B), aluminum (Al), gallium (Ga), or any combination thereof. An annealing process may be performed to form a composite conductive material, such as a silicide, at the interface between the first terminal 138 and the first electrode 144. In some embodiments, the body 220 includes, but is not limited to, amorphous silicon, polycrystalline silicon, single crystal silicon, or any combination thereof. In some embodiments, the first terminal 138 and the body 220 may be deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, MOCVD, molecular beam epitaxy (MBE), sputtering, or any combination thereof.

[0091] In some embodiments, first terminal 138 is part of a transistor channel material, such as indium gallium zinc oxide (IGZO), as described below. One end of the IGZO is coupled to capacitor 128, while the other end of the IGZO is coupled to bit line 123. As such, a separate deposition of the first terminal material and / or subsequent annealing thereof is not required.

[0092] like Figure 2H As shown in FIG. 2 (b), one or more hard masks are deposited on top of the body 220 to protect selected areas of the body 220 during a subsequent etching process. In some embodiments, the hard mask material includes, but is not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride, silicon carbide (SiC), or any combination thereof.

[0093] Figure 2I The diagram (a) shows a top view of the XY plane, and Figure 2I Illustration (b) is a cross-sectional view in the YZ plane (eg, in the EE plane passing through a row of body grooves).

[0094] like Figure 2IAs shown in FIG. 2 (a), an array of body grooves 226 is formed. Each body groove 226 extends along the X direction (BL direction), and two adjacent body grooves 226 are distributed along the Y direction (WL direction). The width of the body groove 226 in the X direction is shorter than the length of the body groove 226 in the Y direction. The body groove 226 is etched vertically along the Z direction until at least a portion of the top support structure 150 (c) is exposed. Each body groove 226 can have the same spacing, critical dimension (CD) or size, etc. In some embodiments, the etching of the body 220 for forming the body grooves 226 can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputtering etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0095] An annealing process is then performed to form a thin layer of silicon oxide along the vertical sidewalls 228 of the body trench 226 ( Figure 2I (not shown) to repair the exposed silicon surface. A dielectric fill material 240 is then deposited to fill the body trench 226, followed by a polishing process to level the top surface of the dielectric filler 240 with the top surface of the hard mask 222. The dielectric fill material 240 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The dielectric fill material 240 may be deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, sputtering, or any combination thereof. In some embodiments, the polishing process includes, but is not limited to, chemical mechanical polishing (CMP), mechanical polishing, electrochemical polishing, ultrasonic polishing, or any combination thereof.

[0096] although Figure 2I , but it is understood that the body trench 226 and / or the patterned body 220 may be trapezoidal in shape in the ZY plane, for example due to etching from the top to the bottom. Figure 2R , the patterned body 220 may have a first body end 230 in the positive z-direction and a second body end 232 in the negative z-direction opposite the first body end 230. The second body end 232 is closer to the first terminal 138 than the first body end 230. In some embodiments, in the case of a trapezoidal shape, the first body end 230 is narrower than the second body end 232. Correspondingly, the body groove 226 has an inverted trapezoidal shape in which the top end of the body groove 226 is wider than the bottom end of the body groove 226, wherein the bottom end of the body groove is closer to the first terminal than the top end of the body groove.

[0097] As described above, the first capacitor end 234 is wider than the second capacitor end 236. The second body end 232 is coupled to the first capacitor end 234 via the first terminal 138 and the first electrode 144. Because both the second body end 232 and the first capacitor end 234 are wider, this "back-to-back trapezoidal" configuration facilitates overlying alignment between the patterned body 220 and the first portion of the capacitor cell 214, which facilitates, for example, the use of advanced semiconductor process technologies with narrower pitches.

[0098] like Figure 2J As shown in FIG, vertical gate (VG) trenches 242 are formed, each VG trench extending along the WL line direction (Y axis). The vertical gate trenches 242 penetrate the body 220 and the dielectric filler 240 along the Z direction, so that at least a portion of the top surface of the top support structure 150 (c) is exposed at the bottom of the VG trench 242. In some embodiments, the critical dimensions (CD) (e.g., width and depth) and the spacing between adjacent VG trenches 242 are the same. In some embodiments, the VG trenches 242 can have different lengths along the WL direction (see FIG. Figure 2J ). Trench etching may involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof. In some embodiments, self-aligned double patterning (SADP) is employed to produce finer and more densely packed trench features with smaller pitches.

[0099] Figure 2K The diagram (a) shows a top view of the XY plane, and Figure 2K The diagram (b) is a cross-sectional view in the YZ plane (eg, in the FF plane through a row of vertical transistors). The same layers are also arranged in Figure 2L middle.

[0100] from Figures 2I to 2K , involving multiple process sub-steps to form the vertical transistor 126. Although Figure 2K Not shown, but the process sub-steps are described below.

[0101] At least some of the VG grooves 242 are expanded along the BL direction (X axis), so that the width of the expanded VG grooves 242 ( b ) along the X axis is wider than the width of the unexpanded grooves 242 ( a ). Figure 2KAs shown in FIG, the length of the unextended VG groove 242(a) along the WL direction (Y axis) can be shorter than the length of the extended VG groove 242(b). In some embodiments, although Figure 2K It is not shown in the figure, but it should be understood that the length of the unextended VG groove 242(a) along the WL direction (Y axis) can be longer than or equal to the length of the extended VG groove 242(b). Figure 2K As shown in FIG. 2 (a), the unextended VG trenches 242 (a) and the extended VG trenches 242 (b) are staggered such that an extended VG trench 242 (b) exists between two unextended VG trenches 242 (a) along the BL direction (X-axis). In some embodiments, the expansion process can be achieved by etching, which involves one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputtering etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof. After etching, at least a portion of the remaining body 220 can be used as the first semiconductor body 171 to form the vertical transistor 126.

[0102] For isolation purposes, a bottom dielectric material 246 is deposited into both the extended VG trench 242(b) and the unextended VG trench 242(a), thereby forming the isolation region 160. It should be understood that, depending on the spacing of the VG trenches 242, voids 249 may be formed in the isolation region 160. In some embodiments, the bottom dielectric material 246 may be formed using a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bottom dielectric material 246 may be deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, MOCVD, molecular beam epitaxy (MBE), sputtering, or any combination thereof.

[0103] An etching process may be performed to etch the bottom dielectric material 246 down to a specified height above the top surface of the top support structure 150(c). The bottom dielectric material 246 remaining after etching may function as a gate spacer for isolation purposes. In some embodiments, the etching process is performed only in the extended VG trenches 242(b), while the non-extended VG trenches 242(a) remain unetched and may be protected by a hard mask during etching ( Figure 2K). In some embodiments, the remaining height of the bottom dielectric material 246 in the Z direction after etching can be at least 70 nm above the top surface of the top support structure 150 ( c ). The etching can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H 2 SO 4 / H 2 O 2), or any combination thereof.

[0104] The second body 172 may be deposited on the sidewalls of the VG trench 242, laterally covering the first body 171. The second body 172 may form a transistor channel of the vertical transistor 126 (see Figure 2K 246 ). The second body 172 can be deposited before or after the deposition of the bottom dielectric material 246. The transistor body 130 includes a first body 171 and at least a portion of the second body 172. In some embodiments, the second body 172 laterally covers both the first body 171 and at least a portion of the first terminal 138. The material of the second body 172 can include, but is not limited to, polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO), or any combination thereof. The first body 171 can include the same material as the body 220, including, but not limited to, amorphous silicon, polysilicon, single crystal silicon, or any combination thereof. In some embodiments, the second body 172 has a higher electron mobility than the first body 171. The second body 172 can be deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof.

[0105] In some embodiments, the transistor channel of the vertical transistor 126 is formed by annealing the polysilicon after forming the first body 171 (e.g., polysilicon). Annealing can change the properties of the surface layer of the first body 171 so that the surface layer is suitable for the transistor channel. The surface layer for the transistor channel can be Figure 2K The second body 172 in Figure (b) is shown.

[0106] A gate dielectric 132 layer is deposited on the sidewalls of the VG trench 242 to form a gate oxide. Figure 2KAs shown in FIG. 1 (b), the gate dielectric 132 contacts and laterally covers at least a portion of the second body 172. In some embodiments, the length of the gate dielectric 132 along the Z-axis can be equal to or shorter than the length of the second body 172. In some embodiments, the gate dielectric 132 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, any material having a dielectric constant greater than or equal to 3.9, or any combination thereof. The gate dielectric 132 can be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof.

[0107] The gate electrode 134 is deposited on the surface (including the sidewalls) of the VG trench 242, and the gate electrode 134 laterally covers at least a portion of the gate dielectric 132. In some embodiments, the gate electrode 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer on a TiN layer, such as Figure 2K As shown in FIG. 1 (b), the gate electrode 134 includes two layers: a first gate electrode layer 134 ( a ) (eg, TiN) and a second gate electrode layer 134 ( b ) (eg, W).

[0108] In some embodiments, the top end of the gate electrode 134 can be subsequently recessed or etched such that the top end of the gate electrode 134 is vertically lower than the top surface of the first body 171 along the Z direction, where the "top" end of the gate electrode 134 can be defined as the electrode end in the positive Z direction. Additionally, the bottom end of the gate electrode 134 can contact the top surface of the bottom dielectric material 246, where the "bottom" end of the gate electrode 134 is opposite the top end along the negative Z direction. Thus, the length of the gate electrode 134 along the Z direction can be shorter than the length of the first body 171.

[0109] In some embodiments, the first gate electrode layer 134(a) may have an angled or curved end, for example, an L-shape in an XZ plane view. Figure 2KAs shown in FIG. 1 (b), the L-shaped gate electrode 134 (a) includes two portions: a first portion extending along the Z-axis or along an oblique angle relative to the Z-axis, and a second portion extending along the X-axis. Furthermore, the second portion of the gate electrode 134 (a) extending along the x-axis is closer to the first terminal 138 than the first body end 230. Two adjacent L-shaped gate electrodes 134 in the BL direction (X-axis) can be mirror-symmetrical with respect to the trench isolation region 160. In other words, one L-shaped gate electrode 134 can have a portion extending along the positive x-direction, while its adjacent L-shaped gate electrode 134 can have a portion extending along the negative x-direction, thereby forming a mirror-symmetrical configuration.

[0110] The gate dielectric 132 and the gate electrode 134 form a gate structure 136. In one example, the gate structure 136 can be a "gate oxide / gate poly" gate, wherein the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped polysilicon. In another example, the gate structure 136 can be an HKMG, wherein the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes metal. In some embodiments, the gate structure 136 is formed only in the extended VG trench 242(b). In some embodiments, the gate structure 136 is formed in both the unextended VG trench 242(a) and the extended VG trench 242(b). Figure 2K not shown).

[0111] For isolation purposes, a dielectric material is deposited between two adjacent L-shaped gate electrodes 134 in the extended VG trench 242(b), thereby forming an isolation region 160. The dielectric material can be the same material as the bottom dielectric material 246 or a different material. The dielectric material can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The dielectric material can be deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof.

[0112] A polishing process is performed to polish away the hard mask 222 ( Figure 2J Diagram (b) and Figure 2K After polishing, the top surface of the first body 171 is exposed. The polishing process may include, but is not limited to, chemical mechanical polishing (CMP), mechanical polishing, electrochemical polishing, ultrasonic polishing, or any combination thereof.

[0113] like Figure 2LAs shown in FIG, a dielectric layer is deposited to form BL isolation 248. An array of BL trenches (not shown) is then formed in BL isolation 248 by etching. In some embodiments, each BL trench extends along the BL direction (X-axis), where its X dimension is longer than its Y dimension. The bottom of the BL trench along the Z-axis contacts the top surface of transistor body 130 and the top surface of isolation region 160. The array of BL trenches can be distributed along the Y-axis. In some embodiments, BL isolation 248 can be formed using a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Etching of the BL trenches can be performed using one or more dry and / or wet etching processes including, but not limited to, reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof. In some embodiments, the formation of the BL trench involves self-aligned double patterning (SADP).

[0114] After forming the BL trench, a second terminal 139 is deposited into the BL trench in contact with the transistor body 130, wherein the second terminal 139 only partially fills the BL trench in the Z direction. A conductive material is then deposited into the BL trench on top of the second terminal 139 to form the bit line 123. A polishing process is then performed to polish away excess conductive BL material and ensure that the top surface of the bit line 123 is flush with the top surface of the BL isolation 248. In some embodiments, the material used for the second terminal 139 can include, but is not limited to, single crystal silicon or polycrystalline silicon, SiGe, GaAs, or any combination thereof, doped with an N-type dopant (e.g., phosphorus (P) or arsenic (As)) or a P-type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, the bit line 123 is made of a conductive material (e.g., W, Co, Cu, Al, or any combination thereof). In some embodiments, bit line 123 is made of a composite conductive material, including but not limited to WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. In some embodiments, deposition of second terminal 139 and bit line 123 can be achieved by one or more thin film deposition processes, including but not limited to electroplating, electroless plating, CVD, PVD, ALD, MOCVD, MBE, sputtering, electron beam evaporation, or any combination thereof. In some embodiments, due to the relatively small spacing of bit lines 123 along the WL direction (e.g., the Y direction), gaps 250 can be formed.

[0115] In some embodiments, the second terminal 139 is part of a channel material as described above, such as (IGZO). As such, a separate deposition of the second terminal material is not required.

[0116] refer to Figure 1 and Figure 2M , an interconnect layer 122 is formed on the second semiconductor structure 104. The interconnect layer 122 may be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. After forming the interconnect layer 122, the second semiconductor structure 104 and the first semiconductor structure 102 may be bonded at the bonding interface 106 therebetween.

[0117] As described above, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single crystal silicon (c-Si)), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include a peripheral circuit 112 located on the substrate 110. In some embodiments, the peripheral circuit 112 includes a plurality of transistors (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors) may also be formed on or in the substrate 110. In some examples, the peripheral circuit 112 is formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or a CMOS die.

[0118] In some embodiments, first semiconductor structure 102 further includes an interconnect layer 116 located above peripheral circuitry 112 to transmit electrical signals to and from peripheral circuitry 112. Interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and VIA contacts. Interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which interconnect lines and via contacts may be formed. In other words, interconnect layer 116 may include interconnect lines and via contacts in multiple ILD layers. In some embodiments, peripheral circuitry 112 is coupled to one another via interconnects in interconnect layer 116. The interconnects in interconnect layer 116 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed using dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0119] like Figure 1 and Figure 2MAs shown in , the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may also include a bonding layer 118 located at the back side of the bonding interface 106 and located above the interconnect layer 116 and the peripheral circuit 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 118 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as Figure 1 and Figure 2M As shown in , the second semiconductor structure 104 may also include a bonding layer 120 located at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric material that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric material may be used for hybrid bonding. The bonding contacts 121 may be in contact with the bonding contacts 119 at the bonding interface 106. In some embodiments, as Figure 2M As shown in FIG, a bonding layer 120 includes a dielectric layer opposite a memory cell (eg, a DRAM cell) 124, with a bit line 123 positioned between the dielectric layer and the memory cell 124. The dielectric layer may include a bonding interface 106 having a bonding contact 121.

[0120] like Figure 2N As shown in , the second semiconductor structure 104 is flipped over, and the substrate 201 is removed to at least partially expose the support structure 150, the first electrode 144, and the sacrificial layer 206. In some embodiments, the substrate 201 is removed by a polishing process. The polishing process may include, but is not limited to, chemical mechanical polishing (CMP), mechanical polishing, electrochemical polishing, ultrasonic polishing, or any combination thereof.

[0121] like Figure 2O , the sacrificial layer 206 is at least partially etched away, thereby exposing a first portion of the capacitor cell 214. The etching may involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0122] Figure 2PAn exemplary configuration of a pillar-type capacitor is shown. First, capacitor body 145 is deposited to at least partially cover the surface of first electrode 144, so that first electrode 144 is in contact with and laterally surrounded by capacitor body 145. Second electrode 143 is then formed to at least partially cover capacitor body 145, so that capacitor body 145 is in contact with and laterally surrounded by second electrode 143. In other words, capacitor body 145 is located between first electrode 144 and second electrode 143. After deposition, support structure 150 can be located between first electrode 144 and second electrode 143, or between the first electrodes 144 of two adjacent capacitors 128.

[0123] A filler material 252 may then be deposited to fill the gaps between the different pillar capacitors. Figure 2P As shown in FIG, an etching process is performed to remove unwanted portions of first electrode 144, second electrode 143, capacitor body 145, and filler material 252 in areas outside the capacitor array. In some embodiments, capacitor body 145 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, second electrode 143 comprises the same conductive material as first electrode 144, including but not limited to SiGe, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, first electrode 144 comprises TiN, and second electrode 143 comprises two or more conductive layers, such as a SiGe layer positioned above a TiN layer. In some embodiments, filler material 252 may comprise a dielectric material including but not limited to silicon oxide, silicon nitride, a low-k dielectric, or a high-k dielectric, or any combination thereof.

[0124] Figure 2Q and Figure 1 is the same graph, only the polarity of the Z axis is different. Figure 1 In the , the positive Z axis is upward, and in Figure 2Q The positive Z axis is downward (due to Figure 2N However, this reversal of the z-axis polarity does not have any meaningful impact on the exemplary construction of the 3D semiconductor device.

[0125] like Figure 2QAs shown in FIG, the second semiconductor structure 104 may further include a pad output interconnect layer 156 located above the capacitor 128 and the DRAM cell 124. The pad output interconnect layer 156 may include interconnects (e.g., contact pads 154) located in one or more ILD layers. The second semiconductor structure 104 may further include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends from the dielectric layer of the bonding layer 120 in the z-direction to couple to the second end of the capacitor 128 via the common plate 146. In some embodiments, the ILD layer in which the capacitor 128 is formed has the same dielectric material as the ILD layer into which the transistor body 130 extends, such as silicon oxide.

[0126] Despite Figure 2Q and Figure 1 , but it should be understood that in some embodiments, the capacitor 128 and / or the vertical transistor 126 may have a trapezoidal cross-section in the XZ plane. Figure 2R , the first body end 230 of the vertical transistor 126 may be narrower than the second body end 232 of the vertical transistor 126 , and the first capacitor end 234 may be wider than the second capacitor end 236 .

[0127] Despite Figure 2A-2R Only pillar-type capacitors are shown in FIG. 1 , but it should be understood that the technology implemented herein can be applied to other types of capacitors, such as cup-type capacitors or 3D memory devices based on cup-type capacitors. Figure 3 3 shows an exemplary configuration of a cup-type capacitor 330. The first electrode 301 of the cup-type capacitor 330 may be located on the inner surface of the capacitor trench. The second electrode 303 of the cup-type capacitor 330 may have a "T" shape, wherein a first portion of the "T" shape extends vertically along the z-axis and a second portion of the "T" shape extends laterally along the x-axis (e.g., BL direction). The first electrode 301 of the cup-type capacitor 330 may be isolated from the second electrode 303 by the capacitor body 302 of the cup-type capacitor 330. Similar to Figure 2A-2QIn the process for forming a pillar-type capacitor, the first electrode 301 of the cup-type capacitor 330 can be formed before forming the vertical transistor 310, while the second electrode 303 of the cup-type capacitor 330 and the capacitor body 202 of the cup-type capacitor 330 can be formed after forming the vertical transistor 310. In some embodiments, the first electrode 301 of the cup-type capacitor 330 and the second electrode 303 of the cup-type capacitor 330 include the same material or different materials. In some embodiments, the first electrode 301 and the second electrode 303 include a conductive material including, but not limited to, SiGe, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, at least one of the first electrode 301 or the second electrode 303 includes multiple conductive layers, such as a SiGe layer on a TiN layer. In some embodiments, capacitor body 302 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric including, but not limited to, Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , TiO 2 , or any combination thereof.

[0128] Although Figure 2A-2R Only a mirror-symmetrical gate structure is shown, but it should be understood that other arrangements of gate electrodes may be employed, including but not limited to a single-sided gate structure, a double-sided gate structure, a three-sided gate structure, or a gate-all-around (GAA) structure. Figure 4A A single-sided gate is shown, where the gate electrode 402 is formed congruently on one lateral side of the vertical transistor 404, eg, the right-hand side in the positive X-direction. Figure 4B A double-sided gate configuration is shown, wherein gate electrodes 424 are formed on both lateral sides of the vertical transistor 422, for example, in the positive X direction and the negative X direction. Figure 4A and Figure 4B , but it should be understood that in some embodiments, the gate electrode (e.g., Figure 4A 402 or Figure 4B 424 in FIG. 4 has an angled or curved (e.g., L-shaped) end. In some examples, the L-shaped gate electrode has a first portion extending along the X direction and a second portion extending along the Z direction or at an oblique angle relative to the Z direction, wherein the first portion extending along the X direction is closer to the first terminal 406 (e.g., source terminal) than the second terminal 408 (e.g., drain terminal). In some embodiments, the gate electrode (e.g., Figure 4A 402 or Figure 4B 424) includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode (e.g., Figure 4A 402 or Figure 4B 424) includes two or more conductive layers, such as a W layer located on a TiN layer.

[0129] Figure 5 is a flow chart of an exemplary process 500 for forming a 3D semiconductor device. The 3D semiconductor device may be Figure 1 3D semiconductor device 100 is similar to or the same as, or is a part of, 3D semiconductor device 100 (eg, Figure 1 The second semiconductor structure 104 in Figure 1 The structure of the 3D semiconductor device 100 at an intermediate manufacturing process, or Figure 3 The semiconductor structure 300, or Figure 4A 3D semiconductor structure 410 in, or Figure 4B The 3D semiconductor structure 420 in FIG. Figure 2A-2R The process 500 may include forming Figure 2A-2R Process 500 includes steps that can be performed in any suitable order and / or in any combination.

[0130] At step 502, a first portion of a capacitor of a semiconductor structure is formed on a semiconductor substrate, wherein the first portion of the capacitor includes a first electrode and a dielectric structure, and the first electrode of the capacitor is separated by a sacrificial layer. The first portion of the capacitor may be, for example, Figure 2F-Figure 2O The first portion of capacitor 214 or Figure 3 The first part of the capacitor 316 in the semiconductor structure can be, for example, Figure 1 as well as Figure 2A-2R The second semiconductor structure 104 in the semiconductor substrate can be, for example, Figure 1 as well as Figure 2A-2M The first electrode may be, for example, Figure 1 as well as Figure 2D-2R The first electrode 144, or Figure 3 The first electrode of the cup capacitor 301 in FIG. The dielectric structure may be, for example, Figure 2D-2R The dielectric structure 149 in the sacrificial material can be, for example, Figure 2B-2N The sacrificial layer 206 or Figure 3The sacrificial layer 314 in the semiconductor substrate 201 may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The electrode material may include, but is not limited to, TiN, TaN, Al, W, Cu, Co, Cu, doped polysilicon, silicide, or any combination thereof. The sacrificial layer may be formed using a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0131] In some embodiments, forming a first portion of a capacitor of a semiconductor structure on a semiconductor substrate includes: forming an array of holes through one or more dielectric layers on the semiconductor substrate, depositing a first conductive film on a surface of the array of holes, and filling the array of holes with a dielectric material by depositing a dielectric material on the first conductive film to form a dielectric structure of the capacitor. The dielectric structure in the dielectric structure has a first end and a second end opposite to each other. The first end is closer to the transistor than the second end, and the first end has a larger size than the second end (see Figure 2R ). The dielectric layers are separated by an isolation material. The dielectric layers may be, for example, Figure 2A-Figure 2N The sacrificial layer 206 in the Figure 3 The sacrificial layer 314 in the hole array can be, for example Figure 2C-2R capacitor trench 208 in, or Figure 3 The capacitor trench 340 in the dielectric structure can be Figure 2D-2R The dielectric structure 149 in the conductive film can be, for example, Figure 1 as well as Figure 2D-2R The first electrode 144, or Figure 3 The first electrode of the cup-type capacitor 301 in FIG.

[0132] At step 504, a vertical transistor of the semiconductor structure is formed on top of the first portion of the capacitor. The vertical transistor may be, for example, Figure 1 and Figure 2K-2Q The vertical transistor 126 in Figure 3 The vertical transistor 310 in Figure 4A The vertical transistor 404 or Figure 4B Each vertical transistor extends along a vertical direction (e.g., Z direction); two adjacent vertical transistors and the corresponding isolation region between the two adjacent vertical transistors are placed along a first lateral direction (e.g., X direction) perpendicular to the vertical direction. The first part of the capacitor may be, for example, Figure 2F-2N The first portion of capacitor 214 or Figure 3 The first portion of capacitor 316 in FIG.

[0133] In some embodiments, forming a vertical transistor of a semiconductor structure on a first portion of a capacitor includes: forming a transistor body of the transistor, the transistor body coupled to a first electrode of the capacitor; forming a vertical gate of the transistor adjacent to the transistor body of the transistor; and forming an isolation region between two adjacent transistors. The isolation region has a first end proximate to the first electrode of the capacitor and a second end opposite the first end along a first direction, and the first end has a smaller size than the second end (see Figure 2R ). The transistor body may be, for example, Figure 2H-2R The subject 220, Figure 3 The main body 350 or Figure 4A-4B The body 440 in the isolating area may be, for example, Figure 2K-2Q Isolation area 160, Figure 3 The isolated area 332 or Figure 4A-4B The isolation area 442 in the.

[0134] In some embodiments, forming a transistor of a semiconductor structure on the first portion of the capacitor further comprises: forming a conductive layer on the first portion of the capacitor; annealing the conductive layer, wherein a conductive material of the conductive layer reacts with the first electrode of the capacitor to form a composite conductive material; forming a body on the conductive layer; and forming a trench extending through the layer of composite conductive material and the body to form a first terminal of the transistor and a transistor body of the transistor, respectively. The first terminal may be, for example, Figure 2H-2Q The first terminal 138, Figure 3 The first terminal 334 or Figure 4A-4B The first terminal 406 in the groove can be, for example Figure 2I-2R The main groove 226, Figure 3 The main groove 336 or Figure 4A-4B The main body groove 444 in.

[0135] In some embodiments, the method for forming a semiconductor device further includes: forming a bit line on the second terminal of the transistor, forming at least a conductive interconnect layer on the bit line, and bonding the semiconductor structure to the control structure by bonding a surface of at least the conductive interconnect layer to a surface of a control circuit of the control structure. The bit line may be, for example, Figure 1 、 Figure 2L-2Q Bit line 123, Figure 3 bit line 338 or Figure 4A-4B The second terminal may be, for example, Figure 1 、 Figure 2L-2Q The second terminal 139 or Figure 4A-4B The second terminal 408 in the control structure can be, for example, Figure 1 、 Figure 2M-2Q The first semiconductor structure 102 in FIG.

[0136] At step 506, the semiconductor substrate (eg, Figure 2A-2M The first portion of the capacitor may be, for example, Figure 2F-2N The first portion of capacitor 214 or Figure 3 The first portion of capacitor 316 in FIG.

[0137] At step 508, a second portion of the capacitor is formed by at least partially replacing at least one of a sacrificial material or a dielectric structure located between the first electrodes of the capacitor, the second portion of the capacitor including the second electrode and a capacitor body located between the first electrode and the second electrode. The second portion of the capacitor may be, for example, Figure 2P-2Q The second portion of the capacitor unit 260 or Figure 3 The second part of the capacitor 312 in the sacrificial material can be, for example Figure 2B-2N The sacrificial layer 206 or Figure 3 The dielectric structure may be, for example, a sacrificial layer 314 in Figure 2D-2R The dielectric structure 149 in the capacitor. The first electrode of the capacitor can be, for example, Figure 1 and Figure 2D-2R The first electrode 144, or Figure 3 The first electrode of the cup-type capacitor 301 in FIG. The second electrode may be, for example, Figure 1 and Figure 2P-2Q The second electrode 143 in, or Figure 3 The second electrode of the cup-type capacitor 303 in FIG. The capacitor body may be, for example, Figure 1 and Figure 2P-2Q The capacitor body 145, or Figure 3 The capacitor body of the cup-type capacitor 302 in FIG.

[0138] In some embodiments, the capacitor is a pillar-type capacitor, e.g. Figure 2P-2Q The second portion of the capacitor may include the following process steps: at least partially removing a sacrificial material located between the first electrodes of the capacitor, depositing a dielectric material on the first electrodes to form a capacitor body of the capacitor, and depositing at least one conductive film on the dielectric material to form the second electrode of the capacitor. The sacrificial material may be, for example, Figure 2B-2N The sacrificial layer 206 in the capacitor body can be, for example, Figure 2P-2Q The second electrode of the capacitor may be, for example, Figure 2P-2Q The second electrode 143 in.

[0139] In some embodiments, the capacitor is a cup-type capacitor, e.g. Figure 3The second portion of the capacitor may include the following process steps: removing a portion of the first electrode to expose one end of the dielectric structure (eg, Figure 3 ), removing at least a portion of the dielectric structure to form a trench; depositing a dielectric material on the first electrode in the trench to form a capacitor body of the capacitor (e.g., Figure 3 ), and depositing at least one conductive film in the trench to form a second electrode of the cup-type capacitor (e.g., Figure 3 As described above, the second electrode of the cup-type capacitor may have a "T" shape, wherein a first portion of the "T" shape extends vertically along the z-direction and a second portion of the "T" shape extends laterally along the x-direction. Figure 3 The first electrode 301 in the cup capacitor can be isolated from the second electrode by the capacitor body of the cup capacitor. In some embodiments, the first electrode and the second electrode of the cup capacitor include the same material. In some embodiments, the first electrode and the second electrode include different materials. In some embodiments, the first electrode and the second electrode include a conductive material including, but not limited to, SiGe, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, at least one of the first electrode or the second electrode includes multiple conductive layers, such as a SiGe layer positioned above a TiN layer. In some embodiments, the capacitor body includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, such as, but not limited to, Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof.

[0140] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown in FIG, system 600 may include a host device 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host device 608 may be configured to send data to or receive data from the one or more 3D memory devices 604.

[0141] The 3D memory device 604 may be any 3D memory device disclosed herein, for example, Figure 1 3D semiconductor device 100, or a portion of 3D semiconductor device 100 (eg, Figure 1 The second semiconductor structure 104 in FIG. 1 , or Figure 1 The structure of the 3D semiconductor device 100 at an intermediate manufacturing process, or Figure 3 The semiconductor structure 300, or Figure 4A 3D semiconductor structure 410, or Figure 4B 3D semiconductor structure 420 in. In some embodiments, 3D memory device 604 includes NAND flash memory. Memory controller 606 (also referred to as controller circuit) is coupled to 3D memory device 604 and host device 608. Consistent with embodiments of the present disclosure, 3D memory device 604 may include a plurality of conductive interconnects passing through a cover layer, the plurality of conductive interconnects contacting conductive pads located in a conductive pad layer, and memory controller 606 may be coupled to 3D memory device 604 via at least one of the plurality of conductive interconnects. Memory controller 606 is configured to control 3D memory device 604. For example, memory controller 606 may be configured to operate a plurality of channel structures via word lines. Memory controller 606 may manage data stored in 3D memory device 604 and communicate with host device 608.

[0142] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded MultiMediaCard (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 606 can be configured to control the operations of the 3D memory device 604 (e.g., read operations, erase operations, and program (or write) operations). The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction code (ECC) on data read from or written to the 3D memory device 604. Memory controller 606 may also perform any other suitable functions, such as formatting 3D memory device 604 .

[0143] The memory controller 606 can communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0144] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of terminal electronic products. Figure 6 In one example shown in FIG, a memory controller 606 and a single 3D memory device 604 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc.

[0145] The embodiments of the subject matter described in this disclosure and the actions and operations may be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or a combination of one or more thereof. The embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing device or for controlling the operation of the data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively or in addition, the carrier may be an artificially generated propagated signal, for example, a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof, or a portion thereof. A computer storage medium is not a propagated signal.

[0146] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0147] Generally, a term can be understood, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described.

[0148] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween. Furthermore, “over” or “over” not only means “over something” or “on something,” but also includes the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0149] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0150] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0151] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far away from the substrate. A layer can extend over the entire underlying or overlying structure, or can have a range that is smaller than the range of the underlying or overlying structure. In addition, a layer can be an area of ​​a uniform or non-uniform continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0152] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" can indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0153] In this disclosure, the term “horizontal / horizontally / laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical / vertically” means nominally perpendicular to a lateral surface of a substrate.

[0154] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a "memory string," such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0155] The present disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0156] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0157] Although this disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims defined by the claims themselves, but rather as descriptions of features that may be directed to specific embodiments of specific inventions. Certain features described in this disclosure may also be implemented in combination in a single embodiment in the context of separate embodiments. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any appropriate sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and claims may be directed to sub-combinations or variations of sub-combinations.

[0158] Similarly, although operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequence shown, or that all illustrated operations be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0159] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0160] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: An array structure comprising a plurality of memory cells, wherein a memory cell in the plurality of memory cells comprises a transistor and a capacitor stacked together along a first direction, The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure, wherein the first terminal and the second terminal are located at opposite ends of the transistor body along the first direction, and the gate structure extends along the first direction and is adjacent to the transistor body along a second direction perpendicular to the first direction. wherein the first terminal of the transistor contacts the first electrode of the capacitor along the first direction, and The gate structure includes a conductive film having an angled or curved end, wherein the angled or curved end is closer to the first terminal of the transistor than to the second terminal of the transistor.

2. The semiconductor device according to claim 1, wherein The transistor body includes a first body and a second body contacting each other along the second direction, and The second body has higher electron mobility than the first body, and the second body is closer to the gate structure than the first body.

3. The semiconductor device according to claim 2, wherein The first body includes amorphous silicon, and the second body includes at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO).

4. The semiconductor device according to any one of claims 1 to 3, wherein The transistor body includes at least one of polysilicon, indium gallium zinc oxide (IGZO), or indium gallium silicon oxide (IGSO).

5. The semiconductor device according to any one of claims 1 to 4, wherein The array structure includes an isolation region between transistors of two adjacent memory cells among the plurality of memory cells, The isolation region has a first end close to the first terminal of the transistor and a second end close to the second terminal of the transistor, and the first end has a smaller size than the second end.

6. The semiconductor device according to any one of claims 1 to 5, wherein The capacitor includes a dielectric structure extending along the first direction, and the first electrode is located on at least one surface of the dielectric structure, and The dielectric structure has a first end and a second end opposite to each other along the first direction, and the first end is closer to the first terminal of the transistor than the second end, and the first end has a larger size than the second end.

7. The semiconductor device according to claim 6, wherein The capacitor further includes a second electrode and a capacitor body located between the first electrode and the second electrode, wherein the first electrode surrounds the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and The array structure includes a support structure, which extends along the second direction and is distributed between the first electrode and the second electrode or between first electrodes of two adjacent capacitors along the first direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein The array structure further includes a plurality of bit lines, wherein one bit line among the plurality of bit lines contacts the second terminal of the transistor, and adjacent bit lines are isolated by corresponding isolation regions.

9. The semiconductor device according to claim 8, wherein The array structure is integrated in a first die, and the semiconductor device further includes a second die, wherein the first die includes at least one conductive interconnect, and the one bit line of the plurality of bit lines is coupled to the control circuit in the second die via the at least one conductive interconnect, wherein a surface of the cover layer located above the plurality of bit lines in the first die contacts a surface of the control circuit in the second die, and The plurality of bit lines are closer to the second die than the capacitor.

10. A semiconductor device comprising: An array structure comprising a plurality of memory cells, wherein a memory cell in the plurality of memory cells comprises a transistor and a capacitor stacked together along a first direction, The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure, wherein the first terminal and the second terminal are located at opposite ends of the transistor body along the first direction, and the gate structure extends along the first direction and is adjacent to the transistor body along a second direction perpendicular to the first direction. The transistor body includes at least one of polysilicon, indium gallium zinc oxide (IGZO) or indium gallium silicon oxide (IGSO). wherein the first terminal of the transistor contacts the first electrode of the capacitor along the first direction, and wherein the capacitor includes a dielectric structure extending along the first direction, the first electrode is located on at least one surface of the dielectric structure, and the dielectric structure has a first end and a second end opposite to each other along the first direction, and wherein the first end of the dielectric structure is closer to the first terminal of the transistor than the second end of the dielectric structure, and the first end of the dielectric structure has a larger size along the second direction than the second end of the dielectric structure.

11. The semiconductor device according to claim 10, wherein The array structure includes an isolation region located between transistors of two adjacent memory cells among the plurality of memory cells, and wherein the isolation region has a first end proximate to the first terminal of the transistor and a second end proximate to the second terminal of the transistor, and the first end has a smaller size than the second end.

12. The semiconductor device according to claim 10 or claim 11, wherein The gate structure includes a conductive film having an angled or curved end that is closer to the first terminal of the transistor than to the second terminal of the transistor.

13. The semiconductor device according to any one of claims 10 to 12, wherein The capacitor further includes a second electrode and a capacitor body located between the first electrode and the second electrode, wherein the first electrode surrounds the dielectric structure, the capacitor body covers the first electrode, and the second electrode covers the capacitor body, and The array structure includes a support structure, which extends along the second direction and is distributed between the first electrode and the second electrode or between first electrodes of two adjacent capacitors along the first direction.

14. The semiconductor device according to any one of claims 10 to 13, wherein The array structure further includes a plurality of bit lines, and one of the plurality of bit lines is in contact with the second terminal of the transistor, and adjacent bit lines are isolated by corresponding isolation regions. The array structure is integrated into a first die, and the semiconductor device further includes a second die. wherein the first die includes at least one conductive interconnect, and the one bit line of the plurality of bit lines is coupled to the control circuit in the second die via the at least one conductive interconnect, wherein a surface of the cover layer located above the plurality of bit lines in the first die contacts a surface of the control circuit in the second die, and The plurality of bit lines are closer to the second die than the capacitor.

15. A method comprising: forming a first portion of a capacitor of a semiconductor structure on a semiconductor substrate, wherein the first portion of the capacitor includes a first electrode and a dielectric structure, and the first electrode of the capacitor is separated by a sacrificial material; forming a transistor of the semiconductor structure on the first portion of the capacitor; removing the semiconductor substrate to at least partially expose the first portion of the capacitor; and A second portion of the capacitor is formed by at least partially replacing at least one of the sacrificial material or the dielectric structure located between the first electrodes of the capacitor, wherein the second portion of the capacitor includes a second electrode and a capacitor body located between the first electrode and the second electrode.

16. The method according to claim 15, wherein Forming a second portion of the capacitor by at least partially replacing at least one of the sacrificial material or the dielectric structure between the first electrodes of the capacitor includes: at least partially removing the sacrificial material located between the first electrodes of the capacitor, depositing a dielectric material on the first electrode to form the capacitor body of the capacitor, and At least one conductive film is deposited on the dielectric material to form the second electrode of the capacitor.

17. The method according to claim 15 or claim 16, wherein: Forming the transistor of the semiconductor structure on the first portion of the capacitor includes: forming a transistor body of the transistor, the transistor body coupled to the first electrode of the capacitor; forming a vertical gate of the transistor adjacent to the transistor body of the transistor; and An isolation region is formed between two adjacent transistors, wherein the isolation region has a first end close to the first electrode of the capacitor and a second end opposite to the first end along a first direction, and the first end has a smaller size than the second end.

18. The method according to claim 17, wherein Forming the transistor of the semiconductor structure on the first portion of the capacitor includes: forming a conductive layer on the first portion of the capacitor; annealing the conductive layer so that the conductive material of the conductive layer reacts with the first electrode of the capacitor to form a composite conductive material; forming a body on the conductive layer; and A trench is formed extending through the layer of composite conductive material and the body to form a first terminal of the transistor and the transistor body of the transistor, respectively.

19. The method according to any one of claims 15 to 18, further comprising: forming a bit line on the second terminal of the transistor; forming at least a conductive interconnect layer on the bit line; as well as The semiconductor structure is bonded to the control structure by bonding a surface of at least the conductive interconnect layer to a surface of a control circuit of the control structure.

20. The method according to any one of claims 15 to 19, wherein Forming the first portion of the capacitor of the semiconductor structure on the semiconductor substrate includes: forming an array of holes through one or more dielectric layers in the semiconductor substrate, wherein the dielectric layers are separated by isolation material; depositing a first conductive film on a surface of the array of holes; and filling the array of holes with a dielectric material by depositing the dielectric material on the first conductive film to form a dielectric structure of the capacitor, The dielectric structure in the dielectric structure has a first end and a second end opposite to each other, and the first end is closer to the transistor than the second end, and the first end has a larger size than the second end.

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