Memory and manufacturing method thereof, memory system and electronic equipment

Abstract

The embodiment of the invention discloses a memory and a manufacturing method thereof, a memory system and electronic equipment. The manufacturing method comprises the following steps: forming a substrate structure; wherein the substrate structure comprises a plurality of active parts which are arranged in an array along a first direction and a second direction and a plurality of first conductive parts which are arranged at intervals along the second direction; each first conductive part extends along a first direction and covers the side walls of two adjacent rows of active parts; the first direction and the second direction intersect, and the extension direction of the active part is perpendicular to the first direction and the second direction; forming a storage structure on the first side of the active part; wherein the storage structure is connected with the active part; etching the first conductive part from the second side of the active part to form a plurality of first conductive wires which are arranged at intervals along the first direction; wherein the second side and the first side are opposite to each other along the extension direction of the active part.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and are related to, but not limited to, a memory and a manufacturing method thereof, a memory system, and an electronic device. Background Art

[0002] Planar memory cells have been scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches its lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. However, the manufacturing process for 3D memory is complex, leading to increased manufacturing difficulty. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a memory is provided, comprising:

[0005] Forming a base structure; wherein the base structure includes a plurality of active portions arranged in an array along a first direction and a second direction, and a plurality of first conductive portions arranged at intervals along the second direction; each of the first conductive portions extends along the first direction and covers sidewalls of two adjacent rows of active portions; the first direction and the second direction intersect, and the extension direction of the active portion is perpendicular to both the first direction and the second direction;

[0006] forming a storage structure on a first side of the active portion; wherein the storage structure is connected to the active portion;

[0007] The first conductive portion is etched from the second side of the active portion to form a plurality of first conductive lines spaced apart along the first direction; wherein the second side and the first side are opposite to each other along the extending direction of the active portion.

[0008] In some embodiments, the active portion includes a first active pillar and a second active pillar spaced apart along the second direction; the base structure further includes a plurality of second conductive portions spaced apart along the second direction, each second conductive portion extending along the first direction and covering opposite side walls of the first active pillar and the second active pillar; and the manufacturing method further includes:

[0009] The second conductive portion is etched from the second side to form a plurality of second conductive lines arranged at intervals along the first direction; wherein the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged along the second direction.

[0010] In some embodiments, the first conductive line includes a first sub-conductive line and a second sub-conductive line spaced apart along the second direction; the base structure further includes an isolation structure, the isolation structure being located in the space between the first sub-conductive line and the second sub-conductive line and extending along the first direction; and the manufacturing method further includes:

[0011] forming a first contact plug connected to the first sub-conductive line; wherein the first contact plug is located on a side of the first sub-conductive line relatively far from the storage structure;

[0012] A second contact plug connected to the second sub-conductive line is formed; wherein the second contact plug is located on a side of the second sub-conductive line relatively far away from the storage structure; the second contact plug and the first contact plug are respectively located at two opposite ends along the first direction.

[0013] In some embodiments, the first sub-conductive line is located between the second conductive line and the second sub-conductive line; and the manufacturing method further includes:

[0014] A third contact plug connected to the second conductive line is formed; wherein the third contact plug is located on a side of the second conductive line relatively far from the storage structure; and the third contact plug and the second contact plug are located at the same end opposite to each other along the first direction.

[0015] In some embodiments, the second conductive portion and the first conductive portion are etched simultaneously.

[0016] In some embodiments, the manufacturing method further comprises:

[0017] A plurality of third conductive portions are formed on the second side and arranged at intervals along the first direction; wherein each of the third conductive portions extends along the second direction and is connected to the active portion located in the same column;

[0018] The third conductive portion is etched from the second side to form a plurality of third conductive lines spaced apart along the second direction.

[0019] In some embodiments, the third conductive portion and the first conductive portion are etched simultaneously.

[0020] In some embodiments, the manufacturing method further comprises:

[0021] A fourth contact plug connected to the third conductive line is formed; wherein the fourth contact plug is located on a side of the third conductive line relatively far away from the active portion; and the fourth contact plugs corresponding to two adjacent third conductive lines along the first direction are respectively located at two opposite ends along the second direction.

[0022] In some embodiments, the base structure further includes a plurality of insulating structures, wherein the insulating structures are located between two adjacent columns of active portions; and forming the third conductive portion on the second side of the active portion includes:

[0023] forming a conductive material layer covering the plurality of active portions and the plurality of insulating structures on the second side;

[0024] performing a heat treatment on the conductive material layer; wherein, during the heat treatment, the conductive material layer reacts with the active portion;

[0025] The conductive material layer that has not reacted with the active portion is removed, and the remaining conductive material layer constitutes the third conductive portion.

[0026] In some embodiments, the base structure further includes a substrate layer, and the substrate layer is located on the second side; the manufacturing method further includes:

[0027] Bonding the base structure and the carrier substrate so that the storage structure is located between the base structure and the carrier substrate;

[0028] The substrate layer is removed from a side of the base structure relatively away from the carrier substrate until the active portion is exposed.

[0029] In some embodiments, the first conductive portion covers the sidewalls of the channels and the first doped regions of two adjacent rows of active portions, and the channels are located between the second doped regions and the first doped regions of the active portions; and the manufacturing method further comprises:

[0030] Before etching the first conductive portion, the first conductive portion covering the sidewalls of the first doped regions of two adjacent rows of active portions is removed from the second side.

[0031] In some embodiments, the first conductive portion covers sidewalls of the trenches of two adjacent rows of active portions; the base structure further includes a bottom spacer layer, the bottom spacer layer being located between the two adjacent rows of active portions and covering sidewalls of the first doped regions of the two adjacent rows of active portions, and the trench being located between the second doped region and the first doped region of the active portions; and the fabrication method further includes:

[0032] Before etching the first conductive portion, the bottom spacer layer is removed from the second side until the first conductive portion is exposed.

[0033] In some embodiments, forming the base structure comprises:

[0034] providing a substrate;

[0035] Etching the substrate from a first side of the substrate to form a plurality of first trenches spaced apart along the first direction; wherein each of the first trenches extends along the second direction and has a bottom located in the substrate;

[0036] forming an insulating material layer in the first trench;

[0037] Etching the substrate and the insulating material layer from the first side of the substrate to form a plurality of second trenches spaced apart along the second direction; wherein each second trench extends along the first direction and has a bottom located in the substrate, and a depth of the second trench is less than a depth of the first trench; the plurality of second trenches and the plurality of first trenches separate the substrate into the plurality of active portions;

[0038] The first conductive portion is formed in the second trench.

[0039] According to a second aspect of an embodiment of the present disclosure, a memory is provided, wherein the memory includes a plurality of memory array slices; the memory array slices include:

[0040] A plurality of active portions are arranged in an array along a first direction and a second direction; wherein the first direction and the second direction intersect, and an extension direction of the active portion is perpendicular to both the first direction and the second direction;

[0041] a plurality of first conductive lines arranged at intervals along the second direction; wherein each of the first conductive lines extends along the first direction and covers side walls of two adjacent rows of active portions in the memory array;

[0042] a storage structure located on a first side of the active portion and connected to the active portion;

[0043] The first conductive lines located in the same row in two adjacent memory array slices are arranged at intervals along the first direction.

[0044] In some embodiments, the active portion includes a first active pillar and a second active pillar spaced apart along the second direction; and the memory array chip further includes:

[0045] a plurality of second conductive lines arranged at intervals along the second direction; wherein each second conductive line extends along the first direction and covers two opposite side walls of the first active pillar and the second active pillar in the memory array; the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged along the second direction;

[0046] The second conductive lines located in the same row in two adjacent memory array slices are arranged at intervals along the first direction.

[0047] In some embodiments, the first conductive line includes a first sub-conductive line and a second sub-conductive line spaced apart along the second direction; and the memory array chip further includes:

[0048] a first contact plug, located on a side of the first sub-conductive line relatively far from the storage structure and connected to the first sub-conductive line;

[0049] a second contact plug, located on a side of the second sub-conductive line relatively away from the storage structure and connected to the second sub-conductive line; wherein the second contact plug and the first contact plug are respectively located at two opposite ends along the first direction;

[0050] The isolation structure is located in the space between the first sub-conductive line and the second sub-conductive line and extends along the first direction.

[0051] In some embodiments, the first sub-conductive line is located between the second conductive line and the second sub-conductive line; and the memory array chip further includes:

[0052] The third contact plug is located on a side of the second conductive line relatively away from the storage structure and is connected to the second conductive line; wherein the third contact plug and the second contact plug are located at the same end opposite to each other along the first direction.

[0053] In some embodiments, the storage array slice further includes:

[0054] a plurality of third conductive lines located on a second side of the active portion and spaced apart along the first direction; wherein each of the third conductive lines extends along the second direction and is connected to the active portion located in the same column of the memory array; and the second side and the first side are opposite to each other along the extension direction of the active portion;

[0055] The third conductive lines located in the same column of two adjacent memory array slices are arranged at intervals along the second direction.

[0056] In some embodiments, the storage array slice further includes:

[0057] The fourth contact plug is located on a side of the third conductive line relatively away from the active portion and connected to the third conductive line; wherein the fourth contact plugs corresponding to two adjacent third conductive lines along the first direction are respectively located at two opposite ends along the second direction.

[0058] In some embodiments, the memory includes dynamic random access memory, ferroelectric memory, or phase change memory.

[0059] According to a third aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0060] One or more memories according to any one of the embodiments of the second aspect of the present disclosure;

[0061] A controller is coupled to the memory and configured to control the memory.

[0062] According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: the memory system as described in the third aspect of the embodiment of the present disclosure.

[0063] In this embodiment, the first conductive portion is etched from the second side of the active portion to form a plurality of first conductive lines spaced apart along the first direction. The first conductive lines can be used as word lines, thereby concentrating the processing of the word lines on one side of the substrate (i.e., the second side), which is conducive to simplifying the manufacturing process and reducing the process difficulty and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0065] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0066] Figure 2 is a schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure;

[0067] Figure 3 This is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure;

[0068] Figures 4 to 13 It is a schematic diagram of a manufacturing process of a memory shown in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0070] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0071] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0072] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0073] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0074] Figure 1 1 is a schematic diagram of an electronic device 1 according to an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device.

[0075] like Figure 1 As shown in FIG, an electronic device 1 may include a host HOST and a memory system 30, the memory system 30 having one or more memories 20 and a controller 10. The host HOST may be a processor of the electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The host HOST may be configured to send data to the memory 20 or receive data from the memory 20. The controller 10 is coupled to the memory 20 and the host HOST and is configured to control the memory 20. The controller 10 may manage data stored in the memory 20 and communicate with the host HOST.

[0076] The controller 10 may be configured to control operations of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the controller 10 may also be configured to process error correction codes (ECC) on data read from or written to the memory 20. The controller 10 may also perform any other suitable functions, such as formatting the memory 20.

[0077] In some specific embodiments, the controller 10 and one or more memories 20 can be integrated into various types of storage devices. For example, the controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and the multiple memories 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into various types of terminal electronic products.

[0078] The controller 10 can send or receive data to or from the host HOST, and can send a command CMD and an address ADDR to the memory 20. The controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST. The command generator 110 may generate an access command, a refresh command, etc. by decoding the command CMD received from the host HOST, and may provide the access command and the refresh command to the memory 20 through the device interface 130. An access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. A refresh command may be a signal instructing the memory 20 to read out and rewrite data by accessing a row of the memory cell array 220 corresponding to the refresh address ADDR.

[0079] The address generator 120 in the controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory 20 can generate an address of a memory bank to be accessed when the memory cell array 220 includes a plurality of memory banks.

[0080] The controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20. In some embodiments, the memory 20 includes a memory cell array 220 and a peripheral circuit 210. The memory cell array 220 includes multiple memory banks, each memory bank includes multiple memory array tiles (MAT), each memory array tile includes multiple memory cell rows and multiple memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 210 can write data to or read data from the memory cell array 220 based on the command CMD and address ADDR received from the controller 10, or can provide a control signal CTRL to the row decoder and column decoder for refreshing the memory cells included in the memory cell array 220. In other words, the peripheral circuit 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: a control circuit corresponding to each memory array chip, such as a sensing amplifier (SA) and a word-line driver (WLD), a control circuit corresponding to each memory bank, such as a row decoder and a column decoder, and a control circuit corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0081] The memory 20 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description only uses DRAM as an example.

[0082] Figure 2Schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure. Figure 2 As shown, the dynamic random access memory includes at least one DRAM chip (Die), each DRAM chip includes a memory cell array, and the memory cell array includes a plurality of memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T (Transistor) and a capacitor C (Capacitor). The word line is coupled to the gate of the transistor T, and the bit line is coupled to the drain of the transistor T. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, and the memory cell array uses rows (Row) and columns (Column) to specify the address. By specifying the intersection of the row and column (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and read, write or refresh the data stored therein.

[0083] With the development of dynamic random access memory technology, the size of storage cells is getting smaller and smaller, and its array architecture is composed of 8F 2 Go to 6F 2 Then go to 4F 2 , the architecture of transistors in memory cells has also gradually evolved from planar array transistors to vertical gate transistors, thus forming a three-dimensional memory architecture.

[0084] During the fabrication of three-dimensional memory devices, word and bit line processing is typically dispersed across the substrate. For example, word and bit lines are typically formed on the front side of the substrate, then thinned from the back after flipping. After thinning, the word and bit lines are then separately routed out from the back side. This complicates the fabrication process and increases the difficulty. Furthermore, the dispersed processing of word and bit lines on both sides of the substrate reduces opportunities for cost reduction later on, hindering process integration and increasing process costs. Therefore, simplifying the fabrication process and reducing both difficulty and cost have become pressing technical challenges.

[0085] Based on one or more of the above problems, an embodiment of the present disclosure provides a method for manufacturing a memory.

[0086] Figure 3 1 is a flow chart showing a method for manufacturing a memory according to an embodiment of the present disclosure. Figure 3 As shown, the production method comprises at least the following steps:

[0087] S310: Forming a substrate structure; wherein the substrate structure includes a plurality of active portions arranged in an array along a first direction and a second direction, and a plurality of first conductive portions arranged at intervals along the second direction; each first conductive portion extends along the first direction and covers sidewalls of two adjacent rows of active portions; the first direction and the second direction intersect, and the extension direction of the active portion is perpendicular to both the first direction and the second direction;

[0088] S320: forming a storage structure on a first side of the active portion; wherein the storage structure is connected to the active portion;

[0089] S330: etching the first conductive portion from the second side of the active portion to form a plurality of first conductive lines spaced apart along a first direction; wherein the second side and the first side are opposite to each other along the extending direction of the active portion.

[0090] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0091] Figures 4 to 13 This is a schematic diagram of a memory manufacturing process according to an embodiment of the present disclosure. Figure 3 、 Figures 4 to 13 The method for manufacturing the memory provided in the embodiment of the present disclosure is exemplarily described.

[0092] In step S310, refer to Figures 4 to 7 As shown, a base structure 410 is formed, which includes a plurality of active portions 402 arranged in an array along a first direction and a second direction and a plurality of first conductive portions 403' arranged at intervals along the second direction; each first conductive portion 403' extends along the first direction and covers the side walls of two adjacent rows of active portions 402; the first direction and the second direction intersect, and the extension direction of the active portion 402 is perpendicular to both the first direction and the second direction.

[0093] It should be noted that the first direction, the second direction and the extension direction of the active portion 402 used in the present disclosure are respectively represented as the x-direction, the y-direction and the z-direction in the accompanying drawings, the x-direction and the y-direction are parallel to the surface of the substrate 401, and the z-direction is perpendicular to the surface of the substrate 401. The x-direction and the y-direction intersect, and the angle between the x-direction and the y-direction includes an acute angle, a right angle or an obtuse angle, which will not be described in detail hereafter. In this example, the angle between the x-direction and the y-direction is a right angle, that is, the x-direction, the y-direction and the z-direction are perpendicular to each other. It can be understood that Figure 2 The row direction shown in may be the first direction, and the column direction may be the second direction.

[0094] The active portion 402 may include a first doped region, a channel, and a second doped region (not shown) arranged sequentially along the z-direction. The first doped region may be one of a source and a drain, and the second doped region may be the other of the source and the drain. It will be appreciated that the active portion 402 may serve as the active region of a transistor, with the first doped region of the active portion 402 connected to a bit line, and the second doped region of the active portion 402 connected to a memory structure.

[0095] The first conductive portion 403' is located between two adjacent rows of active portions 402, and covers the opposing sidewalls of the two adjacent rows of active portions 402. In one embodiment, the first conductive portion 403' covers the opposing sidewalls of the channels of the two adjacent rows of active portions 402. It will be appreciated that the first conductive portion 403' will be etched in subsequent processes to form the first conductive line 403, which can serve as a word line.

[0096] In one embodiment, referring to Figures 4 to 6 As shown, step S310 includes: providing a substrate 401; etching the substrate 401 from a first side of the substrate 401 to form a plurality of first trenches S1 spaced apart along a first direction (e.g., the x-direction); wherein each first trench S1 extends along a second direction (e.g., the y-direction) and has its bottom located in the substrate 401; forming an insulating material layer in the first trenches S1; etching the substrate 401 and the insulating material layer from the first side of the substrate 401 to form a plurality of second trenches S2 spaced apart along the second direction; wherein each second trench S2 extends along the first direction and has its bottom located in the substrate 401, and the depth of the second trench S2 is less than the depth of the first trench S1; the plurality of second trenches S2 and the plurality of first trenches S1 separate the substrate 401 into a plurality of active portions 402; and forming first conductive portions 403' in the second trenches S2. Here, depth refers to the dimension of the trench in the z-direction, and the remaining substrate 401 constitutes the substrate layer.

[0097] The material of the substrate 401 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0098] The formation process of the first trench S1 includes, but is not limited to, at least one of dry etching and wet etching. The etched substrate 401 includes a main body portion and a plurality of strip-shaped portions protruding from the main body portion. The strip-shaped portions extend in the same direction as the first trench S1, and the first trench S1 is located between two adjacent strip-shaped portions.

[0099] The insulating material layer includes a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating material layer may be formed by a thin film deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, and an atomic layer deposition process. In practical applications, the insulating material layer covering the surface of substrate 401 may also be removed by etching or planarization.

[0100] The second trench S2 is formed by, but is not limited to, at least one of dry etching and wet etching. The sidewalls of the second trench S2 expose the opposing sidewalls of two adjacent rows of active portions 402. Because the depth of the second trench S2 is less than that of the first trench S1, the bottom of the second trench S2 exposes the substrate 401 and the insulating material layer. Of course, in other embodiments, the depth of the second trench S2 can be equal to the depth of the first trench S1. In this case, the bottom of the second trench S2 only exposes the substrate 401.

[0101] The material of the first conductive portion 403' includes a conductive material, for example, at least one of tungsten, tantalum, titanium, nickel, platinum, titanium nitride, tungsten nitride, and tantalum nitride. Before forming the first conductive portion 403', a gate dielectric layer may be formed in the second trench S2 by oxidation or thin film deposition. The gate dielectric layer covers the surface of the exposed active portion 402 and is located between the active portion 402 and the first conductive portion 403'.

[0102] In this embodiment, a plurality of first trenches S1 extending along the second direction and a plurality of second trenches S2 extending along the first direction can be formed by etching the substrate 401, thereby dividing the substrate 401 into a plurality of active portions 402. The active portions 402 can serve as active regions of transistors. In this way, a plurality of vertical transistors can be formed, which is beneficial to improving the integration level.

[0103] In some embodiments, reference Figures 4 to 7 As shown, step S310 further includes: etching the substrate 401 and the insulating material layer from the first side of the substrate 401 to form a plurality of third trenches S3 spaced apart along the second direction; wherein each third trench S3 extends along the first direction and is located between two adjacent second trenches S2, and the depth of the third trench S3 is less than the depth of the first trench S1; and forming a second conductive portion 404' in the third trench S3. The formation process of the third trench S3 includes, but is not limited to, at least one of dry etching and wet etching. The material of the second conductive portion 404' includes a conductive material, for example, at least one of tungsten, tantalum, titanium, nickel, platinum, titanium nitride, tungsten nitride, and tantalum nitride. Figure 7 FIG shows a top view after forming the first conductive portion 403 ′ and the second conductive portion 404 ′. For ease of understanding, Figure 7The isolation structure, insulating material and top spacer layer are omitted.

[0104] In this embodiment, a third trench S3 is formed by etching the substrate 401 and the insulating material layer. The third trench S3 divides an active portion 402 between two adjacent second trenches S2 into a pair of active pillars, namely a first active pillar 4021 and a second active pillar 4022. Figure 5 As shown, the first active pillars 4021 and the second active pillars 4022 are arranged at intervals along the second direction. Figure 5 Can be along Figure 4 It is obtained by cutting open the position of the dotted line AA'.

[0105] In this embodiment, the third trench S3 and the second trench S2 can be etched simultaneously, and the depth of the third trench S3 is substantially equal to the depth of the second trench S2. Of course, in other embodiments, the third trench S3 and the second trench S2 can be etched sequentially, and the depth of the third trench S3 and the depth of the second trench S2 can be the same or different. It should be noted that the term "substantially equal" as used in this disclosure can mean completely equal or there can be a deviation between the two, but the deviation is within the tolerance range allowed by the process.

[0106] In this embodiment, by filling the third trench S3 with a conductive material, a plurality of second conductive portions 404' spaced apart along the second direction can be formed. Figure 5 As shown, each second conductive portion 404' extends along the first direction and covers the opposing sidewalls of the first active pillar 4021 and the second active pillar 4022. The second conductive portion 404' will be etched in a subsequent process to form a second conductive line 404. The second conductive line 404 can serve as the back gate of the transistor, which can better control the electrical parameters of the transistor. In practical applications, the conductive material on the sidewalls of the second doped region can also be removed by etching, and a top spacer layer is formed at the location where the conductive material is removed. The top spacer layer is used to isolate the second doped region from the gate of the transistor.

[0107] Of course, in other embodiments, the base structure 410 formed in the above step S310 can also be directly provided to perform the following step S320. The provided base structure 410 can be similar to the base structure 410 formed by etching the substrate 401 in the above embodiment, and will not be repeated here.

[0108] In step S320, a storage structure (not shown) is formed on the first side of the active portion 402, and the storage structure is connected to the active portion 402. In a specific example, the storage structure may include a capacitor, and one electrode plate of the capacitor is connected to the second doped region. The capacitor can have various structures, and illustratively, the capacitor includes a cup capacitor, a cylindrical capacitor, or a columnar capacitor. Of course, the storage structure can also be a phase change storage structure or a ferroelectric storage structure.

[0109] In some embodiments, the base structure 410 also includes a substrate layer, which is located on the second side; the above-mentioned manufacturing method also includes: bonding the base structure 410 and the carrier substrate 430 so that the storage structure is located between the base structure 410 and the carrier substrate 430; removing the substrate 401 layer from the side of the base structure 410 relatively away from the carrier substrate 430 until the active part 402 is exposed.

[0110] For example, after forming the storage structure, the base structure 410 with the storage structure formed thereon can be bonded to the carrier substrate 430. After bonding, the storage structure is located between the base structure 410 and the carrier substrate 430. The bonded base structure 410 and the carrier substrate 430 are then inverted so that the substrate layer faces upward. The substrate layer can be removed by etching or planarization to expose the active portion 402. In this example, before bonding, a protective layer 420 covering the storage structure can also be formed, such as Figure 6 As shown, the protective layer 420 is used to protect the formed structure (eg, the base structure 410, the storage structure, etc.). Figure 6 The storage structure is not shown.

[0111] In step S330, refer to Figures 7 to 12 As shown, the first conductive portion 403' is etched from the second side of the active portion 402 to form a plurality of first conductive lines 403 spaced apart along the first direction, with the second side and the first side facing each other along the extending direction of the active portion 402. One of the plurality of first conductive lines 403 spaced apart along the first direction corresponds to a word line of a memory array tile MAT (e.g., Figure 5 or Figure 7 The memory includes multiple memory array slices, each of which can be powered on and off independently to perform independent logical operations such as reading and writing.

[0112] It can be understood that in this embodiment, by etching the first conductive portion 403' from the second side of the active portion 402, a plurality of first conductive lines 403 arranged at intervals along the first direction are formed. The first conductive lines 403 can be used as word lines, thereby concentrating the processing of the word lines on one side of the substrate 401 (i.e., the second side), which is conducive to simplifying the manufacturing process and reducing the process difficulty and process cost.

[0113] In some embodiments, combined Figure 8 and Figure 11As shown, the first conductive portion 403' covers the sidewalls of the channels and first doped regions of two adjacent rows of active portions 402, with the channels located between the second doped regions and the first doped regions of the active portions 402. The above-mentioned fabrication method further includes removing the first conductive portion 403' from the second side, which covers the sidewalls of the first doped regions of the two adjacent rows of active portions 402, before etching the first conductive portion 403'. In practical applications, the portion where the first conductive portion 403' was removed may be filled with a dielectric material to isolate the first doped region from the transistor gate.

[0114] In this embodiment, a first conductive portion 403' can be formed in the second trench S2, covering the sidewalls of the channels and first doped regions of two adjacent rows of active portions 402. Exemplarily, a conductive material is filled into the second trench S2, where a gate dielectric layer is formed, to cover the gate dielectric layer. The conductive material is then etched back until the conductive material on the gate dielectric layer located on the sidewalls of the second doped regions is removed, with the conductive material remaining in the second trench forming the first conductive portion 403'. Before etching the first conductive portion 403', the first conductive portion 403' covering the sidewalls of the first doped regions of the two adjacent rows of active portions 402 is removed from the second side, exposing the first conductive portion 403' covering the sidewalls of the channels of the two adjacent rows of active portions 402. Etching the first conductive portion 403' covering the sidewalls of the channels of the two adjacent rows of active portions 402 can then divide the first conductive portion 403' into a plurality of word lines spaced apart along the first direction, i.e., the division of the word lines is concentrated on one side of the substrate 401.

[0115] In some embodiments, reference Figure 5 As shown, the above-mentioned manufacturing method further includes: filling the second trench S2 formed with the first conductive portion 403' with an isolation material to form an isolation structure 405. The extension direction of the isolation structure 405 can be the same as the extension direction of the second trench S2. It can be understood that after removing the first conductive portion 403' covering the sidewalls of the first doped regions of the two adjacent rows of active portions 402, a pair of sub-conductive portions, namely the first sub-conductive portion 4031' and the second sub-conductive portion 4032', can be formed in the second trench. The first sub-conductive portion 4031' is located between the second conductive portion 404' and the second sub-conductive portion 4032', as shown in FIG. Figure 8 As shown, the isolation structure 405 is located between the first sub-conductive portion 4031 ′ and the second sub-conductive portion 4032 ′.

[0116] In other embodiments, the first conductive portion 403' covers the sidewalls of the channel of two adjacent rows of active portions 402; the base structure 410 further includes a bottom spacer layer (not shown in the figure), which is located between the two adjacent rows of active portions 402 and covers the sidewalls of the first doped regions of the two adjacent rows of active portions 402, and the channel is located between the second doped region and the first doped region of the active portion 402; the above-mentioned manufacturing method further includes: before etching the first conductive portion 403', removing the bottom spacer layer from the second side until the first conductive portion 403' is exposed.

[0117] In this embodiment, a bottom spacer layer can be formed in the second trench S2, covering the sidewalls of the first doped regions of two adjacent rows of active portions 402. Exemplarily, a bottom spacer material is filled into the second trench having a gate dielectric layer formed therein, the bottom spacer material covering the gate dielectric layer. The bottom spacer material is etched back until the bottom spacer material on the gate dielectric layer located on the second doped regions and the trench sidewalls is removed, with the remaining bottom spacer material in the second trench constituting the bottom spacer layer. A first conductive portion 403' is formed in the second trench S2 having the bottom spacer layer formed therein, the first conductive portion 403' being located above the bottom spacer layer. Before etching the first conductive portion 403', the bottom spacer layer is removed from the second side, exposing the first conductive portion 403'. The exposed first conductive portion 403' is then etched to divide the first conductive portion 403' into a plurality of word lines spaced apart along the first direction, i.e., the division of the word lines is concentrated on one side of the substrate 401.

[0118] In some embodiments, reference Figure 11 and Figure 12 As shown, the manufacturing method further includes: etching the second conductive portion 404 ′ from the second side to form a plurality of second conductive lines 404 spaced apart along the first direction; wherein the plurality of first conductive lines 403 and the plurality of second conductive lines 404 are alternately arranged along the second direction.

[0119] In this embodiment, a second conductive portion 404' is etched from the second side of the active portion 402 to form a plurality of second conductive lines 404 spaced apart along the first direction. The second conductive lines 404 can serve as back gates, thereby concentrating the back gate processing on one side of the substrate 401 (i.e., the second side), which is conducive to further simplifying the manufacturing process and reducing the process difficulty and cost.

[0120] In some embodiments, the second conductive portion 404' and the first conductive portion 403' are etched simultaneously, thereby simplifying the manufacturing process. Of course, in other embodiments, the second conductive portion 404' and the first conductive portion 403' can be etched sequentially, and this disclosure has no particular limitation on this.

[0121] For example, a mask layer 440 is formed on the second side of the active portion 402, as shown in FIG. Figure 8The mask layer 440 is patterned to form a patterned mask layer 440, the patterned mask layer 440 includes a first mask pattern 451, the position of the first mask pattern 451 is as shown Figure 9 As shown, Figure 9 The top view after forming the patterned mask layer is shown; the first conductive portion 403' and the second conductive portion 404' are etched with the patterned mask layer 440 as an etching mask to form a plurality of first isolation trenches 452. The positions of the first isolation trenches 452 are as shown in FIG. Figure 10 As shown; a first isolation portion 450 is formed in the first isolation trench 452, and the position of the first isolation portion 450 is as shown Figure 12 It can be understood that the first isolation trench 452 (or the first isolation portion 450) divides the first conductive portion 403' into a plurality of first conductive lines 403, and divides the second conductive portion 404' into a plurality of second conductive lines 404. The patterning process includes photolithography and etching processes.

[0122] In this embodiment, since the first conductive portion 403' and the second conductive portion 404' are etched simultaneously, the first conductive portion 403' and the second conductive portion 404' can be designed using the same mask (also called a mask), which is beneficial to reducing the number of masks required for manufacturing the memory, thereby reducing process costs.

[0123] In some embodiments, reference Figures 8 to 11 As shown, the above-mentioned manufacturing method further includes: forming a plurality of third conductive portions 406' arranged at intervals along the first direction on the second side; wherein each third conductive portion 406' extends along the second direction and is connected to the active portion 402 located in the same column; and etching the third conductive portions 406' from the second side to form a plurality of third conductive lines 406 arranged at intervals along the second direction. Here, the third conductive lines 406 can serve as bit lines.

[0124] The third conductive portion 406' is located on the second side of the active portion 402 and is connected to the active portion 402 located in the same column. In one embodiment, the third conductive portion 406' is connected to the first doped region of the active portion 402 located in the same column. The material of the third conductive portion 406' includes a conductive material, such as at least one of tungsten, tantalum, titanium, nickel, platinum, titanium nitride, tungsten nitride, and tantalum nitride.

[0125] It can be understood that in this embodiment, by etching the third conductive portion from the second side of the active portion 402, a plurality of third conductive lines arranged at intervals along the second direction are formed. The third conductive lines can be used as bit lines, thereby concentrating the processing of word lines and bit lines on one side of the substrate 401 (i.e., the second side), which is conducive to further simplifying the manufacturing process, reducing the process difficulty and process cost.

[0126] In some embodiments, the third conductive portion 406' and the first conductive portion 403' are etched simultaneously, thereby simplifying the manufacturing process. Of course, in other embodiments, the third conductive portion 406' and the first conductive portion 403' can be etched sequentially, and this disclosure has no particular limitation on this.

[0127] In a specific embodiment, the first conductive portion 403 ′, the second conductive portion 404 ′ and the third conductive portion are all etched simultaneously.

[0128] Exemplarily, the patterned mask layer 440 further includes a second mask pattern 461, and the position of the second mask pattern 461 is as follows: Figure 9 The patterned mask layer 440 is used as an etching mask to etch the third conductive portion 406 'to form a plurality of second isolation trenches 462, the positions of the second isolation trenches 462 are as shown; Figure 10 As shown; a second isolation portion 460 is formed in the second isolation trench 462, and the position of the second isolation portion 460 is as shown Figure 12 As shown. It is understandable that the second isolation trench 462 (or the second isolation portion 460) divides the third conductive portion 406' into a plurality of third conductive lines 406. It should be noted that since the third conductive portion 406' is blocked by the active portion in the top view, Figure 10 The third conductive portion 406' is not shown. Figure 10 The second isolation trench 462 is only shown for illustration and is used to understand the position of the second isolation trench 462 .

[0129] In this embodiment, since the first conductive portion 403', the second conductive portion 404' and the third conductive portion 406' are all etched simultaneously, the first conductive portion 403', the second conductive portion 404' and the third conductive portion 406' can be designed using the same mask, which is beneficial to further reduce the number of masks required for manufacturing the memory, thereby reducing process costs.

[0130] In some embodiments, the base structure 410 further includes a plurality of insulating structures, and the insulating structures are located between two adjacent columns of active portions 402. The above-mentioned formation of the third conductive portion 406' on the second side of the active portion 402 includes: forming a conductive material layer covering the plurality of active portions 402 and the plurality of insulating structures on the second side; performing heat treatment on the conductive material layer; wherein, during the heat treatment, the conductive material layer reacts with the active portion 402; removing the conductive material layer that has not reacted with the active portion 402, and the remaining conductive material layer constitutes the third conductive portion 406'.

[0131] In this embodiment, the insulating structure between two adjacent columns of active portions 402 can be the insulating material layer retained in the first trench after the second trench S2 is formed in the above-mentioned embodiment. It can be understood that after removing the substrate 401 layer, the insulating structure can also be exposed while exposing the active portion 402. By forming a conductive material layer covering multiple active portions 402 and multiple insulating structures, and performing a heat treatment on the conductive material layer, during the heat treatment process, the conductive material layer reacts with the active portion 402 to form a metal silicide, which can serve as the third conductive portion 406'. After the heat treatment, the unreacted conductive material layer is removed to obtain the third conductive portion 406', thereby forming the third conductive portion 406' without the need for alignment exposure. That is, in the embodiment of the present disclosure, by depositing a conductive material layer and performing a heat treatment on the conductive material layer, a self-aligned bit line can be formed, which is beneficial to improving the alignment accuracy between the bit line and the active portion 402.

[0132] In some embodiments, reference Figure 11 and Figure 12 As shown, step S330 includes: etching a first sub-conductive portion 4031' from the second side of the active portion 402 to form a plurality of first sub-conductive lines 4031 spaced apart along the first direction; and etching a second sub-conductive portion 4032' from the second side of the active portion 402 to form a plurality of second sub-conductive lines 4032 spaced apart along the first direction. It will be understood that a second trench includes first sub-conductive lines 4031 and second sub-conductive lines 4032 spaced apart along the second direction, and the isolation structure 405 is located in the space between the first sub-conductive lines 4031 and the second sub-conductive lines 4032 and extends along the first direction.

[0133] In this embodiment, by etching the first sub-conductive portion 4031' and the second sub-conductive portion 4032', a pair of word lines, namely, the first sub-conductive line 4031 and the second sub-conductive line 4032, can be formed in a second trench. The first sub-conductive line 4031 is located between the second conductive line 404 and the second sub-conductive line 4032. The first sub-conductive line 4031 covers the sidewall of the first active pillar 4021 that is relatively far from the second conductive line 404, and the second sub-conductive line 4032 covers the sidewall of the second active pillar 4022 that is relatively far from the second conductive line 404. This can increase the density of transistors, thereby integrating more memory cells and improving the integration level of the memory.

[0134] In some embodiments, reference Figure 13As shown, the above-mentioned manufacturing method also includes: forming a first contact plug 471 connected to the first sub-conductive line 4031; wherein the first contact plug 471 is located on a side of the first sub-conductive line 4031 relatively away from the storage structure; forming a second contact plug 472 connected to the second sub-conductive line 4032; wherein the second contact plug 472 is located on a side of the second sub-conductive line 4032 relatively away from the storage structure; the second contact plug 472 and the first contact plug 471 are respectively located at two opposite ends along the first direction.

[0135] Illustratively, a dielectric layer can be formed on the second side of the active portion 402 through a thin film deposition process, the dielectric layer covering the active portion 402, the first conductive line 403, the second conductive line 404 and other structures; a first contact hole and a second contact hole are formed through the dielectric layer by etching, the first contact hole exposing a portion of the first sub-conductive line 4031, and the second contact hole exposing a portion of the second sub-conductive line 4032; a first contact plug 471 and a second contact plug 472 are formed in the first contact hole and the second contact hole, respectively.

[0136] In this embodiment, the first contact plug 471 is used to electrically lead the first sub-conductive line 4031, and the second contact plug 472 is used to electrically lead the second sub-conductive line 4032. Both the first contact plug 471 and the second contact plug 472 are formed on the second side of the active portion 402. In this way, the word line segmentation and lead-out can be concentrated on one side of the substrate 401 (i.e., the second side). This not only simplifies the manufacturing process and reduces the process difficulty, but also increases opportunities for cost reduction, facilitates process integration, and further reduces process costs. In addition, because the first contact plug 471 and the second contact plug 472 are located at opposite ends along the first direction, the first contact plug 471 and the second contact plug 472 can be staggered, thereby increasing the process window for the first contact plug 471 and the second contact plug 472 and improving alignment accuracy.

[0137] In some embodiments, reference Figure 13 As shown, the above-mentioned manufacturing method further includes: forming a third contact plug 473 connected to the second conductive line 404; wherein the third contact plug 473 is located on a side of the second conductive line 404 relatively far from the memory structure; the third contact plug 473 and the second contact plug 472 are located at the same end opposite to each other in the first direction. Exemplarily, a third contact hole can be formed through the dielectric layer by etching, the third contact hole exposing a portion of the second conductive line 404; and the third contact plug 473 is formed in the third contact hole.

[0138] In this embodiment, the third contact plug 473 is used to electrically lead the second conductive line 404. The third contact plug 473 can also be formed on the second side of the active portion 402. In this way, the back gate segmentation and lead-out can be concentrated on one side of the substrate 401 (i.e., the second side). This not only simplifies the manufacturing process and reduces the process difficulty, but also facilitates process integration, which helps to further reduce process costs. In addition, because the third contact plug 473 and the second contact plug 472 are located at the same end opposite to each other in the first direction, the third contact plug 473 and the first contact plug 471 can be located at opposite ends in the first direction, respectively. The third contact plug 473 and the first contact plug 471 can be staggered, thereby increasing the process window of the third contact plug 473 and the first contact plug 471 and improving alignment accuracy.

[0139] In some embodiments, reference Figure 13 As shown, the above-mentioned manufacturing method further includes: forming a fourth contact plug 474 connected to the third conductive line 406; wherein the fourth contact plug 474 is located on a side of the third conductive line 406 relatively far from the active portion 402; and the fourth contact plugs 474 corresponding to two third conductive lines 406 adjacent in the first direction are respectively located at opposite ends in the second direction. Exemplarily, a fourth contact hole can be formed through the dielectric layer by etching, the fourth contact hole exposing a portion of the third conductive line 406; and the fourth contact plug 474 is formed in the fourth contact hole.

[0140] In this embodiment, the fourth contact plug 474 is used to electrically lead the third conductive line 406. The fourth contact plug 474 can also be formed on the second side of the active portion 402. In this way, the bit line segmentation and lead-out can be concentrated on one side of the substrate 401 (i.e., the second side). This not only simplifies the manufacturing process and reduces the process difficulty, but also facilitates process integration, which helps to further reduce process costs. In addition, because the fourth contact plugs 474 corresponding to two third conductive lines 406 adjacent in the first direction are located at opposite ends in the second direction, multiple fourth contact plugs 474 can be staggered, which increases the process window of the fourth contact plugs 474 and improves alignment accuracy.

[0141] Based on the above-mentioned memory manufacturing method, the present disclosure provides a memory, combined with Figure 12 and Figure 13 As shown, the memory includes multiple storage array slices; the storage array slices include:

[0142] A plurality of active portions 402 are arranged in an array along a first direction and a second direction; wherein the first direction and the second direction intersect, and an extension direction of the active portion 402 is perpendicular to both the first direction and the second direction;

[0143] A plurality of first conductive lines 403 are arranged at intervals along the second direction; wherein each first conductive line 403 extends along the first direction and covers the sidewalls of two adjacent rows of active portions 402 in the memory array;

[0144] a storage structure located on a first side of the active portion 402 and connected to the active portion 402;

[0145] The first conductive lines 403 in the same row of two adjacent memory array chips are arranged at intervals along the first direction.

[0146] In some embodiments, the active portion 402 includes a first active pillar 4021 and a second active pillar 4022 spaced apart along the second direction; the memory array chip further includes:

[0147] A plurality of second conductive lines 404 are arranged at intervals along the second direction; wherein each second conductive line 404 extends along the first direction and covers two opposite side walls of the first active pillar 4021 and the second active pillar 4022 in the memory array; the plurality of first conductive lines 403 and the plurality of second conductive lines 404 are alternately arranged along the second direction;

[0148] The second conductive lines 404 located in the same row in two adjacent memory array slices are arranged at intervals along the first direction.

[0149] In some embodiments, the first conductive line 403 includes first sub-conductive lines 4031 and second sub-conductive lines 4032 spaced apart from each other along the second direction; the memory array chip further includes:

[0150] A first contact plug 471 is located on a side of the first sub-conductive line 4031 relatively far from the memory structure and is connected to the first sub-conductive line 4031;

[0151] A second contact plug 472 is located on a side of the second sub-conductive line 4032 relatively away from the memory structure and is connected to the second sub-conductive line 4032; wherein the second contact plug 472 and the first contact plug 471 are respectively located at two opposite ends along the first direction;

[0152] The isolation structure 405 is located in the space between the first sub-conductive line 4031 and the second sub-conductive line 4032 and extends along the first direction.

[0153] In some embodiments, the first sub-conductive line 4031 is located between the second conductive line 404 and the second sub-conductive line 4032; the memory array chip further includes:

[0154] The third contact plug 473 is located on a side of the second conductive line 404 relatively far from the storage structure and is connected to the second conductive line 404 . The third contact plug 473 and the second contact plug 472 are located at the same end opposite to each other along the first direction.

[0155] In some embodiments, the storage array slice further includes:

[0156] A plurality of third conductive lines 406 are located on the second side of the active portion 402 and are spaced apart along the first direction; wherein each third conductive line 406 extends along the second direction and is connected to an active portion 402 located in the same column of the memory array; and the second side and the first side are opposite to each other along the extension direction of the active portion 402;

[0157] The third conductive lines 406 located in the same column in two adjacent memory array chips are arranged at intervals along the second direction.

[0158] In some embodiments, the storage array slice further includes:

[0159] The fourth contact plug 474 is located on a side of the third conductive line 406 relatively away from the active portion 402 and connected to the third conductive line 406 . The fourth contact plugs 474 corresponding to two third conductive lines 406 adjacent in the first direction are located at opposite ends in the second direction.

[0160] In some embodiments, the memory includes dynamic random access memory, ferroelectric memory, or phase change memory.

[0161] Based on the above memory, an embodiment of the present disclosure provides a memory system, including:

[0162] One or more memories as in any of the above embodiments;

[0163] A controller is coupled to the memory and configured to control the memory.

[0164] The memory can correspond to the reference Figure 1 The memory 20 in the embodiment shown and Figure 10 The memory in the illustrated embodiment will not be further described herein regarding the functions, applications, and interactions between the memory 20 and the controller 10 .

[0165] Based on the above memory system, an embodiment of the present disclosure provides an electronic device, including: the memory system in the above embodiment.

[0166] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0167] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0168] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0169] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0170] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a memory, characterized in that: include: Forming a base structure; wherein the base structure includes a plurality of active portions arranged in an array along a first direction and a second direction, and a plurality of first conductive portions arranged at intervals along the second direction; each of the first conductive portions extends along the first direction and covers sidewalls of two adjacent rows of active portions; the first direction and the second direction intersect, and the extension direction of the active portion is perpendicular to both the first direction and the second direction; forming a storage structure on a first side of the active portion; wherein the storage structure is connected to the active portion; The first conductive portion is etched from the second side of the active portion to form a plurality of first conductive lines spaced apart along the first direction; wherein the second side and the first side are opposite to each other along the extending direction of the active portion.

2. The production method according to claim 1, characterized in that The active portion includes a first active pillar and a second active pillar arranged at intervals along the second direction; the base structure further includes a plurality of second conductive portions arranged at intervals along the second direction, each of the second conductive portions extending along the first direction and covering two opposite side walls of the first active pillar and the second active pillar; The production method further comprises: The second conductive portion is etched from the second side to form a plurality of second conductive lines arranged at intervals along the first direction; wherein the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged along the second direction.

3. The production method according to claim 2, characterized in that: The first conductive line includes a first sub-conductive line and a second sub-conductive line spaced apart along the second direction; the base structure further includes an isolation structure, the isolation structure being located in the space between the first sub-conductive line and the second sub-conductive line and extending along the first direction; the manufacturing method further includes: forming a first contact plug connected to the first sub-conductive line; wherein the first contact plug is located on a side of the first sub-conductive line relatively far from the storage structure; A second contact plug connected to the second sub-conductive line is formed; wherein the second contact plug is located on a side of the second sub-conductive line relatively far away from the storage structure; the second contact plug and the first contact plug are respectively located at two opposite ends along the first direction.

4. The production method according to claim 3, characterized in that: The first sub-conductive line is located between the second conductive line and the second sub-conductive line; the manufacturing method further includes: A third contact plug connected to the second conductive line is formed; wherein the third contact plug is located on a side of the second conductive line relatively far from the storage structure; and the third contact plug and the second contact plug are located at the same end opposite to each other along the first direction.

5. The production method according to claim 2, characterized in that: The second conductive portion and the first conductive portion are etched simultaneously.

6. The production method according to claim 1, characterized in that: The production method further comprises: A plurality of third conductive portions are formed on the second side and arranged at intervals along the first direction; wherein each of the third conductive portions extends along the second direction and is connected to the active portion located in the same column; The third conductive portion is etched from the second side to form a plurality of third conductive lines spaced apart along the second direction.

7. The production method according to claim 6, characterized in that: The third conductive portion and the first conductive portion are etched simultaneously.

8. The manufacturing method according to claim 6, characterized in that: The production method further comprises: A fourth contact plug connected to the third conductive line is formed; wherein the fourth contact plug is located on a side of the third conductive line relatively far away from the active portion; and the fourth contact plugs corresponding to two adjacent third conductive lines along the first direction are respectively located at two opposite ends along the second direction.

9. The manufacturing method according to claim 6, characterized in that: The base structure further includes a plurality of insulating structures, wherein the insulating structures are located between two adjacent columns of active portions; and the third conductive portion is formed on the second side of the active portion, comprising: forming a conductive material layer covering the plurality of active portions and the plurality of insulating structures on the second side; performing a heat treatment on the conductive material layer; wherein, during the heat treatment, the conductive material layer reacts with the active portion; The conductive material layer that has not reacted with the active portion is removed, and the remaining conductive material layer constitutes the third conductive portion.

10. The manufacturing method according to claim 1, characterized in that: The base structure further includes a substrate layer, and the substrate layer is located on the second side; the manufacturing method further includes: Bonding the base structure and the carrier substrate so that the storage structure is located between the base structure and the carrier substrate; The substrate layer is removed from a side of the base structure relatively away from the carrier substrate until the active portion is exposed.

11. The production method according to claim 1, characterized in that: The first conductive portion covers the sidewalls of the channels and the first doped regions of two adjacent rows of active portions, and the channels are located between the second doped regions and the first doped regions of the active portions; the manufacturing method further includes: Before etching the first conductive portion, the first conductive portion covering the sidewalls of the first doped regions of two adjacent rows of active portions is removed from the second side.

12. The manufacturing method according to claim 1, characterized in that: The first conductive portion covers the sidewalls of the trenches of two adjacent rows of active portions; the base structure further includes a bottom spacer layer, the bottom spacer layer is located between the two adjacent rows of active portions and covers the sidewalls of the first doped regions of the two adjacent rows of active portions, and the trench is located between the second doped region and the first doped region of the active portions; the manufacturing method further includes: Before etching the first conductive portion, the bottom spacer layer is removed from the second side until the first conductive portion is exposed.

13. The manufacturing method according to claim 1, characterized in that: The forming of the base structure comprises: providing a substrate; Etching the substrate from a first side of the substrate to form a plurality of first trenches spaced apart along the first direction; wherein each of the first trenches extends along the second direction and has a bottom located in the substrate; forming an insulating material layer in the first trench; Etching the substrate and the insulating material layer from the first side of the substrate to form a plurality of second trenches spaced apart along the second direction; wherein each second trench extends along the first direction and has a bottom located in the substrate, and a depth of the second trench is less than a depth of the first trench; the plurality of second trenches and the plurality of first trenches separate the substrate into the plurality of active portions; The first conductive portion is formed in the second trench.

14. A memory, characterized in that: The memory includes a plurality of memory array slices; the memory array slices include: A plurality of active portions are arranged in an array along a first direction and a second direction; wherein the first direction and the second direction intersect, and an extension direction of the active portion is perpendicular to both the first direction and the second direction; a plurality of first conductive lines arranged at intervals along the second direction; wherein each of the first conductive lines extends along the first direction and covers side walls of two adjacent rows of active portions in the memory array; a storage structure located on a first side of the active portion and connected to the active portion; The first conductive lines located in the same row in two adjacent memory array slices are arranged at intervals along the first direction.

15. The memory according to claim 14, wherein: The active portion includes a first active pillar and a second active pillar spaced apart along the second direction; the memory array chip further includes: a plurality of second conductive lines arranged at intervals along the second direction; wherein each second conductive line extends along the first direction and covers two opposite side walls of the first active pillar and the second active pillar in the memory array; the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged along the second direction; The second conductive lines located in the same row in two adjacent memory array slices are arranged at intervals along the first direction.

16. The memory according to claim 15, wherein: The first conductive line includes a first sub-conductive line and a second sub-conductive line arranged at intervals along the second direction; the memory array chip further includes: a first contact plug, located on a side of the first sub-conductive line relatively far from the storage structure and connected to the first sub-conductive line; a second contact plug, located on a side of the second sub-conductive line relatively away from the storage structure and connected to the second sub-conductive line; wherein the second contact plug and the first contact plug are respectively located at two opposite ends along the first direction; The isolation structure is located in the space between the first sub-conductive line and the second sub-conductive line and extends along the first direction.

17. The memory according to claim 16, wherein: The first sub-conductive line is located between the second conductive line and the second sub-conductive line; the memory array chip further includes: The third contact plug is located on a side of the second conductive line relatively away from the storage structure and is connected to the second conductive line; wherein the third contact plug and the second contact plug are located at the same end opposite to each other along the first direction.

18. The memory according to claim 14, wherein: The storage array chip further includes: a plurality of third conductive lines located on a second side of the active portion and spaced apart along the first direction; wherein each of the third conductive lines extends along the second direction and is connected to the active portion located in the same column of the memory array; and the second side and the first side are opposite to each other along the extension direction of the active portion; The third conductive lines located in the same column of two adjacent memory array slices are arranged at intervals along the second direction.

19. The memory according to claim 18, wherein: The storage array chip further includes: The fourth contact plug is located on a side of the third conductive line relatively away from the active portion and connected to the third conductive line; wherein the fourth contact plugs corresponding to two adjacent third conductive lines along the first direction are respectively located at two opposite ends along the second direction.

20. The memory according to claim 14, wherein The memory includes: dynamic random access memory, ferroelectric memory or phase change memory.

21. A memory system, characterized in that: include: One or more memories according to any one of claims 14 to 20; A controller is coupled to the memory and configured to control the memory.

22. An electronic device, characterized in that: include: The memory system of claim 21.

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