Formation method of semiconductor device
By accurately testing the etching rate of the polysilicon layer during the formation of semiconductor devices, the problems of substandard wordline sidewall height and polysilicon residue are solved, thereby improving the quality and reliability of the device.
Patent Information
- Application Number
- CN202510724693.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-05
AI Technical Summary
In the prior art, the etching rate control of the wordline material layer of semiconductor devices is inaccurate, resulting in substandard wordline sidewall height or polysilicon residue, premature failure or column crosstalk problems, and affecting device quality.
By forming an oxide layer and a polysilicon layer on the surface of the substrate in the device area and the logic area, and forming a patterned photoresist layer on the surface of the polysilicon layer, the polysilicon layer is etched to obtain the etching rate to form the word line sidewall. The etching rate of the polysilicon layer is used to accurately test the etching rate of the word line material layer to ensure that the word line sidewall height meets the standard and avoid polysilicon residue.
The method achieves accurate testing of the etching rate of the word line material layer, forms highly qualified word line sidewalls, improves the quality of semiconductor devices, avoids polysilicon residue, and enhances the reliability and yield of the devices.
Smart Images
Figure CN120603243A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device. Background Art
[0002] Please refer to Figure 1 and Figure 2 The semiconductor device includes a device area A and a logic area B adjacent to each other, with functional devices formed in the device area. Logic devices are formed on the substrate of the logic area. Multiple functional devices can be formed simultaneously on the wafer in the entire device area A. The functional devices include a gate structure formed on the surface of the wafer. The gate structure includes a gate oxide layer 102, a floating gate layer 103, a first sidewall 104, a source line 105, a second sidewall 106, and a third sidewall 107 sequentially located on the surface of the wafer 101. A source line opening is formed in the gate oxide layer 102, the floating gate layer 103, and the first sidewall 104. The source line 105 is located in the source line opening. The source line 105 is separated from the gate oxide layer 102, the floating gate layer 103, and the inner wall of the first sidewall 104 by the second sidewall 106. The third sidewall 107 covers the outer wall of the gate oxide layer 102, the floating gate layer 103, and the sidewalls of the first sidewall 104. A wordline material layer 108 is formed on the surface of the wafer 101 and the surface of the gate structure, and the wordline material layer 108 is etched to form wordline sidewalls 109. The wordline sidewalls 109 are located on the surface of the wafer 101 on both sides of the gate structure. Then, source and drain regions 110 are formed in the wafer 101 outside the wordline sidewalls 109. The source and drain regions 110 are used for subsequent connection to form bit lines. While forming the functional devices in the logic area, multiple logic devices are formed on the wafer 101 in the logic area B. For example, the logic gate 111 of the wafer located in the logic area and the fourth sidewalls 112 located on both sides of the logic gate 111. When etching the wordline material layer to form the wordline sidewalls, it is very important to control the etching rate. Otherwise, excessive etching or incomplete etching will occur, ultimately resulting in the wordline sidewall height not meeting the standard or the occurrence of defects such as polysilicon residue.
[0003] The conventional method for testing the etch rate of a wordline material layer involves providing a circular wafer. An oxide layer, which can be formed by depositing silicon dioxide, is formed on the surface of the wafer. A polysilicon layer is then deposited on the surface of the oxide layer, and the thickness of the polysilicon layer is measured. Next, the polysilicon layer is etched using an etching machine, and the etching time is recorded. The thickness of the polysilicon layer after etching is then measured, and the etch rate is calculated based on the thickness of the polysilicon layer after etching, the thickness of the polysilicon layer before etching, and the etching time.
[0004] However, during yield testing, some semiconductor devices were found to exhibit the following defects: some devices in the middle region of the wafer experienced premature failure, while others in the edge region of the wafer exhibited column crosstalk. Analysis revealed that the wordline sidewall height in the middle region of the wafer did not meet the standard, while that in the edge region met the standard. This was due to the etch rate of the wordline material layer in the middle region being higher than that in the edge region. The column crosstalk problem in devices at the edge of the wafer was caused by incomplete etching of the wordline material layer on the substrate surface in the bitline region, or source and drain regions, resulting in polysilicon residue. This is because the etch rate of the wordline material layer at the edge region is higher than that in the middle region. Therefore, it is necessary to accurately measure the etch rate of the wordline material layer of semiconductor devices to prevent defects such as a batch of semiconductor devices having a higher etch rate of the wordline material layer in the middle region than in the edge region. This is the case in some batches of devices where the etch rate of the wordline material layer at the edge region is higher than that in the middle region. If the actual etching rate of the word line material layer cannot be accurately measured, the above-mentioned defective semiconductor devices may occur. Summary of the Invention
[0005] The object of the present invention is to provide a method for forming a semiconductor device, which can accurately test the etching rate of the word line material layer, thereby forming a highly qualified word line sidewall and having no polysilicon residue on the surface of the substrate in the source and drain regions, thereby improving the quality of the semiconductor device.
[0006] In order to achieve the above object, the present invention provides a method for forming a semiconductor device, comprising:
[0007] Providing a first substrate, and dividing the first substrate into a device area and a logic area adjacent to each other using a layout of a split-gate memory;
[0008] forming an oxide layer and a polysilicon layer in sequence on the surface of the first substrate in the device area and the logic area;
[0009] forming a patterned photoresist layer on the surface of the polysilicon layer, wherein the patterned photoresist layer covers the photoresist layer of the logic area;
[0010] Etching the polysilicon layer in the device region and obtaining an etching rate of the polysilicon layer;
[0011] Providing a second substrate, and dividing the second substrate into a device area and a logic area adjacent to each other using a layout of a split-gate memory;
[0012] A gate structure is formed on the surface of the second substrate in the device region, the gate structure comprising a gate oxide layer, a floating gate layer, a first spacer, a source line, a second spacer, and a third spacer sequentially located on the surface of the second substrate, a source line opening being formed in the gate oxide layer, the floating gate layer, and the first spacer, the source line being located in the source line opening, the source line being separated from the gate oxide layer, the floating gate layer, and the inner wall of the first spacer by the second spacer, and the third spacer covering the outer wall of the gate oxide layer, the floating gate layer, and the sidewall of the first spacer;
[0013] forming a word line material layer on a surface of the second substrate in the device region and a surface of the gate structure;
[0014] The word line material layer is etched using the etching rate of the polysilicon layer to form word line sidewalls, and the word line sidewalls are located on the surface of the second substrate at both sides of the gate structure.
[0015] Optionally, in the method for forming the semiconductor device, after forming the word line spacers, the method further includes: forming a source region and a drain region in the second substrate outside the word line spacers.
[0016] Optionally, in the method for forming the semiconductor device, while forming a gate structure on the surface of the second substrate in the device area, it also includes: forming a logic gate and a fourth sidewall on the surface of the second substrate in the logic area, and the fourth sidewall is located on both sides of the logic gate.
[0017] Optionally, in the method for forming a semiconductor device, the thickness of the oxide layer is 800 angstroms to 1200 angstroms.
[0018] Optionally, in the method for forming a semiconductor device, the thickness of the polysilicon layer is 1600 angstroms to 2400 angstroms.
[0019] Optionally, in the method for forming a semiconductor device, the method for obtaining the etching rate of the polysilicon layer includes:
[0020] measuring the thickness of the polysilicon layer in the device region before etching as a first thickness;
[0021] Etching the polysilicon layer in the device area and recording the etching time;
[0022] measuring the thickness of the polysilicon layer after etching as a second thickness;
[0023] The etching rate of the polysilicon layer is calculated according to the difference between the first thickness and the second thickness and the etching time.
[0024] Optionally, in the method for forming a semiconductor device, the method for testing the thickness of the polysilicon layer includes:
[0025] A laser interferometer sends a laser to the polysilicon layer;
[0026] Obtaining two beams of reflected light from the laser on the upper surface and the lower surface of the polysilicon layer;
[0027] The thickness of the polysilicon layer is obtained by the phase difference between the two reflected lights.
[0028] Optionally, in the method for forming the semiconductor device, the method for calculating the etching rate of the polysilicon layer according to the difference between the first thickness and the second thickness and the etching time includes:
[0029] R = (D1-D2) / T;
[0030] Wherein, R is the etching rate, D1 is the first thickness, D2 is the second thickness, and T is the etching time.
[0031] Optionally, in the method for forming the semiconductor device, the method for forming a patterned photoresist layer on the surface of the polysilicon layer includes:
[0032] A photoresist layer is formed on the surface of the polysilicon layer, and the photoresist layer on the surface of the polysilicon layer in the device region is removed to form a patterned photoresist layer.
[0033] Optionally, in the method for forming the semiconductor device, an oxide layer and a polysilicon layer are sequentially formed on the surface of the first substrate in the device area and the logic area by a chemical vapor deposition method.
[0034] The method for forming a semiconductor device provided by the present invention includes: providing a first substrate, dividing the first substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory; sequentially forming an oxide layer and a polysilicon layer on the surface of the first substrate in the device area and the logic area; forming a patterned photoresist layer on the surface of the polysilicon layer, wherein the patterned photoresist layer covers the photoresist layer in the logic area; etching the polysilicon layer in the device area and obtaining an etching rate of the polysilicon layer; providing a second substrate, dividing the second substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory; forming a gate structure on the surface of the second substrate in the device area, The gate structure includes a gate oxide layer, a floating gate layer, a first sidewall, a source line, a second sidewall, and a third sidewall, which are sequentially located on the surface of a second substrate. A source line opening is formed in the gate oxide layer, the floating gate layer, and the first sidewall. The source line is located in the source line opening and is separated from the gate oxide layer, the floating gate layer, and the inner wall of the first sidewall by the second sidewall. The third sidewall covers the outer wall of the gate oxide layer, the floating gate layer, and the sidewall of the first sidewall. A word line material layer is formed on the surface of the second substrate in the device region and the surface of the gate structure. The word line material layer is etched using the etching rate of the polysilicon layer to form word line sidewalls. The word line sidewalls are located on the surface of the second substrate on both sides of the gate structure. The device region and the logic region of the present invention are arranged according to the layout of the device region and the logic region of the semiconductor device to be actually formed. The rate of etching the word line material layer to form the word line is then determined using the substrate in the device region. The etching rate of the polysilicon is accurately tested, and highly qualified word line sidewalls are formed. No polysilicon residue is left on the surface of the substrate in the source and drain regions, thereby improving the quality of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 and Figure 2 It is a schematic structural diagram of a semiconductor device in the prior art;
[0036] Figure 3 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;
[0037] Figure 4 is a schematic structural diagram of a test structure according to an embodiment of the present invention;
[0038] Figure 5 and Figure 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
[0039] In the figure: 101-wafer, 102-gate oxide layer, 103-floating gate layer, 104-first sidewall, 105-source line, 106-second sidewall, 107-third sidewall, 108-word line material layer, 109-word line sidewall, 110-source and drain regions, 111-logic gate, 112-fourth sidewall, 201-second substrate, 202-gate oxide layer, 203-floating gate layer, 204-first sidewall, 205-source line, 206-second sidewall, 207-third sidewall, 208-word line material layer, 209-word line sidewall, 210-source and drain regions, 211-logic gate, 212-fourth sidewall, 301-first substrate, 302-oxide layer, 303-polysilicon layer, 304-patterned photoresist layer. DETAILED DESCRIPTION
[0040] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.
[0041] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.
[0042] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.
[0043] Please refer to Figure 3 The present invention provides a method for forming a semiconductor device, comprising:
[0044] S1: providing a first substrate, and dividing the first substrate into a device area and a logic area adjacent to each other using a split gate memory layout;
[0045] S2: forming an oxide layer and a polysilicon layer in sequence on the surface of the first substrate in the device area and the logic area;
[0046] S3: forming a patterned photoresist layer on the surface of the polysilicon layer, wherein the patterned photoresist layer covers the photoresist layer of the logic area;
[0047] S4: etching the polysilicon layer in the device area and obtaining the etching rate of the polysilicon layer;
[0048] S5: providing a second substrate, and dividing the second substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory;
[0049] S6: forming a gate structure on the surface of the second substrate in the device region, the gate structure comprising a gate oxide layer, a floating gate layer, a first spacer, a source line, a second spacer, and a third spacer sequentially located on the surface of the second substrate, a source line opening being formed in the gate oxide layer, the floating gate layer, and the first spacer, the source line being located in the source line opening, the source line being separated from the gate oxide layer, the floating gate layer, and the inner wall of the first spacer by the second spacer, and the third spacer covering the outer wall of the gate oxide layer, the floating gate layer, and the sidewall of the first spacer;
[0050] S7: forming a word line material layer on the surface of the second substrate and the surface of the gate structure in the device region;
[0051] S8: Etching the word line material layer using the etching rate of the polysilicon layer to form word line sidewalls. The word line sidewalls are located on the surface of the second substrate at both sides of the gate structure.
[0052] First, please refer to Figure 4 A first substrate 301 is provided, and the first substrate is divided into adjacent device areas A and logic areas B using a split-gate memory layout. Next, an oxide layer 302 and a polysilicon layer 303 are sequentially formed on the surfaces of the first substrate 301 in both the device area A and the logic area B. The first substrate 301 comprises a wafer. The oxide layer 302 comprises silicon dioxide. The thickness of the oxide layer 302 can be 800 angstroms to 1200 angstroms. The thickness of the polysilicon layer 303 can be 1600 angstroms to 2400 angstroms. The oxide layer 302 is formed on the surfaces of the first substrate 301 in both the device area A and the logic area B by chemical vapor deposition. A polysilicon layer 303 is formed on the surface of the oxide layer 302 by chemical vapor deposition. After the polysilicon layer 303 is formed, the thickness of the polysilicon layer 303 at this point needs to be tested as a first thickness.
[0053] Next, a photoresist layer is formed on the surface of the polysilicon layer 303. The photoresist layer on the surface of the polysilicon layer 303 in the device area A is removed to form a patterned photoresist layer 304. The present invention forms the patterned photoresist layer 304 according to the actual layout of the gate memory. Only the polysilicon layer 303 exposed by the patterned photoresist layer 304 can reflect the actual wordline sidewalls.
[0054] Next, the polysilicon layer 303 of the device region A is etched, and the etching time and the thickness of the polysilicon layer 303 after etching are recorded as the second thickness. Next, the etching rate of the polysilicon layer is calculated based on the difference between the first thickness and the second thickness and the etching time. The specific method includes:
[0055] R = (D1-D2) / T;
[0056] Wherein, R is the etching rate, D1 is the first thickness, D2 is the second thickness, and T is the etching time.
[0057] In an embodiment of the present invention, a method for testing the thickness of a polysilicon layer includes: a laser interferometer sends a laser to the polysilicon layer; obtains two beams of reflected light from the laser on the upper and lower surfaces of the polysilicon layer; and obtains the thickness of the polysilicon layer through the phase difference between the two beams of reflected light. Specifically, by measuring the phase difference or fringe movement of the interference signal, the thickness of the polysilicon layer can be calculated: d = λ·Δφ4πnd = 4πnλ·Δφ, where: d is the film thickness, λ is the laser wavelength, Δφ is the phase difference, and n is the refractive index of the polysilicon layer. The spot of the laser emitted in the embodiment of the present invention can completely enter the photoresist layer of the device area, so the etching rate of the future word line material layer can be accurately tested by utilizing the rate of etching the polysilicon layer in the device area.
[0058] After obtaining the etching rate of the polysilicon layer, this etching rate can be used to form the word line sidewalls of the semiconductor device. Figure 5 and Figure 6 A second substrate 201 is provided, wherein the second substrate 201 comprises a wafer. The second substrate is divided into a device region A and a logic region B, which are adjacently disposed, using a split gate memory layout. The split gate memory layout in step S5 is the same as the split gate memory layout in step S1.
[0059] Next, a gate structure is formed on the surface of the second substrate 201 in the device area A. The gate structure includes a gate oxide layer 202, a floating gate layer 203, a first sidewall 204, a source line 205, a second sidewall 206 and a third sidewall 207, which are sequentially located on the surface of the second substrate 201. A source line opening is formed in the gate oxide layer 202, the floating gate layer 203 and the first sidewall 204. The source line 205 is located in the source line opening. The source line 205 is separated from the gate oxide layer 202, the floating gate layer 203 and the inner walls of the first sidewall 204 by the second sidewall 206. The third sidewall 207 covers the outer walls of the gate oxide layer 202, the floating gate layer 203 and the side walls of the first sidewall 204.
[0060] Next, a wordline material layer 208 is formed on the surface of the second substrate 201 and the surface of the gate structure in device area A. Next, the wordline material layer 208 is etched using the etch rate of the polysilicon layer obtained in step S4 to form wordline spacers 209. Wordline spacers 209 are located on the surface of the second substrate 201 on both sides of the gate structure. Next, source and drain regions 210, i.e., source and drain regions, are formed in the second substrate outside the wordline spacers 209.
[0061] In which, while a gate structure is formed on the surface of the second substrate 201 in the device area A, a logic gate 211 and a fourth side wall 212 are formed on the surface of the second substrate 201 in the logic area B. The fourth side wall 212 is located on both sides of the logic gate 211. The specific formation steps and formation time are the existing technology and will not be repeated in the embodiments of the present invention.
[0062] In summary, the method for forming a semiconductor device provided in an embodiment of the present invention includes: providing a first substrate, dividing the first substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory; forming an oxide layer and a polysilicon layer on the surface of the first substrate in the device area and the logic area in sequence; forming a patterned photoresist layer on the surface of the polysilicon layer, wherein the patterned photoresist layer covers the photoresist layer of the logic area; etching the polysilicon layer in the device area, and obtaining an etching rate of the polysilicon layer; providing a second substrate, dividing the second substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory; forming a gate on the surface of the second substrate in the device area. The gate structure includes a gate oxide layer, a floating gate layer, a first sidewall, a source line, a second sidewall, and a third sidewall, which are sequentially located on the surface of a second substrate. A source line opening is formed in the gate oxide layer, the floating gate layer, and the first sidewall. The source line is located in the source line opening and is separated from the gate oxide layer, the floating gate layer, and the inner wall of the first sidewall by the second sidewall. The third sidewall covers the outer wall of the gate oxide layer, the floating gate layer, and the sidewall of the first sidewall. A word line material layer is formed on the surface of the second substrate in the device region and the surface of the gate structure. The word line material layer is etched using the etching rate of the polysilicon layer to form word line sidewalls. The word line sidewalls are located on the surface of the second substrate on both sides of the gate structure. The device region and logic region of the present invention are arranged according to the layout of the device region and logic region of the semiconductor device to be actually formed. The rate of etching the word line material layer to form the word line is then obtained using the substrate in the device region. The etching rate of the polysilicon is accurately tested, and highly qualified word line sidewalls are formed. No polysilicon residue is left on the surface of the substrate in the source and drain regions, thereby improving the quality of the semiconductor device.
[0063] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: include: Providing a first substrate, and dividing the first substrate into a device area and a logic area adjacent to each other using a layout of a split-gate memory; forming an oxide layer and a polysilicon layer in sequence on the surface of the first substrate in the device area and the logic area; forming a patterned photoresist layer on the surface of the polysilicon layer, wherein the patterned photoresist layer covers the photoresist layer of the logic area; Etching the polysilicon layer in the device region and obtaining an etching rate of the polysilicon layer; Providing a second substrate, and dividing the second substrate into a device area and a logic area adjacent to each other using a layout of a split gate memory; A gate structure is formed on the surface of the second substrate in the device region, the gate structure comprising a gate oxide layer, a floating gate layer, a first spacer, a source line, a second spacer, and a third spacer sequentially located on the surface of the second substrate, a source line opening being formed in the gate oxide layer, the floating gate layer, and the first spacer, the source line being located in the source line opening, the source line being separated from the gate oxide layer, the floating gate layer, and the inner wall of the first spacer by the second spacer, and the third spacer covering the outer wall of the gate oxide layer, the floating gate layer, and the sidewall of the first spacer; forming a word line material layer on a surface of the second substrate in the device region and a surface of the gate structure; The word line material layer is etched using the etching rate of the polysilicon layer to form word line sidewalls, and the word line sidewalls are located on the surface of the second substrate at both sides of the gate structure.
2. The method for forming a semiconductor device according to claim 1, wherein: After forming the word line spacers, the method further includes: forming a source region and a drain region in the second substrate outside the word line spacers.
3. The method for forming a semiconductor device according to claim 1, wherein: While forming the gate structure on the surface of the second substrate in the device area, the method further includes: forming a logic gate and a fourth spacer on the surface of the second substrate in the logic area, wherein the fourth spacer is located on both sides of the logic gate.
4. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the oxide layer is 800 angstroms to 1200 angstroms.
5. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the polysilicon layer is 1600 angstroms to 2400 angstroms.
6. The method for forming a semiconductor device according to claim 1, wherein: The method for obtaining the etching rate of the polysilicon layer includes: measuring the thickness of the polysilicon layer in the device region before etching as a first thickness; Etching the polysilicon layer in the device area and recording the etching time; measuring the thickness of the polysilicon layer after etching as a second thickness; The etching rate of the polysilicon layer is calculated according to the difference between the first thickness and the second thickness and the etching time.
7. The method for forming a semiconductor device according to claim 6, wherein: The method for testing the thickness of the polysilicon layer includes: A laser interferometer sends a laser to the polysilicon layer; Obtaining two beams of reflected light from the laser on the upper surface and the lower surface of the polysilicon layer; The thickness of the polysilicon layer is obtained by the phase difference between the two reflected lights.
8. The method for forming a semiconductor device according to claim 6, wherein: The method for calculating the etching rate of the polysilicon layer according to the difference between the first thickness and the second thickness and the etching time includes: R = (D1-D2) / T; Wherein, R is the etching rate, D1 is the first thickness, D2 is the second thickness, and T is the etching time.
9. The method for forming a semiconductor device according to claim 1, wherein: The method for forming a patterned photoresist layer on the surface of the polysilicon layer comprises: A photoresist layer is formed on the surface of the polysilicon layer, and the photoresist layer on the surface of the polysilicon layer in the device region is removed to form a patterned photoresist layer.
10. The method for forming a semiconductor device according to claim 1, wherein: An oxide layer and a polysilicon layer are sequentially formed on the surfaces of the first substrate in the device area and the logic area by a chemical vapor deposition method.