Semiconductor device

Abstract

The application discloses a semiconductor device, comprising: a first semiconductor body, comprising a first ohmic contact region and a second ohmic contact region with different conductive types and located on a first surface, and a buried layer with the same conductive type as the second ohmic contact region and located on the first ohmic contact region and the second ohmic contact region close to a second surface; a second semiconductor body located on the first surface, comprising a first semiconductor layer, a third semiconductor layer and a second semiconductor layer with different conductive types and located between the first semiconductor layer and the third semiconductor layer; a first electrode electrically connected with the first ohmic contact region and the third semiconductor layer; a first gate electrically connected with the second ohmic contact region and the first semiconductor layer; a second gate electrically connected with the second semiconductor layer; a first resistive material layer in contact with the second gate and the third semiconductor layer; and a second resistive material layer in contact with the second gate and the first semiconductor layer. The application improves the short circuit problem of the device caused by the charging and discharging of the Miller capacitor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device. BACKGROUND

[0002] A field effect transistor (FET) is a semiconductor device that controls current using the electric field effect. The core is to modulate the channel conductivity by changing the gate voltage.

[0003] In the related art, SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has lower switching loss than bipolar transistors such as IGBT (Insulate-Gate Bipolar Transistor), which makes it more competitive in high-frequency application scenarios, such as being used as a switching device in a bridge circuit.

[0004] However, due to the high saturation carrier mobility of SiC material itself, the short-circuit tolerance time of planar SiC MOSFET is extremely short, so it is difficult for the driving circuit to make effective protection in time. Moreover, SiC MOSFET is used at higher switching frequencies, and higher switching speed brings an increase in dv / dt. Especially in a bridge circuit, the rapid change of the Switch node voltage will cause the Miller capacitor in the power MOSFET to charge and discharge rapidly, and the charging and discharging current will form a potential difference between the gate and source of the power MOSFET through the peripheral driving circuit. This potential difference reaching a certain order of magnitude will cause the device to misopen, resulting in upper and lower tube punch-through short circuit, and finally the device burns out. Therefore, how to improve the short circuit problem of the semiconductor device caused by the charging and discharging of the Miller capacitor in high-frequency applications has become a technical problem to be solved by the personnel in the field. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device to improve the device short circuit problem caused by the charging and discharging of the Miller capacitor in high-frequency applications.

[0006] According to an aspect of the present application, a semiconductor device is provided, comprising at least one cell structure, the cell structure comprising:

[0007] The first semiconductor body comprises a first surface and a second surface arranged oppositely; the first semiconductor body comprises a first ohmic contact region and a second ohmic contact region with different conductive types, both of which are located on the first surface; the first semiconductor body further comprises a buried layer located on one side of the first ohmic contact region and the second ohmic contact region close to the second surface; wherein the buried layer has the same conductive type as the second ohmic contact region;

[0008] The second semiconductor body is located on the first surface of the first semiconductor body; the second semiconductor body comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer; wherein the first semiconductor layer and the third semiconductor layer have the same conductive type as the second ohmic contact region; the second semiconductor layer has the same conductive type as the first ohmic contact region;

[0009] The first electrode and the first gate; the first electrode is electrically connected with the first ohmic contact region and the third semiconductor layer, and the first gate is electrically connected with the second ohmic contact region and the first semiconductor layer;

[0010] The first resistive material layer, the second resistive material layer and the second gate; the second gate is located between the first resistive material layer and the second resistive material layer; wherein the second gate is electrically connected with the second semiconductor; the first resistive material layer is in contact with the second gate and the third semiconductor layer, and the second resistive material layer is in contact with the second gate and the first semiconductor layer.

[0011] Optionally, the first semiconductor body further comprises a first JFET region extending along a first direction and a second JFET region extending along a second direction; the first direction and the second direction intersect with each other, and the first direction is the direction in which the first surface points to the second surface;

[0012] Wherein, the first JFET region and the second JFET region are connected, and the second JFET region is located between the buried layer and the second ohmic contact region.

[0013] Optionally, the first resistive material layer, the second resistive material layer and the second gate are all located on the side of the second semiconductor body away from the first semiconductor body;

[0014] In the second semiconductor body, the second semiconductor layer is located on the surface of the first semiconductor layer close to the first semiconductor body and the sidewall of the first semiconductor layer; and the third semiconductor layer is located on the surface of the second semiconductor layer close to the first semiconductor body and the sidewall of the second semiconductor layer away from the first semiconductor layer.

[0015] Optionally, the surface of the second semiconductor body away from the side of the first semiconductor body is a plane;

[0016] The surface of the second semiconductor body away from the side of the first semiconductor body comprises a first region surface, a third region surface and a second region surface between the first region surface and the third region surface;

[0017] The second region surface is the surface of the second semiconductor layer away from the side of the first semiconductor body, the first region surface is the surface of the first semiconductor layer away from the side of the first semiconductor body, and the third region surface is the surface of the third semiconductor layer away from the side of the first semiconductor body; the second gate electrode is located on the second region surface, the first resistive material layer extends from the second gate electrode along the second region surface to the third region surface of the covered portion, and the second resistive material layer extends from the second gate electrode along the second region surface to the first region surface of the covered portion.

[0018] Optionally, the first electrode and the first gate electrode are located on opposite sides of the second semiconductor body;

[0019] The semiconductor device further comprises a first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode and the sidewall of the second semiconductor body, and the second insulating layer is located between the first gate electrode and the sidewall of the second semiconductor body.

[0020] Optionally, the cell structure further comprises:

[0021] a first ohmic contact layer located on the surface of the first ohmic contact region away from the second surface, and the first electrode is electrically connected to the first ohmic contact region through the first ohmic contact layer;

[0022] and / or a second ohmic contact layer located on the surface of the second ohmic contact region away from the second surface, and the first gate electrode is electrically connected to the second ohmic contact region through the second ohmic contact layer;

[0023] and / or a third ohmic contact layer located on part of the third region surface, and the first electrode is electrically connected to the third semiconductor layer through the third ohmic contact layer;

[0024] and / or a fourth ohmic contact layer located on part of the first region surface, and the first gate electrode is electrically connected to the first semiconductor layer through the fourth ohmic contact layer;

[0025] And / or, a fifth ohmic contact layer is located on a part of the surface of the second region, and the second gate is electrically connected to the second semiconductor layer through the fifth ohmic contact layer.

[0026] Optionally, the cell structure further comprises:

[0027] A third insulating layer is located on the side of the first resistive material layer, the second resistive material layer, the first gate and the second gate away from the first semiconductor body.

[0028] The first electrode is also located on the side of the third insulating layer away from the first semiconductor body, and extends to the first ohmic contact region along the sidewall of the third insulating layer, the sidewall of the first resistive material layer and the sidewall of the second semiconductor body.

[0029] Optionally, the material of the first semiconductor body is different from the material of the second semiconductor body.

[0030] The material of the first semiconductor body comprises silicon carbide, and the material of the second semiconductor body comprises silicon.

[0031] Optionally, the semiconductor device comprises at least two of the cell structures, and two adjacent cell structures are mirror symmetrical in the second direction.

[0032] The technical scheme provided by the embodiment of the application forms a second semiconductor body on the first surface of the first semiconductor body by means of heterogeneous integration, forms a Miller clamp circuit by using the second semiconductor body, the first resistive material layer and the second resistive material layer, and enables the semiconductor device to be turned off in time when short circuit occurs due to crosstalk, thereby avoiding damage and improving the problem of device short circuit caused by charging and discharging of the Miller capacitor in high-frequency applications.

[0033] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0035] Figure 1 is a circuit schematic diagram of a half-bridge circuit provided in the related art;

[0036] Figure 2is a structure sectional view of a semiconductor device provided by an embodiment of the present application;

[0037] Figure 3 is Figure 2 is a working principle diagram of a Miller clamp circuit formed by the second semiconductor body, the first resistive material layer and the second resistive material layer in the structure shown;

[0038] Figure 4 is a circuit schematic diagram of a half-bridge circuit provided by an embodiment of the present application;

[0039] Figure 5 is another structure sectional view of a semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the personnel in the art without creative labor should belong to the protection scope of the present application.

[0041] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0042] As in the background art, in a bridge circuit, the rapid change of the Switch node voltage will cause the Miller capacitor in the power MOSFET to charge and discharge rapidly, and the charging and discharging current will form a potential difference between the gate and the source of the power MOSFET through the peripheral drive circuit, and this potential difference reaching a certain magnitude will cause the device to be mistakenly turned on, so that the upper and lower tubes are short-circuited, and finally the device is burned out. Referring to Figure 1 , Figure 1 is a circuit schematic diagram in which the lower bridge transistor M2 in the half-bridge application has been turned off, and the upper bridge transistor M1 is in the process of being turned on, and the current Flow through the load. Since the power MOSFET is applied to a high frequency scenario, the turn-on process of the upper bridge transistor M1 is completed in a very short time. In the SW point as shown in FIG. 1, the voltage drop at this point changes rapidly during the turn-on process, and this voltage change will cause the Miller capacitance of the lower bridge transistor M2 to be charged. Figure 1 The turn-on process of the upper bridge transistor M1 is completed in a very short time. In the SW point as shown in FIG. 1, the voltage drop at this point changes rapidly during the turn-on process, and this voltage change will cause the Miller capacitance of the lower bridge transistor M2 to be charged. The charging and discharging current will form a potential difference on the peripheral drive circuit loop, thereby causing the originally turned-off lower bridge transistor M2 to be mistakenly turned on. At this time, the upper bridge transistor M1 has already been turned on, and ultimately causes a short circuit from the drain to the GND terminal, and the device is burned out. The peripheral drive circuit includes a gate resistor and a drive circuit for outputting a gate voltage (for example, a turn-on voltage and a turn-off voltage ). The capacitance is the capacitance formed between the gate and the source, and the capacitance is the capacitance formed between the drain and the source.

[0043] To solve the above problems, embodiments of the present application provide a semiconductor device, Figure 2 is a structure cross-sectional view of a semiconductor device provided by embodiments of the present application, referring to Figure 2 , the semiconductor device includes at least one cell structure, and the cell structure includes:

[0044] A first semiconductor body 10 includes oppositely arranged first and second surfaces; the first semiconductor body 10 includes a first ohmic contact region 121 and a second ohmic contact region 122 having different conductive types, both of which are located on the first surface; the first semiconductor body 10 further includes a buried layer 123 located on one side of the first ohmic contact region 121 and the second ohmic contact region 122 close to the second surface, and the buried layer 123 has the same conductive type as the second ohmic contact region 122;

[0045] A second semiconductor body 20 is located on the first surface of the first semiconductor body 10; the second semiconductor body 20 includes a first semiconductor layer 21, a third semiconductor layer 23, and a second semiconductor layer 22 located between the first semiconductor layer 21 and the third semiconductor layer 23; wherein the first semiconductor layer 21 and the third semiconductor layer 23 have the same conductive type as the second ohmic contact region 122; the second semiconductor layer 22 has the same conductive type as the first ohmic contact region 121;

[0046] A first electrode 1 and a first gate G1; the first electrode 1 is electrically connected with the first ohmic contact region 121 and the third semiconductor layer 23, and the first gate G1 is electrically connected with the second ohmic contact region 122 and the first semiconductor layer 21;

[0047] The first resistive material layer 31, the second resistive material layer 32, and the second gate G2; the second gate G2 is located between the first resistive material layer 31 and the second resistive material layer 32; wherein the second gate G2 is electrically connected with the second semiconductor layer 22; the first resistive material layer 31 is in contact with the second gate G2 and the third semiconductor layer 23, and the second resistive material layer 32 is in contact with the second gate G2 and the third semiconductor layer 23.

[0048] Specifically, the first semiconductor body 10 can be formed by one-time epitaxy or by multiple times of epitaxy. That is, the first semiconductor body 10 can be a first semiconductor epitaxial layer 12, or a laminated structure formed by multiple first semiconductor epitaxial layers 12. The first semiconductor body 10 can further include a substrate 11, that is, the first semiconductor body 10 includes the substrate 11 and at least one first semiconductor epitaxial layer 12 formed on one side of the substrate 11. The material of the substrate 11 is the same as that of the first semiconductor epitaxial layer 12.

[0049] In the case where the first semiconductor body 10 includes the substrate 11 and the first semiconductor epitaxial layer 12, the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12, and the first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11. Figure 2 The first semiconductor body 10 shown includes the substrate 11 and one first semiconductor epitaxial layer 12 on one side of the substrate 11, the first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11, and the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12.

[0050] The first semiconductor epitaxial layer 12 comprises a first ohmic contact region 121 and a second ohmic contact region 122 with different conductive types, and a buried layer 123 with the same conductive type as the second ohmic contact region 122, the buried layer 123 being located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 close to the substrate 11. The conductive type of the first ohmic contact region 121 is the same as the conductive type of the first semiconductor epitaxial layer 12, both being the first conductive type, and the doping concentration of the first conductive type ions in the first ohmic contact region 121 is greater than the doping concentration of the first conductive type ions in the first semiconductor epitaxial layer 12; the conductive type of the second ohmic contact region 122 is the second conductive type. The second ohmic contact region 122 and the buried layer 123 can be formed by implanting the second conductive type ions in the first semiconductor epitaxial layer 12, and the doping concentration of the second conductive type ions in the second ohmic contact region 122 can be equal to or not equal to the doping concentration of the second conductive type ions in the buried layer 123. In the embodiment of the application, the first ohmic contact region 121 and the second ohmic contact region 122 are both heavily doped regions. The first ohmic contact region 121 extends from the edge of the first surface to the second ohmic contact region 122, and the orthogonal projection of the first ohmic contact region 121 on the substrate 11 is located in the orthogonal projection of the buried layer 123 on the substrate 11; part of the orthogonal projection of the second ohmic contact region 122 on the substrate 11 overlaps with the orthogonal projection of the buried layer 123 on the substrate 11, and another part of the orthogonal projection of the second ohmic contact region 122 on the substrate 11 does not overlap with the orthogonal projection of the buried layer 123 on the substrate 11.

[0051] The first electrode 1 is in contact with the first ohmic contact region 121, the first gate G1 is in contact with the second ohmic contact region 122, and the second surface of the first semiconductor body 10 further comprises a second electrode 2, the first semiconductor body 10 being used to form a junction field-effect transistor (JFET). The first electrode can be a source electrode, and the second electrode can be a drain electrode; or the second electrode can be a source electrode, and the first electrode can be a drain electrode. The first gate G1 is used to control the formation and disconnection of a channel between the buried layer 123 and the second ohmic contact region 122. When the channel is formed between the buried layer 123 and the second ohmic contact region 122, the first electrode 1 and the second electrode 2 are in conduction. Figure 2 In the structure shown, the first electrode 1 is a source electrode, and the second electrode 2 is a drain electrode. It should be noted that the gate voltage is connected from the second gate G2, and the voltage of the first gate G1 is formed after voltage division by the second resistive material layer 32.

[0052] The second semiconductor body 20 is arranged on one side of the first semiconductor body 10 and on the first surface of the first semiconductor body 10. The second semiconductor body 20 can be formed by one-time epitaxy or by multiple-time epitaxy. That is, the second semiconductor body 20 can be a second semiconductor epitaxial layer or a laminated structure formed by multiple second semiconductor epitaxial layers. The second semiconductor body 20 includes a first semiconductor layer 21, a third semiconductor layer 23, and a second semiconductor layer 22 between the first semiconductor layer 21 and the third semiconductor layer 23. Since the first semiconductor layer 21 and the third semiconductor layer 23 have the same conductive type as the second ohmic contact region 122, the second semiconductor layer 22 has the same conductive type as the first ohmic contact region 121, and the conductive types of the first ohmic contact region 121 and the second ohmic contact region 122 are different, in the second semiconductor body 20, the conductive type of the second semiconductor layer 22 is different from that of the first semiconductor layer 21, and the conductive type of the second semiconductor layer 22 is different from that of the third semiconductor layer 23.

[0053] The first conductive type can be N type and the second conductive type can be P type, that is, the conductive type of the first ohmic contact region 121 is N type and the conductive type of the second ohmic contact region 122 is P type. Alternatively, the first conductive type can be P type and the second conductive type can be N type, that is, the conductive type of the first ohmic contact region 121 is P type and the conductive type of the second ohmic contact region 122 is N type. A PN junction is formed between the second semiconductor layer 22 and the first semiconductor layer 21, and a PN junction is formed between the second semiconductor layer 22 and the third semiconductor layer 23. Figure 2 In the structure shown, the conductive type of the first ohmic contact region 121 is N type and the conductive type of the second ohmic contact region 122 is P type.

[0054] The first electrode 1 is electrically connected with the third semiconductor layer 23, the first gate G1 is electrically connected with the first semiconductor layer 21, and the second gate G2 is electrically connected with the second semiconductor layer 22, so that a BJT (Bipolar Junction Transistor) can be formed on the first semiconductor body 10. In addition, the second gate G2 is arranged between the first resistive material layer 31 and the second resistive material layer 32, the first resistive material layer 31 is in contact with the second gate G2 and the third semiconductor layer 23, the second resistive material layer 32 is in contact with the second gate G2 and the third semiconductor layer 23, a resistance can be formed between the second gate G2 and the first semiconductor layer 21, and a resistance can be formed between the second gate G2 and the third semiconductor layer 23. The first resistive material layer 31 and the second resistive material layer 32 are both high-resistance dielectric layers, for example, the materials of the first resistive material layer 31 and the second resistive material layer 32 include but are not limited to SIPOS (semi-insulating polysilicon). In this way, two current paths can be constructed between the first gate G1 and the first electrode 1 through the second semiconductor body 20, the first resistive material layer 31 and the second resistive material layer 32.

[0055] Figure 3 is Figure 2 The working principle diagram of the Miller clamp circuit formed by the second semiconductor body 20, the first resistive material layer 31 and the second resistive material layer 32 in the structure shown in the figure. When crosstalk occurs, the crosstalk current will first form a forward voltage drop between the emitter of the BJT (the first gate G1 corresponds to the emitter of the BJT) and the second gate G2 through the first resistance R1 formed by the second resistive material layer 32, and a forward voltage drop between the second gate G2 and the collector of the BJT (the first electrode 1 corresponds to the collector of the BJT) through the second resistance R2 formed by the first resistive material layer 31. When the crosstalk current is large enough, the emitter junction of the BJT is forward biased, and the collector junction is reverse biased, the BJT is turned on, and the crosstalk current flows from to , the crosstalk current flows from the inside of the BJT, the voltage of the first gate G1 is clamped to the potential of the first electrode 1, and the JFET device formed by the first semiconductor body 10 is turned off, thereby preventing the bridge arm through device in the circuit from being damaged.

[0056] If a half-bridge circuit is used, and the BJT is a PNP type BJT, the equivalent circuit diagram is as follows Figure 4The crosstalk current in the lower bridge transistor (J2) will first be divided by the first resistor R1 and the second resistor R2, so that the PNP type BJT is turned on, and the gate and source terminals of the lower bridge transistor (J2) are short-circuited through the conduction channel provided by the PNP type BJT, so that the lower bridge transistor (J2) is turned off, thereby preventing the short circuit from occurring.

[0057] The technical scheme provided by the embodiment of the application forms the second semiconductor body 20 on the first surface of the first semiconductor body 10 in a heterogeneous integration manner, forms the Miller clamp circuit by using the second semiconductor body 20, the first resistive material layer 31, and the second resistive material layer 32, and thus the semiconductor device can be turned off in time when a short circuit occurs due to crosstalk, and damage is avoided, thereby improving the problem of device short circuit caused by charging and discharging of the Miller capacitor in high-frequency applications.

[0058] On the basis of the above embodiments, with reference to Figure 2 Optionally, the first semiconductor body 10 further includes a first JFET region 125 extending along a first direction X and a second JFET region 124 extending along a second direction Y; the first direction X is a direction in which the first surface points to the second surface; the first direction X and the second direction Y are arranged to intersect each other, for example, perpendicularly. The first JFET region 125 and the second JFET region 124 are connected, and the second JFET region 124 is located between the buried layer 123 and the second ohmic contact region 122. It can be understood that the first semiconductor epitaxial layer 12 located between the buried layer 123 and the second ohmic contact region 122 is used to form the second JFET region 124, and the first semiconductor epitaxial layer 12 located at the sidewall of the buried layer 123 is used to form the first JFET region 125. In the embodiment of the application, the transverse JFET region (the second JFET region 124) and the longitudinal JFET region (the first JFET region 125) are arranged in series, a longer JFET region is formed, the negative feedback effect of the JFET region on the saturation current is improved, and finally the short-circuit resistance time of the device is improved.

[0059] On the basis of the above embodiments, with reference to Figure 2 Optionally, in the second semiconductor body 20, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 close to the first semiconductor body 10 and the sidewall of the first semiconductor layer 21; the third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 close to the first semiconductor body 10 and the sidewall of the second semiconductor layer 22 away from the first semiconductor layer 21; the first resistive material layer 31, the second resistive material layer 32, and the second gate G2 are all located on the side of the second semiconductor body 20 away from the first semiconductor body 10.

[0060] Specifically, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 close to the first semiconductor body 10 and the side wall of the first semiconductor layer 21, and the cross section of the second semiconductor layer 22 is in the shape of "L"; the third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 close to the first semiconductor body 10 and the side wall of the second semiconductor layer 22 away from the first semiconductor layer 21, and the cross section of the third semiconductor layer 23 is in the shape of "L". The second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 close to the first semiconductor body 10 and the side wall of the first semiconductor layer 21, and the third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 close to the first semiconductor body 10 and the side wall of the second semiconductor layer 22 away from the first semiconductor layer 21, which can ensure that the second semiconductor layer 22 is located between the first semiconductor layer 21 and the third semiconductor layer 23, meet the requirement of forming two PN junctions, and also expose the second semiconductor layer 22 and the third semiconductor layer 23, which is convenient for electrical connection with the second gate G2 and the first electrode 1 respectively, and convenient for the setting of the first resistive material layer 31 and the second resistive material layer 32.

[0061] On the basis of the above embodiments, with reference to Figure 2 Optionally, the surface of the second semiconductor body 20 away from the first semiconductor body 10 is a plane; the surface of the second semiconductor body 20 away from the first semiconductor body 10 includes a first region surface, a third region surface and a second region surface located between the first region surface and the third region surface;

[0062] Among them, the second region surface is the surface of the second semiconductor layer 22 away from the first semiconductor body 10, the first region surface is the surface of the first semiconductor layer 21 away from the first semiconductor body 10, and the third region surface is the surface of the third semiconductor layer 23 away from the first semiconductor body 10; the second gate G2 is located on the second region surface, the first resistive material layer 31 extends from the second gate G2 along the second region surface to the third region surface of the covering part, and the second resistive material layer 32 extends from the second gate G2 along the second region surface to the first region surface of the covering part.

[0063] Specifically, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 close to the first semiconductor body 10 and on the entire sidewall of the first semiconductor layer 21, and the width of the second semiconductor layer 22 on the sidewall of the first semiconductor layer 21 is large enough to carry the second gate G2, part of the first resistive material layer 31 and part of the second resistive material layer 32. The third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 close to the first semiconductor body 10 and on the entire sidewall of the second semiconductor layer 22, and the width of the third semiconductor layer 23 on the sidewall of the second semiconductor layer 22 is large enough to have an area electrically connected to the first electrode 1 and to carry another part of the first resistive material layer 31.

[0064] In addition, the distance from the surface of the second semiconductor layer 22 on the sidewall of the first semiconductor layer 21 away from the first semiconductor body 10 to the first semiconductor body 10 and the distance from the surface of the third semiconductor layer 23 on the sidewall of the second semiconductor layer 22 away from the first semiconductor body 10 to the first semiconductor body 10 are both equal to the distance from the surface of the first semiconductor layer 21 away from the first semiconductor body 10 to the first semiconductor body 10, so that the surface of the second semiconductor body 20 away from the first semiconductor body 10 is a plane, which can further facilitate the arrangement of the second gate G2, the first resistive material layer 31 and the second resistive material layer 32.

[0065] On the basis of the above embodiments, with reference to Figure 2 Optionally, the first electrode 1 and the first gate G1 are located on opposite sides of the second semiconductor body 20.

[0066] The semiconductor device further comprises a first insulating layer 41 and a second insulating layer 42; wherein the first insulating layer 41 is located between the first electrode 1 and the sidewall of the second semiconductor body 20; and the second insulating layer 42 is located between the first gate G1 and the sidewall of the second semiconductor body 20.

[0067] Specifically, the second semiconductor body 20 covers the first surface of the first semiconductor body 10 to expose part of the first ohmic contact region 121 and part of the second ohmic contact region 122, thereby facilitating the electrical connection of the first electrode 1 with the first ohmic contact region 121 and the electrical connection of the first gate G1 with the second contact region. The exposed first ohmic contact region 121 and the exposed second ohmic contact region 122 are located on opposite sides of the second semiconductor body 20, and the first electrode 1 and the first gate G1 are located on opposite sides of the second semiconductor body 20. A first insulating layer 41 is arranged between the first electrode 1 and the sidewall of the second semiconductor body 20 to prevent the electrical connection of the first electrode 1 with the sidewall of the second semiconductor body 20. A second insulating layer 42 is arranged between the first gate G1 and the other sidewall of the second semiconductor body 20 to prevent the electrical connection of the first gate G1 with the sidewall of the second semiconductor body 20, thereby preventing the direct electrical connection of the third semiconductor layer 23 with the first semiconductor layer 21. The material of the first insulating layer 41 includes but is not limited to silicon oxide, and the material of the second insulating layer 42 includes but is not limited to silicon oxide. The first insulating layer 41 and the second insulating layer 42 can be formed synchronously.

[0068] On the basis of the above-mentioned embodiments, with reference to Figure 2 Optionally, the cell structure further comprises:

[0069] The first ohmic contact layer 51 is located on the surface of the first ohmic contact region 121 away from the second surface, and the first electrode 1 is electrically connected with the first ohmic contact region 121 through the first ohmic contact layer 51, thereby reducing the contact resistance between the first electrode 1 and the first ohmic contact region 121;

[0070] And / or, the second ohmic contact layer 52 is located on the surface of the second ohmic contact region 122 away from the second surface, and the first gate G1 is electrically connected with the second ohmic contact region 122 through the second ohmic contact layer 52, thereby reducing the contact resistance between the first gate G1 and the second ohmic contact region 122;

[0071] And / or, the third ohmic contact layer 53 is located on part of the surface of the third region, and the first electrode 1 and the first resistive material layer 31 are electrically connected with the third semiconductor layer 23 through the third ohmic contact layer 53, thereby reducing the contact resistance between the first electrode 1 and the first ohmic contact region 121 and reducing the contact resistance between the first resistive material layer 31 and the first ohmic contact region 121;

[0072] And / or, the fourth ohmic contact layer 54 is located on part of the surface of the first region, and the first gate G1 and the second resistive material layer 32 are electrically connected with the first semiconductor layer 21 through the fourth ohmic contact layer 54, thereby reducing the contact resistance between the first gate G1 and the second ohmic contact region 122 and reducing the contact resistance between the second resistive material layer 32 and the second ohmic contact region 122;

[0073] And / or, the fifth ohmic contact layer 55 is located on part of the surface of the second region, and the second gate G2 is electrically connected with the second semiconductor layer 22 through the fifth ohmic contact layer 55, so as to reduce the contact resistance between the second gate G2 and the second semiconductor layer 22.

[0074] On the basis of the above-mentioned embodiments, with reference to Figure 2 Optionally, the cell structure further comprises a third insulating layer 60; the third insulating layer 60 is located on the side of the first resistive material layer 31, the second resistive material layer 32, the first gate G1 and the second gate G2 away from the first semiconductor body 10; the first electrode 1 is also located on the side of the third insulating layer 60 away from the first semiconductor body 10, and extends to the first ohmic contact region 121 along the side wall of the third insulating layer 60, the side wall of the first resistive material layer 31 and the side wall of the second semiconductor body 20. Among them, the third insulating layer 60 is used as an interlayer dielectric layer to electrically isolate the first electrode 1 from the first gate G1 and the second gate G2. The material of the third insulating layer 60 includes but is not limited to silicon oxide.

[0075] On the basis of the above-mentioned embodiments, optionally, the material of the first semiconductor body 10 is different from the material of the second semiconductor body 20; the material of the first semiconductor body 10 includes but is not limited to silicon carbide; and the material of the second semiconductor body 20 includes but is not limited to silicon.

[0076] On the basis of the above-mentioned embodiments, Figure 5 is another structure cross-sectional view of a semiconductor device provided by the embodiments of the present application, with reference to Figure 5 Optionally, the semiconductor device comprises at least two cell structures, and the two adjacent cell structures are mirror-symmetrical in the second direction Y.

[0077] Among them, the two adjacent cell structures share the same first gate G1; the first semiconductor of the two adjacent cell structures can share the same first electrode 1 and second electrode 2.

[0078] Further, the two adjacent cell structures are synchronously prepared and formed, that is, each same film layer in the two adjacent cell structures is synchronously prepared and formed.

[0079] With reference to Figure 4 The embodiments of the present application further provide a bridge circuit, comprising an upper bridge switching device unit 01 and a lower bridge switching device unit 02; the lower bridge switching device unit 02 comprises at least one semiconductor device according to any of the embodiments of the present application. Further, the upper bridge switching device unit 01 comprises at least one semiconductor device according to any of the embodiments of the present application.

[0080] If the half-bridge circuit is taken as an example, the semiconductor devices in the lower bridge switching device unit 02 include a junction field effect transistor J2 and a corresponding Miller clamp circuit, and the semiconductor devices in the upper bridge switching device unit 01 include a junction field effect transistor J1 and a corresponding Miller clamp circuit. The crosstalk current in the lower bridge transistor (junction field effect transistor J2) will first be divided on the first resistor R1 and the second resistor R2 to turn on the PNP-type BJT, and the gate and source terminals of the lower bridge transistor (junction field effect transistor J2) are short-circuited through the conduction channel provided by the PNP-type BJT, so that the lower bridge transistor (junction field effect transistor J2) is turned off, thereby preventing short circuit.

[0081] It should be noted that the above only describes the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, comprising at least one cell structure, the cell structure comprising: a first semiconductor body comprising oppositely arranged first and second surfaces; the first semiconductor body comprising a first and a second ohmic contact region of different conductivity types, both located at the first surface; the first semiconductor body further comprising a buried layer located at a side of the first and the second ohmic contact region close to the second surface; wherein the buried layer is of the same conductivity type as the second ohmic contact region; a second semiconductor body located at the first surface of the first semiconductor body; the second semiconductor body comprising a first semiconductor layer, a third semiconductor layer and a second semiconductor layer located between the first and the third semiconductor layer; wherein the first and the third semiconductor layer are of the same conductivity type as the second ohmic contact region; the second semiconductor layer is of the same conductivity type as the first ohmic contact region; a first electrode and a first gate; the first electrode is electrically connected to the first ohmic contact region and the third semiconductor layer, the first gate is electrically connected to the second ohmic contact region and the first semiconductor layer; a first resistive material layer, a second resistive material layer and a second gate; the second gate is located between the first resistive material layer and the second resistive material layer; wherein the second gate is electrically connected to the second semiconductor layer; the first resistive material layer is in contact with the second gate and the third semiconductor layer, the second resistive material layer is in contact with the second gate and the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein: the first semiconductor body further comprises a first JFET region extending along a first direction and a second JFET region extending along a second direction; the first direction and the second direction are perpendicular to each other, the first direction is a direction in which the first surface points to the second surface; wherein the first JFET region and the second JFET region are connected, and the second JFET region is located between the buried layer and the second ohmic contact region.

3. The semiconductor device according to claim 1, wherein: the first resistive material layer, the second resistive material layer and the second gate are all located at a side of the second semiconductor body away from the first semiconductor body; in the second semiconductor body, the second semiconductor layer is located at a surface of the first semiconductor layer close to the first semiconductor body and a sidewall of the first semiconductor layer; the third semiconductor layer is located at a surface of the second semiconductor layer close to the first semiconductor body and a sidewall of the second semiconductor layer away from the first semiconductor body.

4. The semiconductor device according to claim 3, wherein the surface of the second semiconductor body away from the first semiconductor body is a flat surface; the surface of the second semiconductor body away from the first semiconductor body comprises a first region surface, a third region surface and a second region surface located between the first region surface and the third region surface; The second region surface is a surface of the second semiconductor layer away from the first semiconductor body, the first region surface is a surface of the first semiconductor layer away from the first semiconductor body, and the third region surface is a surface of the third semiconductor layer away from the first semiconductor body; the second gate electrode is located on the second region surface, the first resistive material layer extends from the second gate electrode along the second region surface to cover a part of the third region surface, and the second resistive material layer extends from the second gate electrode along the second region surface to cover a part of the first region surface.

5. The semiconductor device of claim 1, wherein: the first electrode and the first gate electrode are located on opposite sides of the second semiconductor body; the semiconductor device further comprises a first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode and a sidewall of the second semiconductor body, and the second insulating layer is located between the first gate electrode and a sidewall of the second semiconductor body.

6. The semiconductor device of claim 4, wherein, The cell structure further comprises: a first ohmic contact layer located on a surface of the first ohmic contact region away from the second surface, the first electrode being electrically connected to the first ohmic contact region through the first ohmic contact layer; and / or a second ohmic contact layer located on a surface of the second ohmic contact region away from the second surface, the first gate electrode being electrically connected to the second ohmic contact region through the second ohmic contact layer; and / or a third ohmic contact layer located on a part of the third region surface, the first electrode being electrically connected to the third semiconductor layer through the third ohmic contact layer; and / or a fourth ohmic contact layer located on a part of the first region surface, the first gate electrode being electrically connected to the first semiconductor layer through the fourth ohmic contact layer; and / or a fifth ohmic contact layer located on a part of the second region surface, the second gate electrode being electrically connected to the second semiconductor layer through the fifth ohmic contact layer.

7. The semiconductor device of claim 3, wherein The cell structure further comprises: a third insulating layer located on a side of the first resistive material layer, the second resistive material layer, the first gate electrode and the second gate electrode away from the first semiconductor body; the first electrode is further located on a side of the third insulating layer away from the first semiconductor body, and extends to the first ohmic contact region along a sidewall of the third insulating layer, a sidewall of the first resistive material layer and a sidewall of the second semiconductor body.

8. The semiconductor device of claim 1, wherein The material of the first semiconductor body is different from the material of the second semiconductor body; The material of the first semiconductor body comprises silicon carbide, and the material of the second semiconductor body comprises silicon.

9. The semiconductor device of claim 1, wherein, The semiconductor device comprises at least two of the cell structures, and adjacent two of the cell structures are mirror symmetrical in a second direction.

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