Composite substrate, method for manufacturing the same, semiconductor device, and chip

Abstract

The disclosure provides a composite substrate and a preparation method thereof, a semiconductor device and a chip, and relates to the technical field of semiconductor chips, and aims to solve the problem that the on-resistance of the composite substrate is high due to the high bonding interface resistance after multiple substrates are bonded together. The composite substrate comprises a first substrate, a functional layer and a second substrate which are sequentially stacked; the first substrate and the second substrate are connected through the functional layer; wherein the resistivity of the material of the functional layer is less than or equal to 1x10 ‑4 Ω·cm.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a composite substrate and its preparation method, semiconductor devices, and chips. Background Technology

[0002] With the continuous development of semiconductor technology, composite substrate bonding technology has been widely used in the new energy field, such as power devices, photovoltaics, and solar cells. Composite substrate bonding technology involves bonding multiple substrates together to form a composite substrate. Under the influence of external energy, atoms at the interface of the composite substrate achieve vertical interconnection of multiple substrates through van der Waals forces, molecular forces, and even atomic forces, shortening the connection distance between substrates and reducing heat generation, power consumption, and latency.

[0003] However, in the existing technology, after multiple substrates are bonded together, the bonding interface resistance is high, which makes the on-resistance of the composite substrate high, thus affecting the electrical performance of the chip. Summary of the Invention

[0004] The embodiments of this disclosure provide a composite substrate and its preparation method, a semiconductor device, and a chip, aiming to solve the problem that the bonding interface resistance is high after multiple substrates are bonded together, resulting in high on-resistance of the substrate.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a composite substrate is provided, comprising: a first substrate, a functional layer, and a second substrate stacked sequentially. The first substrate and the second substrate are connected through the functional layer.

[0007] The resistivity of the material in the functional layer is less than or equal to 1×10⁻⁶. -4 Ω·cm.

[0008] In the composite substrate provided in the above embodiments of this disclosure, the functional layer not only connects the first substrate and the second substrate, but also acts as a bridge connecting the first substrate and the second substrate. This is achieved by setting the resistivity of the material of the functional layer to be less than or equal to 1×10⁻⁶. -4 The relatively low resistivity range of Ω·cm helps to reduce the resistance of the bonding interface between the first substrate, the second substrate and the functional layer, and helps to reduce the bonding interface resistance and the on-resistance of the entire composite substrate.

[0009] In some embodiments, the material of the functional layer includes: conductive oxide.

[0010] In some embodiments, the conductive oxide includes at least one of palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate, and strontium ruthenium oxide.

[0011] In some embodiments, the thickness of the functional layer ranges from 1 nm to 2000 nm.

[0012] In some embodiments, the resistivity of the interface between the first substrate and / or the second substrate and the functional layer is in the range of 1 × 10⁻⁶. -4 Ω·cm~4×10 -6 Ω·cm.

[0013] In some embodiments, there are multiple functional layers, and at least two of the multiple functional layers are made of different materials.

[0014] In some embodiments, the materials of the first substrate and / or the second substrate include at least one of the following: silicon substrate, silicon carbide substrate, gallium nitride substrate, gallium arsenide substrate, diamond substrate, gallium oxide substrate, aluminum nitride substrate, and indium phosphide substrate.

[0015] On the other hand, this disclosure provides a method for preparing a composite substrate. The method for preparing the composite substrate includes:

[0016] A functional layer is formed on one side of the first substrate.

[0017] The functional layer and the second substrate are bonded together to form the initial composite substrate.

[0018] The initial composite substrate is subjected to heat treatment to obtain the composite substrate.

[0019] It is understood that the beneficial effects that the composite substrate preparation method provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the composite substrate described above, and will not be repeated here.

[0020] In some embodiments, forming a functional layer on one side of the first substrate includes forming multiple functional layers on one side of the first substrate.

[0021] In some embodiments, bonding the functional layer and the second substrate to form an initial composite substrate includes:

[0022] Another functional layer is formed on the second substrate.

[0023] The functional layer and another functional layer on the second substrate are bonded together to form the initial composite substrate.

[0024] In some embodiments, a functional layer is formed on one side of the first substrate, including:

[0025] The target material of the functional layer is deposited onto the first substrate using magnetron sputtering.

[0026] In some embodiments, the gas pressure range for magnetron sputtering is 1 Pa to 10 Pa.

[0027] In some embodiments, the power range of magnetron sputtering is 100W to 5000W.

[0028] In some embodiments, the temperature range of magnetron sputtering is 20°C to 300°C.

[0029] In some embodiments, prior to bonding the functional layer and the second substrate, the process includes:

[0030] The surface of the functional layer and the surface of the second substrate near the functional layer are activated.

[0031] In some embodiments, the functional layer and the second substrate are bonded together, and the bonding pressure ranges from 500N to 5000N.

[0032] In some embodiments, the initial composite substrate is subjected to heat treatment at a temperature range of 200°C to 1000°C.

[0033] In another aspect, this disclosure provides a semiconductor device. The semiconductor device includes a composite substrate.

[0034] It is understood that the beneficial effects that the semiconductor devices provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the composite substrate mentioned above, and will not be repeated here.

[0035] In another aspect, this disclosure provides a chip. The chip includes: a semiconductor device.

[0036] It is understood that the beneficial effects that the chip provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the composite substrate mentioned above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0038] Figure 1 This is a schematic diagram of the structure of a chip according to some embodiments of the present disclosure;

[0039] Figure 2 This is a schematic diagram of the structure of a composite substrate according to some embodiments of the present disclosure;

[0040] Figure 3This is a schematic diagram of the structure of a composite substrate according to some embodiments of the present disclosure;

[0041] Figure 4 This is a schematic diagram of the structure of a composite substrate according to some embodiments of the present disclosure;

[0042] Figure 5 This is a flowchart illustrating a method for preparing a composite substrate according to some embodiments of the present disclosure;

[0043] Figure 6 This is a structural diagram corresponding to each step in the preparation method of a composite substrate according to Example 1 of this disclosure;

[0044] Figure 7 This is a structural diagram corresponding to each step in the preparation method of a composite substrate according to Example 2 of this disclosure;

[0045] Figure 8 This is a structural diagram corresponding to each step in the preparation method of a composite substrate according to Example 3 of this disclosure. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0052] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0053] The technical terms used in the embodiments of this application are explained below:

[0054] Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. When the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, this type of impurity semiconductor is also called a conductive semiconductor, for example, conductive silicon carbide material doped with nitrogen (N), boron (B), aluminum (Al), etc. Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this application, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0055] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0056] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0057] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0058] The technical solution of this application can be applied to electronic devices, such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices, as well as network devices such as base stations. The electronic device can also be a power amplifier or similar device used in the aforementioned electronic devices. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0059] Embodiments of this disclosure provide a chip 100. For example... Figure 1 As shown, the chip 100 includes a semiconductor device 10.

[0060] Understandably, chip 100 is part of an electronic device and serves as a carrier for integrated circuits. Semiconductor device 10 is a device with conductivity between that of a conductor and an insulator, which can be used to manufacture rectifiers, diodes, transistors, integrated circuits, etc.

[0061] Embodiments of this disclosure provide a semiconductor device 10. The semiconductor device 10 includes a substrate 1.

[0062] Understandably, in the semiconductor device 10, the substrate 1 is the foundation of the entire semiconductor device 10, carrying other film layers. These film layers are precisely fabricated on the substrate 1 through different process steps, such as epitaxial growth, ion implantation, photolithography and etching, to form a semiconductor device 10 with specific functions.

[0063] With the continuous development of semiconductor technology, composite substrate 1A bonding technology has been widely used. This technology bonds multiple substrates 1 together to form a composite substrate 1A. Under the influence of external energy, the atoms at the interface of the composite substrate 1A achieve vertical interconnection of multiple substrates 1 through van der Waals forces, molecular forces, and even atomic forces, thereby shortening the connection distance between substrates 1 and reducing heat generation, power consumption, and delay.

[0064] However, in the existing technology, after multiple substrates 1 are bonded together, the bonding interface resistance is high, which makes the on-resistance of the composite substrate 1A high, thus having a certain impact on the electrical performance of the chip 100.

[0065] Embodiments of this disclosure provide a composite substrate 1A. For example... Figure 2 As shown, the composite substrate 1A includes a first substrate 11, a functional layer 13, and a second substrate 12 stacked sequentially. The first substrate 11 and the second substrate 12 are connected through the functional layer 13.

[0066] The resistivity of the material in functional layer 13 is less than or equal to 1×10⁻⁶. -4 Ω·cm.

[0067] For example, the resistivity of the material of functional layer 13 can be 1×10⁻⁶.-4 Ω·cm, 0.5×10 -4 Ω·cm, 1×10 -5 Ω·cm, 0.5×10 -5 Ω·cm, 1×10 -6 Ω·cm or 0.5×10 -6 Ω·cm, etc., are not limited here.

[0068] Understandably, the functional layer 13 not only connects the first substrate 11 and the second substrate 12, but also acts as a bridge connecting the first substrate 11 and the second substrate 12. This is achieved by setting the resistivity of the material of the functional layer 13 to be less than or equal to 1×10⁻⁶. -4 The relatively low resistivity range of Ω·cm helps to reduce the resistance of the bonding interface between the first substrate 11, the second substrate 12 and the functional layer 13, and helps to reduce the bonding interface resistance and the on-resistance of the entire composite substrate 1A.

[0069] In some embodiments, the material of the functional layer 13 includes: conductive oxide.

[0070] Understandably, conductive oxides have high charge transport capabilities, which helps to effectively transport charges between the first substrate 11, the second substrate 12 and the functional layer 13, thereby reducing the on-resistance. Moreover, as a material for the functional layer 13, conductive oxides can improve the solid-solid contact interface between the first substrate 11, the second substrate 12 and the functional layer 13, which helps to reduce the interface resistance and reduce the interface barrier, thereby reducing the on-resistance of the composite substrate 1A.

[0071] In some embodiments, the conductive oxide includes at least one of palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate, and strontium ruthenium oxide.

[0072] Among them, palladium cobalt oxide has low resistivity and high stability.

[0073] Fluorine-doped tin oxide (FTO) is formed by doping tin oxide with fluorine. The doping of fluorine can significantly reduce the resistivity of tin oxide while maintaining its excellent transparency.

[0074] Among them, aluminum-doped zinc oxide (AZO) is an abbreviation for aluminum-doped zinc oxide transparent conductive glass, and aluminum-doped zinc oxide has a low resistivity.

[0075] Among them, tungsten-doped indium oxide increases the number of free charge carriers through doping, resulting in a lower resistivity.

[0076] Lanthanum nickelate can be crystallized more completely by adjusting the temperature, thereby reducing its resistivity.

[0077] Among them, strontium ruthenium ruthenium, under certain conditions, forms Cooper pairs of electrons that are not scattered by the crystal lattice, which allows the resistivity to be reduced to zero.

[0078] Therefore, by using at least one conductive oxide selected from palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate, and strontium ruthenate as the material of the functional layer 13, the resistance of the bonding interface between the first substrate 11, the second substrate 12, and the functional layer 13 can be further reduced, the interface barrier can be reduced, and thus the on-resistance of the composite substrate 1A can be reduced.

[0079] In some embodiments, the thickness of the functional layer 13 ranges from 1 nm to 2000 nm.

[0080] For example, the thickness of the functional layer 13 can be 1nm, 100nm, 300nm, 500nm, 700nm, 1000nm, 1200nm, 1400nm, 1600nm, 1800nm ​​or 2000nm, etc., and there is no limitation here.

[0081] Understandably, by setting the thickness of the functional layer 13 within the range of 1nm to 2000nm, good contact can be formed between the functional layer 13 and the first substrate 11 and the second substrate 12, reducing gaps and defects at the interface, thereby reducing interface resistance, and further reducing the resistance of the bonding interface and interface resistance, which helps to reduce the on-resistance of the entire composite substrate 1A.

[0082] In some embodiments, the combined resistivity of the interface between the first substrate 11 and / or the second substrate 12 and the functional layer 13 is in the range of 1 × 10⁻⁶. -4 Ω·cm~4×10 -6 Ω·cm.

[0083] For example, the resistivity of the interface between the first substrate 11 and the functional layer 13 can be 1×10⁻⁶. -4 Ω·cm, 1×10 -5 Ω·cm, 1×10 -6 Ω·cm, 2×10 -6 Ω·cm, 3×10 -6 Ω·cm or 4×10 -6 Ω·cm, etc., are not limited here.

[0084] For example, the resistivity of the interface between the second substrate 12 and the functional layer 13 can be 1 × 10⁻⁶. -4 Ω·cm, 1×10 -5 Ω·cm, 1×10 -6 Ω·cm, 2×10 -6 Ω·cm, 3×10 -6 Ω·cm or 4×10-6 Ω·cm, etc., are not limited here.

[0085] Understandably, by providing the first substrate 11 and / or the second substrate 12, the resistivity of the interface between the substrate and the functional layer 13 is 1×10⁻⁶. -4 Ω·cm~4×10 -6 Within the Ω·cm range, the resistivity of the bonding interface is low, which can effectively reduce the resistance encountered by the current when passing through these interfaces, thereby reducing the on-resistance of the entire composite substrate 1A.

[0086] In some embodiments, such as Figure 3 and Figure 4 As shown, there are multiple functional layers 13. At least two of the multiple functional layers 13 are made of different materials.

[0087] Understandably, the arrangement of multiple functional layers 13, with at least two functional layers 13 made of different materials, can further optimize the on-resistance of the entire composite substrate 1A; moreover, the combination of different materials may have different electrical properties, or the materials of different functional layers 13 may have different physical and chemical properties, which enables the composite substrate 1A to adapt to different application scenarios and broaden the scope of application of the composite substrate 1A.

[0088] In some embodiments, the first substrate 11 and / or the second substrate 12 include at least one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, an aluminum nitride substrate, and an indium phosphide substrate.

[0089] Understandably, silicon substrates possess excellent electrical conductivity and thermal stability. Silicon carbide substrates exhibit high thermal conductivity, high hardness, and chemical stability. Gallium nitride substrates offer advantages such as a large bandgap and high electron saturation mobility. Gallium arsenide substrates possess characteristics such as a direct bandgap and high electron mobility. Diamond substrates possess extremely high thermal conductivity and hardness. Gallium oxide substrates possess characteristics such as a wide bandgap and a high breakdown electric field. Aluminum nitride substrates possess characteristics such as high thermal conductivity, good mechanical properties, and chemical stability. Indium phosphide substrates possess characteristics such as a direct bandgap and high electron mobility. In practical applications, the unique physical and chemical properties of the first substrate 11 and / or the second substrate 12 can be used to suit different application scenarios, thus broadening the application range of the composite substrate 1A.

[0090] In some implementation methods, the existing bonding processes for composite substrates 1A mainly include: adhesive bonding, direct bonding, metal bonding, and hybrid metal dielectric bonding. Among them, direct bonding technology is widely used because it is applicable to materials with various crystal orientations, has a wide temperature range, high output per unit time, and can generally guarantee a certain bonding strength.

[0091] Plasma-activated bonding is a primary method in direct bonding. During this process, bonding occurs mainly through van der Waals forces and hydrogen bonds in hydroxyl groups. Finally, heat treatment removes water molecules to form covalent bonds, stabilizing the bond. However, before bonding, the hydroxyl content on the surface of the first substrate 11 or the second substrate 12 is low, making it difficult to provide sufficient hydroxyl groups for subsequent covalent bonding, leading to debonding. Furthermore, the oxide layer on the surface of the first substrate 11 or the second substrate 12 has residual pores and poor density. Water molecules that do not escape in time during subsequent annealing can combine with these pores to form bubbles, severely affecting the bonding quality of the composite substrate 1A.

[0092] Hybrid metal-dielectric bonding, through bumpless direct surface bonding, significantly increases interconnect density and reduces interconnect loss compared to traditional liquid phase bonding, making it a core technology for achieving three-dimensional heterogeneous integration. While surface activation bonding in hybrid metal-dielectric bonding can achieve bonding at room temperature, its activation process requires a high-temperature environment, placing stringent demands on the bonding equipment. Furthermore, while hot pressing has lower requirements for surface flatness, it must be completed at high temperatures and pressures and is inefficient.

[0093] Based on this, embodiments of the present disclosure provide a method for preparing a composite substrate 1A. For example... Figure 5 As shown, the preparation method of the composite substrate 1A includes: S1~S3.

[0094] S1: A functional layer 13 is formed on one side of the first substrate 11.

[0095] For example, the method for forming functional layer 13 can be any of magnetron sputtering, plasma-enhanced chemical vapor deposition, sol-gel method and atomic layer deposition.

[0096] S2: Bond the functional layer 13 and the second substrate 12 to form an initial composite substrate.

[0097] S3: Perform heat treatment on the initial composite substrate to obtain composite substrate 1A.

[0098] For example, the heat treatment can be carried out in an N2 atmosphere for a period of 1 to 2 hours.

[0099] Understandably, S1 allows the functional layer 13 to be attached to the first substrate 11. The functional layer 13 helps reduce the resistance of the bonding interface between the first substrate 11, the second substrate 12, and the functional layer 13, thereby reducing the bonding interface resistance and the overall on-resistance of the composite substrate 1A. S2 allows the first substrate 11, the second substrate 12, and the functional layer 13 to be stacked sequentially to form a stable initial composite substrate structure. S3 allows the bonding structure to be further strengthened through heat treatment, enabling the hydrophilic bonds between the first substrate 11 and the second substrate 12 on the initial composite substrate to form more covalent bonds.

[0100] For example, before forming the functional layer 13 on one side of the first substrate 11, the first substrate 11 and the second substrate 12 can be cleaned in sequence. The first substrate 11 and the second substrate 12 are cleaned in a first and second cleaning process to reduce residues on the first substrate 11 and the second substrate 12, thereby improving the unevenness of the first substrate 11 and the second substrate 12, increasing the vacuum adsorption force of the bonding machine chuck on the back side of the first substrate 11 and the second substrate 12, and improving the twist of the bonding between the first substrate 11 and the second substrate 12. During the first cleaning, the cleaning solution used includes any one or more combinations of hydrofluoric acid, nitric acid, phosphoric acid, and sulfuric acid, with the specific type selected according to the different residues. During the second cleaning, the cleaning solution used includes any one or more combinations of hydrofluoric acid, nitric acid, hydrochloric acid, hydrogen peroxide, and ammonia. The first cleaning mainly removes residual polysilicon and nitrides from the first substrate 11 and the second substrate 12, while the second cleaning mainly removes substances generated during the first cleaning process and metal ions that cannot be removed during the first cleaning.

[0101] This disclosure uses hydrophilic bonding in mixed metal dielectric bonding. The bonding conditions of hydrophilic bonding are mild and can be carried out in an atmospheric environment. The bonding mechanism is to form covalent bonds at the bonding interface by dehydration condensation (Si-OH+Si-OH→Si-O-Si+H2O) between hydrophilic groups on the surface of the dielectric material of the first substrate 11 or the second substrate 12. The metal pads are bonded by annealing diffusion.

[0102] For the composite substrate 1A with multiple functional layers 13,

[0103] In some embodiments, combined with Figure 7 S1 forms a functional layer 13 on one side of the first substrate 11, comprising:

[0104] A multilayer functional layer 13 is formed on one side of the first substrate 11.

[0105] Understandably, the above method can be used to prepare a composite substrate 1A with multiple functional layers 13. The material of each functional layer 13 is not limited and can be selected according to actual needs.

[0106] In some embodiments, combined with Figure 8 S2 bonds the functional layer 13 and the second substrate 12 to form an initial composite substrate, comprising:

[0107] Another functional layer 13 is formed on the second substrate 12.

[0108] The functional layer 13 is bonded to another functional layer 13 on the second substrate 12 to form an initial composite substrate.

[0109] Understandably, the above method can be used to prepare a composite substrate 1A with multiple functional layers 13. The material of each functional layer 13 is not limited and can be selected according to actual needs.

[0110] In some embodiments, S1 forms a functional layer 13 on one side of the first substrate 11, including:

[0111] The material of the functional layer 13 is deposited onto the first substrate 11 using a magnetron sputtering method.

[0112] For example, the gas pressure range of magnetron sputtering is 1 Pa to 10 Pa.

[0113] For example, the gas pressure in magnetron sputtering can be 1 Pa, 2 Pa, 4 Pa, 6 Pa, 8 Pa or 10 Pa, etc., and there is no limitation here.

[0114] For example, the power range of magnetron sputtering is 100W to 5000W.

[0115] For example, the power of magnetron sputtering can be 100W, 200W, 300W, 400W or 500W, etc., and there is no limit here.

[0116] For example, the temperature range of magnetron sputtering is 20°C to 300°C.

[0117] For example, the temperature for magnetron sputtering can be 20°C, 50°C, 100°C, 150°C, 200°C, 250°C, or 300°C, etc., and there is no limitation here.

[0118] For example, PdCoO2 is deposited as the material of functional layer 13 using magnetron sputtering. The thickness of functional layer 13 ranges from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used, and the vacuum is pre-evacuated to <5 × 10⁻⁶. -4Pa; Argon as carrier gas, flow rate 10 sccm~500 sccm; Oxygen flow rate 1 sccm~50 sccm; Total pressure 1 Pa~10 Pa; DC / RF power supply 100W~5000W; Temperature range 20℃~300℃. Immediately after sputtering, anneal in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at an annealing temperature range of 300℃~1000℃ to improve crystallinity and stoichiometry, and to avoid cracking caused by thermal stress from natural cooling.

[0119] In some implementations, from the perspective of the surface structure of hybrid metal dielectric bonding, the bonding region is mostly composed of dielectric material. Therefore, the mechanical strength of the bonding interface strongly depends on the bonding quality of the dielectric material. Improving the hydrophilicity of the dielectric material surface can increase the number of covalent bonds after bonding, thereby improving the bonding quality.

[0120] Therefore, in some embodiments, before bonding the functional layer 13 and the second substrate 12, the following steps are included:

[0121] The surface of the functional layer 13 and the surface of the second substrate 12 near the functional layer 13 are activated.

[0122] Understandably, activation treatment can improve the hydrophilicity of the surfaces of functional layer 13 and second substrate 12, promoting chemical bond formation. The surfaces of the first substrate 11 and the second substrate 12 to be bonded are subjected to plasma treatment; the plasma can be at least one of N2 plasma, O2 plasma, and Ar plasma.

[0123] For example, the conditions for surface activation treatment can be: power 10W~5000W, where higher power may damage the surface smoothness of the sample, and lower power may result in incomplete activation; pressure 2Pa~80Pa, where higher pressure may damage the sample surface, and lower pressure is difficult to implement; and time 1 minute~10 minutes, where longer activation time may cause surface damage and increase the surface roughness of the material, and shorter activation time may not be able to remove surface adsorbed contaminants.

[0124] In some embodiments, S2 bonds the functional layer 13 and the second substrate 12, with a bonding pressure ranging from 500N to 5000N.

[0125] For example, the bonding pressure can be 500N, 1000N, 2000N, 3000N, 4000N, or 5000N, etc., and there is no limitation here.

[0126] Understandably, a bonding pressure in the range of 500N to 5000N helps ensure close contact between the bonding interfaces of the first substrate 11, the second substrate 12 and the functional layer 13, promotes the formation of chemical bonds, helps to achieve higher bonding strength at lower pressure, and improves the bonding quality and stability of the composite substrate 1A.

[0127] In some embodiments, S3 heat-treats the initial composite substrate at a temperature range of 200°C to 1000°C.

[0128] For example, the heat treatment temperature can be 200℃, 300℃, 4000℃, 500℃, 600℃, 700℃, 800℃, 900℃ or 1000℃, etc., and there is no limitation here.

[0129] Understandably, setting the heat treatment temperature within the range of 200℃ to 1000℃ helps to improve the intermolecular interaction and bonding strength between the first substrate 11 and the second substrate 12 on the initial composite substrate, further enabling the hydrophilic bonding between the first substrate 11 and the second substrate 12 on the initial composite substrate to form more covalent bonds, achieving higher bonding strength, and improving the bonding quality and stability of the composite substrate 1A.

[0130] Here, the composite substrate 1A can also be a composite wafer formed by bonding the first wafer and the second wafer together. All descriptions of the composite substrate 1A in this disclosure can be equivalently replaced by the composite wafer. The first substrate 11 and the second substrate 12 can also be equivalently replaced by the first wafer and the second wafer. It should be noted that the composite substrate 1A or the composite wafer provided in this disclosure can be applied to the chip 100, or the composite substrate 1A or the composite wafer can be directly formed on the chip 100.

[0131] Example 1

[0132] Example 1 provides a composite substrate 1A. Combined with... Figure 6 The preparation method of the composite substrate 1A includes: 1D~5D.

[0133] 1D: Provide a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and perform two cleaning cycles on the first substrate 11.

[0134] 2D: A functional layer 13 is deposited on the surface of the first substrate 11 using magnetron sputtering. The material of the functional layer 13 is PdCoO2, and the thickness ranges from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5 × 10⁻⁶. -4Pa; Argon as carrier gas, flow rate 10 sccm~500 sccm; Oxygen flow rate 1 sccm~50 sccm; Total pressure 1 Pa~10 Pa; DC / RF power supply 100W~5000W; Temperature range 20℃~300℃. Immediately after sputtering, anneal in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at an annealing temperature range of 300℃~1000℃. The surface of functional layer 13 is subjected to plasma treatment.

[0135] 3D: A second substrate 12 is provided, which is a 6-inch gallium nitride substrate. The second substrate 12 is cleaned twice in sequence. The bonding surface of the second substrate 12 is subjected to plasma treatment.

[0136] 4D: After aligning the surfaces of the first substrate 11, the functional layer 13, and the bonding interface of the second substrate 12, apply a pressure of 500N~5000N to bring the bonding interface areas of the first substrate 11, the functional layer 13, and the second substrate 12 into contact, forming an initial composite substrate.

[0137] 5D: The initial composite substrate was annealed in an N2 atmosphere at a temperature of 200℃~1000℃ for 1h~2h to obtain composite substrate 1A.

[0138] Example 2

[0139] Example 2 provides a composite substrate 1A. Combined with... Figure 7 The preparation method of the composite substrate 1A includes: 1B~5B.

[0140] 1B: Provide a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and perform two cleaning cycles on the first substrate 11.

[0141] 2B: Three functional layers 13 are deposited on the surface of the first substrate 11 using magnetron sputtering. The material of the functional layers 13 is PdCoO2, and the thickness ranges from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5 × 10⁻⁶. -4 Pa; Argon as carrier gas, flow rate 10 sccm~500 sccm; Oxygen flow rate 1 sccm~50 sccm; Total pressure 1 Pa~10 Pa; DC / RF power supply 100W~5000W; Temperature range 20℃~300℃. Immediately after sputtering, anneal in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at an annealing temperature range of 300℃~1000℃. The surface of functional layer 13 is subjected to plasma treatment.

[0142] 3B: A second substrate 12 is provided, which is a 6-inch GaN substrate. The second substrate 12 is cleaned twice in sequence. The bonding surface of the second substrate 12 is subjected to plasma treatment.

[0143] 4B: After aligning the surfaces of the first substrate 11, the functional layer 13, and the bonding interface of the second substrate 12, apply a pressure of 500N to 5000N to bring the bonding interface areas of the first substrate 11, the functional layer 13, and the second substrate 12 into contact to form an initial composite substrate.

[0144] 5B: The initial composite substrate was annealed in an N2 atmosphere at a temperature of 200℃~1000℃ for 1h~2h to obtain composite substrate 1A.

[0145] Example 3

[0146] Example 3 provides a composite substrate 1A. Combined with... Figure 8 The preparation method of the composite substrate 1A includes: 1C~6C.

[0147] 1C: Provide a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and perform two cleaning cycles on the first substrate 11.

[0148] 2C: A single functional layer 13 is deposited on the surface of the first substrate 11 using magnetron sputtering. The material of the functional layer 13 is PdCoO2, and the thickness of the functional layer 13 ranges from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5 × 10⁻⁶. -4 Pa; Argon as carrier gas, flow rate 10 sccm~500 sccm; Oxygen flow rate 1 sccm~50 sccm; Total pressure 1 Pa~10 Pa; DC / RF power supply 100W~5000W; Temperature range 20℃~300℃. Immediately after sputtering, anneal in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at an annealing temperature range of 300℃~1000℃. The surface of functional layer 13 is subjected to plasma treatment.

[0149] 3C: Provide a second substrate 12, which is a 6-inch GaN substrate, and perform two cleaning cycles on the second substrate 12.

[0150] 4C: A monolayer functional layer 13 is deposited on the surface of the second substrate 12 using magnetron sputtering. The material of the functional layer 13 is PdCoO2, with a thickness ranging from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1), or PdCoO2 targets are used. The vacuum is pre-evacuated to <5 × 10⁻⁶. -4Pa; Argon as carrier gas, flow rate 10 sccm~500 sccm; Oxygen flow rate 1 sccm~50 sccm; Total pressure 1 Pa~10 Pa; DC / RF power supply 100W~5000W; Temperature range 20℃~300℃. Immediately after sputtering, anneal in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at an annealing temperature range of 300℃~1000℃. The surface of functional layer 13 is subjected to plasma treatment.

[0151] 5C: After aligning the surfaces of the first substrate 11, the functional layer 13, and the bonding interface of the second substrate 12, apply a pressure of 500N to 5000N to bring the bonding interface areas of the first substrate 11, the functional layer 13, and the second substrate 12 into contact, forming an initial composite substrate.

[0152] 6C: The initial composite substrate was annealed in an N2 atmosphere at a temperature of 200℃~1000℃ for 1h~2h to obtain composite substrate 1A.

[0153] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A composite substrate, characterized in that, include: A first substrate, a functional layer, and a second substrate are stacked sequentially. The first substrate and the second substrate are connected through the functional layer; The first substrate and / or the second substrate include at least one of the following: a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, and an indium phosphide substrate; Wherein, the resistivity of the material of the functional layer is less than or equal to 1×10⁻⁶. -4 Ω·cm; the number of functional layers is multiple, and at least two of the multiple functional layers are made of different materials; the materials of the functional layers include at least one of palladium cobalt oxide, fluorine-doped tin oxide, lanthanum nickelate, and strontium ruthenium terephthalate; The first substrate and the second substrate are connected to the functional layer by covalent bonds.

2. The composite substrate according to claim 1, characterized in that, The thickness of the functional layer ranges from 1 nm to 2000 nm.

3. The composite substrate according to claim 1, characterized in that, The resistivity of the interface between the first substrate and / or the second substrate and the functional layer is in the range of 1 × 10⁻⁶. -4 Ω·cm~4×10 -6 Ω·cm.

4. A method for preparing a composite substrate, characterized in that, include: A functional layer is formed on one side of a first substrate, and there are multiple functional layers, at least two of which are made of different materials; The first substrate includes at least one of the following: a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, and an indium phosphide substrate; the material of the functional layer includes at least one of the following: palladium cobalt oxide, fluorine-doped tin oxide, lanthanum nickelate, and strontium ruthenium oxide. The functional layer and the second substrate are bonded together to form an initial composite substrate; the second substrate includes at least one of the following: a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, and an indium phosphide substrate. The initial composite substrate is heat-treated to obtain the composite substrate; the first substrate and the second substrate are connected to the functional layer by covalent bonds.

5. The method for preparing the composite substrate according to claim 4, characterized in that, The step of bonding the functional layer and the second substrate to form an initial composite substrate includes: Another functional layer is formed on the second substrate; The functional layer and the other functional layer on the second substrate are bonded together to form an initial composite substrate.

6. The method for preparing the composite substrate according to claim 4, characterized in that, The formation of a functional layer on one side of the first substrate includes: The material of the functional layer is deposited onto a first substrate using a magnetron sputtering method.

7. The method for preparing the composite substrate according to claim 6, characterized in that, The gas pressure range of the magnetron sputtering method is 1 Pa to 10 Pa; and / or, the power range is 100 W to 5000 W; and / or, the temperature range is 20 °C to 300 °C.

8. The method for preparing the composite substrate according to claim 4, characterized in that, Before bonding the functional layer and the second substrate, the process includes: The surface of the functional layer and the surface of the second substrate near the functional layer are activated.

9. The method for preparing the composite substrate according to claim 4, characterized in that, The functional layer and the second substrate are bonded together, and the bonding pressure range is 500N~5000N.

10. The method for preparing the composite substrate according to claim 4, characterized in that, The initial composite substrate is subjected to heat treatment, and the temperature range of the heat treatment is 200℃~1000℃.

11. A semiconductor device, characterized in that, include: The composite substrate as described in any one of claims 1 to 3.

12. A chip, characterized in that, include: The semiconductor device as described in claim 11.

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