CMOS image sensor and forming method thereof
By adopting a multi-layer substrate structure and trench isolation technology in CMOS image sensors, the dark current problem caused by substrate leakage paths is solved, achieving higher sensor performance and reliability.
Patent Information
- Application Number
- CN202410217152.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-09-05
AI Technical Summary
In existing CMOS image sensors, there is a leakage path from other areas of the substrate to the photodiode area, which causes dark current to affect sensor performance.
A multi-layer substrate structure is adopted, including a lower substrate layer, a buried oxide layer and an upper substrate layer. By forming a trench isolation structure and a light-blocking structure in the substrate, the photodiode and the MOS device are isolated, and the buried oxide layer is used to block substrate current leakage and reduce dark current.
It effectively blocks the leakage of substrate current of MOS devices to the photodiode area, reduces dark current, and improves the performance and reliability of the sensor.
Smart Images
Figure CN120603344A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image sensors, and in particular to a CMOS image sensor and a method for forming a CMOS image sensor. Background Art
[0002] CMOS image sensors are widely used in various imaging fields due to their low noise, high integration, and low cost. In the pixel area of a currently used CMOS image sensor, the various electronic components are arranged in a two-dimensional plane on the substrate surface. The photodiode, floating diffusion, and multiple MOS devices (such as transfer transistors, reset transistors, source follower transistors, and row select transistors) share a common substrate. Shallow trench isolation (STI) and well isolation are typically used to isolate components that require substrate isolation.
[0003] However, in the above-mentioned existing CMOS image sensors, there is still a leakage path from other areas of the substrate to the photodiode area, and the resulting dark current will affect the performance of the sensor. Summary of the Invention
[0004] In order to block the leakage path of a CMOS image sensor, reduce leakage current, and improve sensor performance, the present invention provides a CMOS image sensor and a method for forming the CMOS image sensor.
[0005] In one aspect, the present invention provides a CMOS image sensor, comprising:
[0006] A substrate having a front side and a back side facing each other, and comprising a lower substrate layer, a buried oxide layer, and an upper substrate layer stacked in sequence from the back side to the front side, wherein a pixel region is arranged on the substrate, and a groove is provided in the pixel region to expose the lower substrate layer;
[0007] a first element region comprising a photodiode and a floating diffusion region disposed within the exposed lower substrate layer, and a transfer gate electrode structure disposed on the exposed lower substrate layer and between the photodiode and the floating diffusion region, wherein the photodiode is configured to sense radiation entering the lower substrate layer from the back surface; and
[0008] The second element region includes a plurality of MOS devices, wherein the MOS devices have a gate electrode structure arranged on the front side and source / drain regions arranged in the upper substrate layer on both sides of the gate electrode structure.
[0009] Optionally, the CMOS image sensor further includes:
[0010] A first trench isolation structure defines a plurality of active areas on the upper substrate layer, and the first trench isolation structure penetrates the upper substrate layer.
[0011] Optionally, the CMOS image sensor further includes:
[0012] The second trench isolation structure is located between the first element region and the second element region and is a sidewall of the groove. The second trench isolation structure extends from the front surface of the substrate to the lower substrate layer.
[0013] Optionally, the trench isolation structure further includes:
[0014] A third trench isolation structure is located between the first element region and the second element region and surrounds the first element region. The third trench isolation structure extends from the back side into the lower substrate layer.
[0015] Optionally, at various locations in a circumferential direction of the first element region, the second trench isolation structure and the third trench isolation structure are joined in the lower substrate layer.
[0016] Optionally, the plurality of MOS devices in the second element region include source follower transistors, reset transistors and row selection transistors.
[0017] Optionally, the CMOS image sensor further includes a plurality of conductive plugs and a conductive interconnect structure arranged on the front side, wherein the plurality of conductive plugs are respectively connected to the transfer gate electrode structure, the floating diffusion region, and the gate electrode structure and source / drain region of the MOS device, and the conductive interconnect structure is connected to each of the conductive plugs.
[0018] Optionally, the CMOS image sensor further includes:
[0019] a back dielectric layer covering the substrate from the back side; and
[0020] A light-blocking structure is provided on a side of the back dielectric layer away from the substrate, and the light-blocking structure comprises a metal grid surrounding the first element region.
[0021] In another aspect, the present invention provides a method for forming a CMOS image sensor, the method comprising:
[0022] Providing a substrate, the substrate having a front side and a back side opposite to each other, and comprising a lower substrate layer, a buried oxide layer, and an upper substrate layer stacked in sequence from the back side to the front side, wherein a pixel area is arranged on the substrate;
[0023] forming a groove in the pixel area to expose the lower substrate layer;
[0024] doping the exposed lower substrate layer to form a photodiode for sensing radiation entering the lower substrate layer from the back surface;
[0025] forming a transmission gate electrode structure on the exposed lower substrate layer, and forming a gate electrode structure of a plurality of MOS devices on the upper substrate layer, wherein the photodiode is located on one side of the transmission gate electrode structure; and
[0026] The upper substrate layer and the lower substrate layer are doped to form a floating diffusion region in the lower substrate layer located on the side opposite to the transmission gate electrode structure and the photodiode, and to form a source / drain region in the upper substrate layer located on both sides of the gate electrode structure of the plurality of MOS devices.
[0027] Optionally, before forming the groove, the forming method further includes:
[0028] A first trench isolation structure and a second trench isolation structure are formed extending from the substrate front to the lower substrate layer, wherein the first trench isolation structure defines a plurality of active areas in the upper substrate layer, and the second trench isolation structure defines a substrate region to expose the lower substrate layer.
[0029] Optionally, after forming the floating diffusion region and the source / drain region, the forming method further includes:
[0030] forming a trench extending from the back surface into the lower substrate layer, wherein the trench is aligned with the second trench isolation structure in a normal direction of the substrate; and
[0031] An isolation material is filled in the trench to form a third trench isolation structure.
[0032] Optionally, the trench exposes the isolation material in the second trench isolation structure, and the second trench isolation structure and the third trench isolation structure are bonded in the substrate.
[0033] Optionally, after forming the third trench isolation structure, the forming method further includes:
[0034] Covering the back side of the substrate with a back dielectric layer; and
[0035] A light-blocking structure is formed on a side of the back dielectric layer away from the substrate. The light-blocking structure includes a metal grid. The metal grid surrounds the region where the photodiode, the transmission gate electrode structure, and the floating diffusion region are formed from the back.
[0036] In the CMOS image sensor and the method for forming a CMOS image sensor provided by the present invention, the lower substrate layer and the upper substrate layer of the substrate are used to respectively form the components of the pixel area, wherein the photodiode, the floating diffusion region, and the transfer gate electrode structure are formed in the lower substrate layer exposed by the groove, and multiple MOS devices are formed in the upper substrate layer. A buried oxide layer is provided between the upper substrate layer and the lower substrate layer. When the CMOS image sensor is in operation, the buried oxide layer can block the substrate current of the multiple MOS devices from leaking to the photodiode area, thereby helping to reduce dark current and improve sensor performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 This is a schematic diagram of a pixel circuit with a 4T-APS structure.
[0038] Figure 2 FIG. 4 is a flow chart of a method for forming a CMOS image sensor according to an embodiment of the present invention.
[0039] Figures 3A to 3I FIG. 4 is a cross-sectional diagram of a method for forming a CMOS image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION
[0040] The following describes the CMOS image sensor and its method of formation in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in this specification are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps must be performed; some steps may be omitted and / or additional steps not described herein may be added to the method.
[0041] The embodiment of the present invention relates to a CMOS image sensor and a method for forming a CMOS image sensor. The CMOS image sensor is, for example, Figure 1The 4T-APS pixel circuit shown includes four transistors (i.e., 4T): a transfer transistor (corresponding to a transfer gate electrode TX) for transferring photoelectric charge formed by a photodiode to a floating diffusion region FD; a reset transistor (corresponding to a gate electrode RST) for controlling the resetting of the floating diffusion region FD; a source follower transistor (corresponding to a gate electrode SF) for converting a signal voltage of the floating diffusion region FD into an image voltage signal; and a row select transistor (corresponding to a gate electrode SEL) for outputting the image voltage signal to a pixel-level connection structure (e.g., a bit line). However, the CMOS image sensor of the present invention is not limited to a pixel circuit employing a 4T-APS structure. Instead, a pixel circuit of a corresponding structure may be employed based on actual circuit design. For example, the pixel circuit of the CMOS image sensor may also include more transistors than a 4T-APS structure, such as a 5T-APS structure or an 8T-APS structure.
[0042] The following combination Figure 2 as well as Figures 3A to 3I A method for forming a CMOS image sensor according to an embodiment of the present invention will be described.
[0043] Figure 3A The cross-sectional structure of a part of the substrate is shown. Figure 2 and Figure 3A According to a method for forming a CMOS image sensor according to an embodiment of the present invention, step S1 is first performed: providing a substrate 100, wherein the substrate 100 has a front side 100a and a back side 100b opposite to each other, and comprises a lower substrate layer 101, a buried oxide layer 102 (buried oxide), and an upper substrate layer 103 stacked in sequence from the back side 100b to the front side 100a, and a pixel region is arranged on the substrate 100. In the following embodiments, the substrate 100 is, for example, an SOI (Silicon On Insulator) substrate, wherein the lower substrate layer 101 and the upper substrate layer 103 are both silicon layers, and the buried oxide layer 102 is a silicon oxide layer, but the present invention is not limited thereto. For example, in another embodiment, the substrate 100 is a GOI (Germanium On Insulator) substrate, wherein the upper substrate layer 103 is a germanium layer.
[0044] The thickness of the buried oxide layer 102 is, for example, in the range of 0.1 μm to 5 μm. In this embodiment, the thickness of the lower substrate layer 101 is, for example, greater than the thickness of the upper substrate layer 103. The front side 100a of the substrate 100 is the surface of the upper substrate layer 103 away from the lower substrate layer 101, and the back side 100b of the substrate 100 is the surface of the lower substrate layer 101 away from the upper substrate layer 103. It will be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.
[0045] The pixel region arranged on the substrate 100 is used to form pixels of a CMOS image sensor. Figure 3A The cross section shown only shows a single pixel region. It can be understood that the substrate 100 can be arranged with multiple pixel regions, and the process described below can be applied to a part or all of the pixel regions.
[0046] Figure 3B FIG shows a cross-sectional structure after forming the first trench isolation structure 110 and the second trench isolation structure 120 from the front surface 100a of the substrate 100. Figure 3B In this embodiment, before subsequent steps are performed, a first trench isolation structure 110 and a second trench isolation structure 120 are formed on the front surface of the substrate 100. The first trench isolation structure 110 defines a plurality of active regions on the upper substrate layer 103, which can be used to form MOS devices, etc. The second trench isolation structure 120 defines a region of the substrate 100 where the lower substrate layer 101 is to be exposed.
[0047] The first trench isolation structure 110 and the second trench isolation structure 120 are, for example, shallow trench isolation (STI) structures. To simplify the process, the first trench isolation structure 110 and the second trench isolation structure are formed using the same trench isolation process. Both extend from the front surface 100a of the substrate 100 into the lower substrate layer 101, and both have the same depth within the substrate 100. In other embodiments, the first trench isolation structure 110 and the second trench isolation structure 120 may have different depths within the substrate 100. For example, in one embodiment, the first trench isolation structure 110 extends from the front surface 100a of the substrate 100 into the buried oxide layer 102, while the second trench isolation structure 120 extends from the front surface 100a of the substrate 100 into the lower substrate layer 101.
[0048] Figure 3C FIG. 4 shows a cross-sectional structure after forming the groove 10. Figure 2 and Figure 3C , executing step S2, forming a groove 10 exposing the lower substrate layer 101 in the pixel area.
[0049] The recess 10 can be formed using photolithography and etching processes. In this embodiment, the upper substrate layer 103 and the buried oxide layer 102 surrounded by the second trench isolation structure 120 are removed by photolithography and dry or wet etching, thereby exposing the lower substrate layer 101. The sidewalls of the recess 10 are the second trench isolation structure 120, and the bottom surface of the recess 10 is the exposed surface of the lower substrate layer 101 facing the front surface 100a of the substrate 100 (i.e., the top surface of the lower substrate layer 101).
[0050] Figure 3D FIG. 1 shows the cross-sectional structure of the exposed lower substrate layer 101 after doping. Figure 2 and Figure 3D , performing step S3: doping the exposed lower substrate layer 101 to form a photodiode PD for sensing radiation entering the lower substrate layer 101 from the back side 100 b of the substrate 100 .
[0051] When performing step S3, a patterned mask layer may be formed on the substrate 100 to selectively dope the lower substrate layer 101 exposed by the groove 10. Figure 3D As shown, as an example, in step S3, a p-type well region is first implanted on the entire area of the exposed lower substrate layer 101, and then an n-type implant is performed on a portion of the exposed lower substrate layer 101. After heat treatment, a p-type well region 104 extending from the top surface of the lower substrate layer 101 to the interior of the lower substrate layer 101 and an n-type doped region located within the p-type well region 104 are formed. The n-type doped region and the adjacent p-type well region 104 constitute a PN junction type photodiode PD. In addition, a p-type implant can be performed on the top of the p-type well region 104 to form a p-type heavily doped region (not shown), and the n-type doped region is located below the p-type heavily doped region. In some embodiments, if the entire lower substrate layer 101 has p-type doping, the p-type well region implantation may not be performed. The present invention does not impose any special restrictions on the doping method of the photodiode PD in step S3, which can be selected according to actual conditions. For example, in other embodiments, the lower substrate layer 101 as a whole has n-type doping or an n-type well region is formed in the exposed lower substrate layer 101 through n-type well region injection, and a p-type doping region is formed through p-type injection, so that the p-type doping region and the adjacent lower substrate layer 101 region or n-type well region constitute a photodiode PD.
[0052] Figure 3E FIG shows a cross-sectional structure after forming a gate electrode structure. Figure 2 and Figure 3E, executing step S4: forming a transmission gate electrode structure on the exposed lower substrate layer 101, and forming a gate electrode structure of multiple MOS devices on the upper substrate layer 103, wherein the photodiode PD is located on one side of the transmission gate electrode structure.
[0053] In this embodiment, Figure 1 The transfer transistor and the floating diffusion region FD in the pixel circuit shown are arranged on the surface area of the lower substrate layer 101 exposed by the groove 10, while the other transistors in the pixel circuit are arranged on the surface area of the upper substrate layer 103. In step S4, a gate oxide layer 130 is first formed on the surface of the upper substrate layer 103 and the surface of the lower substrate layer 101 exposed by the groove 10; then a gate material layer is deposited, and a photolithography and etching process is performed to pattern the gate material layer and the gate oxide layer 130. A transfer gate electrode TX is formed by the gate material layer on the surface of the gate oxide layer 130 on the lower substrate layer 101, and gate electrodes of multiple MOS devices (such as ) are formed on the surface of the gate oxide layer 130 on the upper substrate layer 103. Figure 3E The MOS device 100 is formed by forming a gate electrode SF, a gate electrode SEL, and a gate electrode RST (shown in the figure); then, using a spacer process, spacers SP are formed on the sides of the transmission gate electrode TX and on the sides of the gate electrodes of the multiple MOS devices, thereby obtaining a transmission gate electrode structure and a gate electrode structure of the multiple MOS devices. During or after forming the spacers SP, LDD ion implantation can be performed to form LDD regions (not shown) in the upper substrate layer 103 on both sides of the gate electrodes of the multiple MOS devices.
[0054] like Figure 3E As shown, the multiple MOS devices to be formed on the upper substrate layer 103 may include a source follower transistor, a reset transistor and a row selection transistor. Figure 1 Taking the 4T-APS structure shown as an example, the source follower transistor, reset transistor, and row select transistor in the pixel circuit are all formed on the upper substrate layer 103. In step S4, the gate electrode structures of the source follower transistor, the reset transistor, and the row select transistor are formed on the upper substrate layer 103. The gate electrode SF, the gate electrode SEL, and the gate electrode RST are the gate electrodes of the source follower transistor, the row select transistor, and the reset transistor, respectively. The upper substrate layer 103 below the gate electrode structure of the reset transistor and the gate electrode structure of the row select transistor is isolated by a first isolation structure 110.
[0055] Figure 3F FIG shows a cross-sectional structure after a floating diffusion region FD is formed on the lower substrate layer 101 and a source / drain region is formed on the upper substrate layer 103. Figure 2 and Figure 3F, perform step S5: doping the upper substrate layer 103 and the lower substrate layer 101 to form a floating diffusion region FD in the lower substrate layer 101 located on the side opposite to the transmission gate electrode structure and the photodiode, and forming source / drain regions (S / D, forming a source region (S) on one side of the same gate electrode and a drain region (D) on the other side) in the upper substrate layer 103 located on both sides of the gate electrode structure of the plurality of MOS devices.
[0056] As an example, the floating diffusion region FD and the source / drain regions can be formed by performing n-type ion implantation on the upper substrate layer 103 and the lower substrate layer 101 from the side where the gate electrode structure is formed, followed by heat treatment. Before performing the n-type ion implantation, a patterned mask layer is formed on the substrate 100, so that the mask layer covers the substrate 100 region other than the region where the floating diffusion region FD and the source / drain regions are formed (such as the region of the lower substrate layer 101 where the photodiode PD is formed). The present invention is not limited to this. Depending on the specific design of the pixel circuit, the doping type of the floating diffusion region FD and the source / drain region may also differ from the above example. For example, in some embodiments, the floating diffusion region FD and the source / drain region may be a heavily p-type doped region formed by p-type ion implantation.
[0057] After the above steps, components of the pixel region are formed on the lower substrate layer 101 and the upper substrate layer 103 of the substrate, respectively. The photodiode, floating diffusion region FD, and transfer gate electrode structure are formed on the lower substrate layer 101, constituting the first component region I of the pixel region. Multiple MOS devices are formed on the upper substrate layer 103, constituting the second component region II of the pixel region. The multiple MOS devices formed on the upper substrate layer 103 are, for example, fully depleted MOS transistors.
[0058] Figure 3G FIG shows a cross-sectional structure after forming a conductive plug CT and a conductive interconnect structure 140. Figure 3G The method for forming a CMOS image sensor of this embodiment may further include the following process: forming a plurality of conductive plugs CT and a conductive interconnect structure 140 on the front surface 100a of the substrate 100, wherein the plurality of conductive plugs CT are respectively connected to the transfer gate electrode structure, the floating diffusion region FD, and the gate electrode structure and source / drain regions of each MOS device; the conductive interconnect structure 140 is located above each of the conductive plugs CT and is respectively connected to each of the conductive plugs CT; the plurality of conductive plugs CT and the conductive interconnect structure 140 are surrounded by a front dielectric layer 150, and the front dielectric layer 150 fills the recess 10.
[0059] The conductive interconnect structure 140 can interconnect the components of the first element area I and the second element area II according to the specific circuit design of the sensor. As an example, the CMOS image sensor of this embodiment adopts the following Figure 1 The pixel circuit shown utilizes the conductive interconnect structure 140 to electrically connect the floating diffusion region FD, a source / drain region of the reset transistor, and the gate electrode SF of the source follower transistor according to the circuit design, connect the other source / drain region of the reset transistor to the power supply terminal, connect one source / drain region of the source follower transistor to the power supply terminal and the other source / drain region to a source / drain region of the row selection transistor, connect the other source / drain region of the row selection transistor to the bit line, and connect the transmission gate electrode TX, the gate electrode RST of the reset transistor, and the gate electrode SEL of the row selection transistor to the corresponding lead-out pads, respectively.
[0060] Figure 3H FIG. 2 shows a cross-sectional structure after forming the third trench isolation structure 160 from the back side 100b of the substrate 100. Figure 3H In this embodiment, after completing the processing on the front side 100a of the substrate 100, a carrier substrate (not shown) is bonded to the front side 100a of the substrate 100 to facilitate processing on the back side 100b of the substrate 100. Specifically, the processing on the back side 100b of the substrate 100 includes forming a trench extending from the back side 100b of the substrate 100 into the lower substrate layer 101. The trench surrounds the first device region I from the back side 100b of the substrate 100, and the trench is aligned with the second trench isolation structure 120, for example, in the normal direction of the substrate 100. Thereafter, the trench is filled with an isolation material to form a third trench isolation structure 160. The third trench isolation structure 160 is, for example, a deep trench isolation (DTI). By forming the third trench isolation structure 160, the first component region I and the second component region II are isolated not only by the second trench isolation structure 120 formed on the front surface 100a of the substrate 100, but also by the third trench isolation structure 160 formed on the back surface 100b of the substrate 100. This effectively blocks leakage paths between components in the first component region I and components in the second component region II within the substrate 100, helping to reduce leakage current and improve sensor reliability. Optionally, the trench exposes the isolation material in the second trench isolation structure 120. After the third trench isolation structure 160 is formed corresponding to the trench, the second trench isolation structure 120 and the third trench isolation structure 160 are joined within the substrate 100. Thus, the second trench isolation structure 120 and the third trench isolation structure 160 form a complete physical isolation between the first component region I and the second component region II within the substrate 100, further reducing leakage current and improving sensor reliability.
[0061] Figure 3I This is the cross-sectional structure after the back dielectric layer 170 and the light-blocking structure 180 are formed. Figure 3I After forming the third trench isolation structure 160, the method for forming a CMOS image sensor in this embodiment may further include the following steps: forming a back dielectric layer 170 covering the back side 100b of the substrate 100; then, forming a light-blocking structure 180 on a side of the back dielectric layer 170 facing away from the substrate 100. The light-blocking structure 180 includes a metal grid MG that surrounds the first device region I from the back side 100b. Specifically, the metal grid MG surrounds the region of the substrate 100 where the photodiode, the transfer gate electrode structure, and the floating diffusion region FD are formed from the back side 100b. In this embodiment, the second trench isolation structure 120, the third trench isolation structure 160, and the metal grid MG located outside the first device region I are aligned, for example, in a direction normal to the substrate 100. The metal grid MG is made of a material with excellent light-isolating properties, such as tungsten. The light-blocking structure 180 may also include a dielectric material covering the metal grid MG. In this embodiment, the light-blocking structure 180 is used to prevent the radiation irradiated to the region where the photodiode is located from spreading to the pixel region outside the first device region I or to the adjacent pixel region.
[0062] The CMOS image sensor of the embodiment of the present invention can be formed using the formation method described in the above embodiment. The CMOS image sensor can have a wafer-level or chip-level size. The CMOS image sensor can be a bonded wafer structure obtained by the above formation method, or a chip or module obtained by further performing a semiconductor dicing process and packaging on the bonded wafer structure.
[0063] Reference Figure 3I According to an embodiment of the present invention, a CMOS image sensor includes a substrate 100 and a first element region I and a second element region II; the substrate 100 has a front surface 100a and a back surface 100b opposite to each other, and includes a lower substrate layer 101, a buried oxide layer 102, and an upper substrate layer 103 stacked in sequence from the back surface 100b to the front surface 100a; the substrate 100 is provided with a pixel region, and in the pixel region, the substrate 100 has a groove 10 exposing the lower substrate layer 101 (refer to Figure 3C); the first element region I includes a photodiode PD and a floating diffusion region FD disposed within the exposed lower substrate layer 101, and also includes a transfer gate electrode structure disposed on the exposed lower substrate layer 101 and located between the photodiode PD and the floating diffusion region FD. The photodiode PD is configured to sense radiation entering the lower substrate layer 101 from the back surface 100b of the substrate 100; the second element region II includes a plurality of MOS devices, each having a gate electrode structure disposed on the front surface 100a of the substrate 100 and source / drain regions disposed within the upper substrate layer 103 on both sides of the gate electrode structure. A p-type well region 104 may be formed around the photodiode PD.
[0064] The plurality of MOS devices in the second element region II may include a source follower transistor (corresponding to the gate electrode SF), a reset transistor (corresponding to the gate electrode RST) and a row select transistor (corresponding to the gate electrode SEL). In some embodiments, the pixel circuit of the CMOS image sensor adopts the following method: Figure 1 The CMOS image sensor may further include a first trench isolation structure 110, which defines a plurality of active areas in the upper substrate layer 103. For example, the reset transistor and the row select transistor are isolated by the first trench isolation structure 110. The first trench isolation structure 110 penetrates the upper substrate layer 103. Optionally, the first trench isolation structure 110 extends from the front surface 100a of the substrate 100 into the lower substrate layer 101. The first trench isolation structure 110 is, for example, a shallow trench isolation.
[0065] The CMOS image sensor may further include at least one of a second trench isolation structure 120 and a third trench isolation structure 160. The second trench isolation structure 120 is located between the first element region I and the second element region II and surrounds the first element region I. The second trench isolation structure 120 is, for example, a sidewall of the recess 10. The second trench isolation structure 120 extends from the front surface 100a of the substrate 100 into the lower substrate layer 101. The third trench isolation structure 160 is located between the first element region I and the second element region II and surrounds the first element region I. The third trench isolation structure 160 extends from the back surface 100b of the substrate 100 into the lower substrate layer 101. Optionally, the second trench isolation structure 120 and the third trench isolation structure 160 are joined within the lower substrate layer 101 at various locations around the circumference of the first element region I.
[0066] Reference Figure 3IOn the front side 100a of the substrate 100, the CMOS image sensor may further include a plurality of conductive plugs CT and a conductive interconnect structure 140. The plurality of conductive plugs CT are respectively connected to the transfer gate electrode structure, the floating diffusion region FD, and the gate electrode structure and source / drain regions of the MOS device. The conductive interconnect structure 140 is connected to each of the conductive plugs. The plurality of conductive plugs CT and the conductive interconnect structure 140 are surrounded by a front dielectric layer 150, which fills the recess 10.
[0067] Reference Figure 3I On the back side 100b of the substrate 100, the CMOS image sensor may include a back dielectric layer 170 and a light-blocking structure 180. The back dielectric layer 170 covers the substrate 100. The light-blocking structure 180 is disposed on a side of the back dielectric layer 170 away from the substrate 100. The light-blocking structure 180 includes a metal grid MG surrounding the first element region I. In this embodiment, the light-blocking structure 180 is used to prevent radiation that impinges on the photodiode region from diffusing to pixel regions outside the first element region I or to adjacent pixel regions.
[0068] In the method for forming a CMOS image sensor and the CMOS image sensor described in the above embodiments, the lower substrate layer 101 and the upper substrate layer 103 of the substrate 100 are used to respectively form components of the pixel region. The photodiode, the floating diffusion region FD, and the transfer gate electrode structure are formed in the lower substrate layer 101 exposed by the recess 10, and multiple MOS devices are formed in the upper substrate layer 103. A buried oxide layer 102 is provided between the upper substrate layer 103 and the lower substrate layer 101. When the CMOS image sensor is operating, the buried oxide layer 102 can block the substrate current of the multiple MOS devices from leaking into the photodiode region, thereby helping to reduce dark current and improve sensor performance.
[0069] It should be noted that the embodiments in this specification are described in a progressive manner, and each part focuses on the differences from other embodiments. The relevant parts can be understood by reference.
[0070] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.
Claims
1. A CMOS image sensor, characterized in that: include: A substrate having a front side and a back side facing each other, and comprising a lower substrate layer, a buried oxide layer, and an upper substrate layer stacked in sequence from the back side to the front side, wherein a pixel region is arranged on the substrate, and a groove is provided in the pixel region to expose the lower substrate layer; a first element region comprising a photodiode and a floating diffusion region disposed within the exposed lower substrate layer, and a transfer gate electrode structure disposed on the exposed lower substrate layer and between the photodiode and the floating diffusion region, wherein the photodiode is configured to sense radiation entering the lower substrate layer from the back surface; as well as The second element region includes a plurality of MOS devices, wherein the MOS devices have a gate electrode structure arranged on the front side and source / drain regions arranged in the upper substrate layer on both sides of the gate electrode structure.
2. The CMOS image sensor according to claim 1, wherein: Also includes: A first trench isolation structure defines a plurality of active areas on the upper substrate layer, and the first trench isolation structure penetrates the upper substrate layer.
3. The CMOS image sensor according to claim 1, wherein: Also includes: A second trench isolation structure is located between the first element region and the second element region and is a sidewall of the groove. The second trench isolation structure extends from the front surface into the lower substrate layer.
4. The CMOS image sensor according to claim 3, wherein: Also includes: A third trench isolation structure is located between the first element region and the second element region and surrounds the first element region. The third trench isolation structure extends from the back side into the lower substrate layer.
5. The CMOS image sensor according to claim 4, wherein: The second trench isolation structure and the third trench isolation structure are joined in the lower substrate layer at various locations in the circumferential direction of the first element region.
6. The CMOS image sensor according to claim 1, wherein: The plurality of MOS devices in the second element region include a source follower transistor, a reset transistor, and a row selection transistor.
7. The CMOS image sensor according to claim 1, wherein: Also includes: A plurality of conductive plugs and conductive interconnect structures are arranged on the front side, wherein the plurality of conductive plugs are respectively connected to the transmission gate electrode structure, the floating diffusion region, and the gate electrode structure and source / drain region of the MOS device, and the conductive interconnect structure is connected to each of the conductive plugs.
8. The CMOS image sensor according to claim 1, wherein: Also includes: a back dielectric layer covering the substrate from the back side; as well as A light-blocking structure is provided on a side of the back dielectric layer away from the substrate, and the light-blocking structure includes a metal grid surrounding the first element region.
9. A method for forming a CMOS image sensor, characterized in that: The forming method comprises: Providing a substrate, the substrate having a front side and a back side opposite to each other, and comprising a lower substrate layer, a buried oxide layer, and an upper substrate layer stacked in sequence from the back side to the front side, wherein a pixel area is arranged on the substrate; forming a groove in the pixel area to expose the lower substrate layer; doping the exposed lower substrate layer to form a photodiode for sensing radiation entering the lower substrate layer from the back surface; forming a transmission gate electrode structure on the exposed lower substrate layer, and forming a gate electrode structure of a plurality of MOS devices on the upper substrate layer, wherein the photodiode is located on one side of the transmission gate electrode structure; and The upper substrate layer and the lower substrate layer are doped to form a floating diffusion region in the lower substrate layer located on the side opposite to the transmission gate electrode structure and the photodiode, and to form a source / drain region in the upper substrate layer located on both sides of the gate electrode structure of the plurality of MOS devices.
10. The forming method according to claim 9, wherein: Before forming the groove, the forming method further includes: A first trench isolation structure and a second trench isolation structure are formed extending from the substrate front to the lower substrate layer, wherein the first trench isolation structure defines a plurality of active areas in the upper substrate layer, and the second trench isolation structure defines a substrate region to expose the lower substrate layer.
11. The forming method according to claim 10, wherein: After forming the floating diffusion region and the source / drain region, the forming method further includes: forming a trench extending from the back surface into the lower substrate layer, wherein the trench is aligned with the second trench isolation structure in a normal direction of the substrate; and An isolation material is filled in the trench to form a third trench isolation structure.
12. The forming method according to claim 11, wherein: The trench exposes the isolation material in the second trench isolation structure, and the second trench isolation structure and the third trench isolation structure are joined in the substrate.
13. The forming method according to claim 9, wherein: The forming method further comprises: Covering the back side of the substrate with a back dielectric layer; and A light-blocking structure is formed on a side of the back dielectric layer away from the substrate. The light-blocking structure includes a metal grid. The metal grid surrounds the region where the photodiode, the transmission gate electrode structure, and the floating diffusion region are formed from the back.