Magnetic tunnel junction without external magnetic field, SOT-MRAM structure, full-electric-control write-in device and manufacturing method

Abstract

The invention relates to a magnetic tunnel junction without an external magnetic field, an SOT-MRAM structure, a full-electric-control write-in device and a manufacturing method, belongs to the technical field of semiconductor devices, and solves the problems that the existing MRAM with a PMA needs an additional magnetic field to realize deterministic SOT magnetic field overturning, so that tunnel junctions are difficult to be arranged tightly in a limited space, and the reliability of the device is poor. And the storage capacity of the device is low. The magnetic tunnel junction comprises a bottom electrode layer, a free layer, a tunneling layer and a reference layer which are sequentially arranged from bottom to top, the bottom electrode layer comprises a first electrode layer and a second electrode layer, and the first electrode layer is located between the second electrode layer and the free layer; wherein the material of the first electrode layer comprises metal capable of enabling the free layer to generate magnetic perpendicular anisotropy; and the material of the second electrode layer comprises metal capable of enabling the free layer to generate tensile stress.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a magnetic tunnel junction, a SOT-MRAM structure, a fully electrically controlled writing device and a manufacturing method thereof that do not require an external magnetic field. Background Art

[0002] Magnetic random access memory (MRAM) is a new type of non-volatile memory that stores information by the magnetization orientation of two ferromagnetic layers. In recent years, the spin-orbit torque (SOT) effect driven by in-plane current has become a key technology for next-generation MRAM writing. The main structure of a SOT-MRAM device consists of a four-layer magnetic tunnel junction (MTJ): a free layer, a reference layer, a tunneling oxide layer, and a bottom electrode layer.

[0003] SOT-MRAM with perpendicular magnetic anisotropy (PMA) has good thermal stability and scalability. However, SOT-MRAM with PMA usually requires an additional magnetic field to achieve deterministic SOT magnetic field switching.

[0004] Existing technologies achieve deterministic SOT magnetic field reversal by setting a magnetic layer outside or inside the tunnel junction. However, the additional magnetic layer will increase the volume of the tunnel junction. In a limited space, it is difficult to arrange the tunnel junctions closely, resulting in low storage capacity of the device. Summary of the Invention

[0005] In view of the above analysis, the present invention aims to provide a magnetic tunnel junction, SOT-MRAM structure, fully electrically controlled write device and manufacturing method that do not require an external magnetic field, so as to solve the problem that existing MRAM with PMA requires an additional magnetic field to achieve deterministic SOT magnetic field reversal, making it difficult to arrange tunnel junctions closely within a limited space, thereby resulting in low storage capacity of the device.

[0006] The purpose of the present invention is mainly achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a magnetic tunnel junction, comprising a bottom electrode layer, a free layer, a tunnel layer, and a reference layer arranged in sequence from bottom to top;

[0008] The bottom electrode layer includes a first electrode layer and a second electrode layer, wherein the first electrode layer is located between the second electrode layer and the free layer;

[0009] Wherein, the material of the first electrode layer includes a metal that can cause the free layer to generate magnetic perpendicular anisotropy;

[0010] The material of the second electrode layer includes a metal capable of generating tensile stress in the free layer.

[0011] Optionally, the first electrode layer and the second electrode layer are repeatedly stacked in sequence.

[0012] Optionally, the bottom electrode layer includes a stacked structure of at least a first electrode layer, a second electrode layer and a first electrode layer.

[0013] Optionally, the material of the second electrode layer includes Ta, Ru or Pt.

[0014] Optionally, the sum of the thicknesses of the second electrode layers is greater than 0.2 nm.

[0015] Optionally, the material of the bottom electrode layer includes W or Mo.

[0016] Optionally, the sum of the thicknesses of the first electrode layers is 4-10 nm.

[0017] Optionally, the bottom electrode layer includes a plurality of second electrode layers, which are spaced apart along the bottom-up direction.

[0018] Optionally, the spin Hall conversion rate of the bottom electrode layer is 40%-48%.

[0019] In a second aspect, the present invention provides a SOT-MRAM structure including the above-mentioned magnetic tunnel junction.

[0020] In a third aspect, the present invention provides a SOT-MRAM fully electrically controlled writing device, comprising the above-mentioned SOT-MRAM structure.

[0021] In a fourth aspect, the present invention provides a method for manufacturing the magnetic tunnel junction, comprising:

[0022] Depositing a first electrode layer, a second electrode layer, a free layer, a tunnel layer and a reference layer on a Si wafer or a circuit wafer to obtain a tunnel junction film;

[0023] annealing the obtained tunnel junction film;

[0024] Processing tunnel junction thin films;

[0025] Protect the processed tunnel junction thin film deposition medium;

[0026] Processing the top and bottom electrodes to obtain a magnetic tunnel junction;

[0027] The first electrode layer is located between the second electrode layer and the free layer;

[0028] Wherein, the material of the first electrode layer includes a metal that can cause the free layer to generate magnetic perpendicular anisotropy;

[0029] The material of the second electrode layer includes a metal capable of generating tensile stress in the free layer.

[0030] In a fifth aspect, the present invention provides a method for manufacturing the above-mentioned SOT-MRAM structure, comprising: metal interconnecting the magnetic tunnel junction manufactured by the above-mentioned manufacturing method with a circuit to obtain the SOT-MRAM structure.

[0031] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0032] (1) The present invention innovatively inserts a metal that can generate tensile stress as an intercalation material (second electrode layer) into the bottom electrode, which can introduce tensile stress into the free layer, causing the easy magnetization axis of the perpendicular anisotropic free layer to deviate from the vertical direction by a small angle. At this time, the magnetic moment of the magnetic material is arranged in a conical row ( Figure 8 Before using the chip, a pre-magnetization horizontal field needs to be applied, and the magnetic moments are flipped to two angles, one above and one below, on one side of the horizontal magnetic field (Figure 9(a)). After the horizontal magnetic field is removed, the direction of the magnetic moment remains on one side (Figure 9(b)). At this time, the direction of the magnetic moment in the magnetic domain wall is consistent with the external magnetic field, and under the action of the current, the left and right magnetic domain walls move in opposite directions ( Figure 10 ), thus achieving deterministic SOT magnetic field reversal without the need for an external magnetic field. Therefore, reducing the size of the tunnel junction allows for denser arrangement of tunnel junctions within a limited space, thereby increasing the device's storage capacity.

[0033] (2) The present invention sets the bottom electrode layer as a [W / X] multilayer film structure, so that the bottom electrode has a higher spin Hall conversion rate (40%-48%) and a lower resistivity, which is beneficial to reducing energy consumption.

[0034] (3) Since the present invention can achieve deterministic SOT magnetic field reversal without the need for an additional magnetic field, the volume of the tunnel junction can be reduced, thereby reducing the volume of the device and facilitating high-density integration of the device.

[0035] (4) The present invention is compatible with CMOS technology and does not require the development of new technology, which is conducive to reducing production costs.

[0036] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages may become obvious from the description or be understood through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0038] Figure 1 Schematic diagram of the structure of a tunnel junction according to one embodiment of the present invention;

[0039] Figure 2 A schematic structural diagram of the bottom electrode layer of the multi-layer film structure of the present invention;

[0040] Figure 3 The magnitude and direction of stresses generated for different metals;

[0041] Figure 4 A negative horizontal external magnetic field is applied to the W / Ta device for initialization. After the magnetic field is removed, the current-induced magnetic moment orientation magnetization reversal curve is obtained.

[0042] Figure 5 The W / Ta device is initialized by applying a positive horizontal external magnetic field. After the magnetic field is removed, the magnetic moment orientation magnetization reversal curve caused by current is shown.

[0043] Figure 6 This is a first-principles calculation of the anisotropy energy of the tunnel junction free layer CoFeB under horizontal tensile stress. Schematic diagram of how the tensile stress causes the spatial angle of the lowest anisotropy energy to deviate from the vertical direction.

[0044] Figure 7 To calculate the anisotropy energy of the tunnel junction free layer CoFeB by first principles when horizontal compressive stress is applied, the compressive stress cannot make the spatial angle of the lowest energy of the anisotropy energy deviate from the vertical direction;

[0045] Figure 8 Schematic diagram of the conical arrangement of magnetic moments after tensile stress is applied;

[0046] Figure 9(a) shows the magnetic moment arrangement after applying a horizontal magnetic field;

[0047] Figure 9(b) shows the magnetic moment arrangement after the magnetic field is removed;

[0048] Figure 10 Schematic diagram of directional magnetization reversal caused by conical arrangement of SOT. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein the accompanying drawings constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0050] In a first aspect, the present invention provides a magnetic tunnel junction, such as Figure 1As shown, it includes a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a pinning layer, a protective layer and a hard mask layer arranged in sequence from bottom to top, that is, the free layer is arranged on the bottom electrode layer, the tunneling layer is arranged on the free layer, the reference layer is arranged on the tunneling layer, the intermediate layer is arranged on the reference layer, the pinning layer is arranged on the intermediate layer, the protective layer is arranged on the pinning layer, and the hard mask layer is arranged on the protective layer.

[0051] The bottom electrode layer includes a first electrode layer and a second electrode layer, and the first electrode layer is located between the second electrode layer and the free layer.

[0052] In a specific embodiment, Figure 2 As shown, the first electrode layer and the second electrode layer are repeatedly stacked in sequence.

[0053] The material of the first electrode layer is a metal that generates perpendicular anisotropy in the tunnel junction free layer, such as tungsten (W) or Mo. The thickness of the first electrode layer is 4-10 nm, such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0054] The material of the second electrode layer is X, where X is a metal that can generate tensile stress in the free layer, for example, tantalum (Ta), ruthenium (Ru) or platinum (Pt). Figure 3 .

[0055] The thickness of the second electrode layer is 0.2-3 nm, for example, 0.2 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm.

[0056] In another specific embodiment, the bottom electrode layer includes a stacked structure of at least a first electrode layer, a second electrode layer, and a first electrode layer.

[0057] Specifically, the number of layers of the second electrode layer can be 1 layer, 2 layers, 3 layers, 4 layers, 5 layers, 6 layers, 7 layers, etc.

[0058] It should be noted that in the bottom electrode layer, the top layer must be the first electrode layer, not the second electrode layer. This is because when the top layer is the second electrode layer, the film forming property will be poor when the free layer is subsequently formed, thereby affecting the device performance.

[0059] Compared to existing single-layer bottom electrode structures, the present invention utilizes a multilayer structure comprising a first electrode layer and a second electrode layer, resulting in a higher spin Hall conversion rate and lower resistivity, significantly reducing energy consumption. Specifically, when the bottom electrode layer is made of a single W layer, the spin Hall conversion rate is only 10%-30%, while a multilayer structure comprising a first electrode layer and a second electrode layer achieves a spin Hall conversion rate of 40%-48%.

[0060] In a preferred embodiment, the ratio of the sum of the thicknesses of the multilayer first electrode layers to the sum of the thicknesses of the multilayer X is (10-2):1, such as 10:1, 9:1, 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, 2:1. If the W ratio is too large, the stress of X cannot be transmitted to the free layer, and the magnetic moment of the free layer cannot be deviated from the vertical direction, so the directional reversal without an external magnetic field cannot be achieved. If the X ratio is too large, it is impossible to achieve good perpendicular magnetic anisotropy and a higher spin Hall angle. Preferably, in the multilayer first electrode layer, the thickness of each first electrode layer is equal, and in the multilayer second electrode layer, the thickness of each second electrode layer is equal.

[0061] The material of the free layer is CoFeB, and the thickness is 0.5-3 nm, for example, 0.5 nm, 0.7 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, and 3 nm.

[0062] The tunneling layer is made of MgO, and has a thickness of 0.5-3 nm, for example, 0.5 nm, 0.7 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, and 3 nm.

[0063] The material of the reference layer is CoFeB and the thickness of the reference layer is about 1 nm.

[0064] The material of the intermediate layer is a non-magnetic material, such as W. The thickness of the intermediate layer is 0.6-0.8 nm, for example, 0.6 nm, 0.7 nm, or 0.8 nm.

[0065] It should be noted that the pinning layer is used to pin the reference layer to a fixed direction, and its material is a CoPt multilayer film with a thickness of 10-15 nm, for example, 10 nm, 12 nm, 14 nm, and 15 nm.

[0066] The protective layer protects the MRAM structure from external environmental influences and prevents oxidation and other chemical reactions. The protective layer is made of Ru and has a thickness of 2-4 nm, for example, 2 nm, 3 nm, or 4 nm.

[0067] The material of the hard mask layer is TiN or Ta, and the thickness is 80-110 nm, for example, 80 nm, 90 nm, 95 nm, 100 nm, 105 nm, or 110 nm.

[0068] In a second aspect, the present invention further provides a SOT-MRAM structure, comprising the above-mentioned magnetic tunnel junction.

[0069] In a third aspect, the present invention further provides a SOT-MRAM fully electrically controlled write device comprising the aforementioned SOT-MRAM structure. The device has a small tunnel junction, which allows for a denser arrangement of tunnel junctions within a limited space, thereby increasing the device's storage capacity.

[0070] In a fourth aspect, the present invention further provides a method for manufacturing a SOT-MRAM structure, which is used to manufacture the above-mentioned SOT-MRAM structure, comprising the following steps:

[0071] Step 1: Depositing a first electrode layer, a second electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a pinning layer, a protective layer and a hard mask layer on a Si wafer or a circuit wafer to obtain a tunnel junction thin film;

[0072] Step 2: annealing the tunnel junction film obtained in step 1 under a horizontal magnetic field;

[0073] Step 3: Processing the tunnel junction film;

[0074] Step 4: Protect the processed tunnel junction thin film deposition medium;

[0075] Step 5: Process the top electrode and bottom electrode to obtain a magnetic tunnel junction;

[0076] Step 6: The obtained magnetic tunnel junction is metal-interconnected with the circuit to obtain a SOT-MRAM structure.

[0077] Specifically, in step 1, the deposited first electrode layer is located between the second electrode layer and the free layer.

[0078] The material of the first electrode layer includes a metal that can cause the free layer to generate magnetic perpendicular anisotropy, such as tungsten (W) or Mo.

[0079] The material of the second electrode layer includes a metal capable of generating tensile stress in the free layer, such as tantalum (Ta), ruthenium (Ru), or platinum (Pt).

[0080] Specifically, the annealing in step 2 is to enhance atomic diffusion at the interface between the W layer and the X layer to form a multilayer film alloy.

[0081] The annealing temperature is 350-400°C, for example, 350°C, 360°C, 370°C, 380°C, 390°C, 400°C.

[0082] The annealing time is 0.5-3 hours, for example, 0.5 hours, 1 hour, 1.5 hours, 2 hours, 2.5 hours, and 3 hours.

[0083] Specifically, step 3 includes: etching the tunnel junction film, where the etching stops at the tunnel layer or the bottom electrode layer; then, etching the hard mask using a reaction gas; and then etching the tunnel junction using the hard mask in an Ar atmosphere.

[0084] Specifically, in step 4, the deposited medium is SiN, and the thickness is 30-60 nm, for example, 30 nm, 40 nm, 50 nm, or 60 nm.

[0085] Specifically, in step 5, the top electrode and the bottom electrode are exposed by using a CMP method.

[0086] It should be pointed out that, unless otherwise specified, the processes and process parameters involved in the manufacturing method of the present invention all adopt the existing technology.

[0087] Example 1

[0088] Step 1: Deposit a seven-layer film structure of a bottom electrode layer (W (1nm) / Ta (0.4nm) / W (1nm) / Ta (0.3) / W (1nm) / Ta (0.3nm) / W (1nm), a free layer (CoFeB, 1nm), a tunneling layer (MgO, 1.2nm), a reference layer (CoFeB, 1nm), an intermediate layer (W, 0.6nm), a pinning layer (CoPt multilayer film, 10nm), a protective layer (Ru, 2nm) and a hard mask layer (TiN, 80nm) on a Si wafer in sequence to obtain a tunnel junction;

[0089] Step 2: Anneal the tunnel junction obtained in step 1 under a horizontal magnetic field (0.5 T) (350°C, 3h);

[0090] Step 3: Etch the tunnel junction, stopping at the tunnel layer; then, etch the hard mask using a reactive gas; then, etch the tunnel junction using the hard mask in an Ar atmosphere;

[0091] Step 4: Deposit SiN dielectric (30 nm thick) on the processed tunnel junction;

[0092] Step 5: CMP method leaks out the top electrode and bottom electrode;

[0093] Step 6: Perform metal interconnection to obtain the SOT-MRAM structure.

[0094] Example 2

[0095] Step 1: Deposit a three-layer film structure of a bottom electrode layer (W (3nm), Ru (3nm), W (3nm)), a free layer (CoFeB, 1nm), a tunneling layer (MgO, 1.2nm), a reference layer (CoFeB, 1nm), an intermediate layer (W, 0.8nm), a pinning layer (CoPt multilayer film, 15nm), a protective layer (Ru, 4nm) and a hard mask layer (Ta, 110nm) on the circuit chip in sequence to obtain a tunnel junction;

[0096] Step 2: Anneal the tunnel junction obtained in step 1 in a horizontal magnetic field (0.5 T) (400°C, 0.5 h);

[0097] Step 3: Etch the tunnel junction, stopping at the bottom electrode layer; then, etch the hard mask using a reactive gas; and then etch the tunnel junction using the hard mask in an Ar atmosphere;

[0098] Step 4: Deposit SiN dielectric (60 nm thick) on the processed tunnel junction;

[0099] Step 5: CMP method leaks out the top electrode and bottom electrode;

[0100] Step 6: Perform metal interconnection to obtain the SOT-MRAM structure.

[0101] Example 3

[0102] Step 1: Deposit a three-layer bottom electrode layer (W (5nm), Pt (3nm), W (3nm), free layer (CoFeB, 1nm), tunneling layer (MgO, 1nm), reference layer (CoFeB, 1nm), intermediate layer (W, 0.7nm), pinning layer (CoPt multilayer film, 12nm), protection layer (Ru, 3nm) and hard mask layer (TiN, 100nm) on the Si wafer in sequence to obtain a tunnel junction;

[0103] Step 2: Anneal the tunnel junction obtained in step 1 under a horizontal magnetic field (0.5 T) (370°C, 1 h);

[0104] Step 3: Etch the tunnel junction, stopping at the tunnel layer; then, etch the hard mask using a reactive gas; then, etch the tunnel junction using the hard mask in an Ar atmosphere;

[0105] Step 4: Deposit SiN dielectric (thickness 45nm) on the processed tunnel junction;

[0106] Step 5: CMP method leaks out the top electrode and bottom electrode;

[0107] Step 6: Perform metal interconnection to obtain the SOT-MRAM structure.

[0108] Comparative Example 1

[0109] This comparative example is basically the same as Example 1, except that the bottom electrode layer deposited in step 1 is a W (5 nm) single-layer film structure.

[0110] In addition, the present invention also tests the spin Hall conversion rate of the bottom electrode materials in the embodiments and comparative examples and whether directional magnetization reversal occurs. The results are listed in Table 1.

[0111] Table 1 Spin Hall conversion rate of the bottom electrode and whether directional magnetization reversal occurs

[0112]

[0113] As can be seen from Table 1, the spin Hall conversion efficiency of the bottom electrode using the [W / X] multilayer film structure (Examples 1-3) is significantly higher than that of the bottom electrode using a single W layer (Comparative Example 1).

[0114] In addition, it can be seen from Table 1 that the tunnel junctions with the bottom electrode having an intercalation layer (second electrode layer) (Examples 1-3) all underwent magnetization reversal in the absence of an external magnetic field, while the tunnel junction with the bottom electrode without an intercalation layer (second electrode layer) (Comparative Example 1) did not undergo magnetization reversal in the absence of an external magnetic field. This proves that inserting a metal intercalation layer (second electrode layer) that can generate tensile stress into the bottom electrode layer can achieve deterministic SOT magnetic field reversal without the need for an external magnetic field.

[0115] In addition, it can be seen from Table 1 that when the intercalation material used is metal W that cannot cause tensile stress in the free layer, directional magnetization reversal cannot occur.

[0116] Depend on Figure 4 It can be seen that after the initial magnetization is performed by applying a negative horizontal magnetic field, the horizontal magnetic field is removed. The positive current causes the magnetic moment to flip to a low-resistance state, while the negative current causes the magnetic moment to flip to a high-resistance state, indicating that the directional reversal of the magnetic moment without an external magnetic field is achieved.

[0117] Depend on Figure 5 It can be seen that after the initial magnetization is performed by applying a positive horizontal magnetic field, the horizontal magnetic field is removed. The positive current causes the magnetic moment to flip to a high-resistance state, while the negative current causes the magnetic moment to flip to a low-resistance state, indicating that the directional reversal of the magnetic moment without an external magnetic field is achieved.

[0118] Depend on Figure 6 It can be seen that after applying 1.3% tensile stress in the calculation, the lowest energy direction of the magnetic moment changes from 180° (vertical direction) to about 150°, and the direction of the magnetic moment deviates from the vertical direction by an angle, indicating that tensile stress can deflect the magnetic moment.

[0119] Depend on Figure 7It can be seen that after applying compressive stress in the calculation, the lowest energy direction of the magnetic moment is still in the vertical direction, indicating that the magnetic moment cannot be deflected.

[0120] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A magnetic tunnel junction, characterized in that: It includes a bottom electrode layer, a free layer, a tunneling layer and a reference layer arranged in sequence from bottom to top; The bottom electrode layer includes a first electrode layer and a second electrode layer, wherein the first electrode layer is located between the second electrode layer and the free layer; Wherein, the material of the first electrode layer includes a metal that can cause the free layer to generate magnetic perpendicular anisotropy; The material of the second electrode layer includes a metal capable of generating tensile stress in the free layer.

2. The magnetic tunnel junction according to claim 1, wherein: The first electrode layer and the second electrode layer are repeatedly stacked in sequence.

3. The magnetic tunnel junction according to claim 1, wherein: The bottom electrode layer includes a stacked structure of at least a first electrode layer, a second electrode layer and a first electrode layer.

4. The magnetic tunnel junction according to any one of claims 1 to 3, characterized in that: The material of the second electrode layer includes Ta, Ru or Pt.

5. The magnetic tunnel junction according to claim 4, wherein: The sum of the thicknesses of the second electrode layers is greater than 0.2 nm.

6. The magnetic tunnel junction according to any one of claims 1 to 3, characterized in that: The material of the bottom electrode layer includes W or Mo.

7. The magnetic tunnel junction according to claim 6, wherein: The total thickness of the first electrode layers is 4-10 nm.

8. The magnetic tunnel junction according to claim 4, wherein: The bottom electrode layer includes a plurality of second electrode layers, which are spaced apart along the bottom-up direction.

9. The magnetic tunnel junction according to any one of claims 1 to 3, characterized in that: The spin Hall conversion rate of the bottom electrode layer is 40%-48%.

10. A SOT-MRAM structure, characterized in that: The magnetic tunnel junction comprises the magnetic tunnel junction according to any one of claims 1 to 9.

11. A SOT-MRAM fully electrically controlled write device, characterized in that: The SOT-MRAM structure according to claim 10 is included.

12. A method for manufacturing a magnetic tunnel junction, characterized in that: include: Depositing a first electrode layer, a second electrode layer, a free layer, a tunnel layer and a reference layer on a Si wafer or a circuit wafer to obtain a tunnel junction film; annealing the obtained tunnel junction film; Processing tunnel junction thin films; Protect the processed tunnel junction thin film deposition medium; Processing the top and bottom electrodes to obtain a magnetic tunnel junction; The first electrode layer is located between the second electrode layer and the free layer; Wherein, the material of the first electrode layer includes a metal that can cause the free layer to generate magnetic perpendicular anisotropy; The material of the second electrode layer includes a metal capable of generating tensile stress in the free layer.

13. A method for manufacturing a SOT-MRAM structure, characterized in that: include: The magnetic tunnel junction manufactured by the manufacturing method according to claim 12 is metal-interconnected with a circuit to obtain a SOT-MRAM structure.

Images