Buffer extrusion and source code synthesis to reduce inference cost on resource constrained systems

Abstract

A processor-implemented method for performing inference tasks on a resource-constrained device includes receiving an input through an artificial neural network (ANN). The ANN includes one or more fusion layers. Input is processed using the one or more fusion layers to generate a fused output. The ANN generates an inference using the fused output.

Description

background Technical Field

[0001] Aspects of the present disclosure generally relate to the processing of convolution computations. Background Art

[0002] An artificial neural network may include a set of interconnected artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method to be executed by a computing device. A convolutional neural network is a feedforward artificial neural network. A convolutional neural network may include a collection of neurons, each of which has a receptive field and collectively spells out an input space. Convolutional neural networks (CNNs), such as deep convolutional neural networks (DCNs), have numerous applications. Specifically, these neural network architectures are used in various technologies such as image recognition, pattern recognition, speech recognition, autonomous driving, and other classification tasks.

[0003] Deep neural networks have significantly improved the performance of classifying streaming data, such as images, videos, inertial measurement unit (IMU) data, and WiFi. It is desirable to integrate such networks with Internet of Things (IoT) devices, smartphones, or other low-power devices that stream data. Unfortunately, classification consumes significant resources due to the amount of computation involved, making it challenging to utilize deep neural networks for real-time, energy-sensitive applications. Summary of the Invention

[0004] The present disclosure is set out in the independent claims. Some aspects of the present disclosure are described in the dependent claims.

[0005] In one aspect of the present disclosure, a processor-implemented method includes receiving an input via an artificial neural network (ANN), the ANN including one or more fusion layers. The method also includes processing the input using the one or more fusion layers to generate a fused output. The method also includes generating an inference using the fused output via the ANN.

[0006] Another aspect of the present disclosure relates to an apparatus comprising means for receiving an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers. The apparatus further comprises means for processing the input using the one or more fusion layers to generate a fused output. The apparatus further comprises means for generating an inference using the fused output via the ANN.

[0007] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for receiving an input through an artificial neural network (ANN), the ANN including one or more fusion layers. The program code also includes program code for processing the input using the one or more fusion layers to generate a fusion output. The program code also includes program code for generating an inference using the fusion output through the ANN.

[0008] Another aspect of the present disclosure relates to a device having a memory and one or more processors coupled to the memory. The processor is configured to receive an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers. The processor is further configured to process the input using the one or more fusion layers to generate a fused output. The processor is further configured to generate an inference using the fused output via the ANN.

[0009] Additional features and advantages of the present disclosure are described below. It will be understood by those skilled in the art that the present disclosure can be readily used as a basis for modifying or designing other structures for carrying out the same purposes as the present disclosure. It will also be recognized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the present disclosure, both in its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the figures is provided for illustration and description purposes only and is not intended to be a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0011] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general-purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0012] Figure 2A 、 Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0013] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0014] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0015] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to aspects of the present disclosure.

[0016] Figure 5 is a block diagram illustrating an architecture for adapting an artificial neural network (ANN) using buffer squeezing in accordance with aspects of the present disclosure.

[0017] Figure 6A and Figure 6B are diagrams illustrating example source code for executing a conventional convolutional layer and source code for executing an example architecture, respectively, according to aspects of the present disclosure.

[0018] Figure 7 is a flow chart illustrating a processor-implemented method for generating inferences for resource-constrained device code in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0019] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the described concepts may be practiced. The detailed description includes specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0020] Based on the teachings, it will be appreciated by those skilled in the art that the scope of the present disclosure is intended to encompass any aspect of the present disclosure, regardless of whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device or method may be implemented using any number of aspects set forth. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structure and functionality that are supplementary to or different from the various aspects of the present disclosure set forth. It should be understood that any aspect of the present disclosure disclosed may be embodied by one or more elements of a claim.

[0021] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] Although specific aspects have been described, numerous variations and permutations of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or purpose. On the contrary, various aspects of this disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0023] Deep neural networks (DNNs) have greatly improved the performance of classifying streaming data, such as images, videos, inertial measurement unit (IMU) data, and WiFi. It is desirable to integrate such networks with Internet of Things (IoT) devices, smartphones, or other low-power devices used to stream data. Unfortunately, the large amount of resources consumed for classification due to the amount of computation involved makes it challenging to utilize DNNs for real-time, energy-sensitive applications on low-power systems, such as central processing units (CPUs), digital signal processors (DSPs), reduced instruction set computers (RISC) processors, microcontroller units (MCUs), and the like.

[0024] The memory system is a determining factor in performance and energy consumption. That is, for existing resource-constrained low-power systems (such as central processing units (CPUs), digital signal processors (DSPs), reduced instruction set computers (RISC) processors, microcontroller units (MCUs), etc.), memory access is a significant cost in terms of both energy and price. Increasing memory size can also lead to increased power consumption and poor data locality, which in turn can lead to increased cache misses and memory traffic. Many deep neural network calculations occur in convolution kernels, which involve matrix multiplication of inputs and weights. A common implementation of convolution kernels is the general matrix multiplication algorithm. However, general matrix multiplication (GEMM) based convolution layer implementations use additional memory space (e.g., C = HxWxK 2 , where K is the kernel size, C is the channel size, H is the height, and W is the weight), which can also be problematic.

[0025] Computer programming loops also play an important role in improving execution speed and reducing overhead for scientific computing kernels (e.g., one-dimensional (1D), two-dimensional (2D), or three-dimensional (3D) convolution kernels). A loop is a programming structure that repeats a sequence of instructions until a condition is met. However, compiler optimization for nested loops (a programming structure in which one or more loops are contained within another loop) can be inefficient.

[0026] On resource-constrained systems such as mobile devices or Internet of Things (IoT) devices, for example, a large portion of the memory footprint of a convolutional neural network is buffers for inputs, outputs, and weights.

[0027] To address these and other challenges, aspects of the present disclosure relate to using buffer squeezing to reduce the inference cost of artificial neural networks. According to aspects of the present disclosure, a conventional neural network architecture comprising a separate convolutional layer, a separate activation layer (e.g., a rectified linear unit (ReLU) layer), and a separate max pooling layer can be replaced by an architecture comprising merged or fused convolutional, max pooling, and activation layers (e.g., ReLU). Buffer squeezing can be used to generate fused convolutional, ReLU, and pooling layers. Buffer squeezing can refer to removing one layer of output buffers and merging the output buffers of two or more layers. For example, a convolutional layer output buffer that accounts for a significant portion of the memory footprint can be removed to address memory size and access challenges. Additionally, in some aspects, nested loops can be transformed to mix instructions from different layers, and instructions can be rescheduled for the compiler.

[0028] Figure 1 An example implementation of a system on a chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured to perform inference tasks for a resource-constrained system. Variables (e.g., neural signals and synaptic weights), system parameters associated with the computing device (e.g., a neural network with weights), latency, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at CPU 102 may be loaded from a program memory associated with CPU 102 or may be loaded from memory block 118.

[0029] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0030] The SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general-purpose processor 102 may include code for receiving input via an artificial neural network (ANN), the ANN including one or more fusion layers. The general-purpose processor 102 may also include code for processing the input using the one or more fusion layers to generate a fusion output. Furthermore, the general-purpose processor 102 may include code for generating inferences using the fusion output via the ANN.

[0031] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning solves a major bottleneck of traditional machine learning. Before the advent of deep learning, machine learning methods for object recognition problems may rely heavily on human-designed features, perhaps in conjunction with shallow classifiers. A shallow classifier can be a two-class linear classifier, for example, in which the weighted sum of the feature vector components can be compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized by engineers with domain expertise for a specific problem domain. In contrast, although deep learning architectures can learn to represent features similar to those that human engineers might design, they require training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0032] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer might learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer might learn to recognize spectral power at specific frequencies. The second layer, taking the output of the first layer as input, might learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers might learn to represent complex shapes in visual data or words in auditory data. Even higher layers might learn to recognize common visual objects or spoken phrases.

[0033] Deep learning architectures perform particularly well when applied to problems with a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can then be combined in different ways at higher levels to identify cars, trucks, and airplanes.

[0034] Neural networks can be designed to have a variety of connection patterns. In a feedforward network, information is passed from lower layers to higher layers, where each neuron in a given layer communicates with neurons in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have loops or feedback (also known as top-down) connections. In a loop connection, the output from a neuron in a given layer can be conveyed to another neuron in the same layer. The loop architecture can help identify patterns that span more than one input data block in the input data blocks delivered to the neural network in sequence. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections can be helpful when the recognition of high-level concepts can assist in discerning specific low-level features of the input.

[0035] The connections between the layers of a neural network can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In the fully connected neural network 202, neurons in a first layer may communicate their output to every neuron in a second layer, such that every neuron in the second layer will receive input from every neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connection pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connection patterns may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive input that is tuned through training to properties of a limited portion of the network's total input.

[0036] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 can be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0037] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2DA detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as a vehicle-mounted camera) is shown. The DCN 200 of the current example can be trained to identify traffic signs and the numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0038] DCN 200 can be trained using supervised learning. During training, DCN 200 can be presented with an image, such as image 226 of a speed limit sign, and can then compute a forward pass to produce output 222. DCN 200 can include a feature extraction portion and a classification portion. Upon receiving image 226, convolution layer 232 can apply a convolution kernel (not shown) to image 226 to generate a first set of feature maps 218. As an example, the convolution kernel of convolution layer 232 can be a 5×5 kernel that generates a 28×28 feature map. In this example, because four different feature maps are generated in first set of feature maps 218, four different convolution kernels are applied to image 226 at convolution layer 232. Convolution kernels can also be referred to as filters or convolution filters.

[0039] The first set of feature maps 218 may be subsampled by a maximum pooling layer (not shown) to generate a second set of feature maps 220. The maximum pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (such as 14×14) is smaller than the size of the first set of feature maps 218 (such as 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0040] exist Figure 2D In the example of FIG200 , the second set of feature maps 220 is convolved to generate a first feature vector 224. In addition, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign," "60," and "100." A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Therefore, the output 222 of the DCN 200 is the probability that the image 226 includes one or more features.

[0041] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers in output 222, such as "30," "40," "50," "70," "80," "90," and "100." Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the ground truth value of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that output 222 of DCN 200 is closer to the target output.

[0042] To adjust a weight, the learning algorithm calculates a gradient vector for the weight. The gradient indicates how much the error will increase or decrease if the weight is adjusted. At the top layer, the gradient may directly correspond to the value of the weight connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient may depend on the value of the weight and the calculated error gradient of the higher layer. The weight can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves a "backward pass" through the neural network.

[0043] In practice, the error gradient of the weights can be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation is referred to as stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, new images can be presented to the DCN, and a forward pass through the network can produce output 222, which can be considered an inference or prediction of the DCN.

[0044] Deep Belief Network (DBN) is a probabilistic model comprising multiple layers of hidden nodes. DBN can be used to extract hierarchical representations of a training data set. DBN can be obtained by stacking layers of restricted Boltzmann machines (RBM). RBM is a type of artificial neural network that can learn probability distributions over a set of inputs. Because RBM can learn probability distributions without information about the category to which each input should be classified, RBM is often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0045] A deep convolutional network (DCN) is a network that is a convolutional network with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the network's weights using gradient descent.

[0046] A DCN can be a feedforward network. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational burden of a DCN can be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0047] The processing of each layer of the convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on this input can be thought of as three-dimensional, with two spatial dimensions along the axes of the image and the third dimension capturing color information. The output of the convolutional connection can be thought of as forming a feature map in the subsequent layer, where each element in the feature map (e.g., 220) receives input from a certain range of neurons in the previous layer (e.g., feature map 218) and from each channel in the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, maximum value (max)(0,x)). The values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0048] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources thousands of times greater than those available to typical researchers just fifteen years ago. New architectures and training paradigms can further improve deep learning performance. Rectified linear units can alleviate the training problem known as vanishing gradients. New training techniques can reduce overfitting and, therefore, enable larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0049] Figure 3 FIG is a block diagram illustrating a deep convolutional network 350. Based on connections and weight sharing, the deep convolutional network 350 may include multiple different types of layers. Figure 3 As shown, the deep convolutional network 350 includes convolution blocks 354A and 354B. Each of the convolution blocks 354A and 354B can be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAXPOOL) 360.

[0050] The convolution layer 356 may include one or more convolution filters that can be applied to the input data to generate a feature map. Although only two convolution blocks 354A, 354B are shown, the present disclosure is not limited thereto, and instead, any number of convolution blocks 354A, 354B may be included in the deep convolutional network 350 according to design preferences. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0051] For example, the parallel filter banks of the deep convolutional network can be offloaded onto the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In alternative embodiments, the parallel filter banks can be offloaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 can access other processing blocks that may be present on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0052] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may also include a logistic regression (LR) layer 364. Each layer 356, 358, 360, 362, 364 of the deep convolutional network 350 has weights (not shown) to be updated between them. The output of each of these layers (e.g., 356, 358, 360, 362, 364) can be used as input to a subsequent layer in the deep convolutional network 350 (e.g., 356, 358, 360, 362, 364) to learn a hierarchical feature representation from the input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is a probability that the input data includes a feature from a set of features.

[0053] Figure 4 4 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functionality. According to aspects of the present disclosure, by using this architecture, it is possible to design applications that can enable various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of SOC 420 to support adaptive rounding for post-training quantization of AI application 402 as disclosed.

[0054] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, the AI ​​application 402 may configure the microphone and camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0055] Runtime engine 408 (which can be compiled code of the runtime framework) can further be accessible to AI application 402. For example, AI application 402 can cause the runtime engine to request inference at specific time intervals or triggered by an event detected by the application's user interface. When the runtime engine is caused to provide an inference response, the runtime engine can in turn transmit a signal to the operating system in operating system (OS) space 410 (such as kernel 412) running on SOC 420. In some examples, kernel 412 can be a LINUX kernel. The operating system can then cause continuous quantization relaxation to be performed on CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. CPU 422 can be directly accessed by the operating system, while other processing blocks can be accessed through drivers (such as drivers 414, 416, or 418 for DSP 424, GPU 426, or NPU 428, respectively). In the illustrative examples, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422 , DSP 424 , and GPU 426 , or may run on NPU 428 .

[0056] Application 402 (e.g., an AI application) can be configured to call functions defined in user space 404, which can, for example, provide detection and recognition of a scene indicating the current operating location of the device. For example, application 402 can configure the microphone and camera differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. Application 402 can make a request to compiled program code associated with a library defined in a scene detection (SceneDetect) application programming interface (API) 406 to provide an estimate of the current scene. The request can ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0057] The runtime engine 408 (which may be compiled code of the runtime framework) may further be accessible to the application 402. For example, the application 402 may cause the runtime engine to request scene estimation at specific time intervals or triggered by an event detected by the application's user interface. Upon causing the runtime engine to estimate the scene, the runtime engine may in turn transmit a signal to an operating system 410 (such as a Linux kernel 412) running on the SOC 420. The operating system 410 may in turn cause the computation to be performed on a CPU 422, a DSP 424, a GPU 426, an NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while the other processing blocks may be accessed through drivers (such as drivers 414-418 for the DSP 424, the GPU 426, or the NPU 428, respectively). In the illustrative example, the differential neural network may be configured to run on a combination of processing blocks (such as the CPU 422 and the GPU 426), or may run on the NPU 428.

[0058] As described, aspects of the present disclosure relate to using buffer squeezing to reduce the inference cost of artificial neural networks. According to aspects of the present disclosure, a conventional neural network architecture comprising a separate convolutional layer, a separate activation layer (e.g., a rectified linear unit (ReLU) layer), and a separate maximum pooling layer can be replaced by an architecture comprising merged or fused convolutional, activation, and pooling layers. Buffer squeezing can be used to generate fused convolutional, activation, and pooling layers.

[0059] Figure 5 is a block diagram illustrating an architecture for adapting an artificial neural network (ANN) using buffer squeezing according to aspects of the present disclosure. The artificial neural network may be, for example, a convolutional neural network. Figure 5 , shows the architecture of a conventional convolutional layer 500. Conventional convolutional layer 500 includes a single convolutional layer 504, a single activation layer 506 (e.g., a ReLU layer), and a single max pooling layer 508. Conventional convolutional layer 500 includes an input buffer 502, which provides input to convolutional layer 504. Convolutional layer 504 receives input from input buffer 502 and performs a convolution operation on the input and weights 510 to produce output, which is stored in output buffer 512. The output of convolutional layer 504 serves as input to activation layer 506. In some aspects, activation layer 506 can be, for example, a rectified linear unit (ReLU). Activation layer 506 retrieves the output of convolutional layer 504 from output buffer 512. Activation layer 506 applies an activation function to the output of convolutional layer 504 and stores the activation layer output in output buffer 512. The activation layer output in output buffer 512 is supplied as input to max pooling layer 508. The max pooling layer 508 then generates an output, which is stored in the output buffer 514 .

[0060] As described, one potential bottleneck of conventional convolutional layer 500 is regarding buffer size. In one example, the buffer size (e.g., output buffer 512) of conventional convolutional layer 500 with a 29.7 kilobyte model size can be 67.604 kilobytes—almost three times the model size.

[0061] According to aspects of the present disclosure, a conventional convolutional layer 500 can be transformed to generate an example architecture 520. As shown, the example architecture includes a fused convolution, activation, and max pooling layer 522. That is, unlike the separate convolutional layer 504, the separate activation layer 506 (e.g., a ReLU layer), and the separate max pooling layer 508 in the conventional convolutional layer 500, the example architecture replaces these separate layers with a fused (e.g., merged) convolution, activation, and max pooling layer 522 (which may be referred to as "fused layer 522"). The fused layer 522 can be generated by squeezing the buffers 512 and 514. For example, in some aspects, the output buffer 512 can be removed. By removing the output buffer 512, memory usage can be significantly reduced.

[0062] Additionally, a nested loop transformation may be used to generate instructions for the fusion layer 522 to mix instructions from previous individual layers (e.g., the convolution layer 504, the activation layer 506, and the max pooling layer 508). Thus, the nested loop transformation may enable the compiler to reschedule instructions relative to the order in which instructions for the conventional convolution layer 500 are executed.

[0063] Additionally, note that the example architecture 520 may include a portion (e.g., a layer) of an artificial neural network. In some aspects, an artificial neural network (e.g., Figure 3 350) can be configured such that each convolutional layer includes a subset of the example architecture 520 or artificial neural network layers.

[0064] Because the inputs to the input buffer 502 and the weights 510 remain unchanged in the example architecture 520 , the accuracy of the output of the example architecture 520 may likewise be substantially similar to or remain unchanged from the accuracy of the conventional convolutional layer 500 .

[0065] In some aspects, the example architecture 520 can be further modified to implement enhancements such as quantization and pruning to further increase the processing speed of the corresponding artificial neural network.

[0066] For example, in some aspects, nested loops can be transformed to mix instructions from different layers. Additionally, in some aspects, instructions can be rescheduled for use by a compiler.

[0067] Figure 6A and Figure 6B5 is a diagram illustrating example source code for executing a conventional convolutional layer 500 and source code for executing an example architecture 520, respectively, according to aspects of the present disclosure. Figure 6A As shown, the example source code for executing the conventional convolutional layer 500 includes a configuration block 600, a convolutional layer block 610, and a maximum pooling layer block 620. The configuration block 600 includes configuration information for defining an output buffer 602 of the convolutional layer and an output buffer 604 of the maximum pooling layer of the artificial neural network. The convolutional layer block 610 defines a function (conv_baseline) for performing a convolution operation on the input and weights and accumulating a partial sum (psum) 614 to generate an output. The maximum pooling layer block 620 defines a function (maxpool) for determining a maximum value (max_item) 624 and assigning the maximum value 624 as an output. The convolutional layer block 610 and the maximum pooling layer block 620 utilize similar structures to perform corresponding functions. That is, both the convolutional layer block 610 and the maximum pooling layer block 620 include a set of nested loops (612, 622).

[0068] refer to Figure 6B , used to execute Figure 5 Example source code for executing the example architecture 520. The example source code for executing the example architecture 520 may include a configuration block 650 and a fusion layer block 660. The configuration block 600, the convolution layer block 610, and the maximum pooling layer block 620 may be transformed and replaced with the configuration block 650 and the fusion layer block 660. In the configuration block 650, the output buffers (602, 604) are defined ( Figure 6A The configuration information of the convolution layer block 610 may be replaced with configuration information 652. That is, the output buffer 602 of the convolution layer block 610 is removed. Instead, the configuration block 650 includes only the output buffer 652, which can be used as the output buffer for the fusion layer specified in the fusion layer block 660.

[0069] In addition, the convolution layer block 610 and the maximum pooling layer block 620 are merged or fused and replaced by the fused layer block 660. Utilizing the similar structures of the convolution layer block 610 and the maximum pooling layer block 620, a nested loop transformation can be performed to mix instructions from the convolution layer block 610 and the maximum pooling layer block 620 to generate the fused layer block 660. The nested loop transformation can help the compiler reschedule instructions, which can improve other performance metrics (e.g., beats, cycles, instructions, I / D cache loads and stores, L2 cache, L2 misses, etc.). Loop transformations can include, for example, loop reordering, unrolling, scalar register replacement, or other transformations.

[0070] Loop unrolling is a loop transformation that attempts to optimize execution speed at the expense of memory size. It attempts to reduce loop overhead by increasing the number of instructions executed between branch operations. Loop unrolling involves adding program code for the loop to be executed multiple times within the loop body. In other words, the loop body can be replicated multiple times based on conditions provided in the loop definition. Scalar register substitution, on the other hand, involves replacing repeated accesses to array elements with temporary scalar values. Instead of accessing array elements in memory, array elements can be accessed via registers.

[0071] exist Figures 6A to 6B In the example of , the code for computing the portion and psum 614 in the convolution layer block 610 can be transformed (e.g., unrolled and scalar register replaced) and included in the fused layer block 660 as code portion 664. The determination of the maximum value 624 of the max pooling layer block 620 can be transformed (e.g., unrolled) and incorporated into the fused layer block 660 as code portion 668. By fusing or merging the convolutional layers, activation layers, and max pooling layers as in the fused layer block 660, the memory footprint of the example architecture 520 can be significantly reduced compared to the memory footprint of the conventional convolution layer 500 corresponding to the separate blocks 610 and 620.

[0072] Thus, by executing source code 650 and 660, an artificial neural network including one or more fusion layers can be operated to, for example, perform an inference task. For example, input can be received by the artificial neural network. The input can include, for example, sensor input or an image.

[0073] In some aspects, the merging of the convolutional layer, the activation layer, and the maximum pooling layer to produce the fusion layer block 660 can be performed such that the accuracy level of the corresponding artificial neural network can be maintained. That is, the accuracy of the artificial neural network corresponding to blocks 600, 610, and 620 can be approximately equal to the accuracy of the artificial neural network corresponding to blocks 650 and 660. In some aspects, further enhancements such as quantization, pruning, or other model compression techniques can be implemented to further increase the processing speed of the corresponding artificial neural network at the expense of some loss of accuracy.

[0074] Therefore, you can use Figure 6B The source code 660 to configure includes Figure 5 The artificial neural network of the fusion layer 522. In some aspects, the artificial neural network can be implemented on a resource-constrained device such as a mobile device or an IoT device.

[0075] In operation, an input may be received by the artificial neural network. The input may be stored in an input buffer 502. The input buffer 502 may be implemented using a configuration block 650. The input may be provided to a fusion layer 522. The fusion layer 522 may execute a set of instructions corresponding to the functionality of a convolutional, activation, and max pooling layer (in Figure 6B 660). The fusion layer 522 may perform a convolution operation on the input and weights and accumulate the partial sums (e.g., t1 to t4) in code block 664. The partial sums may be rectified and max-pooled in code block 668 to generate the fusion layer output. The output of the fusion layer 522 may be stored in the output buffer 514. The output 514 may be provided to successive layers of the artificial network and may be used to compute inferences.

[0076] Figure 7 is a flow chart illustrating a processor-implemented method 700 for generating inferences for resource-constrained device code according to aspects of the present disclosure. The processor-implemented method 700 may be a method using a processor such as, for example, Figure 1 The CPU 102 or NPU 108 is used to execute the Figure 7 As shown, at block 702, the processor receives input via an artificial neural network (ANN), which includes one or more fusion layers. Figure 6B As described, input may be received by the artificial neural network. The input may include, for example, a signal or an image from a sensor.

[0077] The artificial neural network can be, for example, a convolutional neural network. Figure 5 As described, the example architecture 520 may include a portion (e.g., a layer) of an artificial neural network. In some aspects, an artificial neural network (e.g., Figure 3 350) can be configured such that each convolutional layer includes a subset of the example architecture 520 or artificial neural network layers.

[0078] At block 704, the processor processes the input using the one or more fusion layers to generate a fused output. Figure 6B As described, the input may be provided to the fusion layer 522. The fusion layer 522 may execute a set of instructions corresponding to the functionality of the convolution, activation, and max pooling layers (in Figure 6B 660). The fusion layer 522 may perform a convolution operation on the input and weights and accumulate the partial sums (e.g., t1 to t4) in code block 664. The partial sums may be rectified and max-pooled in code block 668 to generate the fusion layer output. The output of the fusion layer 522 may be stored in the output buffer 514.

[0079] At block 706, the processor generates an inference using the fused output via the ANN. Figure 6B As described, output 514 may be provided to successive layers of an artificial network and may be used to compute inferences.

[0080] In some aspects, the output source code 520 may be further modified to implement enhancements such as quantization, pruning, or model compression to trade off some model accuracy for increased processing speed of the corresponding artificial neural network.

[0081] Specific implementation examples are included in the following numbered clauses.

[0082] 1. A processor-implemented method, the processor-implemented method comprising:

[0083] receiving an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers;

[0084] processing the input using the one or more fusion layers to generate a fused output;

[0085] as well as

[0086] Inferences are generated using the fused output by the ANN.

[0087] 2. The processor-implemented method of clause 1, wherein the one or more fusion layers perform a set of merging functions of convolutional layers, activation layers, and max pooling layers.

[0088] 3. The processor-implemented method of clause 1 or 2, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

[0089] 4. A processor-implemented method according to any of clauses 1 to 3, wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

[0090] 5. A device comprising:

[0091] Memory; and

[0092] At least one processor coupled to the memory, the at least one processor

[0093] Configured to:

[0094] receiving an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers;

[0095] processing the input using the one or more fusion layers to generate a fused output; and

[0096] Inferences are generated using the fused output by the ANN.

[0097] 6. The apparatus of clause 5, wherein the one or more fusion layers perform a set of merging functions of convolutional layers, activation layers, and max pooling layers.

[0098] 7. The apparatus of clause 5 or 6, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

[0099] 8. An apparatus according to any of clauses 5 to 7, wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

[0100] 9. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0101] Program code for receiving input via an artificial neural network (ANN), the ANN comprising one or more fusion layers;

[0102] program code for processing the input using the one or more fusion layers to generate a fused output; and

[0103] Program code for generating an inference using the fused output via the ANN.

[0104] 10. The non-transitory computer-readable medium of clause 9, wherein the one or more fusion layers perform a set of merging functions of convolutional layers, activation layers, and max pooling layers.

[0105] 11. The non-transitory computer-readable medium of clause 9 or 10, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

[0106] 12. The non-transitory computer-readable medium of any one of clauses 9 to 11, wherein the ANN comprises a convolutional layer, an activation layer, or a max pooling layer.

[0107] 13. A device comprising:

[0108] means for receiving input via an artificial neural network (ANN), the ANN comprising one or more fusion layers;

[0109] means for processing the input using the one or more fusion layers to generate a fused output; and

[0110] Means for generating an inference using the fused output via the ANN.

[0111] 14. The apparatus of clause 13, wherein the one or more fusion layers perform a set of merging functions of convolutional layers, activation layers, and max pooling layers.

[0112] 15. The apparatus of clause 13 or 14, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

[0113] 16. An apparatus according to any of clauses 13 to 15, wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

[0114] In some aspects, the receiving means, processing means, and / or generating means may be the CPU 102, program memory associated with the CPU 102, the DSP 106, the NPU 108, the fully connected layer 362, the NPU 428, and / or the routing connection processing unit 216 configured to perform the functions recited. In other configurations, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0115] Specific implementation examples are described in the following numbered clauses:

[0116] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. These means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally speaking, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired means-plus-function components with similar numbers.

[0117] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, and the like. Furthermore, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0118] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to encompass: a, b, c, ab, ac, bc, and abc.

[0119] The various illustrative logical blocks, modules, and circuits described in conjunction with this disclosure may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic components, discrete hardware components, or any combination thereof, designed to perform the functions described. While a general purpose processor may be a microprocessor, in an alternative embodiment, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0120] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of the two. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. A storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral with the processor.

[0121] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0122] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0123] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, the machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging materials.

[0124] In a hardware implementation, the machine-readable medium may be part of a processing system separate from the processor. However, as will be readily appreciated by those skilled in the art, the machine-readable medium or any portion thereof may be external to the processing system. By way of example, the machine-readable medium may include a transmission line, a carrier modulated by data, and / or a computer product separate from the device, all of which may be accessed by the processor via a bus interface. Alternatively or in addition, the machine-readable medium or any portion thereof may be integrated into the processor, such as in the case of a cache and / or general register file. Although the various components discussed may be described as having specific locations, such as local components, they may also be configured in various ways, such as with certain components being configured as part of a distributed computing system.

[0125] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of a machine-readable medium, all of which are linked together with other support circuits via an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application-specific integrated circuit (ASIC) having a processor, bus interface, user interface, support circuits, and at least a portion of a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic components, discrete hardware components, or any other suitable circuits, or any combination of circuits capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0126] The machine-readable medium may include multiple software modules. These software modules include instructions that, when executed by a processor, cause a processing system to perform various functions. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, a software module may be loaded from a hard drive into RAM. During execution of the software module, the processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When reference is made below to the functionality of a software module, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. Furthermore, it should be understood that various aspects of the present disclosure result in improvements to the functionality of a processor, computer, machine, or other system that implements such aspects.

[0127] If implemented in software, each function may be stored as one or more instructions or codes on or sent through a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other media that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is sent from a website, server, or other remote source using a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwaves, the coaxial cable, optical cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. As used herein, disks and optical disks include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and optical disks. Optical disks, where magnetic disks typically reproduce data magnetically, and optical disks, which use lasers to reproduce data optically. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Furthermore, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0128] Thus, certain aspects may include a computer program product for performing the operations presented herein. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions, which are executable by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0129] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such a device can be coupled to a server to facilitate the transmission of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk) so that once the storage component is coupled to or provided to the device, the user terminal and / or base station can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to the device can be utilized.

[0130] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, the processor-implemented method comprising: receiving an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers; processing the input using the one or more fusion layers to generate a fused output; as well as Inferences are generated using the fused output by the ANN.

2. The processor-implemented method of claim 1 , wherein the one or more fusion layers perform a set of merging functions of convolutional layers, activation layers, and max pooling layers.

3. The processor-implemented method of claim 1, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

4. The processor-implemented method of claim 1 , wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

5. A device comprising: Memory; and at least one processor coupled to the memory, the at least one processor configured to: receiving an input via an artificial neural network (ANN), the ANN comprising one or more fusion layers; processing the input using the one or more fusion layers to generate a fused output; as well as Inferences are generated using the fused output by the ANN.

6. The apparatus of claim 5, wherein the one or more fusion layers perform a set of merging functions of a convolutional layer, an activation layer, and a maximum pooling layer.

7. The apparatus of claim 5, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

8. The device of claim 5, wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

9. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code for receiving input via an artificial neural network (ANN), the ANN comprising one or more fusion layers; program code for processing the input using the one or more fusion layers to generate a fused output; and Program code for generating an inference using the fused output via the ANN.

10. The non-transitory computer-readable medium of claim 9, wherein the one or more fusion layers perform a set of merging functions of a convolutional layer, an activation layer, and a max pooling layer.

11. The non-transitory computer-readable medium of claim 9, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

12. The non-transitory computer-readable medium of claim 9, wherein the ANN comprises a convolutional layer, an activation layer, or a max pooling layer.

13. A device comprising: means for receiving input via an artificial neural network (ANN), the ANN comprising one or more fusion layers; means for processing the input using the one or more fusion layers to generate a fused output; and Means for generating an inference using the fused output via the ANN.

14. The apparatus of claim 13, wherein the one or more fusion layers perform a set of merging functions of a convolutional layer, an activation layer, and a maximum pooling layer.

15. The apparatus of claim 13, wherein the ANN is operated using one of a mobile device or an Internet of Things (IoT) device.

16. The device of claim 13, wherein the ANN comprises one or more of a convolutional layer, an activation layer, or a max pooling layer.

Images