Redundancy of arrays of non-volatile memory cells using tag registers and redundancy of redundant arrays using tag registers

Abstract

Numerous examples of systems and methods for implementing redundancy are disclosed. In one example, a system includes an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to a respective row in the array and a respective row in the redundant array, and including a row tag register and a redundant row tag register.

Description

[0001] Priority Declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 442,723, filed on February 1, 2023, and entitled “Redundancy for Artificial Neural Network Array,” and U.S. Patent Application No. 18 / 134,928, filed on April 14, 2023, and entitled “Redundancy For An Array Of Non-Volatile Memory Cells Using Tag Registers.” Technical Field

[0003] Numerous examples of circuits and methods for implementing redundancy for arrays of non-volatile memory cells using tag registers are disclosed. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network is illustrated, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, this complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high-cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicants previously disclosed an artificial (simulated) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The nonvolatile memory array operates as an analog neural memory and includes nonvolatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cells

[0009] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls its electrical conductivity), and is formed over a portion of the source region 14. A wordline terminal 22 (which is typically coupled to a wordline) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls its electrical conductivity), and a second portion extending upward and over the floating gate 20. The floating gate 20 and the wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to wordline terminal 22.

[0011] The memory cell 210 is programmed by source side injection (SSI) with hot electrons by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). Electrons flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, they accelerate and become heated. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons are injected through the gate oxide onto the floating gate 20.

[0012] Memory cell 210 is read by placing a positive read voltage across drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0014] Table 1: Figure 2 Operation of the flash memory unit 210

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, Figure 3 A quad-gate memory cell 310 is depicted, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0018] Table 2: Figure 3 Operation of the flash memory unit 310

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] Figure 4 Depicted is a tri-gate memory cell 410, which is another type of flash memory cell. Figure 3 The memory cell 310 is identical to the memory cell 410 except that the memory cell 410 does not have a separate control gate. Except that no control gate bias is applied, the erase operation (thus erasing by using the erase gate) and the read operation are the same as Figure 3 The programming operation is also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during the programming operation to compensate for the lack of control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0022] Table 3: Figure 4 Operation of the flash memory unit 410

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] Figure 5 Depicted is a stacked gate memory cell 510, which is another type of flash memory cell. Figure 2 18 and drain region 16. Memory cell 210 is similar to that of FIG10 , except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electrons flowing from source region 14 toward drain region 16, and read operations are similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read, erase, and program operations:

[0026] Table 4: Figure 5 Operation of the flash memory unit 510

[0027]

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of nonvolatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured so that each memory cell could be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells was provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is effectively analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0031] Neural Networks Using Nonvolatile Memory Cell Arrays

[0032] Figure 6 This example conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0033] For this example, S0 is the input layer, which is a 32×32 pixel RGB image with 5 bits of precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and provided by the first synapse of CB1 for generating a pixel in one of the feature maps of layer C1. The 3×3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of three pixels on the right is added and a column of three pixels on the left is released), whereby the nine pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3×3 filter has scanned all three colors and all bits (precision values) across the entire 32×32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 have been calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30×30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 is composed of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as edge identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. The purpose of pooling function P1 is to average neighboring locations (or a max function can also be used) to, for example, reduce dependencies on edge locations and reduce the size of the data before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays, each with 15×15 pixels). Synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4×4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse on CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, that is, every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, this output can indicate the identification or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3, and CB4 in FIG. 1 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0038] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33, and each output line (source line or bit line) adds them together to produce an output, which will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient due to its in-situ memory calculations.

[0039] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summation of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The elements of the feature map of layer C1 in the image processing unit are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from existing neuron layers or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 constitute a plurality of neurons.

[0041] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 FIG. 1 is a block diagram illustrating the use of multiple layers of VMM arrays 32, labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog levels of the matrix multiplier of the input VMM array 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input to the input VMM array 32a.

[0043] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates output that is provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a separate physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Figure 9 Depicted is a neuron VMM array 900, which is particularly suitable for Figure 3 The memory cells 310 shown are used as synapses and components for neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0046] In VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even-numbered rows are used, and in another example, only odd-numbered rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, the non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is the product of (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current into an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of the reference memory cell or the peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] Iout=wa*Io*e (Vg) / nVt ,Right now

[0057] Iout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate body bias voltage, and the substrate body bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061]

[0062] where Vth0 is the threshold voltage with zero substrate bias, is the surface potential, and γ is the bulk effect parameter.

[0063] The word line or control gate may be used as the input to the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=α(Vgs-Vth)

[0067] Meaning that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can serve as the input of the memory cell operating in the linear region. The bit line or source line can serve as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids= 1 / 2*β*(Vgs-Vth) 2 ;β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means the weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region. The bit line or source line can be used as the output of an output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear, or saturation regions) of each layer or multiple layers of a neural network.

[0075] US Patent No. 10,748,630 describes Figure 7 Other examples of VMM arrays 32 of FIGURE 1 are incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Figure 10 Depicted is a neuron VMM array 1000, which is particularly suitable for Figure 2 Memory cell 210 is shown and serves as a synapse between the input layer and the next layer. VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. Reference arrays 1001 and 1002, arranged in the column direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected via a multiplexer 1014 (only partially depicted), into which the current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert into input voltages to supply to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits and is also highly power-efficient. Here, the voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts the operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Figure 10 Operations of the VMM array 1000:

[0080]

[0081] Figure 11 Depicted is a neuron VMM array 1100 particularly suitable for use in Figure 2Memory cell 210 is shown and serves as a synapse and component for neurons between the input layer and the next layer. VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 extend in the row direction of VMM array 1100. The VMM array is similar to VMM 1000, except that in VMM array 1100, the word lines extend in the vertical direction. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts the operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Figure 11 Operation of the VMM array 1100

[0084]

[0085] Figure 12 Depicted is a neuron VMM array 1200, which is particularly suitable for Figure 3 Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected via a multiplexer 1212 (only partially shown), with the current input flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a corresponding multiplexer 1205 and a cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) for each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0086] The memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages to provide to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array and then adds all the results (cell currents) to produce the output, which appears at BL0-BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all the currents from the memory cells connected to that particular bit line.

[0087] The VMM array 1200 implements unidirectional tuning of the nonvolatile memory cells in the memory array 1203. That is, each nonvolatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell is erased and the sequence of partial programming operations begins again. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (this is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0088] Table 7 depicts the operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0089] Table 7: Figure 12 Operation of the VMM array 1200

[0090]

[0091] Figure 13 Depicted is a neuron VMM array 1300, which is particularly suitable for Figure 3Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the nonvolatile memory cells connected to that particular bit line.

[0092] Table 8 depicts the operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0093] Table 8: Figure 13 Operation of the VMM array 1300

[0094]

[0095] Figure 14 Depicted is a neuron VMM array 1400, which is particularly suitable for Figure 2 The memory cell 210 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In the VMM array 1400, the inputs INPUT0, ..., INPUT N On bit lines BL0, BL N The signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0096] Figure 15 Depicted is a neuron VMM array 1500, which is particularly suitable for Figure 2 The memory cell 210 is shown and serves as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, INPUT1, INPUT2 and INPUT3 are received on the source lines SL0, SL1, SL2 and SL3 respectively, and the outputs OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0097] Figure 16 Depicted is a neuron VMM array 1600, which is particularly suitable for Figure 2 The memory unit 210 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0098] Figure 17 Depicted is a neuron VMM array 1700, which is particularly suitable for Figure 3 The memory unit 310 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0099] Figure 18 Depicted is a neuron VMM array 1800 particularly suitable for use in Figure 4 The memory unit 410 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT n On the vertical control gate lines CG0, ..., CG N The signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0100] Figure 19Depicted is a neuron VMM array 1900, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are received at the gates of bit line control gates 1901-1, 1901-2, ..., 1901-(N-1), and 1901-N, which are coupled to bit lines BL0, ..., BL N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0101] Figure 20 Depicted is a neuron VMM array 2000, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On bit lines BL0, BL N Generate on.

[0102] Figure 21 Depicted is a neuron VMM array 2100, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, ..., CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical source lines SL0, ..., SL N On the generation, each source line SL i The source line coupled to all memory cells in column i.

[0103] Figure 22 Depicted is a neuron VMM array 2200, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, ..., CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical bit lines BL0, BL N On the generated, where each bit line BL i The bit line coupled to all memory cells in column i.

[0104] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0105] Generally speaking, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two hybrid memory cells (the average of the two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In the case of two hybrid memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0106] Figure 23 A VMM system 2300 is depicted. In some examples, the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 2300, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 2301 and 2302), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. While described above with respect to W− lines interspersed among W+ lines in an alternating manner, in other examples, the W+ lines and W− lines may be arbitrarily located anywhere in the array.

[0107] Figure 24Another example is depicted in a VMM system 2410 where positive weights W+ are implemented in a first array 2411 and negative weights W− are implemented in a second array 2412 that is separate from the first array, and the resulting weights are appropriately combined via a summing circuit 2413 .

[0108] Figure 25 A VMM system 2500 is depicted, in which weights W stored in a VMM array are stored as a differential pair of W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). VMM system 2500 includes array 2501 and array 2502. Half of the bit lines in each of arrays 2501 and 2502 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of arrays 2501 and 2502 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. Subtraction operations are performed by summing circuits (such as summing circuits 2503, 2504, 2505, and 2506), which receive current from the W+ lines and the W- lines. The outputs of the W+ lines and the W- lines from each array 2501, 2502, respectively, are combined to effectively give W = W+ - W- for each (W+, W-) element pair for all (W+, W-) line pairs. Additionally, the W values ​​from each array 2501 and 2502 can be further combined by summing circuits 2507 and 2508 so that each W value is the result of subtracting the W value from array 2502 from the W value from array 2501, meaning that the final result from summing circuits 2507 and 2508 is the difference of two differences.

[0109] Each nonvolatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0110] Prior art non-volatile memory systems outside the context of VMMs and neural networks provide redundant rows. During manufacturing and testing, rows containing one or more bad cells are identified and the addresses of such bad rows are recorded in a non-volatile table along with a mapping of the bad row to a specific redundant row. During operation, if the address of a bad row is received during a write or read operation, the system disables reading or writing of that row and instead enables reading or writing of the specific redundant row associated with the bad row in the non-volatile table.

[0111] Figure 26A prior art memory system 2600 for replacing a row containing one or more redundant rows is disclosed. Memory system 2600 includes an address comparator 2601, an inverter 2602, a row decoder 2603, a redundant row decoder 2604, an array 2605, a redundant array 2606, and a table 2607. During manufacturing and testing, table 2607 is populated with the addresses XA'[10:0] of bad rows and the addresses XRA[10:0] of corresponding redundant rows assigned to replace the corresponding bad rows. Table 2607 is stored in a non-volatile storage device, such as a ROM, flash memory, or a set of fuses.

[0112] During a read or write operation, an address XA[10:0] is received for the read or write operation. Address comparator 2601 compares the address with the address of the bad row stored in table 2607. In this example, an example bad address XRA[10:0] is shown. If address comparator 2601 identifies a match indicated by ADDR MATCH, the received address XA[10:0] is a known bad address. Signal ADDR MATCH is applied to redundant row decoder 2604 as enable signal EN_RED_XDEC, and the inverse of ADDR MATCH is applied to row decoder 2603 as disable signal DISABLE_XDEC_B. Row decoder 2603 also receives address XA[10:0]. However, because row decoder 2603 receives the disable signal, it does not take any action on array 2605. Instead, redundant row decoder 2604 is enabled and a corresponding row in redundant array 2606 corresponding to a corresponding redundant row previously assigned to a corresponding bad row indicated by XA[10:0], which is obtained as XRA[10:0] from table 2607, is enabled. Thus, a write or read operation is performed on the corresponding redundant row instead of the corresponding bad row.

[0113] This prior art redundancy mechanism is not applicable to neural read operations in a VMM in an artificial neural network because during a neural read operation, multiple rows are read at a time and no individual addresses XA are received that can form the basis for comparison with a set of addresses of known bad rows. Therefore, an artificial neural network requires a redundancy mechanism for use during a neural read operation. Summary of the Invention

[0114] Numerous examples of circuits and methods for implementing redundancy in an array of nonvolatile memory cells using tag registers are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0115] Figure 1 A diagram illustrating an artificial neural network.

[0116] Figure 2A prior art split-gate flash memory cell is depicted.

[0117] Figure 3 Another prior art split-gate flash memory cell is depicted.

[0118] Figure 4 Another prior art split-gate flash memory cell is depicted.

[0119] Figure 5 Another prior art split-gate flash memory cell is depicted.

[0120] Figure 6 A diagram illustrating different levels of an artificial neural network utilizing one or more non-volatile memory arrays.

[0121] Figure 7 FIG. 1 is a block diagram illustrating a VMM system.

[0122] Figure 8 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems.

[0123] Figure 9 Another example of a VMM system is depicted.

[0124] Figure 10 Another example of a VMM system is depicted.

[0125] Figure 11 Another example of a VMM system is depicted.

[0126] Figure 12 Another example of a VMM system is depicted.

[0127] Figure 13 Another example of a VMM system is depicted.

[0128] Figure 14 Another example of a VMM system is depicted.

[0129] Figure 15 Another example of a VMM system is depicted.

[0130] Figure 16 Another example of a VMM system is depicted.

[0131] Figure 17 Another example of a VMM system is depicted.

[0132] Figure 18 Another example of a VMM system is depicted.

[0133] Figure 19 Another example of a VMM system is depicted.

[0134] Figure 20 Another example of a VMM system is depicted.

[0135] Figure 21 Another example of a VMM system is depicted.

[0136] Figure 22 Another example of a VMM system is depicted.

[0137] Figure 23 Another example of a VMM system is depicted.

[0138] Figure 24 Another example of a VMM system is depicted.

[0139] Figure 25 Another example of a VMM system is depicted.

[0140] Figure 26 A prior art memory system with redundancy is depicted.

[0141] Figure 27 Depicts the VMM system.

[0142] Figure 28 Depicted are example input blocks for implementing row redundancy in a VMM array.

[0143] Figure 29 Depicted are example input blocks for implementing row redundancy in a VMM array.

[0144] Figure 30 Depicted is the row tag register loading circuitry.

[0145] Figure 31 Depicted is the row register loading circuit.

[0146] Figure 32 Depicts a row register load operation.

[0147] Figure 33 Depicts a row tag register load operation.

[0148] Figure 34 Depicted are neural reading methods.

[0149] Figure 35 Depicted are output blocks for implementing column redundancy in a VMM array.

[0150] Figure 35 Depicted are neural reading methods. DETAILED DESCRIPTION

[0151] VMM system architecture

[0152] Figure 27A block diagram of a VMM system 2700 is depicted. The VMM system 2700 includes a VMM array 2701, a redundant array 3519A (redundant row array), a redundant array 3519B (redundant column array), a row decoder 2702, a high voltage decoder 2703, a column decoder 2704, a bit line driver 2705 (such as a bit line control circuit for programming), an input circuit 2706, an output circuit 2707, a control logic unit 2708, and a bias generator 2709. The VMM system 2700 also includes a high voltage generation block 2710, which includes a charge pump 2711, a charge pump regulator 2712, and a high voltage level generator 2713. The VMM system 2700 also includes a (program / erase or weight tuning) algorithm controller 2714, an analog circuit 2715, a control engine 2716 (which may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited thereto), a test control logic component 2717, and a static random access memory (SRAM) block 2718 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial and output neuron data) or data used for programming (such as data for an entire row or multiple rows). Here, redundant arrays 3519A and 3519B are shown as being part of the same physical array as the VMM array 2701, but one of ordinary skill in the art will appreciate that the redundant arrays 3519A and 3519B and the VMM array 2701 may alternatively be located in respective separate physical arrays.

[0153] Input circuitry 2706 may include circuitry such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 2706 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. Input circuitry 2706 may implement a temperature compensation function for the input levels. Input circuitry 2706 may implement an activation function, such as a ReLU or a sigmoid. Input circuitry 2706 may store digital activation data to be applied as an input signal or combined with an input signal during programming or read operations. The digital activation data may be stored in registers. Input circuitry 2706 may include circuitry for driving array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuitry and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0154] Output circuitry 2707 may include circuitry such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting analog neuron outputs into digital bits), an AAC (analog-to-analog converter, such as, but not limited to, a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. Output circuitry 2707 may convert the array output into activation data. Output circuitry 2707 may implement an activation function, such as a rectified linear activation function (ReLU) or a sigmoid. Output circuitry 2707 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. Output circuitry 2707 may implement a temperature compensation function for the neuron output or array output (such as a bitline output) to maintain approximately constant power consumption of the array over a temperature range or to improve the accuracy of the array (neuron) output, such as by maintaining approximately the same IV slope over a temperature range. The output circuit 2707 may include a register for storing output data.

[0155] VMM array 2701, redundant array 3519A, and redundant array 3519B each include an array of nonvolatile memory cells arranged in rows and columns, wherein the nonvolatile memory cells are Figure 2 、 Figure 3 、 Figure 4 or Figure 5 210, 310, 410, or 510, or other types known to those skilled in the art. In one example, a nonvolatile memory cell is Figure 2 、 Figure 3 or Figure 4 In another example, the nonvolatile memory cell is as shown in FIG. Figure 5 A stacked-gate flash memory cell is shown.

[0156] Figure 28An input block 2800 is depicted that provides row (or sector) redundancy during neural read operations of the VMM array 2701 . Input block 2800 includes: address decoders 2801-0 to 2801-n, each corresponding to one of row numbers 0 to n in VMM array 2701; redundant address decoders 2811-0 to 2811-m, each corresponding to one of redundant row numbers 0 to m in redundant array 3519A; row registers 2802-0 to 2802-n, each corresponding to one of rows numbered 0 to n in VMM array 2701 and coupled to the associated address decoder 2801; redundant row registers 2812-0 to 2812-m, each corresponding to one of redundant row numbers 0 to m in redundant array 3519A and coupled to the associated redundant address decoder 2811; and row tag registers 2803-0 to 2803-n, each corresponding to one of row numbers 0 to n in VMM array 2701. corresponding to, and coupled to, the associated address decoder 2801 and row register 2802; redundant row tag registers 2813-0 to 2813-m, which correspond to one of the redundant row numbers 0 to m in the redundant array 3519A, respectively, and are coupled to the associated redundant address decoder 2811 and redundant row register 2812; digital-to-analog (DAC, which may be referred to as row DACs, or local DACs) converters 2804-0 to 2804-n, which correspond to one of the row numbers 0 to n in the VMM array 2701, respectively, and are coupled to the associated row register 2802 and row tag register 2803; and redundant digital-to-analog converters 2814-0 to 2814-m, which correspond to one of the rows numbered 0 to m in the redundant array 3519A, respectively, and are coupled to the associated redundant row register 2812 and redundant row tag register 2813.

[0157] Optionally, rows are organized into sectors, and sectors are organized into sector groups. In one example, a corresponding sector contains two rows, and a corresponding sector group contains four sectors. Optionally, row register 2802 and redundant row register 2812 can each store 8 bits, 4 bits, 16 bits, or any other number of bits. Optionally, row tag register 2803 and redundant row tag register 2813 can each store 1 bit, which operates as a tag bit for its associated row.

[0158] At the start of a neural read operation, the row registers 2802-0 to 2802-n and the redundant row registers 2812-0 to 2812-m are loaded with digital input bits DINx (where x is the number of bits in DIN, such as 128 bits), where the digital input bits may come from the original input data (e.g., an image) or from the output of a previous network layer to be applied to that particular row during the neural read operation. ENRR is an enable signal that is used to enable loading of the row registers. When enabled, the clock signal CLK is used to load the digital input bits DINx into the corresponding row registers 2802 and redundant row registers 2812. In one example, x=128, and the row registers 2802 and redundant row registers 2812 each store 8 bits, in which case 16 row registers 2802 and redundant row registers 2812 may be loaded per clock cycle. In the event that a particular row of the VMM array 2701 is known to be a bad row, its associated redundant row register will be loaded as a replacement or supplement to the row register for the bad row. Reference is made below Figure 32 This register load operation is described in more detail.

[0159] Reference again Figure 28 At the start of a neural read operation, or before a neural read operation, if the associated row is a good row and is enabled (which would be indicated by a DIN received for the row tag bit = "1"), the row tag registers 2803-0 and 2803-n are respectively loaded with a first value (e.g., "1"), and if the associated row is a bad row (which would be indicated by a DIN received for the row tag bit = "0"), the row tag registers are respectively loaded with a second value (e.g., "0"). Similarly, if the redundant row is to be used and enabled (which would be indicated by a DIN for the redundant row tag bit = "1"), the redundant row tag registers 2813-0 to 2813-m are respectively loaded with a third value (e.g., "1"), and if the redundant row is not to be used (which would be indicated by a DIN for the redundant row tag bit = "0"), the redundant row tag registers are respectively loaded with a fourth value (e.g., "0"). DINx, ENRT (which is the enable signal to enable loading of the row tag register) and CLK signals are referenced below. Figure 30 The tag bit loading circuit 3000 described in more detail is used together for this tag register loading operation. In the example where x=128, 128 row tag registers 2803 and redundant row tag registers 2813 are loaded per clock cycle. Figure 33 This row tag register load example is described in more detail.

[0160] Alternatively, instead of loading all row tag registers 2803 and all redundant row tag registers 2813 with tag bit values, the row address XA[k:0] is used to access one bad row or one redundant row at a time, and the associated row tag register 2803 is directly loaded with a second value (e.g., "0") to indicate the bad row, and the associated redundant row tag register 2813 is loaded with a third value (e.g., "1") to indicate that the redundant row will be used.

[0161] Reference again Figure 28 After loading the row register 2802, redundant row register 2812, row tag register 2803, and redundant row tag register 2813, a neural read operation can be performed. In the neural read operation, the address (XA[k:0]) is not required because all rows in the VMM array are to be read at once, and instead, read operations for those rows can be enabled by a global enable signal ENRDG. All row registers 2802 receiving the enable signal ENRDG output their stored activation signals to their associated digital-to-analog converters 2804. If the tag bit in the row tag register 2803 indicates a good row (e.g., tag bit = "1"), the row tag register 2803 will assert an output enable signal to the associated digital-to-analog converter 2804 (e.g., output = "1"). If the tag bit in the row tag register 2803 indicates a bad row (e.g., tag bit = "0"), the row tag register 2803 will deassert an output enable signal to the associated digital-to-analog converter 2804 (e.g., output = "0"). Then, digital-to-analog converter 2804 receiving the asserted output enable signal from row tag register 2802 converts the received digital value received from the associated row register 2803 into analog voltages CG0 to CGn, which are applied to corresponding control gate lines in VMM array 2701.

[0162] In another example, the global enable signal ENRDG enables the DAC to convert the inputs from the row register and the tag bit into analog voltages CGx, which are applied to the corresponding control gates in the VMM array 2701. In this case, the row register and the tag bit are pre-enabled. In another example, the global enable signal ENRDG enables the analog output CGx of the DAC through an output multiplexer (not shown) at the DAC output so as to be applied to the corresponding control gates in the VMM array 2701. In this case, the row register, the tag bit, and the DAC are pre-enabled.

[0163] Similarly, during a neural read operation, a redundant address (XRA[k:0]) is not required, and instead, a read operation of the redundant row can be enabled by a global enable signal ENRDG. All redundant row registers 2812 that receive the enable signal ENRDG output their stored activation signals to their associated redundant digital-to-analog converters 2814. If the tag bit in the row tag register 2813 indicates that a redundant row is to be used (e.g., redundant tag bit = "1"), the redundant row tag register 2813 will assert an output enable signal to the associated redundant digital-to-analog converter 2814 (e.g., output = "1"). If the tag bit in the redundant row tag register 2813 indicates that a redundant row is not to be used (e.g., redundant tag bit = "0"), the redundant row tag register 2814 will de-assert the output enable signal to the associated redundant digital-to-analog converter 2814 (e.g., output = "0"). Redundant digital-to-analog converter 2814, which receives an asserted output enable signal from redundant row tag register 2812, converts the digital value received from the associated redundant row register 2813 into analog voltages CGR0 to CGRm, which are applied to corresponding control gate lines in redundant array 2719A. Similarly to a regular row, a global enable signal ENRDG optionally enables the DAC, or enables the output of the DAC for a regular row.

[0164] The end result is that all good rows in VMM array 2701, but not bad rows, will receive input values, and redundant rows in redundant array 2719 associated with bad rows in VMM array 2701 will receive input values ​​and will receive the desired output current (such as in the form of current from the bit lines of VMM array 2701 and redundant array 3519A) as the output of the neural read operation. The row tag register and the redundant row tag register are used to identify the row and redundant row to be read during a neural read operation.

[0165] Figure 29 An input block 2900 is depicted, which is connected to Figure 282904, and redundant sample-and-hold logic and buffers 2914, as well as a global digital-to-analog converter (DAC) 2920 and sample-and-hold (S / H) and DAC logic circuit 2910. During a neural read operation, activation data from row register 2802 and redundant row register 2812 is provided to the corresponding S / H logic and buffers 2804. The S / H and DAC logic 2910 controls the global DAC 2920 to provide a global DAC analog voltage to the local S / H logic and buffers 2904. The S / H and DAC logic 2920, in conjunction with logic within the logical S / H logic and buffers 2904, samples the corresponding global DAC analog voltage into a local buffer within the logic S / H and logic buffers. Further details regarding the specific implementation of the sample and hold buffer, global digital-to-analog converter, and S / H and DAC logic circuits are included in U.S. patent application Ser. No. 18 / 077,686, filed Dec. 8, 2022, and entitled “Input Circuit for Artificial Neural Network Array,” which is incorporated herein by reference. The row tag register 2803 and the redundant row tag register 2813 are similar to those described above for Figure 28 The asserted or deasserted output enable signal is generated in the same manner as described above. The sample and hold buffer 2904 receiving the asserted output enable signal from the row tag register 2803 or the redundant row tag register 2813 and the redundant sample and hold buffer apply the analog voltages CGR0 to CGRm held by them to the corresponding control gate lines in the redundant array 2719A.

[0166] Figure 30 Depicted is a row tag register loading circuit 3000 that includes address comparators 3001 and 3011 and switches 3002 , 3003 , 3012 , and 3013 and is used to load tag bits and redundant tag bits received as DIN during a load operation into the row tag register 2803 and the redundant row tag register 2813 .

[0167] The address comparator 3001 and switches 3002 and 3003 are used to load data into the row tag register 2803. The address comparator 3001 compares the received row address XA[k:0] with the known bad address XA′[k:0] stored in table 2607. If there is a match, switch 3003 is closed and switch 3002 is open, and DIN_INT, which is the input to the corresponding tag register, is grounded (i.e., DIN_INT = "0"). This will cause the tag bit loaded into the tag bit register to be "0". If there is a mismatch, switch 3003 is open and switch 3002 is closed, and DIN_INT is the same value as the received DIN value, which defaults to "1". As a result of this operation, if the row is a good row, the stored tag bit will be "1" (a first value), and if the row is a bad row, the stored tag bit will be "0" (a second value).

[0168] Address comparator 3011 and switches 3012 and 3013 are used to program redundant tag bit register 2813. Address comparator 3011 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3013 closes and switch 3012 opens, and DIN_INT will have the same value as the received DIN value, which defaults to "1". This will cause the redundant tag bit loaded into the redundant tag bit register to be "1". If there is a mismatch, switch 3013 opens and switch 3012 closes, which will cause DIN_INT to be grounded (i.e., DIN_INT = "0"). This will cause the redundant tag bit loaded into the redundant tag bit register to be "0". As a result of this operation, if the redundant row is to be used, the stored redundant tag bit will be "1" (a first value), and if the redundant row is not to be used, the stored redundant tag bit will be "0" (a second value).

[0169] Figure 31 Depicted is a row register loading circuit 3100 that includes address comparators 3101 and 3111 and switches 3102, 3103, 3112, and 3113 and is used to load the row register 2802 and the redundant row register 2812 with activation data received as DIN during a load operation.

[0170] The address comparator 3101 and switches 3102 and 3103 are used to load data into the row register 2802. The address comparator 3101 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3103 is closed and switch 3102 is opened, and DIN_INT, which is the input of the corresponding row register 2802, is grounded (i.e., DIN_INT[7:0]="0"). This will cause the bits loaded into the corresponding row register 2802 to be all "0". If there is a mismatch, switch 3103 is opened and switch 3102 is closed, and DIN_INT[7:0] is the same as the received DIN[7:0] value, which means that the received activation data will be loaded into the row register 2802. As a result of this operation, if the row is a good row, the activation data will be stored, and if the row is a bad row, all 0s will be stored.

[0171] Address comparator 3111 and switches 3112 and 3113 are used to program redundant row register 2812. Address comparator 3111 compares the received row address XA[k:0] with the known bad address XA'[k:0] stored in table 2607. If there is a match, switch 3113 closes and switch 3112 opens, and DIN_INT[7:0] will have the same value as the received DIN[7:0] value, meaning that the received activation data will be loaded into redundant row register 2812. If there is a mismatch, switch 3113 opens and switch 3112 closes, which causes DIN_INT[7:0] to be grounded (DIN_INT[7:0] = "0"). This causes all bits loaded into the corresponding redundant row register 2812 to be "0." As a result of this operation, if the redundant row is to be used, the activation data will be stored, and if the redundant row is not to be used, all 0s will be stored.

[0172] Figure 32 Depicts a row register load operation 3200 for loading data for row group i into a previously referenced Figure 28 、 Figure 30 and Figure 31 The row register 2802 and redundant row register 2812 are described.

[0173] In operation 3201, input block 2800 receives the row group address of row group i (the row group address includes the first group of bits contained in address XA[k:0] to indicate the specific row group), the row addresses of the rows within row group i (these row addresses include the second group of bits contained in address XA[k:0] to identify the specific rows within the row group), and data DIN[127:0] to be loaded into the row registers corresponding to those row addresses within row group i.

[0174] In operation 3202, the system determines whether the row group address matches any stored row group address containing bad rows as indicated in table 2607. If not, then row group i and its rows do not contain any bad rows, and the load operation proceeds to operation 3204. If yes, then row group i does contain at least one bad row, and the load operation proceeds to operation 3203.

[0175] In operation 3203, the system identifies the redundant row registers associated with the row addresses of the bad rows in row group i and loads the bits in DIN[127:0] corresponding to the associated bad row addresses. For example, if table 2607 indicates that row address X1 in row group i is a bad row, table 2607 will further identify a redundant row to use instead of row X1. Thereafter, the data in DIN[127:0] for bad row X1 is loaded into the associated redundant row registers.

[0176] In operation 3204, the system loads DIN[127:0] into the row registers in row group i. This includes loading data into bad row X1. The data in bad row X1 will not actually be used in subsequent read or neural read operations because the row's associated row tag bits will indicate that the row is bad. Alternatively, the system may instead load no data or a known pattern of data (such as all "0s") into any bad row (such as row X1).

[0177] Figure 33 Depicted is a row tag register load operation 3300 for loading data into a previously referenced Figure 28 、 Figure 36 B and the row tag register 2803 and redundant row tag register 2813 described in Figure 37A.

[0178] In operation 3301, the system receives the row group address of row group i (the row group address includes the first set of bits contained in address XA[k:0] to indicate the specific row group), the row addresses of the rows within row group i (these row addresses include the second set of bits contained in address XA[k:0] to identify the specific rows within the row group), and the data DIN[127:0] to be loaded into the row tag registers corresponding to those row addresses within row group i.

[0179] In operation 3302, the system determines whether the row group address matches any stored row group address containing bad rows as indicated in table 2607. If not, row group 1 does not contain any bad rows, and the load operation proceeds to operation 3303. If yes, row group 1 does contain at least one bad row, and the load operation proceeds to operation 3304.

[0180] In operation 3303, the system loads DIN[127:0] into the row tag register in row group i.

[0181] In operation 3304, the system identifies those redundant row tag registers associated with the bad rows in row group i by consulting table 2607 and loads the bits in DIN[127:0] (which may all be "1") into the redundant row tag register corresponding to the associated row address. For example, if table 2607 indicates that row address X1 in group i is a bad row, table 2607 will further identify a redundant row to be used in place of row X1. The row tag data associated with bad row X1 in the row tag data register will then be loaded with a "0" to indicate that the row is a bad row. The redundant row tag data in the associated redundant row tag data register will be loaded with a "1" to indicate that the redundant row will be used. The row tag data associated with row address X1 in DIN[127:0] will be stored in the redundant row tag register associated with redundant row address R1.

[0182] In operation 3305, the system loads DIN[127:0] into the row tag register for rows in row group i that are not bad rows and are associated with redundant rows, and loads "0" into the row tag register for bad rows associated with redundant rows.

[0183] In this way, the row tag register is loaded with bits to indicate which rows are good rows and which rows are bad rows, and the redundant row tag register is loaded with bits to indicate which redundant rows will be used during a read or neural read operation and which redundant rows will not be used during a read or neural read operation.

[0184] Figure 34 Depicted is a neural reading method 3400. The neural reading method 3400 includes operations 3401, 3402, and 3403.

[0185] Operation 3401 includes converting data stored in a row register into a first set of analog voltages based on a value stored in the row tag register, and applying the first set of analog voltages to a corresponding row of non-volatile memory cells in an array of non-volatile memory cells. In one option, converting the data stored in the row register includes receiving digital data from the row tag register by a digital-to-analog converter and generating the first set of analog voltages. In another option, converting the data stored in the row register includes sampling and holding the first set of analog voltages by a sample and hold buffer in response to the digital data from the row tag register.

[0186] Operation 3402 includes converting data stored in the redundant row register into a second set of analog voltages based on a value stored in the redundant row tag register, and applying the second set of analog voltages to corresponding rows of non-volatile memory cells in a redundant array of non-volatile memory cells. In one option, converting the data stored in the redundant row register includes receiving digital data from the redundant row tag register by a redundant digital-to-analog converter and generating the second set of analog signals. In another option, converting the data stored in the redundant row register includes sampling and holding the second set of analog voltages by a sample and hold buffer in response to the digital data from the redundant row tag register.

[0187] Operation 3403 includes receiving current from an array of nonvolatile memory cells and a redundant array of nonvolatile memory cells.

[0188] The array in method 3400 may include an array of nonvolatile memory cells. The nonvolatile memory cells may include stacked gate flash memory cells such as Figure 5 ) or a split-gate flash memory cell (such as a Figures 2 to 4 2 and 4).

[0189] Redundancy can also be implemented on a column basis rather than a row basis. Figure 35 Describes the use Figure 27The redundant array 2719B in the VMM array 2701 implements the output block 3500 of the column redundancy of the VMM array 2701. Each column in the VMM array 2701 is associated with a corresponding column multiplexer 3501, a corresponding analog-to-digital converter 3502, a corresponding address comparator 3504, and a switch, as shown. Prior to a neural read operation, a set of column addresses known to be bad columns are identified (these bad columns can be determined by comparing with the addresses in table 3513), and the tag bits in the column tag register 3503 are set to identify those bad columns. For example, a tag bit "0" can indicate a bad column, and a tag bit "1" can indicate a good column. Thereafter, during a neural read operation, columns whose tag bits indicate bad columns are not coupled to the output through the switch. For those columns, instead, the corresponding redundant columns in the redundant array 2719B are read using the redundant column multiplexer 3511 and redundant analog-to-digital converter 3512 and associated switches as shown. Thus, data from good columns in the VMM array 2701 will be output instead of bad columns, and redundant data associated with bad columns in the redundant array 2719 will be output. The tag bits in the column tag register 3503 are used to indicate good columns to be used and bad columns to be unused during neural read operations. One or more analog-to-digital converters 3502 convert the analog signal from the column multiplexer 3501 into one or more bits, and one or more redundant analog-to-digital converters 3512 convert the analog signal from the redundant column multiplexer 3511 into one or more bits.

[0190] Figure 36 A neural reading method 3600 is depicted that utilizes the output block 3400. The method 3600 includes operations 3601, 3602, and 3603. Operation 3601 includes setting a column tag bit associated with a column in an array in a column tag bit register to a first value or a second value based on data in a table. Operation 3602 includes: receiving a current from a column in the array associated with a column tag bit of a first value; and converting, by one or more analog-to-digital converters, the current received from the column in the array into digital data. Operation 3603 includes: receiving a current from a redundant column in a redundant array when the redundant column is associated with a column in the array associated with a column tag bit of a second value; and converting, by one or more redundant analog-to-digital converters, the current received from the redundant column in the redundant array into digital data.

[0191] The array in method 3600 may include an array of nonvolatile memory cells. The nonvolatile memory cells may include stacked gate flash memory cells such as Figure 5 ) or a split-gate flash memory cell (such as a Figures 2 to 4 2 and 4).

[0192] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly on" (intervening materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (intervening materials, elements, or spaces disposed therebetween), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly mounted to" (intervening materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include forming the element directly on the substrate without intervening materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; a redundant array of nonvolatile memory cells arranged in rows and columns; and an input block coupled to a corresponding row in the array and a corresponding row in the redundant array and comprising a row tag register and a redundant row tag register; wherein the row tag registers respectively store one of a first value indicating that the corresponding row of the array of the non-volatile memory cells is to be used and a second value indicating that the corresponding row of the array of the non-volatile memory cells is not to be used, and the redundant row tag registers respectively store one of a third value indicating that the corresponding row of the redundant array of the non-volatile memory cells is to be used and a fourth value indicating that the corresponding row of the redundant array of the non-volatile memory cells is not to be used, and wherein the row tag register and the redundant row tag register identify a row to be read and a redundant row during a neural read operation. 2 . The system of claim 1 , wherein the input block comprises row registers respectively coupled to the row tag registers.

3. The system of claim 2, wherein the input block comprises address decoders respectively coupled to the row registers. 4 . The system of claim 3 , wherein the input block comprises one or more digital-to-analog converters coupled to the row tag register.

5. The system of claim 3, wherein the input block comprises sample and hold buffers respectively coupled to the row tag registers.

6. The system of claim 1, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are split gate flash memory cells.

7. The system of claim 1, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are stacked gate flash memory cells.

8. A method comprising: converting data stored in a row register into a first set of analog voltages based on a value stored in a row tag register, and applying the first set of analog voltages to a corresponding row of nonvolatile memory cells in an array of nonvolatile memory cells; converting data stored in a redundant row register into a second set of analog voltages based on a value stored in the redundant row tag register, and applying the second set of analog voltages to a corresponding row of nonvolatile memory cells in a redundant array of nonvolatile memory cells; as well as Current is received from the array of nonvolatile memory cells and the redundant array of nonvolatile memory cells.

9. The method according to claim 8, wherein: Converting data stored in the row register includes receiving digital data from the row tag register by a digital-to-analog converter and generating the first set of analog voltages; and Converting the data stored in the redundant row register includes receiving the digital data from the redundant row tag register by a redundant digital-to-analog converter and generating the second set of analog voltages.

10. The method according to claim 8, wherein: Converting the data stored in the row register includes sampling and holding the first set of analog voltages by a sample and hold buffer in response to the digital data from the row tag register; and Converting the data stored in the redundant row register includes sampling and holding, by a sample and hold buffer, the second set of analog voltages in response to the digital data from the redundant row tag register.

11. A system, comprising: an array of non-volatile memory cells arranged in rows and columns; a redundant array of nonvolatile memory cells arranged in rows and columns; and an output block coupled to a corresponding column in the array and a corresponding column in the redundant array and comprising a column multiplexer, a column tag register, and a redundant column multiplexer; wherein the column tag registers respectively store one of a first value indicating that a corresponding column of the array of the non-volatile memory cells is to be used and a second value indicating that the corresponding column of the array of the non-volatile memory cells is not to be used and an associated redundant column of the redundant array of the non-volatile memory cells is to be used, and wherein the column tag registers identify a column to be used during a neural read operation.

12. The system of claim 11 , wherein the output block comprises one or more analog-to-digital converters to convert the analog signal from the column multiplexer into one or more bits, and one or more redundant analog-to-digital converters to convert the analog signal from the redundant column multiplexer into one or more bits.

13. The system of claim 11, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are split gate flash memory cells.

14. The system of claim 11, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are stacked gate flash memory cells.

15. A method comprising: receiving a current from a column in the array associated with a column tag bit of a first value; as well as Current is received from a redundant column in a redundant array when the redundant column is associated with a column in the array associated with a column tag bit of a second value.

16. The method according to claim 15, comprising: converting the current received from the columns in the array into digital data by one or more analog-to-digital converters; as well as The current received from the redundant columns in the redundant array is converted into digital data by one or more redundant analog-to-digital converters.

17. The method according to claim 15, comprising: A column tag bit in a column tag bit register associated with a column in the array is set to a first value or a second value based on data in a table.

18. The method of claim 15, wherein the array comprises an array of non-volatile memory cells and the redundant array comprises an array of non-volatile memory cells.

19. The method of claim 18, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are split gate flash memory cells.

20. The method of claim 18, wherein the nonvolatile memory cells in the array of nonvolatile memory cells and the nonvolatile memory cells in the redundant array of nonvolatile memory cells are stacked gate flash memory cells.

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