Method of manufacturing semiconductor device having backside power delivery network using laser lift-off layer

Abstract

A method for manufacturing a semiconductor device is disclosed. The method includes forming a stack on a first substrate. A laser lift-off layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures on a first side of the stack. The method includes attaching a second substrate on the first side to the stack, wherein the plurality of first interconnect structures is between the stack and the second substrate; the first substrate is removed by applying radiation on the laser lift-off layer. The method includes forming a plurality of second interconnect structures on a second side of the stack opposite the first side.

Description

[0001] Cross-references to related patents and applications

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 18 / 104,272, filed January 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a method for fabricating a semiconductor device having a backside power delivery network, and in particular to a method for such a device using a laser lift-off layer. Background Art

[0004] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0005] At least one aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method may include forming a stack on a first substrate, wherein a laser lift-off layer is interposed between the stack and the first substrate; forming a plurality of first interconnect structures on a first side of the stack; attaching a second substrate to the stack on the first side, wherein the plurality of first interconnect structures are interposed between the stack and the second substrate; removing the first substrate by applying radiation to the laser lift-off layer; and forming a plurality of second interconnect structures on a second side of the stack opposite the first side.

[0006] In some embodiments, at least some of the plurality of second interconnect structures are operable to function as a power delivery network.

[0007] In some embodiments, the method may further include growing a first semiconductor layer on a third substrate and then growing the stack on the first semiconductor layer; and attaching the first substrate to the stack, wherein the laser lift-off layer and the dielectric layer are between the first substrate and the first semiconductor layer in the second semiconductor layer.

[0008] In some embodiments, the method may further include removing the third substrate to expose the first semiconductor layer; removing the first semiconductor layer to expose a second semiconductor layer of the second semiconductor layers; and patterning the stack, followed by a step of forming a plurality of first interconnect structures. The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other. The first semiconductor layer includes a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon. The second concentration is significantly lower than the first concentration. The first semiconductor layer serves as an etch stop layer for the step of removing the third substrate, which step includes at least a wet etching process.

[0009] In some embodiments, the laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

[0010] At least another aspect of the present disclosure relates to a method for fabricating a semiconductor device. The method may include forming a stack on a first substrate; forming a laser lift-off layer and a dielectric layer on a second substrate; flipping the second substrate and attaching the dielectric layer to a first side of the stack; removing the first substrate from a second side of the stack, the second side being opposite the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures on the second side; removing the second substrate through the laser lift-off layer to expose the first side of the stack; and forming a plurality of second interconnect structures on the first side.

[0011] In some embodiments, at least some of the plurality of second interconnect structures are operable to function as a power delivery network.

[0012] In some embodiments, the method may further include attaching a third substrate to the second side of the stack; and flipping the stack over, followed by the steps of removing the second substrate.

[0013] In some embodiments, the method may further include growing a first semiconductor layer between the second side of the stack and the first substrate. The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other. The first semiconductor layer includes a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon. The second concentration is significantly lower than the first concentration. The first semiconductor layer serves as an etch stop layer for a step of removing the first substrate, the step including at least a wet etching process.

[0014] In some embodiments, the laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

[0015] Yet another aspect of the present disclosure may be directed to a method for fabricating a semiconductor device. The method may include forming a stack on a first substrate, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of each other; sequentially forming a laser lift-off layer and a dielectric layer on a second substrate; flipping the second substrate and attaching the dielectric layer to a first side of the stack; removing the first substrate from a second side of the stack, the second side being opposite to the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures above the plurality of device features; attaching a third substrate to the second side of the stack; flipping the third substrate together with the second substrate; removing the second substrate by applying radiation to the laser lift-off layer; and forming a plurality of second interconnect structures on opposite sides of the device features relative to the plurality of first interconnect structures.

[0016] In some embodiments, the laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

[0017] These and other aspects and embodiments are discussed in detail below. The above information and the following detailed description include illustrative examples of various aspects and embodiments, and provide an overview or framework for understanding the nature and characteristics of the claimed aspects and embodiments. The accompanying drawings provide an illustration and further understanding of the various aspects and embodiments, and are incorporated into and constitute a part of this specification. Various aspects can be combined, and it will be readily understood that the features described in the context of one aspect of the invention can be combined with other aspects. Various aspects can be implemented in any convenient form. As used in the specification and claims, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" include plural references. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and not intended to be drawn to scale. Unless indicated as representing prior art, the drawings represent aspects of the present disclosure. For clarity, not every component may be labeled in every drawing. In the drawings:

[0019] Figure 1 A flow chart illustrating a method for forming an isolation structure of a transistor structure according to an embodiment; and

[0020] Figures 2A to 2L According to the embodiment, Figure 1 Cross-sectional views of a device during various fabrication stages of a method. DETAILED DESCRIPTION

[0021] Reference will now be made to the illustrative embodiments depicted in the accompanying drawings, and specific language will be used herein to describe these embodiments. However, it will be understood that this is not intended to limit the scope of the claims or this disclosure. Changes and further modifications to the inventive features shown herein that would occur to those skilled in the relevant art and to those skilled in the art who have access to this disclosure, as well as additional applications of the principles of the subject matter shown herein, are to be considered within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of this disclosure. The illustrative embodiments described in the detailed description are not meant to limit the subject matter presented.

[0022] The present disclosure provides various embodiments of a method for forming a semiconductor device having at least one power rail formed on the backside of a plurality of transistors. In various embodiments, each of the transistors can be configured as any of a variety of transistor structures (e.g., a gate-all-around (GAA) transistor structure, a FinFET structure, a channel-all-around (CAA) transistor structure, etc.). As disclosed herein, the method can include forming a laser lift-off layer disposed between the backside of a stack of multiple semiconductor layers (some of which may later be formed into respective conductive channels of the transistors) and a carrier substrate. The carrier substrate is typically formed as a sacrificial substrate to provide mechanical support for the stack during the formation of the transistors and a plurality of front-side interconnect structures above the transistors (commonly referred to as front-end-of-line (FEOL) and back-end-of-line (BEOL) processes, respectively). In the prior art, such carrier substrates are removed by a polishing process (e.g., a chemical mechanical polishing (CMP) process), which can sometimes damage the already formed transistors and front-side interconnect structures. By using a laser lift-off layer to remove the carrier substrate, the disclosed method can advantageously avoid these problems. For example, the carrier substrate can be easily removed by applying radiation (e.g., laser) to the laser lift-off layer without applying any mechanical force to the transistor or the front-side interconnect structure. Furthermore, after removing the carrier substrate, the back side of the transistor can be used, thereby allowing multiple power rails to be formed on the back side of the transistor.

[0023] Figure 1A flow chart of a method 100 for forming a backside interconnect structure of a transistor structure according to one or more embodiments of the present disclosure is shown. For example, at least some of the operations (or steps) of method 100 can be used to form a plurality of interconnect structures on the back side of a FinFET structure, a GAA transistor structure, a CAA transistor structure, a vertical transistor structure, etc. At least some of such backside interconnect structures can form a power delivery network for the transistor structure, that is, deliver power to the transistor structure. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be understood that the backside interconnect structures can be formed in the embodiment of the present disclosure. Figure 1 Additional operations are provided before, during, and after method 100, and some other operations may be only briefly described herein.

[0024] In some embodiments, the operations of method 100 may be respectively as follows: Figures 2A to 2L 1 and 2. The cross-sectional views of an example semiconductor device 200 (eg, including a GAA transistor structure) at various stages of fabrication are shown, which will be discussed in further detail below. It should be understood that for the sake of brevity, Figures 2A to 2L The semiconductor device 200 shown may not include a complete GAA transistor structure. For example, the following figures of the semiconductor device 200 may not show or include source / drain structures coupled to opposite sides of each channel or a gate electrode wrapped around each channel.

[0025] Corresponding to Figure 1 Operation 102, Figure 2A is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages, wherein a stack 210 is formed on a first substrate 202 , according to various embodiments of the present disclosure. Figure 2A The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0026] The first substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the first substrate 202 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. For example, the semiconductor material of the first substrate 202 may include silicon; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0027] In various embodiments, a first substrate 202 may be provided to epitaxially grow a stack 210 on itself. The stack 210 includes a plurality of first semiconductor layers 214 and a plurality of second semiconductor layers 216 alternately disposed on top of each other along a vertical direction. As will be discussed below, the first semiconductor layers 214 may be later removed or replaced with a wrapped gate structure of a GAA transistor, and the second semiconductor layers 216 may collectively serve as a channel of the GAA transistor. Therefore, the first semiconductor layers 214 and the second semiconductor layers 216 are sometimes referred to as "sacrificial layers 214" and "channel layers 216," respectively. For example, in Figure 2A In the embodiment, one of the second semiconductor layers 216 is disposed over one of the first semiconductor layers 214 , and then another of the first semiconductor layers 214 is disposed over the second semiconductor layer 216 , and so on.

[0028] The semiconductor layers 214 and 216 may have respective different thicknesses. Further, the first semiconductor layer 214 may have different thicknesses from one layer to another. The second semiconductor layer 216 may have different thicknesses from one layer to another. The thickness of each of the semiconductor layers 214 and 216 may be in the range of from a few nanometers to tens of nanometers. In some embodiments, one of the layers of the stack 210 closest to the first substrate 202 may be thicker than the other semiconductor layers 214 and 216. In an embodiment, each of the first semiconductor layers 214 has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each of the second semiconductor layers 216 has a thickness ranging from about 5 nm to about 20 nm.

[0029] In various embodiments, the first semiconductor layer 214 and the second semiconductor layer 216 have different compositions. For example, the first semiconductor layer 214 and the second semiconductor layer 216 have compositions that provide different oxidation rates and / or different etching selectivities between the layers. In an embodiment, the first semiconductor layer 214 each includes silicon germanium (Si 1-x Ge x ), and each of the second semiconductor layers 216 includes silicon (Si). In an embodiment, each of the second semiconductor layers 216 may be undoped or substantially free of dopants (eg, having a thickness from about 0 cm -3 to about 1×10 17 cm -3 Each of the first semiconductor layers 214 is Si 1-x Ge x , including Ge in a molar ratio less than 50% (x<0.5). For example, in a 1-x Ge x The molar ratio of Ge in the first semiconductor layer 214 may be approximately 15% to 35%. In addition, the first semiconductor layers 214 may include different compositions therebetween, and the second semiconductor layers 216 may include different compositions therebetween.

[0030] Alternatively or additionally, any of the semiconductor layers 214 and 216 may include other materials, such as compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. The materials of the semiconductor layers 214 and 216 may be selected based on providing different oxidation rates and / or etching selectivities.

[0031] In some embodiments, the stack 210 further includes an optional semiconductor layer 212 between the first semiconductor layer 214 closest to the first substrate 202 and the first substrate 202 (when the first substrate 202 is disposed relatively below the stack 210). The semiconductor layer 212 can be similar to the first semiconductor layer 210, but have a different molar ratio of germanium (e.g., a molar ratio of germanium that is significantly higher than that of the first semiconductor layer 214). Such a semiconductor layer 212 can serve as an etch stop layer when removing the first substrate 202, as will be discussed later.

[0032] The semiconductor layers 214 and 216 can be epitaxially grown from the first substrate 202 or the semiconductor layer 212 (if formed). For example, each of the semiconductor layers 214 and 216 can be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process (such as a metal organic CVD (MOCVD) process), and / or other suitable epitaxial growth process. During the epitaxial growth, the crystal structure of the first substrate 202 or the semiconductor layer 212 can be extended upward, resulting in the semiconductor layers 214 and 216 having the same or similar crystal orientation as the first substrate 202 or the semiconductor layer 212.

[0033] Corresponding to Figure 1 Operation 104, Figure 2B is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages according to various embodiments of the present disclosure, wherein a second substrate 220 covered by a laser lift-off (LLO) layer 222 and a dielectric layer 224 is provided. Figure 2B The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0034] In various embodiments, an LLO layer 222 and a dielectric layer 224 are sequentially formed on the second substrate 220. The dielectric layer 224 may be used to bond the second substrate 220 to the stack 210 (as shown below). Figure 2C ), wherein the LLO layer 222 is interposed between the second substrate 220 and the dielectric layer 224. The second substrate 220 can be configured to provide mechanical support for a workpiece (e.g., including a plurality of device features and front-side interconnect structures, as will be described below). Further, in some embodiments, the second substrate 220 can be easily removed (e.g., without using any polishing process) by using the LLO layer 222.

[0035] The second substrate 220 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (for example, with p-type or n-type dopants) or undoped; or a dielectric, such as silica glass. In some embodiments, the second substrate 220 can be a wafer (such as a silicon wafer) or a glass panel. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. For example, the semiconductor material of the second substrate 220 can include silicon; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof.

[0036] The LLO layer 222 can be induced to undergo thermochemical dissociation when a laser is applied, thereby allowing the second substrate 220 to be later removed from the workpiece. In some embodiments, the LLO layer 222 may include a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, titanium nitride, a metal, and a metal oxide. The LLO layer 222 may be deposited or thermally grown on the second substrate 220. The dielectric layer 224 may be configured as an interlayer dielectric (ILD) or an intermetallic dielectric (IMD) material. The dielectric layer 224 may include one or more low-k dielectric materials, such as silicon oxide (SiO2).

[0037] Corresponding to Figure 1 Operation 106, Figure 2C is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages, wherein a second substrate 220 is attached to the first substrate 202 , according to various embodiments of the present disclosure. Figure 2C The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0038] As shown, the second substrate 220 is attached (eg, directly bonded) to the first substrate 202 with the LLO layer 222, the dielectric layer 224, and the stack 210 interposed between the two substrates. Figure 2CIn the example shown in FIG. 2 , one of the second semiconductor layers 214 (of the stack 210) that is furthest from the first substrate 202 contacts the dielectric layer 224. In various embodiments, the stack 210 has a first side 210A and a second side 210B. A plurality of front-side interconnect structures are configured to be formed on the first side 210A; and a plurality of back-side interconnect structures are configured to be formed on the second side 210B. Therefore, the first side 210A and the second side 210B are sometimes referred to as the "front side 210A" and the "back side 210B," respectively.

[0039] Corresponding to Figure 1 Operation 108, Figure 2D is a cross-sectional view of a semiconductor device 200 during one of various fabrication stages, wherein the workpiece (ie, the partially formed semiconductor device 200 ) is flipped over, according to various embodiments of the present disclosure. Figure 2D The cross-sectional view may be cut along a direction perpendicular to the longitudinal direction of one or more channels of the semiconductor device 200 (eg, the longitudinal direction of the active / dummy gate structures of the semiconductor device 200). After flipping, the front side 210A is located above the back side 210B, as shown in FIG. Figure 2D shown.

[0040] Corresponding to Figure 1 Operation 110, Figure 2E is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages, with the first substrate 202 removed, according to various embodiments of the present disclosure. Figure 2E The cross-sectional view may be cut along a direction perpendicular to the longitudinal direction of one or more channels of the semiconductor device 200 (e.g., the longitudinal direction of the active / dummy gate structures of the semiconductor device 200). In some embodiments, the first substrate 202 is removed by at least one of a polishing process or a wet etching process. Given a high percentage of germanium molar ratio, the semiconductor layer 212 can serve as an etch stop layer during the removal of the first substrate 202.

[0041] Corresponding to Figure 1 Operation 112, Figure 2F is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages, with semiconductor layer 212 removed, according to various embodiments of the present disclosure. Figure 2F The cross-sectional view may be cut along a direction perpendicular to the longitudinal direction of one or more channels of the semiconductor device 200 (e.g., the longitudinal direction of the active / dummy gate structures of the semiconductor device 200). In some embodiments, when the molar ratio of germanium between the semiconductor layer 212 and the semiconductor layer 214 is different, the semiconductor layer 212 may be selectively removed by a suitable etchant.

[0042] Corresponding to Figure 1Operation 114, Figure 2G is a cross-sectional view of a semiconductor device 200 at one of various manufacturing stages, wherein a plurality of active regions (eg, 210A, 210B, and 210C) are defined in a stack 210. In some embodiments, Figure 2G The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0043] After removing the semiconductor layer 212, exposing the (topmost) layer of the first semiconductor layer 214 on the front side of the stack 210A, the stack 210 may then be patterned to form active regions, such as 210A to 210C. Figure 2G A mask layer 225 (which may include multiple layers, such as a pad oxide layer and an overlying pad nitride layer) is formed on the top semiconductor layer 214 (of the embodiment of the present invention). The pad oxide layer can be a thin film containing silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer can serve as an adhesion layer between the topmost semiconductor layer 214 and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbide nitride, etc. or a combination thereof. For example, the pad nitride layer can be formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0044] Next, the mask layer 225 can be patterned using photolithography techniques. Typically, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, the photoresist material is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask.

[0045] Subsequently, a patterned mask can be used to pattern the exposed portions of semiconductor layers 214 and 216 to form a plurality of grooves (or openings), thereby defining device regions 211A to 211C, each of which is disposed between adjacent grooves. When multiple active areas are formed, such grooves can be disposed between any adjacent active areas in the active areas. In some embodiments, device regions 211A to 211C are formed by etching grooves in semiconductor layers 214 and 216 (if formed) using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. In some embodiments, the plurality of grooves can be parallel to each other and closely spaced strips relative to each other (when viewed from the top). In some embodiments, the grooves can each be continuous and surround a corresponding one of the device regions 211A-C.

[0046] Corresponding to Figure 1 Operation 116, Figure 2H is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages, the semiconductor device including a plurality of device features 230 and a plurality of front-side interconnect structures 234. In some embodiments, Figure 2H The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0047] In various embodiments, after defining the device regions 211A to 211C, multiple processes may be performed to form multiple device features (e.g., including device feature 230), thereby forming multiple (e.g., GAA) transistors. For example, after defining the device regions 211A to 211C, at least one dummy gate structure may be formed to cover (e.g., span) the device regions 211A to 211C. Next, the corresponding portion of each of the device regions 211A to 211C not covered by the dummy gate structure is replaced with an epitaxial structure, which may serve as the source / drain region of the GAA transistor. Next, the semiconductor (sacrificial) layer 214 and the dummy gate structure of the device regions 211A to 211C are replaced with device features 230, which are gate structures (hereinafter referred to as "gate structures 230"). Each of these gate structures 230 may include a gate metal with a gate dielectric between the gate metal and the semiconductor (channel) layer 216, such that the gate structure surrounds (wraps around) a corresponding number of the semiconductor (channel) layers 216. In some embodiments, after the gate structures 230 are formed, a plurality of GAA transistors are completed. For example, each of the gate structures 230 together with the semiconductor layer 216 and the corresponding source / drain regions surrounding it can form a GAA transistor. Next, on the front side 210A, a front side interconnect structure 234 can be formed above the GAA transistor. These front side interconnect structures 234 formed of a metal material (e.g., copper) are typically embedded in a dielectric layer 236 having an IMD material (e.g., silicon oxide). Such a layer formed of a dielectric layer 236 including one or more front side interconnect structures 234 is typically referred to as a metallization layer. Although in Figure 2I Only one such metallization layer is shown in FIG, but it should be understood that multiple metallization layers may be formed over the GAA transistor.

[0048] Corresponding to Figure 1 Operation 118, Figure 2I is a cross-sectional view of semiconductor device 200 at one of various manufacturing stages, wherein third substrate 240 is attached (eg, bonded) to a workpiece. In some embodiments, Figure 2IThe cross-sectional view of FIG200 may be cut along a direction perpendicular to the longitudinal direction of one or more channels of the semiconductor device 200 (e.g., the longitudinal direction of the active / dummy gate structures of the semiconductor device 200). As shown, the third substrate 240 is in contact with the dielectric layer 236. In some embodiments, the third substrate 240 may be configured to provide mechanical support for the workpiece while forming a plurality of interconnect structures on the back side of the transistor, as will be discussed below.

[0049] The third substrate 240 (such as the substrate 220) can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, an insulator, etc. In some embodiments, the third substrate 240 can be a wafer, such as a silicon wafer, which can be a blank wafer or can have active devices formed therein. Although not shown, the substrate 240 can have a contact structure that is directly or indirectly electrically connected to the interconnect structure 234 through a hybrid bonding process.

[0050] Corresponding to Figure 1 Operation 120, Figure 2J is a cross-sectional view of a semiconductor device 200 during one of various fabrication stages, wherein the workpiece (ie, the partially formed semiconductor device 200 ) is flipped over, according to various embodiments of the present disclosure. Figure 2J The cross-sectional view may be cut along a direction perpendicular to the longitudinal direction of one or more channels of the semiconductor device 200 (eg, the longitudinal direction of the active / dummy gate structures of the semiconductor device 200). After flipping, the back side 210B is located above the front side 210A, as shown in FIG. Figure 2J shown.

[0051] Corresponding to Figure 1 Operation 122, Figure 2K is a cross-sectional view of the semiconductor device 200 at one of various fabrication stages, with the second substrate 220 removed, according to various embodiments of the present disclosure. Figure 2K The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0052] In various embodiments, the second substrate 220 may be removed by a laser lift-off (LLO) process. In such an LLO process, radiation or other optical energy (e.g., a laser beam) irradiates the workpiece through the exposed surface of the second substrate 220, wherein the radiation passes through the second substrate 220 and reaches the LLO layer 222 ( Figure 2J). In various embodiments, the second substrate 220 can be optically transparent to the wavelength of light energy. As a non-limiting example, the laser radiation incident on the second substrate 220 can be 248nm radiation from a KrF pulsed excimer laser with a pulse width of 38ns. The energy that passes through the second substrate 220 is then absorbed by the LLO layer 222, which causes thermochemical dissociation in the LLO layer 222. The workpiece (although including the GAA transistor and the front-side interconnect structure bonded to the third substrate 240) can be released, disconnected, or otherwise decoupled from the second substrate 220. Accordingly, the LLO layer 222 can sometimes be referred to as a release layer. The LLO process can be performed in a vacuum, air, or other ambient environment, and is typically performed at an elevated temperature (e.g., above 250°C).

[0053] Corresponding to Figure 1 Operation 124, Figure 2L is a cross-sectional view of a semiconductor device 200 at one of various fabrication stages according to various embodiments of the present disclosure, wherein a plurality of backside interconnect structures 254 are formed. Figure 2L The cross-sectional view may be cut along a direction perpendicular to a longitudinal direction of one or more channels of the semiconductor device 200 (eg, a longitudinal direction of an active / dummy gate structure of the semiconductor device 200 ).

[0054] As shown, relative to the front side interconnect structure 234 formed on the front side 210A of the GAA transistor, the back side interconnect structure 254 is formed on the back side 210B of the GAA transistor. These back side interconnect structures 254 are typically formed of a metal material (e.g., copper). In some embodiments, at least some of the back side interconnect structures 254 can be operatively used as a power delivery network for the GAA transistor, i.e., delivering or otherwise carrying power to the GAA transistor. The front side structure 234 can be formed as a hybrid bonded interconnect, or can be indirectly connected to an interconnect that can be further connected by a hybrid bonding process. Thus, the front side can allow a connection between two devices that are directly bonded to each other, while the back side interconnect allows shared connections such as power and / or grounding to be provided from outside the bonded device / substrate.

[0055] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. However, the embodiments can be practiced without such specific details. Components having substantially the same functional configuration are denoted by similar reference characters, and therefore any redundant descriptions may be omitted.

[0056] The various techniques have been described as a plurality of discrete operations to aid understanding of the various embodiments. The order of description should not be interpreted as implying that these operations are necessarily order-dependent. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0057] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer on a base substrate structure or a layer (such as a thin film) overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0058] Those skilled in the art will also appreciate that many variations can be made to the operation of the technology explained above while still achieving the same goals of the present invention. The scope of this disclosure is intended to encompass such variations. Thus, the above description of the embodiments of the present invention is not intended to be restrictive. On the contrary, any limitation to the embodiments of the present invention is presented in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stack on a first substrate, wherein a laser lift-off layer is interposed between the stack and the first substrate; forming a plurality of first interconnect structures on a first side of the stack; attaching a second substrate to the stack on the first side, wherein the plurality of first interconnect structures are interposed between the stack and the second substrate; removing the first substrate by applying radiation to the laser lift-off layer; as well as A plurality of second interconnect structures are formed on a second side of the stack opposite the first side.

2. The method according to claim 1, wherein At least some of the plurality of second interconnect structures are operable to function as a power delivery network.

3. The method of claim 1, further comprising: growing a first semiconductor layer on a third substrate and then growing the stack on the first semiconductor layer; as well as The first substrate is attached to the stack, wherein the laser lift-off layer and the dielectric layer are interposed between the first substrate and a first semiconductor layer of the second semiconductor layer.

4. The method of claim 3, further comprising: removing the third substrate to expose the first semiconductor layer; removing the first semiconductor layer to expose a second semiconductor layer among the second semiconductor layers; as well as The stack is patterned, followed by the step of forming a plurality of first interconnect structures.

5. The method according to claim 3, wherein: The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other.

6. The method according to claim 5, wherein: The first semiconductor layer includes a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon.

7. The method according to claim 6, wherein: The second concentration is significantly lower than the first concentration.

8. The method of claim 7, wherein: The first semiconductor layer serves as an etch stop layer for a step of removing the third substrate, which step includes at least a wet etching process.

9. The method of claim 1, wherein: The laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

10. A method for manufacturing a semiconductor device, the method comprising: forming a stack on a first substrate; forming a laser lift-off layer and a dielectric layer in sequence on a second substrate; flipping the second substrate and attaching the dielectric layer to the first side of the stack; removing the first substrate from a second side of the stack, the second side opposite the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures on the second side; removing the second substrate through the laser lift-off layer to expose the first side of the stack; as well as A plurality of second interconnect structures are formed on the first side.

11. The method according to claim 10, wherein: At least some of the plurality of second interconnect structures are operable to function as a power delivery network.

12. The method of claim 10, further comprising: attaching a third substrate to the second side of the stack; as well as The stack is flipped over, followed by a step of removing the second substrate.

13. The method of claim 10, further comprising growing a first semiconductor layer between the second side of the stack and the first substrate.

14. The method of claim 13, wherein: The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other.

15. The method of claim 14, wherein: The first semiconductor layer includes a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon.

16. The method of claim 15, wherein: The second concentration is significantly lower than the first concentration.

17. The method of claim 16, wherein: The first semiconductor layer serves as an etch stop layer for a step of removing the first substrate, which step includes at least a wet etching process.

18. The method of claim 10, wherein: The laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

19. A method for manufacturing a semiconductor device, the method comprising: forming a stack on a first substrate, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of each other; forming a laser lift-off layer and a dielectric layer in sequence on a second substrate; flipping the second substrate and attaching the dielectric layer to the first side of the stack; removing the first substrate from a second side of the stack, the second side opposite the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures over the plurality of device features; attaching a third substrate to the second side of the stack; turning over the third substrate together with the second substrate; removing the second substrate by applying radiation to the laser lift-off layer; as well as A plurality of second interconnect structures are formed on opposite sides of the device features relative to the plurality of first interconnect structures.

20. The method of claim 19, wherein: The laser lift-off layer includes a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, silicon carbide nitride, titanium nitride, a metal, and a metal oxide.

Images