Embedded cooling system for advanced device packaging

Abstract

In some embodiments, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be placed between the encapsulation cover and the second side of the cold plate, and one or more surfaces of the second side of the cold plate may be spaced apart from the encapsulation cover to define coolant channels therebetween. An adhesive layer may seal the encapsulation cover to the cold plate around a perimeter of the coolant channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 435,145, filed on December 23, 2022, the entire contents of which are incorporated herein. Technical Field

[0003] The present disclosure relates to advanced packaging of microelectronic devices, and more particularly to an embedded cooling system for device packaging and a method for manufacturing the same. Background Art

[0004] Energy consumption poses a significant challenge to the future of large-scale computing, as global computing energy demand grows at a rate that most consider unsustainable. Some models predict that by 2030, the information, communications, and technology (ICT) ecosystem could account for more than 20% of global electricity consumption, with direct electricity consumption in large computing centers accounting for more than one-third of this energy use. Cooling costs contribute significantly to the energy needs of computing centers, as even small increases in operating temperatures can negatively impact the performance of microprocessors, memory devices, and other electronic components.

[0005] Heat dissipation in high power density chips is also a key challenge because improvements in chip performance (e.g., through increased gate density and multi-core microprocessors) have led to increased power density, and a corresponding increase in heat flux, leading to increased chip temperatures. These increased temperatures are undesirable because they can degrade the operating performance, efficiency, and reliability of the chip. Cooling systems used to maintain the chip at a desired operating temperature typically use one or more heat dissipation devices (e.g., heat sinks, heat pipes, cold pipes, and radiators) to dissipate heat, which are thermally coupled to the chip using a flexible thermally conductive material (TIM) (e.g., thermal paste, thermally conductive adhesive, thermally conductive gap filler, etc.). The thermal interface material is in thermal contact with the surfaces of the chip and the heat dissipation device to promote heat transfer between them. Unfortunately, the combined thermal resistance of the thermal interface material and the thermal resistance at the interface boundary area inhibits heat transfer from the chip to the heat dissipation device, thereby undesirably reducing the cooling efficiency of the cooling system.

[0006] Therefore, there is a need in the art for improved economizer cooling systems and methods of making the same. Summary of the Invention

[0007] The embodiments herein provide an integrated cooling assembly embedded within a device package. The embedded cooling assembly shortens the thermal resistance path between the device and the heat sink and reduces thermal connectivity between devices placed in the same package.

[0008] In some embodiments, a device package may include a package substrate, a package lid positioned on the package substrate, and an integrated cooling assembly positioned between the package substrate and the package lid. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be positioned between the package lid and the second side of the cold plate, and one or more surfaces of the second side of the cold plate may be spaced apart from the package lid to define a coolant channel therebetween. The adhesive layer may seal the package lid to the cold plate around a perimeter of the coolant channel.

[0009] In some embodiments, a device package may include an integrated cooling assembly comprising: a cold frame, a first high-intensity device, and a second high-intensity device. The cold plate may include a plurality of sidewalls surrounding an opening positioned through the cold plate. The first high-intensity device and the second high-intensity device may each include a first die and one or more second dies directly bonded to the first die. The first die may be directly bonded to opposite sides of the cold frame, wherein the cold frame forms a perimeter of a coolant channel positioned between the first high-intensity device and the second high-intensity device. The backside surfaces of the second die may face each other within the coolant channel.

[0010] In some embodiments, a method of manufacturing a device package may include directly bonding a first substrate to a second substrate, singulating an integrated cooling assembly from the bonded substrates. The first substrate may include a semiconductor device, the second substrate may include a cold plate, and the integrated cooling assembly may include the cold plate bonded to the semiconductor device. The method may include attaching a package lid to the cold plate, and connecting the semiconductor device to the package substrate before or after attaching the package lid. The cold plate may include a first side directly bonded to the semiconductor device and a second side opposite the first side, the second side may include one or more surfaces spaced apart from the package lid to define a coolant channel therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing and other objects and advantages of the present disclosure will become apparent upon consideration of the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic plan view of an example of a system panel according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic partial side cross-sectional view of a device package mounted on a PCB according to an embodiment of the present disclosure;

[0014] Figure 3A yes Figure 2 Schematic exploded isometric view of the device package in;

[0015] Figure 3B yes Figure 3A A schematic cross-sectional view of the device package taken along line AA';

[0016] Figure 4A is a schematic isometric view of an integrated cooling assembly according to an embodiment of the present disclosure;

[0017] Figure 4B yes Figure 4A A schematic cross-sectional view of the integrated cooling assembly taken along line BB';

[0018] Figure 4C is a schematic side view of a thermoelectric cooling device according to an embodiment of the present disclosure;

[0019] Figure 5 is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0020] Figure 6 is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0021] Figure 7A is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0022] Figure 7B yes Figure 7A Schematic exploded isometric view of the integrated cooling assembly and bonding layer in the .

[0023] Figure 8A is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0024] Figure 8B yes Figure 8A Schematic exploded isometric view of the integrated cooling assembly and bonding layer in the .

[0025] Figure 9 is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0026] Figure 10A is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0027] Figure 10B yes Figure 10A A schematic cross-sectional view of the integrated cooling assembly taken along line CC';

[0028] Figure 10C is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure;

[0029] Figure 11 is a diagram illustrating a method for manufacturing a device package according to an embodiment of the present disclosure;

[0030] Figure 12 yes Figure 11 Example device packaging at different stages of the method.

[0031] The drawings herein are for illustration purposes only and depict various embodiments of the present invention. It should be understood that additional or alternative structures, components, systems and methods can be implemented within the principles set forth in this disclosure. DETAILED DESCRIPTION

[0032] The embodiments herein provide an integrated cooling assembly embedded in a device package. The embedded cooling assembly shortens the thermal resistance path between the device and the heat sink and reduces thermal communication between devices placed in the same package.

[0033] As used herein, the term "substrate" means and includes any workpiece, wafer, or article that provides a base material or support surface from which or on which components, elements, devices, assemblies, modules, systems, or features of the heat generating devices, packaged components, and cooling assembly components described herein may be formed. The term "substrate" also includes a "semiconductor substrate" that provides support material (on which components of a semiconductor device may be prepared or attached) and any material layers, features, and / or electronic devices formed thereon, in, or through it.

[0034] As described below, semiconductor substrates herein generally have a "device side" (e.g., a side on which semiconductor device elements (such as transistors, resistors, and capacitors) are fabricated) and a "back side" opposite the device side. The term "active side" should be understood to include the surface of the device side of the substrate, and may include the device side surface of the semiconductor substrate and / or the surface of any material layer, device element, or feature formed thereon or extending outwardly therefrom, and / or any opening formed therein. Thus, it should be understood that the material forming the active side may vary depending on the stage of device fabrication and assembly. Similarly, the term "non-active side" (opposite to the active side) includes the non-active side of the substrate at any stage of device fabrication, including the surface of any material layer, any feature formed thereon or extending outwardly therefrom, and / or any opening formed therein. Thus, the terms "active side" or "non-active side" may include the corresponding surface of the semiconductor substrate at the beginning of device fabrication as well as any surface formed during material removal (e.g., after a substrate thinning operation). Depending on the stage of device fabrication or assembly, the terms "active side" and "inactive side" are also used to describe the surfaces of material layers or features formed on, in, or through a semiconductor substrate, regardless of whether these material layers or features ultimately exist in the fabricated or assembled device.

[0035] Spatially relative terms are used herein to describe relationships between elements, such as the relationship between substrates, heat generating devices, cooling assembly components, device packaging components, and other features described below. Unless otherwise specified, terms such as "above," "over," "upper," "upwardly," "outwardly," "on," "below," "under," "beneath," "lower," and the like generally refer to the X, Y, and Z directions illustrated in the accompanying drawings. Therefore, it should be understood that the spatially relative terms used herein are intended to cover different orientations of the substrate and are not limited by the direction of gravity unless otherwise specified. Unless otherwise specified, terms describing the relationship between elements, such as "disposed on," "embedded in," "coupled to," "connected by," "attached to," "bonded to," used alone or in combination with spatially relative terms, include relationships with intermediate elements as well as direct relationships without intermediate elements.

[0036] Unless otherwise noted, the term "cold plate" generally refers to a base plate or a stack of base plates bonded directly to each other, which can be bonded to a semiconductor device. The cold plate can include material layers and / or metal features formed on or in the surface of the base plate or base plate stack that facilitate direct dielectric bonding or hybrid bonding with the semiconductor device. The direct bonding method enables heat from the semiconductor device to be transferred through the cold plate to a fluid flowing over it without the use of a thermal interface material. Unless otherwise noted, the device packages and cold plates described herein can be used with any desired fluid coolant (e.g., liquid, gas, and / or vapor phase coolants). Therefore, these terms should not be interpreted as limiting the coolant to any one fluid phase.

[0037] Figure 11 is a schematic plan view of an example of a system panel 100 according to an embodiment of the present disclosure. Generally, the system panel 100 includes a printed circuit board (here, PCB 102), a plurality of device packages 301 mounted on the PCB 102, and a plurality of coolant lines 108 that fluidly couple each of the device packages 301 to a coolant source 110. It is contemplated that the coolant can be delivered to each of the device packages 301 in any desired fluid phase (e.g., liquid, vapor, gas, or a combination thereof) and can flow from the device packages 301 in the same phase or in different phases. In some embodiments, the coolant is delivered to the device packages 301 and returned therefrom as a liquid, and the coolant source 110 can include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant can be delivered to the device packages 301 as a liquid, evaporated into a liquid within the device packages, and returned to the coolant source 110 as a vapor. In these embodiments, the device package 301 may be fluidly coupled in parallel to the coolant source 110 , and the coolant source 110 may include or further include a compressor (not shown) for condensing the received vapor into liquid form.

[0038] Figure 2 yes Figure 1 1 is a schematic partial side cross-sectional view of a portion of a system panel 100. As shown, each device package 301 is placed in a socket 114 of a PCB 102 and connected thereto using a plurality of pins 116 or by other suitable connection methods, such as solder bumps (not shown). The device package 301 can be mounted in the socket 114 and fastened to the PCB 102 using a fixing frame 106 and a plurality of fasteners 112 (e.g., compression screws), the plurality of fasteners 112 being collectively configured to apply a relatively uniform downward force on the upward-facing edge of the device package 301. The uniform downward force ensures proper pin contact between the device package 301 and the socket 114.

[0039] As shown, each device package 301 is placed in a socket 114 of the PCB 102 and connected thereto using a plurality of pins 116 or by other suitable connection methods, such as solder bumps (not shown). The device package 301 can be mounted in the socket 114 and fastened to the PCB 102 using a fixing frame 106 and a plurality of fasteners 112 (e.g., compression screws), which are collectively configured to apply a relatively uniform downward force on the upward-facing edge of the device package 301. The uniform downward force ensures proper pin contact between the device package 301 and the socket 114.

[0040] Figure 3A is a schematic exploded isometric view of the device package 301 . Figure 3Bis a schematic cross-sectional view of device package 301 taken along line AA'. Generally, device package 301 includes a package substrate 302, an integrated cooling assembly 303, and a package lid 308. Device package 301 also includes an adhesive layer 322 that attaches the integrated cooling assembly 303 to the package lid 308 to define a coolant channel 310 therebetween.

[0041] Typically, the package substrate 302 is formed of a rigid material (such as an epoxy or resin-based laminate) that supports the integrated cooling assembly and the package lid 308. The package substrate 302 typically includes conductive features that electrically couple the integrated cooling assembly 303 to the PCB 102. The integrated cooling assembly 303 may include a semiconductor device (here, device 304) placed on the package substrate 302 and a cold plate 306 bonded to the device 304. Here, the device 304 has an active side 318 and an inactive back side 320 opposite the active side 318. The active side 318 includes device components (e.g., transistors, resistors, and capacitors) formed thereon or therein. As shown, the active side 318 is positioned adjacent to and facing the package substrate 302. The active side 318 can be electrically connected to the package substrate 302 using conductive bumps 319, which are encapsulated by a first underfill layer 321 placed between the device 304 and the package substrate 302. The first underfill layer 321 may include a cured polymer resin or epoxy resin that provides mechanical support for the conductive bumps 319 and prevents thermal fatigue.

[0042] Here, the cold plate 306 is attached to the device backside 320 without the use of an intermediate adhesive material, for example, by being directly bonded to the device backside 320, such that the cold plate 306 and the device backside 320 are in direct thermal contact. In some embodiments, the cold plate 306 is attached to the device backside 320 using a direct dielectric bonding process. In other embodiments, the cold plate 306 is attached to the device backside 320 using a mixture of direct dielectric bonding and direct metal bonds formed therebetween. For example, in some embodiments, one or both of the device backside 320 and the device-facing side of the cold plate 306 include dielectric material layers, for example, a first dielectric material layer 334A and a second dielectric material layer 334B, respectively, and the cold plate 306 is directly bonded to the device backside 320 via bonds formed between the dielectric material layers 334A-B. In some embodiments, cold plate 306 is bonded directly to device backside 320 using a hybrid bonding technique, where bonds are formed between dielectric material layers 334A-B and between metal features placed in dielectric material layers 334A-B (such as between first metal pad 336A and second metal pad 336B).

[0043] Suitable dielectrics that can be used as dielectric material layers 334A-B include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, metal oxides, metal nitrides, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some embodiments, one or both of dielectric material layers 334A-B are formed from an inorganic dielectric material (i.e., a dielectric material that is substantially free of organic polymers). Typically, one or both of layers 334A-B are deposited to a thickness greater than the thickness of the native oxide, such as approximately 1 nm or greater, 5 nm or greater, 10 nm or greater, 50 nm or greater, 100 nm or greater, or 200 nm or greater. In some embodiments, one or both of layers 334A-B are deposited to a thickness of 301 nm or less (e.g., 200 nm or less, 100 nm or less, or 50 nm or less).

[0044] Advantageously, direct bonding of dielectric and (optionally) metal surfaces eliminates the need for an intervening adhesive layer or thermal interface material (TIM) layer between the device 304 and the cold plate 306. Consequently, the device package 301 reduces the thermal resistance of the heat transfer path 326 (e.g., by a factor of 50 or more) compared to the heat transfer path of a conventional device package. Methods for forming direct dielectric and hybrid bonds are described below.

[0045] As shown, the upward-facing surface of cold plate 306 forms a cavity comprising a base surface 309 that forms the bottom of coolant channel 310 and sidewalls 311 that surround and protrude upward from base surface 309. The upward-facing surface of sidewalls 311 forms a peripheral surface 313 that supports adhesive layer 322. Typically, when device package 301 is assembled, coolant channel 310 comprises a space between base surface 309 and package lid 308. Adhesive layer 322 attaches peripheral surface 313 to package lid 308 and forms an impermeable barrier that prevents coolant delivered to coolant channel 310 from reaching and damaging active side 318 of device 304. Adhesive layer 322 absorbs the linear expansion difference between the different materials and can therefore be considered a decoupling adhesive material that allows for a CTE difference between package lid 308 and cold plate 306. In some embodiments, adhesive layer 322 includes a decoupling film placed between and adhered to each of cold plate 306 and package lid 308 .

[0046] In some embodiments, the cold plate 306 includes a plurality of raised features 324 (such as fins, posts, or struts extending upward from the base surface 309). The raised features 324 provide increased surface area and disrupt the laminar fluid flow at the interface between the coolant and the cold plate 306, thereby increasing heat transfer between the two. To further enhance heat dissipation from the device, the raised features 324 can include and / or be formed from a thermally conductive metal (such as copper). Typically, the raised features 324 are arranged in a repeating pattern. In some embodiments, the raised features 324 can be arranged in a random pattern.

[0047] In some embodiments, cold plate 306 is made of a material having a coefficient of thermal expansion (CTE) substantially similar to the CTE of the bulk semiconductor substrate of device 304. For example, in some embodiments, device 304 may be formed on a single crystal silicon substrate, while cold plate 306 may be formed from a single crystal silicon or polycrystalline silicon substrate. Forming cold plate 306 from a CTE-matched material (relative to the bulk substrate material of device 304) prevents undesirable separation of device 304 and cold plate 306 during repeated thermal cycling.

[0048] In some embodiments, the cold plate 306 can be formed of an amorphous silicon material, such as a bulk substrate material including a metal, a metal alloy, a ceramic, a composite material, or other low CTE material suitable for bonding using the methods described below. For example, the cold plate 306 can be formed of a bulk material selected from the group consisting of copper, aluminum, copper alloys (e.g., copper-molybdenum alloys and copper-tungsten alloys), iron-cobalt-nickel alloys (e.g., copper-cobalt-nickel alloys of Magellan Industries, Inc., South Norwalk, Connecticut, USA), and aluminum. ), iron-cobalt-nickel-silver alloys, iron-nickel alloys (e.g., Magellan's superalloys), iron-nickel-silicon alloys, aluminum silicon carbide, aluminum silicon alloys, beryllium, beryllium oxide, and beryllium oxide composites, aluminum graphite fibers, copper graphite fibers, metal diamond composites (e.g., aluminum diamond composites and silver diamond composites), metal oxides, metal nitrides, and combinations thereof. Non-silicon substrate materials may be prepared for bonding as described below and may or may not include a layer of dielectric material deposited on the device-facing side to form a bonding surface.

[0049] The package lid 308 typically includes one or more vertical or angled sidewall portions 308A and a transverse portion 308B that spans and connects the sidewall portions 308A. The sidewall portion 308A extends upward from the outer peripheral surface of the package substrate 302 to surround the device 304 and the cold plate 306 placed thereon. The transverse portion 308B is placed above the cold plate 306 and is typically separated from the cold plate 306 by a gap corresponding to the thickness of the adhesive layer 322. Coolant circulates through the coolant channels 310 via inlet / outlet openings 312 formed through the transverse portion 308B. Cooling lines can be attached to the device package 301 using threads formed in the sidewalls of the inlet / outlet openings 312 and / or connector features surrounding the openings 312 and extending upward from the surface of the transverse portion 308B.

[0050] Typically, the package cover 308 is formed of a semi-rigid or rigid material so that the package cover 308 is fixed to the frame 106 ( Figure 2 ) At least a portion of the downward force applied to package lid 308 is transferred to the supporting surface of package substrate 302, rather than to cold plate 306 and the device 304 thereunder. In some embodiments, package lid 308 is formed of a thermally conductive metal, such as aluminum or copper. In some embodiments, package lid 308 serves as a heat sink that redistributes heat from one or more electronic components within a multi-component device package, such as described below.

[0051] As noted above, adhesive layer 322 thermally couples cold plate 306 to package lid 308 and, in combination, defines coolant channel 310. As shown, adhesive layer 322 is positioned between outer peripheral surface 313 of cold plate 306 and lateral portion 308B of package lid 308. Here, cold plate 306 forms the lower or base surface of coolant channel 310 and at least a portion of the coolant channel's sidewalls, package lid 308 forms the upper surface of coolant channel 310, and adhesive layer 322 forms a seal between package lid 308 and outer peripheral surface 313 of cold plate 306. In other embodiments, adhesive layer 322 may be positioned between sidewall 311 of cold plate 306 and sidewall portion 308A of package lid 308. Typically, when device package 301 is assembled, adhesive layer 322 forms an impermeable barrier that prevents coolant delivered to coolant channel 310 from reaching and damaging active side 318 of device 304.

[0052] In some embodiments, the device package 301 further includes a second bottom fill layer 338 (eg, Figure 3B), which is positioned in the gap area outside of the coolant channel 310, such as between the package lid 308, the adhesive layer 322, and the package substrate 302. For example, the second underfill layer 338 may include a polymer or epoxy material extending upward from the package substrate 302 to encapsulate and / or surround the device 304 and, in some embodiments, at least a portion of the cold plate 306. When used, the second underfill layer 338 can provide mechanical support, thereby improving system reliability and extending the useful life of the device package 301. For example, the second underfill layer 338 can reduce mechanical stresses that can weaken interfacial bonds and / or electrical connections between components of the device package 301, such as stresses caused by vibration, mechanical and thermal shock, and / or fatigue caused by repeated thermal cycling. In some embodiments, the second underfill layer 338 may be a thermally conductive material, such as a polymer or epoxy with one or more thermally conductive additives, such as silver and / or graphite.

[0053] Figure 4A is a schematic isometric view of an integrated cooling assembly 403 that increases heat dissipation from high heat flux areas (ie, hot spot areas 408 ) relative to heat dissipation from adjacent areas of the device 304 . Figure 4B Yes (along Figure 4A Schematic side cross-sectional view of the integrated cooling assembly 403 (taken along line BB' of FIG), showing an embedded thermoelectric cooler (here, TEC 404) placed over a device hotspot 408. Figure 4C 4 is a close-up view of a TEC 404. Generally, the integrated cooling assembly 403 includes one or more TECs 404, each TEC 404 positioned within a corresponding cavity formed in a cold plate 406. Generally, each TEC 404 includes alternating n-type semiconductor pillars 410 and p-type semiconductor pillars 412 electrically connected in series via a plurality of conductive plates 414. Each TEC 404 is coupled to a DC power supply 416, and as current flows therethrough, heat is transferred from a first side of the TEC 404 positioned adjacent to a hot spot region 408 to a second side of the TEC 404 adjacent to the cold plate 406. Each TEC 404 can be bonded to one or both of the device 304 and the cold plate 406 using a direct bonding method described below.

[0054] Here, power is delivered to TEC 404 using metal interconnects and / or vias (such as through-substrate vias (TSVs) 418 shown) formed in, on, or through device 304. In some embodiments, power is delivered to TEC 404 using conductive features formed in or between interface surfaces of device 304 and cold plate 406. In some embodiments, power can be delivered to TEC 404 through conductive features (e.g., metal interconnects and vias formed in and / or through cold plate 406).

[0055] In some embodiments, the number (count), density, size, and / or shape of raised features 324 extending upward from base surface 309 in an area disposed above TEC 404 is different than the surrounding area of ​​base surface 309. For example, Figure 4A-4B As shown in FIG, a surface region 409 positioned above the TEC 404 has fewer or no protrusions than adjacent areas of the base surface 309, which increases the volume flow rate of the coolant above the region 409, thereby increasing the relative heat transfer from that region.

[0056] Figure 5 FIG2 is a schematic side cross-sectional view of an example of a multi-component device package 501 including a cold plate 506 bonded directly to the backside surfaces of two or more devices. As shown, device package 501 includes a package substrate 502 (e.g., an interposer that facilitates connectivity between device 304 and device stack 604), an integrated cooling assembly 503, a package lid 308, and an adhesive layer 322. Integrated cooling assembly 503 may include multiple devices (which may be singulated (e.g., device 304) and / or placed in a vertical device stack 504) and a cold plate 306 bonded to each of the devices 304 and device stack 504. In some embodiments, device 304 may include a processor, and device stack 504 may include multiple memory devices. As shown, device 304 and device stack 504 are placed in a side-by-side arrangement on package substrate 302 and electrically connected thereto using suitable methods. Cold plate 506 is placed over the back side of device 304 and the back side of the topmost device in stack 504 and is bonded directly thereto. Here, cold plate 506 is sized to provide a bonding surface for attachment to device 304 and device stack 504, but otherwise may be the same or substantially similar to other cold plates described herein. For example, cold plate 506 may include any one or a combination of the features of the cold plates described with respect to other figures herein. In some embodiments, integrated cooling assembly 503 may include one or more TECs 404 ( Figure 4B ), which is embedded between the cold plate 506 and the first device 904A and / or between the cold plate 506 and the device stack 504.

[0057] Figure 6 FIG6 is a schematic side cross-sectional view of an example of a multi-component device package 601 that includes an integrated cooling assembly 303 and a device stack 604, wherein heat is transferred from the device stack 604 to the integrated cooling assembly 303 via a package lid 608. Here, the device package 601 includes a package substrate 502, an integrated cooling assembly 303, one or more second devices (shown here as device stack 604), and a package lid 608. Typically, the integrated cooling assembly 303 is coupled to the package lid 608 using an adhesive layer 322 to define coolant channels 310 positioned therebetween. The device stack 604 can be placed on the package substrate 502 in a side-by-side arrangement with the device 304. As described above, heat generated by the device 304 is dissipated to a coolant circulating through the coolant channels (here, coolant channels 310) via inlet / outlet openings 312 formed through the package lid 608. The package lid 608 can be formed of a thermally conductive material and act as a heat sink. The heat generated by the device stack 604 is dissipated to the coolant via the package lid 608, which is thermally coupled to the device stack 604 using the TIM layer 616. Advantageously, the cold plate 306 blocks the thermal path between the device 304 and the device stack 604 to prevent heat transfer therebetween. Thus, the device package 601 can be advantageously used to facilitate closely spaced devices (such as high-power devices and memory stacks) on an interposer, thereby providing latency reduction while eliminating undesirable heat transfer therebetween.

[0058] In some embodiments, the device package 601 further includes a heat spreader 608A that is placed on a portion of the package lid 601 above the device stack 604. The heat spreader 608A can be thermally coupled to the package lid 608 using a TIM layer (not shown) or by direct bonding using the methods described herein. In some embodiments, the device package 601 includes one or more TECs 404 and / or a second underfill layer 338, as shown above.

[0059] Figure 7A is a schematic side cross-sectional view of device package 701 with adhesive attached between package lid 308 and interior surface 715 of cold plate 706 . Figure 7Bis a schematic isometric exploded view of an integrated cooling assembly 703 and an adhesive layer 322. Generally, device package 701 includes a package substrate 302, an integrated cooling assembly 703, and a package lid 308. Integrated cooling assembly 703 includes device 304 and a cold plate 706, which is directly bonded to device 304 using an adhesive layer 722. Adhesive layer 722 includes a first portion 722A disposed on outer peripheral surface 313 and a second portion 722B disposed on inner surface 715 (the surface of cold plate 706 disposed inward from outer peripheral surface 313). Here, first portion 722A forms a hermetic seal between cold plate 706 and package lid 308 to define the perimeter of coolant channel 710 disposed between cold plate 706 and package lid 308. Second portion 722B attaches inner surface 715 to a corresponding portion of package lid 308 disposed thereover. The inner surface 715 can be positioned on a protrusion extending upward from the base surface 309 (as shown), or can include an area of ​​the base surface 309. The additional attachment location provided by the second portion 722B significantly reduces or prevents deformation of the package cover 308 due to the circulation of high-pressure coolant through the coolant channel 710. Thus, the additional attachment location allows for an increased flow rate of the coolant, which in turn provides increased cooling efficiency. It is contemplated that the additional attachment location provided by the second portion 722B can be used with any of the device packages described herein.

[0060] Figure 8A is a schematic side cross-sectional view of device package 801 in which a portion of integrated cooling assembly 803 protrudes into the lower surface of package lid 808 to provide additional structural support. Figure 8B is a schematic isometric exploded view of an integrated cooling assembly 803. As shown, the integrated cooling assembly 803 includes a device 304 and a cold plate 806 directly bonded to the device 304. The cold plate 806 includes a plurality of plates that are patterned and directly bonded to each other, shown here as a first plate 812 and a second plate 814 directly bonded to the first plate 812. The first plate 812 can be substantially similar to the cold plates 306, 406, 506 described above, or include any combination of features thereof. Here, the first plate 812 includes the base surface 309, raised features 329, sidewalls 311, and peripheral surface 313 described above with respect to the cold plate 306. The second plate 814 includes a plurality of sidewalls 811 that are aligned with and bonded to the sidewalls 311 of the first plate 812. A blind opening formed in the interior surface of package lid 808 and / or a protrusion extending downwardly from the interior surface forms a well region that is sized and shaped to receive an upper portion of sidewall 811. In some embodiments, sidewall 811 forms a rectangular ring (when viewed in the z-direction), and well region 820 has a corresponding rectangular ring shape.

[0061] Here, the integrated cooling assembly 803 can be attached to the package lid 808 by an adhesive layer 822 placed in the well area 820. The adhesive layer 822 surrounds the upper portion of the sidewall 811 to form an airtight seal between the cold plate 806 and the package lid 808 and defines the perimeter of the coolant channel 810. In some embodiments, the adhesive layer 822 is formed of a flexible material that forms an impermeable seal around the perimeter of the coolant channel 810 when compressed between the package lid 808 and the cold plate 806.

[0062] In some embodiments, the second plate 814 includes one or more internal supports 815 (one shown) connecting the opposing sidewalls 811A and spaced apart from each of the sidewalls 811B. In these embodiments, portions of the well region 820 can be sized and shaped to receive upper portions of the internal supports 815. When in use, the internal supports 815 provide structural support for the second plate 814 and further secure the package cover 808 to the integrated cooling assembly 803. The additional attachment points provided by the internal supports 815 can significantly reduce or prevent deformation of the package cover 808 due to the circulation of high-pressure coolant through the coolant channels 810. Thus, the additional attachment points allow for increased coolant flow rates, which correspondingly improves cooling efficiency. It is contemplated that features of the device package (such as the cold plate 806 and package cover 808 described above) can be advantageously combined with features of any other item in the device package described herein.

[0063] Figure 9 is a schematic side cross-sectional view of a device package 901 in which one or more cold plates 906 are positioned to cool portions of a 3DIC device 904. Typically, the device package 901 includes an integrated cooling assembly 903 placed on and electrically connected to a package substrate 302, and a package lid 908 placed over the integrated cooling assembly 903. The integrated cooling assembly 903 includes a 3DIC device 904, which includes a first device 904A and one or more second devices 904B (one shown), and one or more cold plates 906. Here, the first device 904A is placed facing the package substrate 302, i.e., with the active side facing down, and the second device 904B is placed and bonded to a portion of the backside of the first device 904A. The first device 904A includes a plurality of interconnects formed between the active side and the backside, such as through-substrate vias (TSVs 918). In these embodiments, the first device 904A and the second device 904B can be interconnected using TSVs 918 and hybrid bonding formed between the active side of the second device 904B and the back side of the first device 904A. In some embodiments, one or more second devices or device stacks 604 are directly bonded to and interconnected with the first device 904A using direct hybrid bonding.

[0064] Here, the first device 904A is cooled using one or more cold plates 906 (two shown), which are placed in a side-by-side arrangement with the second device 904B and bonded to the backside of the first device 904A. Each of the one or more cold plates 906 is attached to the package lid 908 using an adhesive layer 822, wherein the adhesive material forms a hermetic seal between the outer peripheral surface of the cold plate 906 and the package lid 908, thereby at least partially defining a coolant channel therebetween. Heat generated by the first device 904A is dissipated from the device package via coolant flowing through the coolant channel 910 positioned above it. In some embodiments, the second device 904B is thermally coupled to the package lid 908 using a TIM layer 616. In these embodiments, the package lid 908 can serve as a heat sink, such that heat generated by the second device 904B is transferred to the coolant in the coolant channel 910 via a heat transfer path including the TIM layer 616 and the package lid 908.

[0065] Figure 10A is a schematic side cross-sectional view of a device package 1001 , wherein a coolant channel 1010 is positioned between a first HI device 1004A and a second HI device 1004B of an integrated cooling assembly 1003 . Figure 10B is an integrated cooling assembly 1003 along Figure 10A Schematic cross-sectional view taken along line CC' of FIG. Here, device package 1001A includes a package substrate 302, an integrated cooling assembly 1003 placed on the package substrate 302, and (optionally) a package lid 1008 placed above the integrated cooling assembly 1003. The integrated cooling assembly 1003 forms a fluid cavity that includes a first heterogeneous integrated (HI) device 1004A, a second HI device 1004B, and a frame-shaped cold plate. Here, a cold frame 1006 is placed between the first HI device 1004A and the second HI device 1004B.

[0066] Typically, the first HI device 1004A and / or the second HI device 1004B include multiple dissimilar integrated circuits that are connected to each other via hybrid bonding to form a heterogeneous integration. For example, the first HI device 1004A may include an interposer 1005A and multiple semiconductor devices 1007A (and / or device stacks) placed in a side-by-side arrangement on the interposer 1005A. Here, the semiconductor devices 1007A are interconnected through the interposer 1005A using hybrid bonds formed therebetween. The second device 1004B is a 3DIC integration that includes a base die 1005B and one or more second devices 1007B (e.g., chiplets) bonded to the base die 1005B via, for example, hybrid bonding. In other embodiments, both devices are 2.5DIC or 3DIC integrations, or the relative positions of the first HI device 1004A and the second HI device 1004B may be swapped. In some embodiments, the interposer 1005A and / or the base die 1005B include a plurality of conductive features (not shown) (eg, bond pads) formed in peripheral surfaces thereof.

[0067] The cold frame 1006 generally includes a plurality of side walls that form a polygonal ring shape (e.g., a rectangular ring shape) when viewed from the Z direction. In some embodiments, the cold frame 1006 may also include a plurality of vias 1018 ( Figure 10B ), these vias are placed in the sidewalls and extend between the opposite surfaces of the board (in the Z direction). The cold frame 1006 is aligned with and bonded to the outer peripheral surfaces of the interposer and / or die 1005A-B using hybrid bonding. As shown, the devices 1004A-B and the cold frame 1006 bonded therebetween jointly define a coolant channel 1010, wherein the backside surfaces of the devices 1007A-B are placed in the coolant channel 1010. The coolant fluid circulates through the coolant channel 1010 via inlet openings / outlet openings 1022 formed through the opposite sidewalls of the cold frame 1006. In some embodiments, the device package 1001A may include a package cover 1008 placed above the integrated cooling assembly 1003 and an adhesive material or molding material 1038 placed between the package cover 1008 and the integrated cooling assembly. In these embodiments, cooling fluid may be delivered to channel 1010 via a flow path including inlet / outlet openings 1012, openings in molding material 1038, and openings 1022 formed through the plate sidewalls, each of which are in registration or fluid communication with one another.

[0068] In device package 1001A, integrated cooling assembly 1003 is placed and electrically connected to package substrate 302, for example, via conductive bumps 319 placed between the package substrate and interposer 1005A. A second device 1004B is in electrical communication with the package substrate through vias 1018 and hybrid bonds formed between interposer 1005A, cold frame 1006, and base die 1005B.

[0069] Figure 10C FIG1 is a schematic side cross-sectional view of a device package 1011 having a coolant channel 1010 positioned between a first HI device 1004A and a second HI device 1004B of an integrated cooling assembly 1003, wherein the first HI device 1004A is electrically connected to a first package substrate 302A, and the second HI device 1004B is electrically connected to a second package substrate 302B. In these embodiments, the device package 1011 can be positioned between and connect opposing PCBs 102A-B.

[0070] Figure 11 A method 1100 is shown that may be used to manufacture the device packages described herein. Figure 12 Aspects of method 1100 are illustrated using a device package 301 at various stages of the manufacturing process. At least some of the features of device package 301 described below can be found with reference to FIG. 3 . However, it is contemplated that method 1100 can be used to manufacture any of the device packages described herein. At block 1102 , method 1100 includes aligning a first substrate 1202 with a second substrate 1204 , wherein first substrate 1202 includes a plurality of dies (e.g., devices 304) to be singulated and second substrate 1204 includes a plurality of cold plates 306 to be singulated. Cold plates 306 can be formed from one or more base plates 924a-b (two are shown) according to any of the embodiments described above in FIG. 4-7 . As shown, first substrate 1202 includes a plurality of devices 304 arranged in a rectangular array and spaced apart from one another by a plurality of scribe lines 1206 extending in the X and Y directions, thereby forming a grid pattern.

[0071] The first substrate 1202 may include a bulk material and a plurality of material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for fabricating semiconductor devices (such as silicon, silicon germanium, germanium, III-V semiconductor materials, II-VI semiconductor materials, or combinations thereof). For example, in some embodiments, the first substrate 1202 may include a single crystal wafer (such as a silicon wafer), a plurality of device components formed in or on the silicon wafer, and a plurality of interconnect layers formed above the plurality of device components. In other embodiments, the substrate may include a reconstituted substrate (e.g., a substrate formed from a plurality of singulated devices embedded in a support material).

[0072] After forming the device 304, the bulk material of the first substrate 1202 can be thinned using one or more backgrinding, etching, and polishing operations that remove material from the back side. Thinning the first substrate 1202 can include using a combination of grinding and etching processes to reduce the thickness (in the Z direction) to about 450 μm or less (such as about 301 μm or less, or about 150 μm or less). After thinning, the back side can be polished to a desired smoothness using a chemical mechanical polishing (CMP) process and a dielectric material layer deposited thereon. In some embodiments, the dielectric material layer can be polished to a desired smoothness to prepare the substrate 1202 for a bonding process. In some embodiments, the method 1100 includes forming a plurality of metal features in the dielectric material layer (e.g., by using a damascene process) in preparation for a hybrid bonding process.

[0073] In some embodiments, the active side is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. When used, the carrier substrate provides support for the thinning operation and / or the thinned material to facilitate substrate handling during one or more of the subsequent manufacturing operations described herein. In some embodiments, the second substrate 1204 is formed from a plurality of substrates (not shown), each substrate comprising a single bulk material that is patterned to define a plurality of plates, such as Figure 8B 1 and 12. The first and second plates 806A, 806B of the integrated cooling assembly 803 are shown. When viewed from above (in the Z direction), each of the plurality of substrates can have substantially the same size and shape as the first substrate 1202, such that the interface surfaces are substantially coextensive with each other. In some embodiments, the thickness (in the Z direction) of each of the substrates is between about 0.5 mm and about 10 mm, or between about 1 mm and about 8 mm, or between about 1 mm and 6 mm, such as about 0.5 mm or greater, such as about 1 mm or greater, or about 2 mm or greater, or about 10 mm or less, such as about 8 mm or less, or about 6 mm or less.

[0074] In some embodiments, the second substrate 1204 is formed from a bulk material having a linear coefficient of thermal expansion (CTE) substantially similar to that of the bulk material of the first substrate 1202, where CTE is the fractional change in length of a material (in the XY plane) per degree of temperature change. In some embodiments, the CTE of the first substrate and the CTE of the second substrate are matched such that, when measured over a desired temperature range, the CTE of the second substrate 1204 is within approximately + / - 20% or less of the CTE of the first substrate 1202 (such as within + / - 15% or less, within + / - 10% or less, or within approximately + / - 5% or less). In some embodiments, the CTEs are matched across a temperature range from approximately -60°C to approximately 200°C or from approximately 60°C to approximately 175°C. In one exemplary embodiment, the CTE-matched materials each comprise silicon. For example, the bulk material of the first substrate 1202 can comprise single crystal silicon, while the bulk material of the second substrate 1204 can comprise single crystal silicon or polycrystalline silicon. In some embodiments, method 1100 includes forming a layer of dielectric material on a lower surface of second substrate 1204 and optionally forming a plurality of metal features.

[0075] At block 1104, the method 1100 includes directly bonding a plurality of cold plates 306 formed in the second substrate 1204 to the plurality of devices 304 in the first substrate 1202. As described above, the bonding surfaces can each include a dielectric material layer, and directly bonding the first substrate 1202 and the second substrate 1204 includes forming a dielectric bond between the first dielectric material layer 334A and the second dielectric material layer 334B. Alternatively, the first substrate 1202 and the second substrate 1204 can be directly bonded using a mixture of dielectric bonds and metallic bonds formed between metallic features.

[0076] Typically, directly bonding the surfaces (of the dielectric material layer) includes preparing, aligning, and contacting the surfaces. Preparing the surfaces can include smoothing the respective surfaces to a desired surface roughness, such as between 0.1 and 3.0 nm RMS, activating the surfaces to weaken or open chemical bonds in the dielectric material, and terminating the surfaces with a desired species. Smoothing the surfaces can include polishing the substrates 1202, 1204 using a chemical mechanical polishing (CMP) process. Activating and terminating the surfaces with a desired species can include exposing the surfaces to free radical species formed in a plasma.

[0077] In some embodiments, the plasma is formed from a nitrogen-containing gas (e.g., N2), and the terminator species include nitrogen and hydrogen. In some embodiments, a wet cleaning process (e.g., by exposing the surface to an aqueous ammonia solution) can be used to activate the surface. In some embodiments, a dielectric bond can be formed using a dielectric material layer deposited on only one of substrates 1202 and substrate 1204 (rather than both substrates). In these embodiments, a direct dielectric bond can be formed by directly contacting the deposited dielectric material layer of one substrate with a bulk material surface (e.g., a bulk semiconductor or polysilicon material surface) of the other substrate. In such embodiments, the bulk material surface can include a thin layer of native oxide, or can be cleaned prior to contact to be substantially free of native oxide.

[0078] At block 1104, forming a direct dielectric bond directly between the substrates includes bringing the prepared and aligned surfaces into direct contact at a temperature below 150° C. (such as below 100° C., for example below 30° C.) or about room temperature (e.g., between 20° C. and 30° C.). Without being bound by theory, it is believed that hydrogen termination species diffuse from the interfacial bonding surfaces and form chemical bonds between the remaining nitrogen species during the direct bonding process. In some embodiments, an annealing process is used to enhance direct bonding, wherein the substrates are heated to and maintained at a temperature above about 30° C. and below about 450° C. (e.g., above about 50° C. and below about 250° C.) or about 150° C. for a duration of about 5 minutes or longer (such as about 15 minutes). Typically, bonding strengthens over time even without the application of heat. Therefore, in some embodiments, the method does not include heating the substrates.

[0079] In embodiments where hybrid dielectric bonding and metal bonding are used to bond the substrates, the method may further include planarizing or recessing the metal features below the field surface prior to contacting and bonding the dielectric material layer. After forming the dielectric bond, the substrates 1202, 1204 may be heated to a temperature of 150°C or higher and maintained at the elevated temperature for a duration of about 1 hour or longer (such as between 8 and 24 hours) to form a direct metallurgical bond between the metal features. Suitable direct dielectric and hybrid bonding techniques that may be used to perform aspects of the methods described herein include and They are all commercially available from Adeia Holding, Inc., San Jose, California, USA.

[0080] At block 1106, method 1100 includes singulating the plurality of integrated cooling assemblies 303 from the bonded substrates. Singulation after bonding imparts unique structural properties to the integrated cooling assemblies 303 because the bonding surface of each cold plate 306 has the same perimeter as the backside of the device 304 bonded thereto. Thus, the sidewalls of the cold plate 306 are generally flush with the edges of the device 304 about their common perimeter. In some embodiments, the cold plates 306 are singulated from the second substrate 1204 using a process that cuts or separates the second substrate 1204 in a vertical plane (i.e., parallel to the Z direction). In these embodiments, the sides of the cold plates 306 are substantially perpendicular to the backsides of the devices (i.e., the horizontal (XY) plane of the attachment interface between the device 304 and the cold plate 306). In some embodiments, the cold plates 306 are singulated using a saw or laser cutting process.

[0081] At block 1108 , the method includes connecting the integrated cooling assembly to the package substrate 302 and attaching the package lid 308 to the integrated cooling assembly 303 using the adhesive layer 322 . In some embodiments, the method also includes at least partially encapsulating the integrated cooling assembly 303 with a second underfill layer 338 .

[0082] The above-described method advantageously provides an embedded cold plate that eliminates and / or significantly reduces the thermal resistance path typically associated with cooling systems attached to the outside of the device package. The cold plate can be attached to the semiconductor device using direct dielectric or hybrid dielectric and metal bonding methods. Compared to conventional silicon-silicon bonding methods (such as thermocompression bonding methods), such bonding methods allow for a relatively low thermal budget while providing significantly improved bond strength.

[0083] The cold plate and semiconductor device can be formed from CTE-matched materials, eliminating the need for an intermediate TIM layer. The cold plate and package lid can be formed from CTE-mismatched materials and attached to each other using a flexible adhesive material. The flexible adhesive absorbs the linear expansion differences between the package lid and cold plate during repeated thermal cycling, extending the life of the device package.

[0084] This specification discloses embodiments including but not limited to the following:

[0085] 1. A device package comprising: a package substrate; a package lid positioned on the package substrate; an integrated cooling assembly positioned between the package substrate and the package lid, the integrated cooling assembly comprising a semiconductor device and a cold plate, the cold plate comprising a first side attached to the semiconductor device and a second side opposite the first side; and an adhesive layer positioned between the package lid and the second side of the cold plate, wherein: one or more surfaces of the second side of the cold plate are spaced apart from the package lid to define a coolant channel therebetween; and the adhesive layer seals the package lid to the cold plate around a perimeter of the coolant channel. 2. The device package of item 1, wherein the cold plate is attached to the semiconductor device by direct dielectric bonding. 3. The device package of item 1, wherein the cold plate is attached to the semiconductor device by direct hybrid bonding. 4. The device package of item 1, further comprising a coolant fluid positioned in the coolant channel. 5. The device package of item 1, wherein the coolant channel forms a fluid pathway between an inlet opening and an outlet opening positioned through the package lid. 6. The device package of item 1, further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in an area outside the coolant channel. 7. The device package of item 1, wherein: the second side of the cold plate comprises a base surface and sidewalls surrounding the base surface and extending upward from the base surface to form a cavity; and the first portion of the adhesive layer is positioned between the sidewalls and the package lid. 8. The device package of item 7, wherein the adhesive layer comprises one or more second portions that attach the cold plate and the package lid in one or more locations inward of the perimeter of the coolant channel. 9. The device package of item 7, wherein the second side of the cold plate further comprises a plurality of raised features extending upward from the base surface. 10. The device package of item 9, wherein the raised features comprise thermally conductive metal. 11. The device package of item 1, wherein the integrated cooling assembly further comprises a thermoelectric cooler positioned between the hot spot region of the semiconductor device and the portion of the cold plate positioned above the hot spot region. 12. The device package of item 11, wherein the thermoelectric cooler is electrically coupled to the package substrate via an interconnect placed through the semiconductor device. 13. The device package of item 11, wherein: the second side of the cold plate includes a plurality of raised features; and the pattern density, size, and / or shape of the raised features in the area above the thermoelectric cooler is different from that of adjacent areas. 14. The device package of item 11, wherein the thermoelectric cooler is directly bonded to the cold plate, the semiconductor device, or both. 15. The device package of item 1, wherein: the adhesive layer includes a first portion and a second portion, the first portion sealing the package lid to the cold plate around the perimeter of the coolant channel, the second portion being placed inwardly around the perimeter of the coolant channel; and the second portion of the adhesive layer attaches the interior surface of the cold plate to a corresponding portion of the package lid placed thereover.16. The device package of item 7, wherein the inwardly facing surface of the package lid includes a continuous well region, the well region being sized and shaped to receive a portion of a sidewall of the cold plate. 17. The device package of item 16, wherein the adhesive layer comprises a flexible material that surrounds an upper portion of the sidewall positioned in the well region. 18. The device package of item 17, wherein: the cold plate further comprises one or more internal supports connecting a pair of opposing sidewalls; and the continuous well region is sized and shaped to receive an upper portion of the internal supports. 19. The device package of item 18, wherein the adhesive layer at least partially surrounds an upper portion of the internal supports positioned in the well region. 20. The device package of item 18, wherein: the cold plate comprises a first plate and a second plate directly bonded to the first plate; and the second plate forms an upper portion of the sidewall positioned at least partially in the well region. 21. The device package of item 1, wherein: the semiconductor device comprises a first device and a second device directly bonded to the first device; the integrated cooling assembly comprises one or more cold plates attached to the first device; and each of the one or more cold plates is sealed to the package lid via an adhesive layer to define a perimeter of a coolant channel disposed therebetween. 22. The device package of item 21, wherein the second device is thermally coupled to the package lid via a TIM layer disposed therebetween. 23. A device package comprising: a package substrate; a package lid positioned on the package substrate; an integrated cooling assembly positioned between the package substrate and the package lid, the integrated cooling assembly comprising a first semiconductor device, one or more second semiconductor devices arranged in a device stack, and a cold plate, wherein the cold plate comprises a first side and a second side opposite the first side; the first semiconductor device and the device stack are attached to the first side of the cold plate in a side-by-side arrangement; and an adhesive layer positioned between the package lid and the second side of the cold plate, wherein one or more surfaces of the second side of the cold plate are spaced apart from the package lid to define a coolant channel therebetween; and the adhesive layer seals the package lid to the cold plate around a perimeter of the coolant channel. 24. The device package of item 23, wherein the cold plate is attached to the semiconductor device by direct dielectric bonding. 25. The device package of item 23, wherein the cold plate is attached to the semiconductor device by direct hybrid bonding.26. A device package comprising: a package substrate; a package lid positioned on the package substrate; an integrated cooling assembly positioned between the package substrate and the package lid, the integrated cooling assembly comprising a first semiconductor device and a cold plate, the cold plate comprising a first side attached to the semiconductor device and a second side opposite the first side; an adhesive layer positioned between the package lid and the second side of the cold plate, wherein: one or more surfaces of the second side of the cold plate are spaced apart from the package lid to define a coolant channel therebetween; and the adhesive layer seals the package lid to the cold plate around a perimeter of the coolant channel; a device stack electrically connected to the package substrate in a side-by-side arrangement with the integrated cooling assembly; and a first TIM layer positioned between the device stack and the package lid. 27. The device package of item 26, wherein the package lid comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the coolant channel. 28. The device package of item 26, further comprising a heat sink thermally coupled to an outer side surface of the package lid, wherein the package lid comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the heat sink. 29. A device package comprising: an integrated cooling assembly comprising: a cold frame comprising a plurality of sidewalls; and a first device and a second device, each comprising a first die and one or more second dies directly bonded to the first die, wherein the first die are directly bonded to opposite sides of the cold frame, the cold frame forming a perimeter of a coolant channel positioned between the first and second devices, and backside surfaces of the second dies face each other within the coolant channel. 30. The device package of item 29, wherein conductive features positioned through the cold frame sidewalls electrically connect the first and second devices. 31. The device package of item 29, wherein the integrated cooling assembly is positioned on a first package substrate. 32. The device package of item 31, further comprising a second package substrate positioned on a side of the integrated cooling assembly opposite the first package substrate. 33. The device package of item 32, wherein the device package is positioned between a first PCB and a second PCB, the first package substrate connecting the first device to the first PCB, and the second package substrate connecting the second device to the second PCB. 34. A method of manufacturing a device package, the method comprising: directly bonding a first substrate comprising a semiconductor device to a second substrate comprising a cold plate; singulating an integrated cooling assembly comprising a semiconductor device and a cold plate from the bonded first and second substrates, the cold plate comprising a first side directly bonded to the semiconductor device and a second side opposite the first side; sealingly attaching a package lid to the second side of the cold plate, wherein one or more surfaces of the second side of the cold plate are spaced apart from the package lid to define a coolant channel therebetween; and, before or after attaching the package lid to the cold plate, connecting the semiconductor device to the package substrate. 35. The method of item 34, wherein the cold plate is directly bonded to the semiconductor device by direct hybrid bonding.36. The method of item 34, wherein the encapsulating lid is sealingly attached to the cold plate using an adhesive layer disposed therebetween. 37. The method of item 36, wherein: the second side of the cold plate includes a base surface and sidewalls surrounding the base surface and extending upward from the base surface to form a cavity; and a first portion of the adhesive layer is disposed between the sidewalls and the encapsulating lid. 38. The method of item 37, wherein the adhesive layer includes one or more second portions that attach the cold plate and the encapsulating lid in one or more locations inwardly of the perimeter of the coolant channel.

[0086] The embodiments discussed above are intended to be illustrative and not limiting. Those skilled in the art will appreciate that various aspects of the cooling assembly, device package, and method discussed herein may be omitted, modified, combined, and / or rearranged without departing from the scope of the present invention. Only the following claims are intended to define what is encompassed by the present invention.

Claims

1. A device package, comprising: Package substrate; A packaging cover is placed on the packaging substrate; an integrated cooling assembly positioned between the package substrate and the package lid, the integrated cooling assembly comprising a semiconductor device and a cold plate, the cold plate comprising a first side attached to the semiconductor device and a second side opposite the first side; as well as an adhesive layer disposed between the package lid and the second side of the cold plate, wherein: One or more surfaces of the second side of the cold plate are spaced apart from the package cover to define a coolant channel between the one or more surfaces and the package cover; as well as The adhesive layer seals the package cover to the cold plate around a perimeter of the coolant channel. 2 . The device package of claim 1 , the cold plate being attached to the semiconductor device by direct dielectric bonding. 3 . The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonding. 4 . The device package of claim 1 , further comprising a coolant fluid disposed in the coolant channel. 5 . The device package of claim 1 , wherein the coolant channel forms a fluid passage between an inlet opening and an outlet opening disposed through the package cover. 6 . The device package of claim 1 , further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in an area outside the coolant channel.

7. The device package according to claim 1, wherein: The second side of the cold plate includes a base surface and sidewalls surrounding the base surface and extending upwardly from the base surface to form a cavity; and A first portion of the adhesive layer is positioned between the sidewall and the package cover. 8 . The device package of claim 7 , wherein the adhesive layer comprises one or more second portions that attach the cold plate and the package lid in one or more locations inward of the perimeter of the coolant channel. 9 . The device package of claim 7 , wherein the second side of the cold plate further comprises a plurality of raised features extending upward from the base surface.

10. The device package of claim 9, wherein the raised feature comprises a thermally conductive metal.

11. The device package of claim 1, wherein the integrated cooling assembly further comprises a thermoelectric cooler positioned between a hot spot region of the semiconductor device and a portion of the cold plate positioned over the hot spot region.

12. The device package of claim 11, wherein the thermoelectric cooler is electrically coupled to the package substrate via an interconnect placed through the semiconductor device.

13. The device package according to claim 11, wherein: the second side of the cold plate comprising a plurality of raised features; as well as The pattern density, size, and / or shape of the raised features in the area above the thermoelectric cooler is different than in adjacent areas.

14. The device package of claim 11, wherein the thermoelectric cooler is directly bonded to the cold plate, the semiconductor device, or both.

15. The device package according to claim 1, wherein: The adhesive layer includes a first portion that seals the package cover to the cold plate around a perimeter of the coolant channel and a second portion that is positioned inwardly of the perimeter of the coolant channel; as well as The second portion of the adhesive layer attaches the interior surface of the cold plate to a corresponding portion of the encapsulation lid placed over the interior surface of the cold plate. 16 . The device package of claim 7 , wherein an inwardly facing surface of the package lid includes a continuous well region sized and shaped to receive a portion of the sidewall of the cold plate. 17 . The device package of claim 16 , wherein the adhesive layer comprises a flexible material surrounding an upper portion of the sidewall disposed in the well region.

18. The device package according to claim 17, wherein: The cold plate further includes one or more internal supports connecting a pair of opposing side walls; and The continuous well region is sized and shaped to receive an upper portion of the inner support. 19 . The device package of claim 18 , wherein the adhesive layer at least partially surrounds an upper portion of the internal support positioned in the well region.

20. The device package of claim 18, wherein: The cold plate includes a first plate and a second plate bonded directly to the first plate; and The second plate forms the upper portion of the sidewall that is at least partially positioned in the well region.

21. The device package of claim 1, wherein: The semiconductor device includes a first device and a second device directly bonded to the first device; The integrated cooling assembly includes one or more cold plates attached to the first device; as well as Each of the one or more cold plates is sealed to the encapsulation cover by the adhesive layer to define the perimeter of the coolant channel respectively positioned between each of the one or more cold plates and the encapsulation cover. 22 . The device package of claim 21 , wherein the second device is thermally coupled to the package lid via a TIM layer positioned between the second device and the package lid.

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