Optoelectronic semiconductor device

Abstract

An optoelectronic semiconductor device includes at least one control unit having a first main surface and a wiring structure. The optoelectronic semiconductor device further comprises at least one optoelectronic semiconductor chip electrically conductively connected to the control unit and a carrier having an assembly side. The control unit is arranged on the assembly side and the optoelectronic semiconductor chip is arranged on the first main surface. The wiring structure includes at least one connection point disposed on the first main surface and electrically conductively connected to the carrier. The at least one optoelectronic semiconductor chip may be a micro LED.

Description

[0001] An optoelectronic semiconductor device is described. In addition, a method of using the optoelectronic semiconductor device is described.

[0002] The object to be achieved is, in particular, to provide a highly efficient optoelectronic semiconductor component which can be produced at low cost and with short process chains.

[0003] This object is achieved by an optoelectronic semiconductor component having the features of independent claim 1 and a method having the features of independent claim 10. Advantageous embodiments and further developments are the subject matter of the respective dependent patent claims.

[0004] According to at least one embodiment of the optoelectronic semiconductor device, the optoelectronic semiconductor device includes at least one control unit having a first main surface and a wiring structure. The wiring structure is arranged, for example, at the first main surface. That is, the first main surface is at least partially formed by the wiring structure. The wiring structure may include conductive paths and other circuit elements, such as transistors and switches. The conductive elements of the wiring structure may be formed from a metal such as gold, copper or aluminum. The control unit may be formed by an integrated circuit. The maximum lateral dimension of the integrated circuit may be in the micrometer range, for example less than 500 μm. Viewed from the first main surface, the control unit may have a square shape with an edge length of between 100 μm and 300 μm. In such a case, the control unit is also referred to as a micro integrated circuit, or μIC for short. In particular, the μIC is characterized by a thickness of at most 50 μm.

[0005] According to at least one embodiment, the optoelectronic semiconductor component includes at least one optoelectronic semiconductor chip electrically conductively connected to a control unit. In particular, the optoelectronic semiconductor chip is driven and controlled by the control unit. The at least one optoelectronic semiconductor chip is preferably connected to the control unit via a wiring structure.

[0006] For example, exactly one optoelectronic semiconductor chip is assigned to exactly one control unit. It is also possible to assign more than one (for example three) semiconductor chips to one control unit. The semiconductor chips are, for example, light emitting diodes (LEDs), laser diodes or photodiodes.

[0007] For example, if three semiconductor chips in the form of LEDs are assigned to a control unit, each semiconductor chip can emit light in a different spectral range. One of the three semiconductor chips can emit light in the red spectral range, one can emit light in the green spectral range, and one can emit light in the blue spectral range. In this case, the semiconductor chips can be controlled by the control unit so that the optoelectronic semiconductor component can emit mixed light from these spectral ranges, for example, white light or light of essentially any color.

[0008] The wiring structure includes, for example, contact metal as a contact surface for at least one optoelectronic semiconductor chip. That is, the semiconductor chip can be electrically contacted with the contact metal. The contact metal may include a first region and a second region, to which the cathode and anode of the at least one optoelectronic semiconductor chip are connected, respectively. The contact metal may be formed from at least one metal such as gold, copper, and aluminum. The cathode and anode of the at least one optoelectronic semiconductor chip may be arranged on the same side of the semiconductor chip, for example, on the side facing the control unit. In this case, the semiconductor chip may be a flip chip. At least the cathode or anode may also be arranged on the side facing away from the control unit. In this case, the first region and / or the second region of the contact metal are connected to the cathode and / or the anode via conductor tracks. The conductor tracks may be bonding wires.

[0009] The maximum lateral dimension of the semiconductor chip can be below 100 μm. In this case, if the semiconductor chip is an LED, the semiconductor chip is also called a "micro-LED". In particular, a micro-LED can be considered as any light-emitting diode (LED) with particularly small dimensions - usually not a laser.

[0010] In particular, generally speaking (which may be considered a very important criterion besides the size) the growth substrate is removed from the micro-LEDs such that a typical height of such micro-LEDs is in the range of, for example, 1.5 μm to 10 μm.

[0011] In principle, a micro-LED does not necessarily have to have a rectangular emitting surface. For example, the LED may have an emitting surface wherein any lateral extent of the emitting surface in a plan view of the layers of the LED's layer stack is less than or equal to 100 μm or less than or equal to 70 μm.

[0012] For example, in the case of rectangular micro-LEDs, edge lengths of less than or equal to 70 μm or less than or equal to 50 μm (especially in the plan view of the layers of the layer stack) are often cited as criteria.

[0013] In most cases, such micro-LEDs are arranged on a wafer having a retaining structure that is non-destructively detachable for the micro-LEDs.

[0014] Micro-LEDs are currently being used, in particular, for displays. Micro-LEDs form pixels or sub-pixels and emit light of a defined color. The small pixel size and high density at close range make micro-LEDs particularly suitable for small, monolithic displays in AR applications, particularly data glasses. Furthermore, other applications such as the present optoelectronic semiconductor device are being developed. Further applications include, among others, the use of micro-LEDs in data communications or pixelated lighting applications.

[0015] Different ways of spelling micro-LED can be found in the relevant literature, such as μLED, μ-LED, uLED, u-LED or micro light-emitting diode.

[0016] For example, the semiconductor chip is an LED including an emitting surface. Considering the emitting surface, the emitting surface may have a rectangular shape with a length between 70 μm and 100 μm and a width between 40 μm and 70 μm. Furthermore, the height of the semiconductor chip measured parallel to the emitting surface may be, for example, between 1.5 μm and 10 μm.

[0017] According to at least one embodiment, an optoelectronic semiconductor component includes a carrier having an assembly side. The carrier can be a foil, in particular a transparent foil. A "transparent" element, as used herein and hereinafter, particularly means that the element is transparent to a human observer. For example, the carrier is formed using or from polyethylene terephthalate (PET).

[0018] According to at least one embodiment, the control unit is arranged on the assembly side, and the optoelectronic semiconductor chip is arranged on a first main surface of the control unit. In particular, when viewed from the assembly side, the control unit at least partially covers the carrier, and when viewed from the first main surface, the optoelectronic semiconductor chip at least partially covers the control unit.

[0019] According to at least one embodiment, at least one connection point is arranged on the first main surface. The at least one connection point is electrically conductively connected to the carrier. In particular, the at least one connection point is arranged adjacent to the optoelectronic semiconductor chip on the first main surface. That is, the optoelectronic semiconductor chip does not overlap the connection point when viewed from the first main surface. The at least one contact point is preferably formed from at least one metal such as gold, copper, and aluminum.

[0020] In particular, the connection point is conductively connected to the carrier, for example, via a contact structure. The contact structure preferably comprises at least one metal. For example, the contact structure is formed from solder or a conductive pillar comprising, for example, copper. Alternatively, the contact structure is formed from a conductive adhesive. The contact structure may also comprise a conductive pillar (e.g., formed from copper or nanowires), or be formed from electroplated or printed interconnects.

[0021] In at least one embodiment, an optoelectronic semiconductor device includes at least one control unit having a first main surface and a wiring structure. The optoelectronic semiconductor device further includes at least one optoelectronic semiconductor chip conductively connected to the control unit and a carrier having an assembly side. The control unit is arranged on the assembly side, and the optoelectronic semiconductor chip is arranged on the first main surface. The wiring structure includes at least one connection point, which is arranged on the first main surface and conductively connected to the carrier.

[0022] The optoelectronic semiconductor device described herein is based, inter alia, on the following technical considerations. In order to form a dynamic transparent display, for example for pixelated car taillights or pixelated interior lights, it is preferred to form a driver in the foil to increase the functionality of the foil. Therefore, a separate control unit for each light point is a flexible solution. However, such an arrangement results in high costs during manufacturing. The method of combining a control unit and an optoelectronic semiconductor chip usually involves forming a through-hole passing through the control unit, which is expensive. In other methods, the optoelectronic semiconductor chip is arranged next to the control unit so that the semiconductor chip does not partially cover the control unit. However, in this arrangement, the optoelectronic semiconductor device has a larger footprint.

[0023] The optoelectronic semiconductor device described herein utilizes the concept of arranging the optoelectronic semiconductor device and connection points for the control unit and / or the optoelectronic semiconductor device together on the first main side of the control unit. This arrangement reduces the footprint of the optoelectronic semiconductor device to essentially the footprint of the control unit, and eliminates the need for vias through the control unit. Furthermore, the semiconductor device described herein can be produced at low cost. In particular, short process chains and high production yields can be achieved.

[0024] According to at least one embodiment, the optoelectronic semiconductor chip is arranged between the carrier and the control unit, and the optoelectronic semiconductor chip is only directly connected to the control unit. For example, the optoelectronic semiconductor chip is directly mechanically and / or electrically connected to the control unit. In particular, the first main side of the control unit faces the assembly side of the carrier. Preferably, there is a gap between the optoelectronic semiconductor chip and the carrier. That is, the optoelectronic semiconductor chip does not contact the carrier. However, for example, a transparent filling material may be between the optoelectronic semiconductor chip and the carrier. Transparent here can mean that the filling material is also transparent to the light generated in the optoelectronic semiconductor chip. In this case, if at least one semiconductor chip is an LED or a laser diode, the emission direction of the light generated during operation of the semiconductor chip passes through the carrier.

[0025] According to at least one embodiment, the control unit includes a metallization layer on a second main surface opposite the first main surface. The metallization layer can serve as a light shielding layer. In addition, the metallization can form a reflector for light generated by the at least one optoelectronic semiconductor chip during operation. The metallization layer can include at least one metal, such as gold, silver, palladium, or copper. In particular, the metallization layer blocks and / or reflects light generated by the at least one optoelectronic semiconductor chip during operation at the second main surface of the control unit. In other words, optical and / or electrical crosstalk between other control units of the optoelectronic device or other optoelectronic semiconductor devices can be advantageously reduced.

[0026] Additionally or alternatively, the control unit may include an absorption element (such as a black resist) or a dielectric mirror (such as a distributed Bragg reflector) at the second main surface. The absorption element may be formed from a material that absorbs light emitted by the at least one optoelectronic semiconductor chip during operation. The absorption element and / or the dielectric mirror may reduce optical and / or electrical crosstalk.

[0027] According to at least one embodiment, the control unit includes traces of a test structure, which are accessible at at least one surface of the control unit. In particular, a side surface of the control unit is a surface connecting the first main surface and the second main surface. The traces of the test structure are preferably conductively connected to the wiring structure of the control unit. The traces of the test structure are, for example, formed from the same material as the wiring structure. In particular, the wiring structure and the traces of the test structure are, for example, formed as one piece in a common process. For example, the traces of the test structure are exposed at at least one side surface.

[0028] According to at least one embodiment, the wiring structure comprises a top layer and an intermediate layer forming at least a portion of the first main side, wherein the traces of the test structure are present in the top layer and / or the intermediate layer. For example, the traces of the test structure in the top layer comprise a different material than the traces of the test structure in the intermediate layer. In particular, the intermediate layer is formed between the first main surface and the substrate of the control unit. The substrate can be a semiconductor material such as silicon. In particular, the substrate is present on the side of the wiring structure opposite to the first main surface of the control unit.

[0029] According to at least one embodiment, during operation of the optoelectronic semiconductor device, the first connection point of the wiring structure provides a power supply contact, and the second connection point of the wiring structure provides a ground contact. The first and second connection points are arranged near opposite corners of the control unit, as viewed from the first main surface. For example, the control unit may have a rectangular shape, as viewed from the first main surface. In this case, for example, the first connection point is arranged near the upper right corner, and the second connection point is arranged near the lower left corner.

[0030] According to at least one embodiment, the carrier includes a conductive structure on the assembly side. The conductive structure is, for example, a metal mesh. The conductive structure preferably comprises at least one metal and is preferably formed of copper. The carrier is formed, for example, from a transparent material. The conductive structure, i.e., the metal mesh, is formed from such thin wires that the carrier appears transparent overall.

[0031] According to at least one embodiment, the control unit is arranged on the conductive structure, and the conductive structure is conductively connected to the wiring structure. For example, the conductive connection between the conductive structure and the wiring structure is formed by a contact structure.

[0032] According to at least one embodiment, an optoelectronic semiconductor device includes a plurality of semiconductor chips and a plurality of control units on a carrier, wherein at least one semiconductor chip is assigned to each control unit. The conductive structure includes a first conductive area and a second conductive area electrically isolated from each other. All first connection points are conductively connected to the first conductive area, and all second connection points are conductively connected to the second conductive area. In particular, a common power supply is thus supplied to all control units via the first conductive area. In the same manner, a common contact is supplied to all control units via the second conductive area. The isolation of the first conductive area and the second conductive area is achieved, for example, by gaps in the conductive structure. Alternatively, the grid can be oxidized in certain areas to achieve the isolation of the first conductive area and the second conductive area.

[0033] According to at least one embodiment, each control unit includes a third connection point and a fourth connection point, wherein at least some of the plurality of control units are connected in series via the third connection point and the fourth connection point. For example, the third connection point provides a data input port for the control unit, and the fourth connection point provides a data output port for the control unit. In particular, the third connection point and the fourth connection point are conductively connected via a third conductive region of the conductive structure, which is electrically isolated from the first conductive region and the second conductive region of the conductive structure. For example, a particular control unit on a carrier includes a third connection point that is conductively connected to a fourth connection point of an adjacent control unit on the carrier, and includes a fourth connection point that is conductively connected to a third connection point of another adjacent control unit on the carrier.

[0034] According to at least one embodiment, each control unit includes a fifth connection point and a sixth connection point, wherein the fifth connection points and the sixth connection points of different control units are connected in series. For example, the fifth connection point can provide a clock input port for the control unit, and the sixth connection point can provide a clock output port for the control unit. In particular, the fifth connection point and the sixth connection point are conductively connected via a fourth conductive region of the conductive structure, which is electrically isolated from the first conductive region to the third conductive region of the conductive structure.

[0035] Advantageously, due to the formation of the connection points and the division of the conductive structure into multiple conductive areas, a single conductive structure is sufficient to supply multiple control units. In particular, the conductive structure can comprise a single layer, preferably a single metal mesh layer. This means that electrical contacting of the control units, and therefore of the semiconductor devices, is relatively simple.

[0036] The conductive structure may also comprise a multilayer structure. In this case, at least two mesh layers may be stacked on top of each other. For example, the conductive structure may include multiple through-holes. At least some of the mesh layers may be connected via through-holes. In particular, each conductive area may be formed by a single mesh layer. Preferably, in this case, the through-holes are connected to connection points of the control unit.

[0037] According to at least one embodiment, a coating is disposed on a carrier, wherein the control unit and the semiconductor chip are embedded in the coating. For example, the coating is formed of a dielectric. Preferably, the coating is transparent. In particular, the coating is disposed on the assembly side of the carrier. The coating protects the at least one control unit and the at least one optoelectronic semiconductor chip from environmental influences. The coating may comprise at least one of the following materials: silicone, parylene, siloxane, epoxy, acrylate, or thermoplastic resin.

[0038] According to at least one embodiment, at least one control unit is at least partially covered by a passivation layer. For example, the passivation layer covers the control unit at all locations except for the area of ​​the first main surface where the connection points and / or the at least one optoelectronic semiconductor chip are arranged. Preferably, the at least one optoelectronic semiconductor chip is covered by the passivation layer on the surface of the first main surface that does not directly face the control unit. In other words, the emission surface of the semiconductor chip facing away from the first main surface and / or the side surfaces extending transversely to the emission surface can be covered by the passivation layer. In this case, the passivation layer is preferably transparent to the light generated by the semiconductor chip during operation. The passivation layer is formed, for example, of silicon nitride.

[0039] Furthermore, a method for producing an optoelectronic semiconductor component is specifically described. In particular, the optoelectronic semiconductor component described above can be produced by this method. That is, all features disclosed for the optoelectronic semiconductor component are also disclosed for the method, and vice versa.

[0040] According to at least one embodiment of a method for producing an optoelectronic semiconductor device, a control unit assembly is provided. In a subsequent step, a wiring structure is formed on a first main surface of the control unit assembly, wherein the wiring structure includes a test structure. The wiring structure is formed, for example, using a complementary metal oxide semiconductor process (CMOS process). In particular, connection points and contact metals are formed on the first main surface of the control unit assembly.

[0041] Subsequently, a plurality of optoelectronic semiconductor chips are arranged on the wiring structure so that the semiconductor chips are connected in series. In particular, the wiring structure includes connection points and contact metal. The connection points and contact metal are formed, for example, by electroplating or other suitable processes. For example, the optoelectronic semiconductor chips are arranged on the contact metal. Preferably, the semiconductor chips are arranged so that the connection points are freely accessible at the first main surface of the complex of the control unit. That is, from the first main surface, the semiconductor chips do not overlap with the connection points. Before arranging the semiconductor chips, an adhesive, such as an electrically insulating material, can be arranged on the wiring structure. The insulating material is preferably an adhesive. The insulating material can be applied by a spin coating process. In areas not covered by the semiconductor chips, the insulating material can be removed after applying the semiconductor chips. The removal of the insulating material is performed, for example, by oxygen plasma treatment.

[0042] According to at least one embodiment of the method, optoelectronic semiconductor chips and / or control units are tested by applying a test voltage to a test structure. The optoelectronic semiconductor chips are particularly connected in series via the test structure. The optoelectronic semiconductor chips and / or control units can be tested in parallel or in series. That is, all semiconductor chips and / or control units can be tested simultaneously or sequentially. For example, the optoelectronic semiconductor chips can be subjected to optical or electronic testing. For example, the test voltage is applied and the optical properties of the semiconductor chips are measured, for example, using a camera.

[0043] According to at least one embodiment of the method, an auxiliary carrier is placed on the second main surface of the composite body of the control unit, wherein the auxiliary carrier includes a release layer. The release layer can be formed from a material that can be removed by laser radiation. Preferably, the release layer is directly connected to the composite body of the control unit. The release layer can be removed by laser radiation in the ultraviolet spectral range.

[0044] Preferably, the auxiliary support is transparent to radiation in the ultraviolet spectral range.With such a support, the release layer can be effectively irradiated with laser radiation in the ultraviolet spectral range.

[0045] According to at least one embodiment of the method, the control unit complex is separated into a plurality of individual control units. In particular, each individual control unit comprises at least one optoelectronic semiconductor chip and at least one connection point, which is preferably freely accessible on the first main surface, i.e., not covered by any optoelectronic semiconductor chip. After separation, each individual control unit is mechanically connected to an auxiliary carrier. Separation is performed, for example, by laser singulation.

[0046] According to at least one embodiment of the method, at least one of the control units is applied to a carrier comprising a connection structure, the carrier being arranged at a first main surface of the control unit opposite to the auxiliary carrier. In the same method step or subsequently, the auxiliary carrier is removed, wherein the release layer is irradiated with laser radiation, in particular laser radiation in the ultraviolet spectral range. Preferably, the control unit applied to the carrier is electrically connected to the carrier during the application of the control unit. In this case, the contact structure can be arranged on the assembly side of the carrier, to which the control unit is electrically connected. The contact structure can be a solder. The transfer from the auxiliary carrier to the carrier involving laser radiation is also called laser induced forward transfer, abbreviated as LIFT. Further details of LIFT are given, for example, in the publication by FURON CHENG et al.: Mass transfer techniques for large-scale and high-density microLED arrays. Int. J. Extrem. Manuf. 4 (2022) 042005 (30 pp), the disclosure of which is incorporated herein by reference.

[0047] The transfer to the carrier is preferably carried out only for control units (respectively optoelectronic semiconductor chips) formed from the control unit assembly whose optical and / or electrical properties were within manufacturing tolerances during a previously performed test of the control unit assembly.

[0048] Advantageously, the method described herein includes a short process chain, resulting in low costs. Furthermore, high yields can be achieved when the optoelectronic semiconductor chips are tested before they are transferred to a carrier. Through this testing, only control units and / or optoelectronic semiconductor chips whose optical and / or electrical properties are within predeterminable manufacturing tolerances are transferred to a carrier and used in the finished optoelectronic semiconductor device. Furthermore, no intermediate carrier solution is required, as the control units are transferred directly from the auxiliary carrier to the carrier via laser-induced forward transfer.

[0049] According to at least one embodiment, the semiconductor chips are connected in series via a test structure before separation. During separation, the test structure is partially removed. For example, the test structure is removed from the separation trench formed during separation of the control unit assembly. However, the test structure remains accessible at the sides of the separation trench. In particular, these sides form the side surfaces of the control unit in the finished optoelectronic semiconductor device.

[0050] According to at least one embodiment of the method, the auxiliary carrier is applied by lamination. Advantageously, lamination is easier to implement than gluing or welding, requiring only adhesive tape and simple laminating equipment. The adhesive tape used for lamination can be selected to be suitable for the LIFT process. Specifically, the adhesive tape can be transparent to radiation in the UV range and can include a release layer. For example, the adhesive tape can serve as the auxiliary carrier.

[0051] According to at least one embodiment of the method, the control unit assembly is formed from a wafer, wherein the wafer includes a test area in which at least a portion of the test structure is located. During testing of the optoelectronic semiconductor chip, a test voltage is applied to the test area. For example, a needle array is applied to the test area. Advantageously, by testing the control units and / or optoelectronic semiconductor chips on the wafer, a large number of control units and / or optoelectronic semiconductor chips can be tested in a single process step.

[0052] According to at least one embodiment of the method, a metallization layer is applied to the second main surface of the control unit assembly before the auxiliary carrier is applied. In addition to or as an alternative to the metallization layer, an absorption element or a dielectric mirror can be applied to the second main surface. The metallization layer and / or the absorption element and / or the dielectric mirror can reduce optical and / or electrical crosstalk between the individual control units.

[0053] According to at least one embodiment of the method, the carrier comprises an electrically conductive structure, wherein during application of the control unit to the carrier, the control unit is electrically conductively connected to the electrically conductive structure. For example, a contact structure is arranged on the electrically conductive structure and is electrically connected to the electrically conductive structure.

[0054] According to at least one embodiment of the method, the control unit assembly includes a substrate between the wiring structure and the second main surface of the control unit. In one embodiment, during separation of the control unit assembly, a separation trench is created in the control unit assembly, extending from the first main surface of the control unit assembly into the substrate. Subsequently, an additional auxiliary carrier is placed on the first main surface of the control unit assembly, and after placement of the additional auxiliary carrier, the substrate is partially removed from the second main surface of the control unit assembly. The additional auxiliary carrier is, for example, an adhesive tape.

[0055] In an alternative embodiment, during the separation of the control unit assembly, the substrate is first partially removed, starting from the second main surface of the control unit assembly. Subsequently, a further auxiliary carrier is arranged on the first main surface of the control unit assembly, and after the arrangement of the further auxiliary carrier, a separation trench is produced in the control unit assembly, extending from the second main surface of the control unit assembly into the substrate.

[0056] According to at least one embodiment of the method for forming the separation trench, the separation trench is generated by laser radiation and / or plasma. Furthermore, the substrate is removed by grinding. For example, grinding is performed only on the central area of ​​the wafer, while the peripheral edge areas of the wafer are not ground. This grinding process is known as the TAIKO process and provides enhanced mechanical stability of the wafer.

[0057] According to at least one embodiment of the method, the control unit assembly includes a buried oxide layer buried in the substrate. The buried oxide layer may include or be made of silicon dioxide. During the separation of the control unit assembly, separation trenches are formed from the first main surface of the control unit assembly, which separation trenches terminate in the buried oxide layer. Alternatively or additionally, when removing the substrate, the removal of the substrate from the second main surface of the control unit assembly terminates in the buried oxide layer. That is, for both the formation of the separation trenches and the removal of the substrate, the buried oxide layer can be used as an indicator for controlling the grinding amount or the depth of the separation trenches.

[0058] Further advantages, advantageous embodiments, and further developments of the optoelectronic semiconductor device will become apparent from the following exemplary embodiments illustrated in conjunction with the schematic diagrams. Identical elements, elements of the same type, or elements having the same effect are provided with the same reference numerals in the figures. The figures and element proportions shown in the figures should not be considered true to scale. On the contrary, individual elements may be shown exaggerated for better representation and / or understanding.

[0059] In the attached figure:

[0060] FIG1 shows an exemplary embodiment of an optoelectronic semiconductor component described herein in a schematic cross-sectional view;

[0061] Figure 1B shows a schematic cross-sectional view of a portion of an exemplary embodiment of an optoelectronic semiconductor component described in detail herein;

[0062] Figure 2 and Figure 3 shows a plan view of an exemplary embodiment of an optoelectronic semiconductor device described herein;

[0063] Figures 4 to 10 shows positions in an exemplary embodiment of a method for producing an optoelectronic semiconductor component described herein;

[0064] Figures 11A to 12 A view showing an assembly of a control unit used in a method for producing an optoelectronic semiconductor component according to an exemplary embodiment;

[0065] Figures 13 to 19shows locations in an exemplary embodiment of a method for producing an optoelectronic semiconductor component described herein; and

[0066] Figures 20 to 25 Exemplary embodiments of optoelectronic devices described herein are shown from different perspectives.

[0067] Figure 1A A schematic cross-sectional view of a first exemplary embodiment of a semiconductor component 100 is shown. The semiconductor component 100 comprises a control unit 1 on a carrier 3. The control unit 1 comprises a substrate 15, which may be a semiconductor material such as silicon, and a wiring structure 4. The wiring structure 4 forms a first main surface 11 of the control unit 1, which faces an assembly side 30 of the carrier 3.

[0068] In the present exemplary embodiment, the carrier 3 is a foil, which is preferably transparent. The foil is made of PET. At the assembly side 30, the carrier 3 comprises an electrically conductive structure 31 formed by a metal mesh. The material of the metal mesh is preferably copper.

[0069] At least one optoelectronic semiconductor chip 2 is arranged on the first main surface 1. The optoelectronic semiconductor chip 2 is, for example, a light-emitting diode, or LED. The semiconductor chip 2 is electrically connected to the wiring structure 4 via metal contacts 21 a, 21 b. Specifically, the metal contacts 21 a, 21 b include a first region 21 a and a second region 21 b, the first region 21 a being electrically connected to, for example, the cathode of the semiconductor chip 2, and the second region 21 b being connected to, for example, the anode of the semiconductor chip 2. The first region 21 a and the second region 21 b of the contact metal are separated from each other by an insulating material 22. The insulating material 22 is, for example, an adhesive. Both the anode and cathode of the semiconductor chip 2 are formed on the side of the semiconductor chip 2 facing the control unit 1.

[0070] The semiconductor chip 2 is driven and / or controlled by the control unit 1. In addition to the semiconductor chip 2, connection points 40 are formed on the first main surface 11 of the control unit 1. The contact points 40 can be used to externally contact the control unit 1 and are thus electrically conductively connected to the wiring structure 4. As seen from the first main surface 11, the semiconductor chip 2 and the contact points 40 each partially cover the first main surface 11, but the semiconductor chip 2 does not cover any part of any connection point 40.

[0071] The contact metals 21a, 21b and the connection point 40 are each formed of at least one metal. In the present exemplary embodiment, the contact metals 21a, 21b and the connection point 40 are formed of gold.

[0072] The connection points 40 are electrically conductively connected to the electrically conductive structures 31 of the carrier 3 via contact structures 32. In the present example, the contact structures 32 are formed by solder bumps. A metallization layer 14 is arranged on a second main surface 12, which is opposite the first main surface 11. In the present exemplary embodiment, the metallization layer 14 is formed from one or more metals such as silver, aluminum, and gold. The metallization layer 14 can serve as a reflector or light shielding layer for light generated in the optoelectronic semiconductor chip 2 during operation. The traces of the test structure 5 are accessible at the side surface 13 of the control unit 1. The traces of the test structure 5 are electrically conductively connected to the wiring structure 4.

[0073] The control unit and the optoelectronic semiconductor chip 2 are embedded in a coating 9. The coating 9 is arranged on the assembly side 30 of the carrier 3. The coating 9 completely surrounds the control unit 1 and the semiconductor chip 2. The coating 9 thus protects the control unit 1 and the semiconductor chip 2 from environmental influences.

[0074] Figure 1B Shown as Figure 1A The dotted line A in the Figure 1A Detailed representation of a region of the optoelectronic semiconductor device 100. The wiring structure 4 comprises a top layer 41 and an intermediate layer 42. The top layer forms at least a portion of the first main surface 11. The intermediate layer 42 is arranged between the top layer 41 and the substrate 15. The conductive elements in the top layer 41 of the wiring structure 4 are preferably formed from gold, but other metals such as copper or aluminum can also be used. In the intermediate layer 42, the conductive elements of the wiring structure 4 are preferably formed from aluminum, but other metals such as copper can also be used. An electrical insulator is arranged between the conductive elements of the wiring structure 4, such as the conductive paths and circuit elements.

[0075] The wiring structure 4 comprises a plurality of conducting paths and circuit elements, such as transistors 45 . By means of the wiring structure 4 , the control unit 1 forms a circuit element which controls the optoelectronic semiconductor chip 2 .

[0076] Figure 2 FIG. 1 shows a plan view of a control unit 1 of an optoelectronic semiconductor device 100 according to a first exemplary embodiment. The control unit comprises six connection points 40, 401 to 406. The top layer 41 of the wiring structure 4 may be Figure 2 40 is shown as a solid line, while the intermediate layer 42 is shown as a dashed line. The first connection point 401 provides a power contact for the control unit and / or the optoelectronic semiconductor chip 2. The second connection point 402 provides a ground contact, the third connection point 403 provides a data input port, the fourth connection point 404 provides a data output port, the fifth connection point 405 provides a clock input port, and the sixth connection point 406 provides a clock output port for the control unit 1. By applying a voltage and / or current to the connection points 40, the optoelectronic semiconductor chip 2 can be operated.

[0077] The optoelectronic semiconductor chip 2 is an LED that emits light of different colors. For example, a first LED 2a emits in the red spectral range, a second LED 2b emits in the green spectral range, and a third LED 2c emits in the blue spectral range. By combining the light from these three LEDs, white light or light of essentially any color can be emitted.

[0078] Viewed from the first main surface 11, the control unit 1 has a square shape. In this exemplary embodiment, the control unit 1 has a dimension 18 of 250 μm in a first direction. The dimension 19 in a second direction perpendicular to the first direction can be the same. In the first direction, each optoelectronic semiconductor chip 2a, 2b, 2c can have a dimension 28 of 80 μm, and in the second reference direction, each optoelectronic semiconductor chip 2a, 2b, 2c can have a dimension 29 of 40 μm. In the first direction, each connection point 401 to 406 can have a dimension 408 of 50 μm, and in the second direction, each connection point 401 to 406 can have a dimension 409 of 50 μm. In the second direction 410, the space between two adjacent connection points 401 to 406 can be 50 μm.

[0079] Figure 3 An optoelectronic semiconductor component according to a second exemplary embodiment is shown in a plan view of the assembly side 30 of a carrier 3. On the assembly side 30, a plurality of control units 1 are arranged on an electrically conductive structure 31. Three optoelectronic semiconductor chips 2 are assigned to each control unit 1. Each control unit 1 with its semiconductor chips 2 corresponds to the control unit 1 with its semiconductor chips 2 described in conjunction with the first exemplary embodiment.

[0080] The conductive structure 31 is divided into two rows 311, 312 by a spacer 305. Each control unit 1 is conductively connected to the conductive structure 31. The conductive structure 31 is divided into individual conductive areas 301 to 304 in each row 311, 312. The first conductive area 301 of each row 311, 312 is conductively connected to all first connection points 401 in that row 311, 312. In other words, the first conductive area 301 of each row 311, 312 forms a common power contact for all control units 1 in that row 311, 312. In each row 311, 312, all second connection points 402 are conductively connected to the second conductive area 302, which forms a common ground contact for all control units 1 in that row 311, 312. The third conductive area 303 of each row 311, 312 forms connections that connect the data input connection points 403 and the data output connection points 404 of the different control units in that row 311, 312 to each other. The control units 1 in a row 311, 312 are connected in series via the second conductive region 303. The same applies to the fourth conductive region 304 and the fifth and sixth connection points 405, 406, respectively. The conductive regions 301 to 304 are electrically isolated from one another by spacers 305. Spacers 305 can be gaps in the conductive structure 31.

[0081] Figure 4 A schematic cross-sectional view shows a first position of a method for producing an optoelectronic semiconductor device 100 according to an exemplary embodiment. A control unit assembly 6 is provided at the first position. The control unit assembly 6 includes a first main surface 61 and a second main surface 62 opposite the first main surface 61. The control unit assembly 6 includes a substrate 15 on which a wiring structure 4 is formed. The wiring structure is formed, for example, by a CMOS process. Connection points 40 are formed on the first main surface 61 of the control unit assembly. The connection points 40 are formed, for example, by electroplating. The control unit assembly 6 includes a test structure 5 and a test area 53. The materials of the substrate 15, the wiring structure 4, the test structure 5, and the connection points 40 can be the same as those described in conjunction with the first embodiment of the optoelectronic device 100.

[0082] In the second stage of the method, the electrically insulating material 22 is arranged on the first main surface 61 of the composite body of the control unit ( Figure 5 The insulating material 22 may be an adhesive. The insulating material 22 completely covers the first major surface 61. The insulating material may be applied by a spin coating process.

[0083] In a third step of the method, the optoelectronic semiconductor chip 2 is arranged on the first main surface 61 ( Figure 6The semiconductor chips 2 are in contact with the contact metals 21 a, 21 b. As described in conjunction with the first exemplary embodiment of the optoelectronic semiconductor device, the different regions of the contact metals 21 a, 21 b are electrically isolated from one another and form the anode and cathode of each semiconductor chip 2. In regions of the first main surface 61 where no semiconductor chips 2 are present, the electrically insulating material 22 is removed. For example, the insulating material 22 is removed using an oxygen plasma. The optoelectronic semiconductor chips 2 are connected in series via the test structure 5.

[0084] like Figure 6 As shown, for testing the optoelectronic semiconductor chip 2, a needle array 54 is applied to the test area 53. A voltage is supplied to the test structure 5 via the needle array 54. This voltage operates the optoelectronic semiconductor chip 2 and the optical and / or electrical properties of the optoelectronic semiconductor chip 2 can be tested.

[0085] In another process step, the substrate can be ground from the second major surface 62 ( Figure 7 ). In particular, the substrate 15 is ground in the central region 65, while the overall thickness of the substrate 15 remains unchanged in the edge region 66. Before grinding the substrate 15, the control unit assembly 6 is preferably arranged on a further auxiliary carrier 8. The auxiliary carrier 8 can be an adhesive tape.

[0086] In a further step of the method, a metallization layer 14 is applied to the second main surface 62 ( Figure 8 The metallization layer 14 may comprise the same materials as described in conjunction with the first exemplary embodiment of the optoelectronic semiconductor component 100 and provide the same effects.

[0087] exist Figure 9 In the method shown, the additional auxiliary carrier 8 is removed and the control unit assembly 6 is applied to the auxiliary carrier 7 including the release layer 71. The release layer 71 directly adjoins the metallization layer 14. The release layer 71 can be removed by laser radiation. In particular, the auxiliary carrier 7 is a so-called LIFT carrier.

[0088] exist Figure 9 In the embodiment of the present invention, the control unit complex 6 is separated into individual control units 1. Separation trenches 64 are formed through the test structure 5. The test structure 5 is accessible from the sides of the separation trenches 64. Separation is performed, for example, by laser singulation. After separation, each control unit 1 includes at least one semiconductor chip 2 and at least one connection point 40.

[0089] In a further step of the method, the control unit 1 comprising the optoelectronic semiconductor chip 2 is transferred to a carrier 3 which comprises, on the assembly side 30, the electrically conductive areas 31 and the contact structures 32 ( Figure 10The transfer is performed by removing the release layer 71 by laser radiation 72 in the ultraviolet spectral range, while the control unit is brought close to or in contact with the carrier 3. The carrier 3, the conductive regions 31, and the contact structures 32 can comprise the same materials and provide the same effects as described in conjunction with the first exemplary embodiment of the optoelectronic semiconductor component 100. Preferably, only control units 1 (respectively semiconductor chips 2) whose electrical and / or optical properties are within predetermined manufacturing ranges during testing are transferred.

[0090] Figure 11A A plan view of a control unit complex 6 is shown, which can be used in conjunction with Figures 4 to 10 The method discussed. The complex 6 of the control unit is a wafer 63. The test area 53 is formed at the edge of the wafer 63. Figure 11A , a needle array 54 is shown being applied to a test area 53 .

[0091] Figure 11B Shown as Figure 11A Indicated by B Figure 11A As shown, the individual control units 1 formed in the control unit complex 6 are electrically conductively connected via the test structure 5 and are also electrically conductively connected to the test area 53 via the test structure 5. In particular, the control units 1 in the control unit complex 6 can be connected to, for example, a reference Figure 2 The control unit 1 described in conjunction with the first exemplary embodiment of semiconductor device 100 is identical. A needle array 54 is used for the first to fourth test connection points 501, 502, 503, 504, which are electrically connected to the first to fourth connection points 401, 402, 403, 404 of a row 601, 602 of the first control unit 1 via a wiring structure 4. All other control units 1 in a control unit complex 6 within a row 601, 602 are connected in series via the wiring structure 4 and the test structure 5. Thus, by using the needle array, an entire row of control units 1 and / or the semiconductor chips 2 associated with each control unit 1 can be tested simultaneously.

[0092] Figure 12 A detailed representation of the separation of the complex 6 of control units into individual control units 1 is shown. The complex 6 of control units can be Figure 11B The complex shown in . Figure 12 As shown, separation trenches 64 extend through the test structure, wherein the test structure is at least partially removed.

[0093] Figures 13 to 19 A schematic cross-sectional view illustrating in detail the method for separating the complex 6 of the control unit is shown. Figure 13In the embodiment, the composite body 6 of the control unit may comprise a buried oxide layer 16 buried in the substrate 15. Other aspects of the composite body 6 of the control unit are similar to those of, for example, Figure 6 The same complex as shown in . Figure 13 compared to, Figure 14 The control unit complex shown does not include a buried oxide layer.

[0094] Figure 15 The method step of removing a portion of the connection structure 40 by laser radiation 72 is shown. The material of the connection point 40 is removed in the region where the separation trench 64 will subsequently be formed. Figure 16 As shown, separation trenches 64 are formed. The separation trenches are formed starting from the first main surface 61 and ending at the buried oxide layer 16. The separation trenches are formed, for example, by laser cutting or plasma cutting.

[0095] In a subsequent process step, a passivation layer 91 is applied to the control unit assembly ( Figure 17 ). A passivation layer 91 is applied to the first main surface 61. The passivation layer 91 may include a silicon nitride material. The passivation layer 91 covers the first main surface 61 and the surface of the semiconductor chip 2 facing away from the first main surface 61. The passivation layer 91 also covers the side surfaces of the separation trenches 64. The passivation layer 91 is removed in the openings 92. In these openings 92, the connection points 40 are freely accessible.

[0096] Subsequently, a further auxiliary carrier 8 is applied to the first main surface 61 ( Figure 18 ). The other auxiliary carrier 8 can be a tape. Figure 19 As shown, in a subsequent process step, singulation is performed by grinding the substrate 15 starting from the second main surface 62 of the control unit composite. The grinding ends in the buried oxide layer 16. The buried oxide layer thus serves as a predetermined end point for both the formation of the separation trenches 64 and the grinding of the substrate 15, and thus for the final thickness of the control units 1. By grinding, the control unit composite 6 is separated into the individual control units 1, which are mechanically connected via a further auxiliary carrier 8. Figure 19 The control unit 1 can then be transferred to an auxiliary carrier 7, e.g. Figure 9 shown.

[0097] Figure 20 1 , the contact structure 32 is formed by an electrically conductive stud, for example, of copper. The electrically conductive stud can be bonded with solder.

[0098] Figure 21A schematic cross-sectional view shows another exemplary embodiment of an optoelectronic semiconductor component 100 in which the contact structure 32 is formed by nanowires. In addition, the space between the assembly side 30 of the control unit 1 and the first main surface 11 is filled with glue 33. The glue 33 is preferably electrically insulating. The mechanical stability of the control unit 1 on the carrier 3 is ensured by the glue 33. In all other respects, Figure 21 Example embodiments of Figure 20 The exemplary embodiments are the same.

[0099] Figure 22 A further exemplary embodiment of an optoelectronic semiconductor component 100 is shown in a schematic sectional illustration. Figure 20 and Figure 21 In contrast to the exemplary embodiment of FIG. 1 , first main surface 11 of control unit 1 does not face carrier 3. Glue 33 is arranged between control unit 1 and carrier 3, and control unit 1 is fixed to carrier 3 by glue 33. To establish electrical contact between connection point 40 and conductive structure 31, interconnection 34 is formed. For example, interconnection 34 is formed by printing or electroplating.

[0100] Figure 23 A further exemplary embodiment of an optoelectronic semiconductor component 100 is shown in a schematic cross-sectional view. Compared to the exemplary embodiment of FIG. 1 , Figure 23 The optoelectronic semiconductor chip 2 of the embodiment of the present invention does not have both a cathode and an anode on the same side (i.e., the side facing the first main surface 11 of the control unit 1). For example, the cathode of the semiconductor chip 2 is formed on the side facing away from the control unit 1. The first region 21a of the contact metal 21a, 21b is electrically connected to the cathode of the semiconductor chip 2 via a conductor track 21c. The space between the conductor track 21c and the first main surface 11 is filled with an electrically insulating material 22.

[0101] Figure 24 1 shows a plan view of the first main surface 11 of the control unit 1 according to an exemplary embodiment. Figure 2 compared to, Figure 24 The control unit 1 comprises an additional connection point 401c providing a power contact for the control unit 1. The connection point 401 in this example only provides a power contact for the optoelectronic semiconductor chips 2a, 2b, 2c.

[0102] Figure 25 1 shows a plan view of the first main surface 11 of the control unit 1 according to an exemplary embodiment. Figure 2 In contrast, only one semiconductor chip 2 is assigned to the control unit 1 .

[0103] The invention is not limited to the exemplary embodiments based on its description. On the contrary, the invention covers any novel feature and any combination of features, which in particular includes a combination of features in the patent claims, even if this feature or combination itself is not explicitly mentioned in the patent claims or the exemplary embodiments.

[0104] This patent application claims the priority of German patent application 102023101808.6, the disclosure content of which is incorporated herein by reference.

[0105] Reference Mark

[0106] 100 Optoelectronic semiconductor devices

[0107] 1 Control unit

[0108] 11 First main surface of the control unit

[0109] 12 Second main surface of the control unit

[0110] 13 Side surface of the control unit

[0111] 14 Metallization layer

[0112] 15 substrate

[0113] 16 Buried oxide layer

[0114] 18 Dimensions in the first direction

[0115] 19 Dimensions in the second direction

[0116] 2, 2a, 2b, 2c optoelectronic semiconductor chips 21a, 21b contact metal

[0117] 21c Conductor Track

[0118] 22 Insulation Materials

[0119] 28 Dimensions in the first direction

[0120] 29 Dimensions in the second direction

[0121] 3 carriers

[0122] 30 Assembly side of the carrier

[0123] 31 Conductive structure

[0124] 32 Contact structure

[0125] 33 Adhesive

[0126] 34 Interconnection 301-304 first conductive region to fourth conductive region 305 Isolation

[0127] 311, 312 conductive structure rows

[0128] 4 Wiring Structure

[0129] 40 connection points

[0130] 41 Top Floor

[0131] 42 Middle Layer

[0132] 45 transistors

[0133] 401-406 First connection point to sixth connection point

[0134] 408 Dimension in the first direction

[0135] 409 Dimensions in the second direction

[0136] 410 Distance in the second direction

[0137] 5 Test Structure

[0138] 53 test area

[0139] 54-pin array

[0140] 501-504 first test connection point to fourth test connection point

[0141] 6 Complex of control units

[0142] 61 First major surface of the composite

[0143] 62 Second major surface of the composite

[0144] 63 chips

[0145] 64 separation line

[0146] 65 Central Area

[0147] 66 Marginal Area

[0148] Rows 601-603

[0149] 7 Auxiliary carrier

[0150] 71 release layer

[0151] 72 Laser radiation

[0152] 8 Additional auxiliary vectors

[0153] 9 Coating

[0154] 91 passivation layer

[0155] 92 Open your mouth.

Claims

1. An optoelectronic semiconductor device (100), comprising at least one control unit (1), said at least one control unit (1) having a first main surface (11) and a wiring structure (4), at least one optoelectronic semiconductor chip (2) which is electrically conductively connected to the control unit (1), and a carrier (3) having an assembly side (30), in the control unit (1) is arranged on the assembly side (30) and the optoelectronic semiconductor chip (2) is arranged on the first main surface (11), - the wiring structure (4) comprises at least one connection point (40), - all connection points (40) are arranged exclusively on the first main surface (11) and are electrically conductively connected to the carrier (3), - the control unit (1) comprises traces of a test structure (5), said traces being accessible at at least one side surface (13) of the control unit (1), and - The traces of the test structure (5) are electrically conductively connected to the wiring structure (4) of the control unit (1).

2. The optoelectronic semiconductor device (100) according to claim 1, wherein - the optoelectronic semiconductor chip (2) is arranged between the carrier (3) and the control unit (1), and The optoelectronic semiconductor chip (2) is directly connected only to the control unit (1).

3. The optoelectronic semiconductor component (100) according to claim 1, wherein The control unit (1) comprises a metallization layer (14) at a second main surface (12) opposite to the first main surface (11).

4. The optoelectronic semiconductor component (100) according to claim 1, wherein - the wiring structure (4) comprises a top layer (41) and at least one intermediate layer (42), the top layer (41) forming at least a part of the first main side (11), and - traces of the test structure (5) are present in at least one of the top layer (41) and the middle layer (42).

5. The optoelectronic semiconductor component (100) according to claim 1, wherein During operation - a first connection point (401) of the wiring structure (4) provides a power contact, - the second connection point (402) of the wiring structure (4) provides a ground contact, and - the first connection point (401) and the second connection point (402) are arranged near opposite corners of the control unit (1) as seen from the first main surface (11).

6. The optoelectronic semiconductor component (100) according to claim 1, wherein - the carrier (3) comprises an electrically conductive structure (31) at the assembly side (30), - the control unit (1) is arranged on the conductive structure (31), and - The conductive structure (31) is conductively connected to the wiring structure (4).

7. The optoelectronic semiconductor component (100) according to claim 5, wherein The optoelectronic semiconductor component (100) comprises a plurality of semiconductor chips (2) and a plurality of control units (1), - at least one semiconductor chip (2) is assigned to each control unit (1), - the conductive structure (31) comprises a first conductive region (311) and a second conductive region (312) electrically isolated from each other, and - All first connection points (401) are conductively connected to the first conductive area (301), and all second connection points (402) are conductively connected to the second conductive area (302).

8. The optoelectronic semiconductor device (100) according to claim 7, wherein - each control unit (1) comprises a third connection point (403) and a fourth connection point (404), - At least some of the plurality of control units (1) are connected in series via the third connection point (403) and the fourth connection point (404).

9. The optoelectronic semiconductor component (100) according to claim 1, wherein The at least one optoelectronic semiconductor chip (2) is a micro-LED.

10. A method for producing an optoelectronic semiconductor device (100), comprising the following steps: - providing a complex of control units (6), - forming a wiring structure (4) at a first main surface (61) of the complex of the control unit, wherein the wiring structure (4) comprises a test structure (5), - applying a plurality of optoelectronic semiconductor chips (2) to the wiring structure (4) such that the semiconductor chips (2) are connected in series, - testing the optoelectronic semiconductor chip (2) by applying a test voltage to the test structure (5), - applying an auxiliary carrier (7) on the second main surface (62) of the composite body of the control unit, wherein the auxiliary carrier (7) comprises a release layer (71), - separating the complex of control units (6) into a plurality of individual control units (1), each mechanically connected to the auxiliary carrier (7), - applying at least one of the control units (1) to a carrier (3), wherein the carrier (3) is arranged at a first main surface (11) of the control unit opposite the auxiliary carrier (7), - Removing the auxiliary carrier (7), wherein the release layer (71) is irradiated with laser radiation (72).

11. The method according to claim 10, wherein - before separation, the semiconductor chips (2) are connected in series by means of the test structure (50), and - During separation, the test structure (50) is partially removed.

12. The method according to claim 10 or 11, wherein: The auxiliary carrier (7) is applied by a lamination process.

13. The method according to claim 10, wherein - the control unit complex (61) is formed by a wafer (63), - said wafer (63) comprises a test area (53), - at least a portion of the test structure (5) is located in the test area (53) - during testing of the optoelectronic semiconductor chip (1), applying the test voltage to the test region (53).

14. The method according to claim 10, wherein: Before the auxiliary carrier (7) is applied, a metallization layer (13) is applied to the second main surface (62) of the control unit composite.

15. The method according to claim 10, wherein - the carrier (3) comprises a conductive structure (31) During application of the control unit (1) to the carrier (3), the control unit (1) is electrically conductively connected to the electrically conductive structure (31).

16. The method according to claim 10, wherein The control unit complex (6) comprises a substrate (15) between the wiring structure (4) and the second main surface (62) of the control unit complex, and During separation of the complex (6) of the control unit - producing a separation trench (64) in the control unit composite (6), the separation trench (64) extending from the first main surface (61) of the control unit composite into the substrate (15) or completely through the control unit composite (6) from the second main surface (62) of the control unit composite, - arranging a further auxiliary carrier (8) at the first main surface (61) of the control unit complex, and - Partially removing the substrate (15) starting from the second main surface (62) of the control unit composite.

17. The method according to claim 16, wherein - the separation trenches (64) are generated by means of laser radiation (72) and / or plasma, and - Removal of the substrate (15) by grinding.

18. The method according to claim 16 or 17, wherein - the control unit complex (6) comprises a buried oxide layer (16) buried in the substrate (15), - a separation trench (64) formed from the first main surface (61) of the control unit complex terminates in the buried oxide layer (16), and / or - the removal of the substrate (15) starting from the second main surface (62) of the control unit composite ends at the buried oxide layer (16).

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