Manufacturing method of field effect transistor

Abstract

The invention discloses a manufacturing method of a field effect transistor. A p-type impurity concentration in a lower layer of a p-type trench is appropriately adjusted. The method for manufacturing the field effect transistor includes: a body layer forming step of forming a p-type body layer by ion implantation of a p-type impurity; a trench forming step of forming a trench on the upper surface of the semiconductor substrate; a p-type trench lower layer forming step for forming a p-type trench lower layer on the lower side of the trench by implanting a p-type impurity into the bottom surface of the trench in a state where the upper surface of the semiconductor substrate is covered with an ion implantation mask; and a gate electrode forming step of forming a gate insulating film and a gate electrode in the trench. In the p-type trench lower layer forming step, a p-type impurity is injected at a higher concentration than in the body layer forming step.

Description

Technical Field

[0001] (Cross-reference of related applications)

[0002] This application is a related application of Japanese patent application No. 2023-027494 filed on February 24, 2023, claims priority based on the Japanese patent application, and cites all the contents described in the Japanese patent application as the contents constituting the present specification.

[0003] The technology disclosed in this specification relates to a method for manufacturing a field-effect transistor. Background Art

[0004] Japanese Patent Publication No. 2009-194065 discloses a trench-gated field-effect transistor. The field-effect transistor comprises a plurality of p-type deep layers protruding downward from a body layer. Each p-type deep layer extends so as to intersect a trench when the semiconductor substrate is viewed from above. The plurality of p-type deep layers are arranged with spacers spaced apart in their width direction. An n-type deep layer is disposed within each spacer. Each p-type deep layer and each n-type deep layer extend from the body layer to a position below the bottom surface of the trench. An n-type drift layer is disposed below the p-type deep layer and the n-type deep layer. This structure can improve the withstand voltage of the field-effect transistor. Summary of the Invention

[0005] In a field-effect transistor having a deep p-type layer and a deep n-type layer, providing a p-layer extending along the trench below the trench (hereinafter referred to as the p-type trench lower layer) can reduce the feedback capacitance of the field-effect transistor and enable high-speed switching. This specification proposes a technique for effectively reducing the feedback capacitance of the field-effect transistor by appropriately adjusting the p-type impurity concentration of the p-type trench lower layer during the field-effect transistor manufacturing process.

[0006] The method for manufacturing a field-effect transistor disclosed in this specification includes a semiconductor substrate preparation step, a body layer formation step, a trench formation step, a p-type trench lower layer formation step, and a gate electrode formation step. In the semiconductor substrate preparation step, a semiconductor substrate comprising an n-type drift layer, multiple p-type deep layers, and multiple n-type deep layers is prepared. Multiple p-type deep layers and multiple n-type deep layers are arranged above the n-type drift layer. When the semiconductor substrate is viewed from above, each p-type deep layer extends along a first direction and is arranged with spacers spaced apart in a second direction orthogonal to the first direction. Each n-type deep layer is arranged within a corresponding spacer. A semiconductor substrate is prepared in which the n-type deep layer has a higher n-type impurity concentration than the n-type drift layer. In the body layer formation step, p-type impurities are ion-implanted into the semiconductor substrate to form the multiple p-type deep layers and a p-type body layer that contacts the multiple n-type deep layers from above. In the trench formation step, a trench is formed on the upper surface of the semiconductor substrate. Here, the trench is formed in such a manner that, when viewing the semiconductor substrate from above, the trench intersects the plurality of p-type deep layers, the trench penetrates the body layer, and the lower end of the trench is located above the lower ends of the plurality of p-type deep layers. In the p-type trench lower layer forming step, p-type impurities are implanted into the bottom surface of the trench while the upper surface of the semiconductor substrate is covered with an ion implantation mask, thereby forming a p-type trench lower layer on the lower side of the trench that is connected to the p-type deep layers. In the gate electrode forming step, a gate insulating film and a gate electrode are formed within the trench. In the p-type trench lower layer forming step, p-type impurities are implanted at a higher concentration than in the body layer forming step.

[0007] Furthermore, the p-type trench lower layer may be formed at a position in contact with the bottom surface of the trench or at a position away from the bottom surface of the trench (ie, at a position deeper than the bottom surface of the trench).

[0008] In this manufacturing method, since ion implantation of the body layer and ion implantation of the p-type trench lower layer are performed in separate steps, the p-type impurity concentration in the p-type trench lower layer can be controlled independently of the p-type impurity concentration in the body layer. In the p-type trench lower layer formation step, p-type impurities are implanted at a higher concentration than in the body layer formation step. Therefore, when a voltage is applied to a field-effect transistor manufactured using this manufacturing method, the p-type trench lower layer is less likely to be depleted. Consequently, the feedback capacitance of the field-effect transistor can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional perspective view of the MOSFET 10 (a view showing an xz cross section excluding the p-type deep layer 36 ).

[0010] Figure 2It is a cross-sectional perspective view of the MOSFET 10 with the source electrode 22 and the interlayer insulating film 20 omitted (a view showing an xz cross section not including the p-type deep layer 36 ).

[0011] Figure 3 1 is an enlarged xy cross-section of the MOSFET 10 including the p-type trench lower layer 35 , the p-type deep layer 36 , and the n-type deep layer 37 , and is an enlarged cross-sectional view of the MOSFET 10 showing the arrangement of the p-type trench lower layer 35 , the p-type deep layer 36 , and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above.

[0012] Figure 4 It is an enlarged xy cross-section of the MOSFET 10 including the trench 14 , the p-type deep layer 36 , and the n-type deep layer 37 , and is an enlarged cross-sectional view of the MOSFET 10 showing the arrangement of the trench 14 , the p-type deep layer 36 , and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above.

[0013] Figure 5 It is an enlarged yz cross-sectional view of the MOSFET 10 including the p-type deep layer 36 and the n-type deep layer 37 .

[0014] Figure 6 It is a cross-sectional perspective view of the MOSFET 10 (a view showing an xz cross section including the p-type deep layer 36 ).

[0015] Figure 7 3 is a cross-sectional view showing the distribution of the non-depleted region in the p-type trench lower layer 35 .

[0016] Figure 8 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0017] Figure 9 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0018] Figure 10 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0019] Figure 11 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0020] Figure 12 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0021] Figure 13 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0022] Figure 14 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0023] Figure 15 It is an explanatory diagram of a method for manufacturing MOSFET 10 .

[0024] Figure 16 It is an explanatory diagram of a manufacturing method of a modification example.

[0025] Figure 17 The MOSFET of the first modification example is Figure 1 Corresponding cutaway perspective view.

[0026] Figure 18 The MOSFET of the second modification example is Figure 1 Corresponding cutaway perspective view.

[0027] Figure 19 The MOSFET of the third modification example is Figure 1 Corresponding cutaway perspective view.

[0028] Figure 20 The fourth modified example of MOSFET and Figure 1 Corresponding cutaway perspective view.

[0029] Figure 21 The MOSFET of the fifth modification example is Figure 1 Corresponding cutaway perspective view.

[0030] Figure 22 The MOSFET of the sixth modification example is Figure 1 Corresponding cutaway perspective view.

[0031] Figure 23 The MOSFET of the seventh modification example is Figure 1 Corresponding cutaway perspective view.

[0032] Figure 24 The MOSFET of the eighth modification example is Figure 1 Corresponding cutaway perspective view.

[0033] Figure 25 The MOSFET of the ninth modification example is Figure 6 Corresponding cutaway perspective view. DETAILED DESCRIPTION

[0034] In the manufacturing method of one example disclosed in this specification, the ion implantation depth in the p-type trench lower layer forming step may be shallower than the ion implantation depth in the body layer forming step.

[0035] Alternatively, multiple ion implantations may be performed while varying the ion implantation depth during the p-type trench lower layer formation step. In this case, the "ion implantation depth during the p-type trench lower layer formation step" refers to the deepest ion implantation depth during the p-type trench lower layer formation step. Alternatively, multiple ion implantations may be performed while varying the ion implantation depth during the bulk layer formation step. In this case, the "ion implantation depth during the bulk layer formation step" refers to the deepest ion implantation depth during the bulk layer formation step.

[0036] According to this configuration, a thin p-type trench lower layer can be formed, and the breakdown voltage of the field effect transistor can be improved.

[0037] In one example of the manufacturing method disclosed in this specification, in the p-type trench lower layer forming step, the p-type trench lower layer may be formed so that its lower end is located above lower ends of the n-type deep layers.

[0038] According to this configuration, the depletion layer is less likely to extend from the p-type trench lower layer to the drift layer when the field effect transistor is in the on state, and thus the on resistance of the field effect transistor can be reduced.

[0039] In one example of the manufacturing method disclosed in this specification, in the p-type trench lower layer forming step, the p-type trench lower layer may be formed so as to be in contact with the bottom surface of the trench. The total amount of p-type impurities in the p-type trench lower layer may be set so that a non-depleted region remains in a portion of the p-type trench lower layer in contact with the gate insulating film when a rated voltage is applied to the field effect transistor.

[0040] According to this configuration, the feedback capacitance of the field effect transistor can be effectively reduced.

[0041] In one example of the manufacturing method disclosed in this specification, the p-type trench lower layer forming step may include forming the p-type trench lower layer including a first p-type trench lower layer and a second p-type trench lower layer. The second p-type trench lower layer has a higher p-type impurity concentration than the first p-type trench lower layer, and the second p-type trench lower layer is located above or below the first p-type trench lower layer.

[0042] In one example of the manufacturing method disclosed in this specification, in the p-type trench lower layer forming step, p-type impurities may be implanted into the bottom surface of the trench while the bottom surface and side surfaces of the trench are exposed.

[0043] This configuration allows the formation of a p-type trench lower layer having a width substantially equal to the width of the trench bottom surface. This configuration suppresses the electric field applied to the gate insulating film and reduces the on-resistance of the field effect transistor.

[0044] In one example of the manufacturing method disclosed in this specification, in the trench forming step, an etching mask may be formed on the upper surface of the semiconductor substrate, and the upper surface of the semiconductor substrate may be etched through the etching mask to form the trench. In the p-type trench lower layer forming step, the etching mask may also be used as the ion implantation mask.

[0045] According to this configuration, a field effect transistor can be manufactured efficiently.

[0046] In one example of the manufacturing method disclosed in this specification, the semiconductor substrate may be prepared in the semiconductor substrate preparation step, including an n-type connection layer. The n-type connection layer may be disposed below each of the p-type deep layers to connect the n-type deep layers. The n-type connection layer may have a higher n-type impurity concentration than the n-type drift layer.

[0047] According to this configuration, the depletion layer is less likely to extend from the p-type deep layer to the drift layer when the field effect transistor is in the on state, and thus the on resistance of the field effect transistor can be reduced.

[0048] Figure 1 、 Figure 2 The MOSFET 10 (metal-oxide-semiconductor field effect transistor) of the embodiment shown has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (a direction orthogonal to the z direction) is referred to as the x direction, and a direction orthogonal to the x direction and the z direction is referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). In addition, the semiconductor substrate 12 can also be made of other semiconductor materials such as silicon and gallium nitride. A plurality of grooves 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. Figure 2 As shown, the plurality of grooves 14 extend long along the y direction on the upper surface 12a. The plurality of grooves 14 are arranged at intervals in the x direction.

[0049] like Figure 1 、 Figure 2 As shown, the inner surface (ie, the side surface and the bottom surface) of each trench 14 is covered by a gate insulating film 16. A gate electrode 18 is arranged in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. Figure 1 As shown, the upper surface of each gate electrode 18 is covered by an interlayer insulating film 20. A source electrode 22 is provided on the upper portion of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is provided on the lower portion of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0050] like Figure 1 、 Figure 2 As shown, the semiconductor substrate 12 has multiple source layers 30 , multiple contact layers 32 , a body layer 34 , multiple p-type trench lower layers 35 , multiple p-type deep layers 36 , multiple n-type deep layers 37 , an n-type connection layer 37 x , a drift layer 38 and a drain layer 40 .

[0051] Each source layer 30 is an n-type layer having a high n-type impurity concentration. Each source layer 30 is disposed in an area partially encompassing the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the uppermost portion of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends long in the y-direction along the side surface of the trench 14.

[0052] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. Each contact layer 32 is disposed within a region partially encompassing the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends elongated in the y-direction.

[0053] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below the plurality of source layers 30 and the plurality of contact layers 32. The body layer 34 contacts the plurality of source layers 30 and the plurality of contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 via the gate insulating film 16.

[0054] Each p-type trench lower layer 35 is a p-type layer disposed on the lower side of the corresponding trench 14. The p-type impurity concentration of each p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32. Each p-type trench lower layer 35 is in contact with the gate insulating film 16 at the bottom surface of the corresponding trench 14. The width of each p-type trench lower layer 35 (i.e., the dimension in the x-direction) is substantially equal to the width of the bottom surface of the trench 14 above it (i.e., the dimension in the x-direction). Figure 3As shown, when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction (y direction in this example) of the corresponding trench 14 .

[0055] Each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32. Figure 4 As shown, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 extends long in the x-direction, perpendicular to the longitudinal direction of the trench 14 (in this example, the y-direction). The plurality of p-type deep layers 36 are arranged at intervals in the y-direction. Hereinafter, the portion between the plurality of p-type deep layers 36 is referred to as a spacer 39 (see Figure 1 and Figure 2 ).like Figure 5 As shown, the p-type deep layer 36 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the p-type deep layer 36 in the z direction (hereinafter referred to as the depth Dp) is larger than the dimension of the p-type deep layer 36 in the y direction (hereinafter referred to as the width Wp). Figure 6 As shown, each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Figure 3 As shown, each p-type deep layer 36 is in contact with the p-type trench lower layer 35 arranged on the lower side of the trench 14 .

[0056] Each n-type deep layer 37 is an n-type layer disposed in the corresponding spacer 39. Each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38. Figure 1 、 Figure 2 As shown, each n-type deep layer 37 is in contact with the lower surface of the body layer 34. Each n-type deep layer 37 is in contact with the side surfaces of the p-type deep layers 36 on both sides thereof. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position lower than the bottom surface of each trench 14 and the lower surface of each p-type deep layer 36. Figure 5 As shown, the n-type deep layer 37 in the spacer 39 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the n-type deep layer 37 in the z direction (hereinafter referred to as the depth Dn) is larger than the dimension of the n-type deep layer 37 in the y direction (hereinafter referred to as the width Wn). Figure 1 、 Figure 2 As shown, each n-type deep layer 37 is in contact with the gate insulating film 16 on the side of the trench 14 located below the body layer 34 within each spacer 39. Figure 3 As shown, each n-type deep layer 37 is in contact with the p-type trench lower layer 35 arranged on the lower side of the trench 14 .

[0057] like Figure 5 As shown, an n-type connection layer 37x is disposed below each p-type deep layer 36. The n-type connection layer 37x has a higher n-type impurity concentration than the drift layer 38. The n-type connection layer 37x has approximately the same n-type impurity concentration as the n-type deep layer 37. Each n-type connection layer 37x is in contact with the lower surface of the corresponding p-type deep layer 36. Each n-type connection layer 37x connects the two n-type deep layers 37 located on either side of the p-type deep layer 36.

[0058] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than each n-type deep layer 37. The drift layer 38 is disposed below the n-type deep layer 37 and the n-type connection layer 37x. The drift layer 38 is in contact with the n-type deep layer 37 and the n-type connection layer 37x from below.

[0059] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0060] Next, the operation of MOSFET 10 will be described. MOSFET 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential greater than the gate threshold is applied to each gate electrode 18, a channel forms in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 to the n-type deep layer 37. Consequently, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38. In other words, MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced from a value greater than the gate threshold to a value less than the gate threshold, the channel disappears, and the flow of electrons ceases. In other words, MOSFET 10 is turned off.

[0061] Next, the operation of the MOSFET 10 when it is turned on will be described in more detail. If a channel is formed, electrons flow from the source layer 30 through the channel into the n-type deep layer 37. Electrons flow from the upper end to the lower end of the n-type deep layer 37 and flow into the drift layer 38. Therefore, a path for electron flow (i.e., a current path) is formed in the n-type deep layer 37. When the MOSFET 10 is turned on, a depletion layer of a predetermined width extends from the p-type trench lower layer 35 and the p-type deep layer 36 to the n-type deep layer 37 due to the built-in potential. The wider the width of the depletion layer in the n-type deep layer 37, the narrower the current path in the n-type deep layer 37. In this embodiment, the n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38, so the width of the depletion layer extending in the n-type deep layer 37 is narrow. Therefore, a wider current path is ensured in the n-type deep layer 37. As a result, the on-resistance of the MOSFET is reduced.

[0062] Furthermore, because the drift layer 38 has a low n-type impurity concentration, a depletion layer easily expands within the drift layer 38. If the p-type trench lower layer 35 and the p-type deep layer 36 were directly in contact with the drift layer 38, a relatively wide depletion layer would expand from the p-type trench lower layer 35 and the p-type deep layer 36 into the drift layer 38 when the MOSFET 10 is in the on state. In this case, the depletion layer narrows the current path within the drift layer 38, increasing the on-resistance of the MOSFET 10. In contrast, in this embodiment, an n-type deep layer 37 and an n-type connection layer 37x having a higher n-type impurity concentration than the drift layer 38 are provided below the p-type trench lower layer 35 and the p-type deep layer 36. In other words, the p-type trench lower layer 35 and the p-type deep layer 36 are not in contact with the drift layer 38. Therefore, when the MOSFET 10 is in the on state, the depletion layer is less likely to expand into the drift layer 38. Therefore, in MOSFET 10 of the present embodiment, the on-resistance is further reduced.

[0063] Next, the operation of the MOSFET 10 when it is turned off will be described in more detail. If the channel disappears, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and each n-type deep layer 37. Therefore, a depletion layer expands from the body layer 34 to each n-type deep layer 37. In addition, each p-type deep layer 36 is electrically connected to the body layer 34 and has a potential substantially the same as that of the body layer 34. Therefore, if the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, the depletion layer also expands from each p-type deep layer 36 to each n-type deep layer 37. Furthermore, each p-type trench lower layer 35 is electrically connected to the body layer 34 via each p-type deep layer 36 and has a potential substantially the same as that of the body layer 34. Therefore, if the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type trench lower layer 35 and each n-type deep layer 37. Therefore, the depletion layer extends from each p-type trench lower layer 35 to each n-type deep layer 37. In this way, each n-type deep layer 37 is rapidly depleted by the depletion layer extending from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36. In particular, because each p-type trench lower layer 35 is located below the corresponding trench 14, the area surrounding the bottom surface of the trench 14 is well depleted. This significantly alleviates the electric field concentration near the bottom surface of the trench 14. In particular, because the width of the p-type trench lower layer 35 is approximately equal to the width of the bottom surface of the trench 14, the electric field applied to the gate insulating film 16 covering the bottom surface of the trench 14 can be appropriately alleviated. Furthermore, due to the depletion layer extending from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36, the entirety of each n-type deep layer 37 is depleted. Furthermore, the n-type impurity concentration in each n-type deep layer 37 is higher than that in the drift layer 38. Therefore, the depletion layer is less likely to expand within each n-type deep layer 37 than within the drift layer 38. However, since each n-type deep layer 37 is sandwiched between the p-type deep layers 36, the entire n-type deep layer 37 is depleted. Furthermore, the depletion layer extends into the drift layer 38 via each n-type deep layer 37 and the n-type connection layer 37x. Because the n-type impurity concentration in the drift layer 38 is low, substantially the entire drift layer 38 is depleted. The high voltage applied between the drain electrode 24 and the source electrode 22 is maintained by the depleted drift layer 38 and each n-type deep layer 37. Consequently, the MOSFET 10 has a high withstand voltage.

[0064] In addition, when the MOSFET 10 is turned off, the depletion layer extends from the n-type deep layer 37 to the p-type trench lower layer 35. As described above, the p-type impurity concentration of the p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34. Therefore, it is difficult for the depletion layer to expand in the p-type trench lower layer 35, and a non-depleted region remains in the p-type trench lower layer 35 when the MOSFET 10 is turned off. In particular, in the present embodiment, the total amount of p-type impurities in each p-type trench lower layer 35 is set in such a way that a non-depleted region remains in each p-type trench lower layer 35 when a rated voltage is applied between the drain electrode 24 and the source electrode 22. Therefore, as Figure 7 As shown, within each p-type trench lower layer 35, a non-depleted region 60 remains in a portion of the portion in contact with the gate insulating film 16 covering the bottom surface of the trench 14. Thus, when the MOSFET 10 is in the off state, the non-depleted region 60 remains in the lower portion of the trench 14, reducing the capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24. Consequently, the MOSFET 10 can switch at high speed.

[0065] Next, the operation of the MOSFET 10 when the body diode is turned on will be described. Within the MOSFET 10, a pn diode (the so-called body diode) is formed by the p-type anode layer comprising the contact layer 32, the body layer 34, the p-type deep layer 36, and the p-type trench lower layer 35, and the n-type cathode layer comprising the n-type deep layer 37, the n-type connection layer 37x, the drift layer 38, and the drain layer 40. When the potential of the source electrode 22 becomes higher than that of the drain electrode 24, the body diode turns on. When the body diode turns on, holes flow from the p-type anode layer into the drift layer 38, flowing downward within the drift layer 38. When the holes reach the interface between the drift layer 38 and the drain layer 40, crystal defects grow at that interface. In this embodiment, the n-type deep layer 37 and the n-type connection layer 37x, each having a higher n-type impurity concentration than the drift layer 38, are provided below the p-type trench lower layer 35 and the p-type deep layer 36. That is, the p-type trench lower layer 35 and the p-type deep layer 36 are not in contact with the drift layer 38. The n-type deep layer 37 and the n-type connection layer 37x suppress the inflow of holes from the p-type trench lower layer 35 and the p-type deep layer 36 into the drift layer 38. This suppresses the growth of crystal defects at the interface between the drift layer 38 and the drain layer 40.

[0066] Next, a method for manufacturing MOSFET 10 will be described. MOSFET 10 is manufactured from a semiconductor substrate whose entire structure is composed of drain layer 40 .

[0067] (Semiconductor substrate preparation process)

[0068] First, a semiconductor substrate preparation process is performed. In the semiconductor substrate preparation process, first, as shown in FIG. Figure 8 As shown in FIG. 1 , an n-type epitaxial layer 50 is formed on the drain layer 40 using epitaxial growth technology. Figure 9As shown, by implanting ions into the upper surface of the semiconductor substrate, an n-type deep layer 37, an n-type connection layer 37x, and a p-type deep layer 36 are formed within the epitaxial layer 50. Here, n-type and p-type impurities are introduced into a depth range R1 away from the upper surface of the semiconductor substrate 12 to form the n-type deep layer 37, the n-type connection layer 37x, and the p-type deep layer 36. Specifically, n-type impurities are first introduced into the depth range R1 in a planar manner. Next, p-type impurities are counterdoped into a portion of the depth range R1 through a mask to form the p-type deep layer 36. The remaining n-type layer in the depth range R1 becomes the n-type deep layer 37 and the n-type connection layer 37x. Furthermore, the low-concentration n-type layer remaining below the depth range R1 becomes the drift layer 38. Furthermore, a low-concentration n-type layer also remains above the depth range R1.

[0069] As described above, this process forms a structure in which a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37 are arranged above the drift layer 38. When viewed from above, the p-type deep layers 36 extend in the x-direction and are arranged with spacers spaced apart in the y-direction. The n-type deep layers 37 are arranged within each spacer. The n-type connection layer 37x is arranged below the p-type deep layers 36 to connect the n-type deep layers 37 to each other. The n-type impurity concentrations of the n-type deep layers 37 and the n-type connection layer 37x are higher than the n-type impurity concentration of the drift layer 38. Alternatively, the n-type deep layer 37, the n-type connection layer 37x, and the p-type deep layer 36 can be formed by sequentially introducing n-type impurities and p-type impurities through masks corresponding to the n-type deep layers 37, the n-type connection layer 37x, and the p-type deep layer 36, respectively. Furthermore, by adjusting the concentration of the n-type impurity in the depth range R1 to be high in advance when epitaxially growing the epitaxial layer 50 , ion implantation for forming the n-type deep layer 37 and the n-type connection layer 37 x can be omitted.

[0070] (Body layer forming step)

[0071] Next, the body layer forming step is performed. In the body layer forming step, Figure 10 As shown, a body layer 34 is formed on the surface of the semiconductor substrate 12 by ion implanting p-type impurities into the upper surface of the semiconductor substrate. The body layer 34 is formed so that the body layer 34 is in contact with a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37 from above. By implanting the p-type impurity multiple times while varying the ion implantation depth, the body layer 34 is formed entirely within the depth range above the p-type deep layers 36 and the n-type deep layers 37. Figure 10 The depth D1 is the distance in the z direction from the upper surface of the semiconductor substrate to the lower end of the bulk layer 34. The depth D1 is the deepest ion implantation depth in the bulk layer forming step.

[0072] (Diffusion Layer Formation Step)

[0073] Next, the diffusion layer forming step is performed. In the diffusion layer forming step, as shown in FIG. Figure 11 As shown, n-type impurities and p-type impurities are introduced into the surface layer of the semiconductor substrate using ion implantation technology, thereby forming the source layer 30 and the contact layer 32 .

[0074] (Trench Formation Process)

[0075] Next, a groove forming process is performed. In the groove forming process, Figure 12 As shown, an etching mask 52 is formed on the upper surface of the semiconductor substrate (i.e., the upper surface of the epitaxial layer 50). The etching mask 52 has an opening 52a. Next, the upper surface of the semiconductor substrate is dry-etched through the etching mask 52. That is, the upper surface of the semiconductor substrate exposed in the opening 52a is dry-etched. As a result, a plurality of grooves 14 are formed on the upper surface of the semiconductor substrate. Here, when the epitaxial layer 50 is observed from the top, each groove 14 is formed in such a manner that the groove 14 intersects with the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37. In addition, each groove 14 is formed in such a manner that each groove 14 passes through the source layer 30 and the body layer 34 and the lower end (i.e., the bottom surface) of each groove 14 is located within the depth range of the p-type deep layer 36 and the n-type deep layer 37. That is, the depth of the trench 14 is adjusted so that the lower end of the trench 14 is located above the lower ends of the n-type deep layer 37 and the p-type deep layer 36 .

[0076] (P-Type Trench Lower Layer Formation Step)

[0077] Next, a p-type trench lower layer forming process is performed. In the p-type trench lower layer forming process, as shown in FIG. Figure 13 、 Figure 14As shown, ion implantation is used to form the p-type trench lower layer 35. Specifically, the etching mask 52 used in the trench formation process is used directly as an ion implantation mask, and p-type impurities are implanted into the semiconductor substrate from above. Ion implantation is performed while the bottom and side surfaces of the trench 14 are exposed. The p-type impurities are implanted into the bottom surface of the trench 14. Since the side surfaces of the trench 14 are roughly parallel to the ion implantation direction, almost no p-type impurities are implanted into the side surfaces of the trench 14. Since the upper surface of the semiconductor substrate is covered by the mask 52, no p-type impurities are implanted into the upper surface of the semiconductor substrate. Therefore, p-type impurities can be selectively implanted into the bottom surface of the trench 14. Thus, the p-type trench lower layer 35 is formed in the lower portion of the trench 14. By implanting the p-type impurities multiple times while varying the ion implantation depth, the p-type trench lower layer 35 having a predetermined thickness is formed. The p-type trench lower layer 35 is formed within a depth range that overlaps with the p-type deep layer 36. Therefore, the p-type trench lower layer 35 is connected to each p-type deep layer 36. Furthermore, the p-type trench lower layer 35 is formed so that it is exposed at the bottom surface of the trench 14. Since the bottom and side surfaces of the trench 14 are exposed, the p-type impurities are implanted throughout the bottom surface of the trench 14. Consequently, the p-type trench lower layer 35 is formed to have a width substantially the same as the bottom surface of the trench 14. Furthermore, the etching mask 52 is removed after the p-type trench lower layer formation step.

[0078] In this embodiment, since the ion implantation of the p-type trench lower layer 35 is performed in a process different from the ion implantation of the body layer 34, the p-type impurity concentration of the p-type trench lower layer 35 can be controlled independently of the p-type impurity concentration of the body layer 34. In the p-type trench lower layer formation process, p-type impurities are implanted at a higher concentration than in the body layer formation process. Therefore, the p-type impurity concentration of the p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34. If the p-type impurity concentration of the p-type trench lower layer 35 is increased, the p-type trench lower layer 35 is less likely to be depleted when the MOSFET 10 is turned off. Therefore, the feedback capacitance of the MOSFET 10 can be reduced. In particular, here, as Figure 7 As shown, the total amount of p-type impurities implanted into each p-type trench lower layer 35 is adjusted so that, when the rated voltage is applied to the MOSFET 10, a non-depleted region 60 remains in a portion of the p-type trench lower layer 35 that is in contact with the gate insulating film 16. Therefore, the feedback capacitance of the MOSFET 10 can be effectively reduced.

[0079] in addition, Figure 13 、 Figure 14The depth D2 is the distance in the z-direction from the bottom surface of the trench 14 to the lower end of the p-type trench lower layer 35. The depth D2 is the deepest ion implantation depth during the p-type trench lower layer formation process. In this embodiment, since the ion implantation of the p-type trench lower layer 35 is performed in a separate process from the ion implantation of the body layer 34, the ion implantation depth D2 of the p-type trench lower layer 35 can be controlled independently of the ion implantation depth D1 of the body layer 34. In this embodiment, the ion implantation depth D2 is shallower than the ion implantation depth D1. As a result, the p-type trench lower layer 35 can be formed so that the lower end of the p-type trench lower layer 35 is located above the lower end of the n-type deep layer 37. In other words, the p-type trench lower layer 35 can be formed so that the lower end of the p-type trench lower layer 35 does not contact the drift layer 38. Therefore, as described above, the depletion layer is less likely to extend into the drift layer 38 in the on-state, reducing the on-resistance of the MOSFET 10.

[0080] (Gate Electrode Forming Step)

[0081] Next, a gate electrode forming process is performed. In the gate electrode forming process, as shown in FIG. Figure 15 As shown in FIG. 1 , a gate insulating film 16 is formed to cover the inner surface of the trench 14 . Furthermore, a gate electrode 18 is formed in the trench 14 .

[0082] Next, an interlayer insulating film 20, a source electrode 22, and a drain electrode 24 are formed. Figure 1 MOSFET 10 is shown.

[0083] In the above-described manufacturing method, etching mask 52 is directly used as an ion implantation mask, thereby efficiently manufacturing MOSFET 10. In other embodiments, an ion implantation mask may be formed on the upper surface of the semiconductor substrate after etching mask 52 is removed.

[0084] In addition, in the above-mentioned manufacturing method, ion implantation of the p-type trench lower layer 35 is performed in a state where the bottom and side surfaces of the trench 14 are exposed (i.e., the semiconductor substrate is exposed in a state where the bottom and side surfaces of the trench 14 are exposed). According to this structure, p-type impurities can be implanted into the entire bottom surface of the trench 14, so that a p-type trench lower layer 35 having a width substantially the same as the width of the bottom surface of the trench 14 can be formed. According to this structure, the electric field applied to the gate insulating film 16 covering the bottom surface of the trench 14 can be effectively alleviated. Furthermore, according to this structure, since the width of the p-type trench lower layer 35 is not too wide, a wider current path can be ensured in the n-type deep layer 37, and the on-resistance of the MOSFET can be reduced. In addition, as Figure 16As shown, ion implantation of the p-type trench lower layer 35 can also be performed after forming a sacrificial oxide film 54 covering the bottom and side surfaces of the trench 14. This configuration can suppress the penetration of impurities into the side surfaces of the trench 14. Furthermore, in this case, the implantation range of the p-type impurities at the bottom surface of the trench 14 is narrowed. However, since the thickness of the sacrificial oxide film 54 is relatively thin, even with this configuration, a p-type trench lower layer 35 having a width close to the width of the bottom surface of the trench 14 can be formed.

[0085] Hereinafter, a MOSFET according to a modified example will be described.

[0086] exist Figure 17 In the MOSFET of the first modified example shown in FIG. 1 , a p-type trench lower layer 35 is formed at a position spaced downward from the bottom surface of the trench 14. Figure 17 In the process of forming the p-type trench lower layer, the p-type trench lower layer 35 is not formed in the depth range R2a near the bottom surface of the trench 14, and the p-type trench lower layer 35 is formed in the depth range R2b below the depth range R2a. In this way, even if the p-type trench lower layer 35 is arranged at a position away from the trench 14, the feedback capacitance can be reduced and the electric field can be relaxed. In addition, in the process of forming the p-type trench lower layer, the p-type impurities are not injected into the depth range R2a, but are injected into the depth range R2b, so that the p-type trench lower layer 35 can be formed. Figure 17 structure.

[0087] exist Figure 18 In the MOSFET of the second modified example shown, the p-type trench lower layer 35 includes a first p-type trench lower layer 35a and a second p-type trench lower layer 35b. The first p-type trench lower layer 35a is disposed within a depth range R2a near the bottom surface of the trench 14. The second p-type trench lower layer 35b is disposed within a depth range R2b below the depth range R2a. The second p-type trench lower layer 35b has a higher p-type impurity concentration than the first p-type trench lower layer 35a.

[0088] exist Figure 19 In the MOSFET of the third variant shown, a second p-type trench lower layer 35b (i.e., a layer with a high p-type impurity concentration) is configured within the depth range R2a, and a first p-type trench lower layer 35a (i.e., a layer with a low p-type impurity concentration) is configured within the depth range R2b.

[0089] exist Figure 18 、 Figure 19 In any MOSFET, the feedback capacitance is reduced and the electric field is relaxed by the p-type trench lower layer 35. Figure 19 In the case where the second p-type trench lower layer 35b having a high p-type impurity concentration is disposed at a position in contact with the bottom surface of the trench 14, Figure 18The feedback capacitance becomes lower than that of the case where the feedback capacitance is greater than 0.1. The appropriate feedback capacitance varies depending on the application of the MOSFET 10. When a lower feedback capacitance is required, Figure 19 The structure can be used when such low feedback capacitance is not required. Figure 18 structure. Figure 18 The structure can be formed by implanting p-type impurities at a low concentration into the depth range R2a and implanting p-type impurities at a high concentration into the depth range R2b in the p-type trench lower layer formation step. Figure 19 The structure can be formed by implanting p-type impurities at a high concentration into the depth range R2a and implanting p-type impurities at a low concentration into the depth range R2b in the p-type trench lower layer formation step.

[0090] exist Figure 20 In the MOSFET of the fourth modified example shown, the lower end of the p-type trench lower layer 35 is located at the same depth as the lower end of the n-type deep layer 37. Figure 21 In the MOSFET of the fifth modified example shown, the lower end of the p-type trench lower layer 35 is located below the lower end of the n-type deep layer 37. Figure 20 and Figure 21 In the embodiment, the p-type trench lower layer 35 is in contact with the drift layer 38. In these configurations as well, the p-type trench lower layer 35 can provide the effects of reducing feedback capacitance and relaxing the electric field.

[0091] exist Figure 22 In the MSOFET of the sixth modification shown in FIG. 1 , the lower end of the p-type deep layer 36 is located at the same depth as the lower end of the n-type deep layer 37. Figure 23 In the MOSFET of the seventh modified example shown in FIG. 1 , the lower end of the p-type deep layer 36 is located below the lower end of the n-type deep layer 37 . Figure 22 、 Figure 23 In the embodiment, the n-type contact layer 37x does not exist below the p-type deep layer 36, and the p-type deep layer 36 is in contact with the drift layer 38. In these configurations, a high breakdown voltage can be obtained by the p-type deep layer 36.

[0092] exist Figure 24 In the MOSFET of the eighth modified example shown, n-type deep layer 37 includes a first n-type deep layer 37a and a second n-type deep layer 37b. First n-type deep layer 37a is positioned above second n-type deep layer 37b. First n-type deep layer 37a has a higher n-type impurity concentration than second n-type deep layer 37b. First n-type deep layer 37a is positioned above the lower end of trench 14. Providing first n-type deep layer 37a, which has a higher n-type impurity concentration, ensures a wider current path in n-type deep layer 37. Consequently, the on-resistance of the MOSFET can be further reduced.

[0093] exist Figure 25 In the MOSFET of the ninth modified example shown, the p-type deep layer 36 includes a first p-type deep layer 36a and a second p-type deep layer 36b. The first p-type deep layer 36a is arranged above the second p-type deep layer 36b. The first p-type deep layer 36a has a higher p-type impurity concentration than the second p-type deep layer 36b. The first p-type deep layer 36a is arranged above the lower end of the trench 14. According to this structure, the p-type impurity concentration at the intersection of the p-type deep layer 36 and the p-type trench lower layer 35 can be prevented from becoming extremely high, and the p-type impurity concentration of the p-type deep layer 36 can be locally increased. Therefore, the generation of leakage current caused by excessive ion injection can be suppressed, and a high withstand voltage can be achieved by the p-type deep layer 36.

[0094] The configuration of the disclosed technology is listed in the specification of this application.

[0095] (Composition 1)

[0096] A method for manufacturing a field effect transistor, comprising:

[0097] a semiconductor substrate preparation step of preparing a semiconductor substrate, the semiconductor substrate having an n-type drift layer, a plurality of p-type deep layers, and a plurality of n-type deep layers, wherein the plurality of p-type deep layers and the plurality of n-type deep layers are arranged on an upper portion of the n-type drift layer, and when the semiconductor substrate is viewed from above, the p-type deep layers extend along a first direction and are arranged with spacers spaced apart in a second direction orthogonal to the first direction, the n-type deep layers are arranged in corresponding spacers, and the n-type deep layers have a higher n-type impurity concentration than the n-type drift layer;

[0098] a body layer forming step of forming a p-type body layer that contacts the plurality of p-type deep layers and the plurality of n-type deep layers from above by ion implanting p-type impurities into the semiconductor substrate;

[0099] a trench forming step of forming a trench on the upper surface of the semiconductor substrate, wherein the trench is formed so that, when the semiconductor substrate is viewed from above, the trench intersects the plurality of p-type deep layers, the trench penetrates the body layer, and the lower end of the trench is located above the lower ends of the plurality of p-type deep layers;

[0100] a p-type trench lower layer forming step of implanting p-type impurities into the bottom surface of the trench while covering the upper surface of the semiconductor substrate with an ion implantation mask, thereby forming a p-type trench lower layer connected to each of the p-type deep layers on the lower side of the trench; and

[0101] a gate electrode forming step of forming a gate insulating film and a gate electrode in the trench;

[0102] In the p-type trench lower layer forming step, a higher concentration of p-type impurities is implanted compared to the body layer forming step.

[0103] (Composition 2)

[0104] The method for manufacturing a field effect transistor according to configuration 1, wherein:

[0105] The ion implantation depth in the p-type trench lower layer forming step is shallower than the ion implantation depth in the bulk layer forming step.

[0106] (Composition 3)

[0107] The method for manufacturing a field effect transistor according to configuration 1 or 2, wherein:

[0108] In the p-type trench lower layer forming step, the p-type trench lower layer is formed so that a lower end of the p-type trench lower layer is located above a lower end of each of the n-type deep layers.

[0109] (Composition 4)

[0110] The method for manufacturing a field effect transistor according to any one of Configurations 1 to 3, wherein:

[0111] In the p-type trench lower layer forming step, the p-type trench lower layer is formed in such a manner that the p-type trench lower layer is in contact with the bottom surface of the trench.

[0112] The total amount of p-type impurities in the p-type trench lower layer is set so that a non-depleted region remains in a portion of the p-type trench lower layer in contact with the gate insulating film when a rated voltage is applied to the field effect transistor.

[0113] (Composition 5)

[0114] The method for manufacturing a field effect transistor according to any one of Configurations 1 to 4, wherein:

[0115] In the p-type trench lower layer forming step,

[0116] forming the p-type trench lower layer having a first p-type trench lower layer and a second p-type trench lower layer,

[0117] The second p-type trench lower layer has a higher p-type impurity concentration than the first p-type trench lower layer, and the second p-type trench lower layer is located above or below the first p-type trench lower layer.

[0118] (Composition 6)

[0119] The method for manufacturing a field effect transistor according to any one of Configurations 1 to 5, wherein:

[0120] In the p-type trench lower layer forming step, p-type impurities are implanted into the bottom surface of the trench in a state where the bottom surface and side surfaces of the trench are exposed.

[0121] (Composition 7)

[0122] The method for manufacturing a field effect transistor according to any one of Configurations 1 to 6, wherein:

[0123] In the trench forming step, an etching mask is formed on the upper surface of the semiconductor substrate, and the upper surface of the semiconductor substrate is etched through the etching mask to form the trench.

[0124] In the p-type trench lower layer forming step, the etching mask is used as the ion implantation mask.

[0125] (Composition 8)

[0126] The method for manufacturing a field effect transistor according to any one of Configurations 1 to 7, wherein:

[0127] In the semiconductor substrate preparation step, the semiconductor substrate having an n-type connection layer is prepared.

[0128] The n-type connection layer is disposed under each of the p-type deep layers to connect the n-type deep layers to each other.

[0129] The n-type impurity concentration of the n-type connection layer is higher than the n-type impurity concentration of the n-type drift layer.

[0130] While the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technologies described in the claims include technologies resulting from various modifications and alterations to the specific examples exemplified above. The technical elements described in this specification or the drawings may exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies exemplified in this specification or the drawings may achieve multiple objectives simultaneously, and achieving one of these objectives alone may be technically useful.

Claims

1. A method for manufacturing a field effect transistor, characterized in that: have: A semiconductor substrate preparation step of preparing a semiconductor substrate, the semiconductor substrate having an n-type drift layer (38), a plurality of p-type deep layers (36), and a plurality of n-type deep layers (37), wherein the plurality of p-type deep layers and the plurality of n-type deep layers are arranged on an upper portion of the n-type drift layer in the semiconductor substrate, and when the semiconductor substrate is viewed from above, the p-type deep layers extend along a first direction and are arranged with spacers spaced apart in a second direction orthogonal to the first direction, the n-type deep layers are arranged in corresponding spacers, and the n-type impurity concentration of each n-type deep layer is higher than the n-type impurity concentration of the n-type drift layer; a body layer forming step of forming a p-type body layer (34) that contacts the plurality of p-type deep layers and the plurality of n-type deep layers from above by ion-implanting p-type impurities into the semiconductor substrate; A trench forming step of forming a trench (14) on the upper surface of the semiconductor substrate, wherein the trench is formed in such a manner that when the semiconductor substrate is viewed from above, the trench intersects with the plurality of p-type deep layers, the trench penetrates the body layer, and the lower end of the trench is located above the lower ends of the plurality of p-type deep layers; a p-type trench lower layer forming step of implanting p-type impurities into the bottom surface of the trench while covering the upper surface of the semiconductor substrate with an ion implantation mask, thereby forming a p-type trench lower layer (35) connected to each of the p-type deep layers on the lower side of the trench; as well as a gate electrode forming step of forming a gate insulating film (16) and a gate electrode (18) in the trench; In the p-type trench lower layer forming step, a higher concentration of p-type impurities is implanted compared to the body layer forming step.

2. The method for manufacturing a field effect transistor according to claim 1, wherein: The ion implantation depth in the p-type trench lower layer forming step is shallower than the ion implantation depth in the bulk layer forming step.

3. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the p-type trench lower layer forming step, the p-type trench lower layer is formed so that a lower end of the p-type trench lower layer is located above a lower end of each of the n-type deep layers.

4. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the p-type trench lower layer forming step, the p-type trench lower layer is formed in such a manner that the p-type trench lower layer is in contact with the bottom surface of the trench. The total amount of p-type impurities in the p-type trench lower layer is set so that a non-depleted region (60) remains in a portion of the p-type trench lower layer in contact with the gate insulating film when a rated voltage is applied to the field effect transistor.

5. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the p-type trench lower layer forming step, forming the p-type trench lower layer having a first p-type trench lower layer (35a) and a second p-type trench lower layer (35b), The second p-type trench lower layer has a higher p-type impurity concentration than the first p-type trench lower layer, and the second p-type trench lower layer is located above or below the first p-type trench lower layer.

6. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the p-type trench lower layer forming step, p-type impurities are implanted into the bottom surface of the trench while the bottom surface and side surfaces of the trench are exposed.

7. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the trench forming step, an etching mask is formed on the upper surface of the semiconductor substrate, and the upper surface of the semiconductor substrate is etched through the etching mask to form the trench. In the p-type trench lower layer forming step, the etching mask is used as the ion implantation mask.

8. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein: In the semiconductor substrate preparation step, the semiconductor substrate having an n-type connection layer (37x) is prepared. The n-type connection layer is disposed under each of the p-type deep layers to connect the n-type deep layers to each other. The n-type impurity concentration of the n-type connection layer is higher than the n-type impurity concentration of the n-type drift layer.

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