Quasi-static C-V method with fixed forced application of DC current and leakage correction

Abstract

A quasi-static C-V method with fixed forced application of DC current and leakage correction. A test and measurement instrument is described having a current source configured to output a constant current to a device under test (DUT); a voltage sensor configured to sense a voltage of the DUT, where the voltage sensor is configured to: measure a first set of voltages that vary over time when the current source outputs the first current to the DUT; measuring a second set of voltages over time while the current source outputs a second current to the DUT, the second current having a different polarity than the first current; and measuring a third set of voltages over time while the current source outputs a third current to the DUT, the third current having the same polarity as the first current. Further, the test and measurement instrument includes one or more processors configured to derive a capacitance of the DUT based on the second and third currents.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a nonprovisional application and claims the benefit of U.S. Provisional Application No. 63 / 562,841, filed on March 8, 2024, entitled “QUASISTATIC C-VMETHOD WITH FIXED FORCE DC CURRENT AND LEAKAGE CORRECTION,” and U.S. Provisional Application No. 63 / 700,105, filed on September 27, 2024, entitled “INTERFACETRAP DENSITY OF ADEVICE USING FORCE CURRENT QUASISTATIC CV.” The disclosure of each of these applications is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to testing and measurement technology, and more particularly, to testing and measurement technology for power devices. Background Art

[0004] Capacitance-voltage (CV) measurements are used in the analysis of semiconductor materials and in the manufacture of semiconductor devices. CV is particularly useful for characterizing metal oxide semiconductors (MOS). Some of the many MOS device characteristics that can be extracted from CV data include mobile charge in the oxide, oxide capacitance, interface traps, doping profile, flatband voltage, doping concentration, minority carrier lifetime, and input / output capacitance.

[0005] For most semiconductor CV measurements, high frequencies (typically 100kHz to 1MHz) are used. However, for some CV measurements, low-frequency or quasi-static techniques are required. This is the case with interface trap density (DIT) measurements on MOS caps, where quasi-static CV is able to detect interface traps. At high frequencies, interface traps cannot change state quickly enough to affect device capacitance. Therefore, both high-frequency and low-frequency measurements are required to determine the amount of trapped charge.

[0006] Available quasi-static CV solutions typically involve using a source measure unit (SMU) to force a voltage and measure the current. For example, the ramp rate technique and the very low frequency capacitance-voltage technique used by the SMU for CV measurements use current measurements to derive the capacitance of the device under test (DUT). These techniques are effective on traditional silicon MOS devices. However, with high-power devices, such as SiC MOS devices, the higher capacitance makes these techniques difficult to use because the higher capacitance may lead to unstable results. The stability of the SMU's feedback ammeter is typically specified based on the load capacitance or source impedance. Depending on the model of the SMU, the SMU's ammeter may be unstable even with capacitances of several hundred picofarads.

[0007] Therefore, a method is needed to derive the quasi-static (DC) capacitance of high-power devices using an SMU. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order that the above features may be understood in detail, a more detailed description of the above briefly summarized features may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical example implementations and are therefore not to be considered as limiting the scope thereof.

[0009] Figure 1 is a diagram illustrating a device under test (DUT) coupled to a source measure unit (SMU) for deriving quasi-static capacitance-voltage (CV) characteristics of the DUT according to some examples.

[0010] Figure 2 Included are graphs of current generated by an SMU versus time and graphs of voltage across terminals of the SMU versus time according to some examples.

[0011] Figure 3 A leakage measurement circuit with an SMU and a circuit representing a DUT is shown according to some examples.

[0012] Figure 4A is a graph illustrating voltage versus time for a DUT using the quasi-static capacitance-voltage technique described herein, according to some examples.

[0013] Figure 4B is a graph illustrating the resulting forward and reverse CV curves produced by the quasi-static capacitance-voltage technique described herein, according to some examples.

[0014] Figure 5 is a flow chart of the operation of an SMU to obtain the capacitance of a DUT according to some examples.

[0015] Figure 6An SMU connected to a silicon carbide (SiC) metal oxide semiconductor (MOS) DUT is illustrated, showing circuit potentials, according to some examples.

[0016] Figure 7 is a graph of forward and reverse capacitance curves as a function of surface potential using a quasi-static capacitance-voltage technique according to some examples.

[0017] Figure 8 is a graph showing forward and reverse capacitance curves as a function of surface potential based on a quasi-static capacitance-voltage technique in which oxide capacitance is removed, according to some examples.

[0018] Figure 9 The surface potential (V s ) as a function of the interface trap density (DIT).

[0019] Figure 10 is a flow chart for deriving interface trap capacitance using a quasi-static capacitance-voltage technique, according to some examples.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0021] This disclosure describes the use of a source measure unit (SMU) to derive quasi-static capacitance by measuring voltage rather than current because the measured voltage is stable under a capacitive load. This disclosure describes a quasi-static capacitance-voltage (QSCV) measurement technique that uses a method of forcing a fixed current into the gate terminal of a device under test (DUT) (such as a power device or a metal oxide semiconductor field effect transistor (MOSFET)), measuring the voltage as a function of time, and deriving the capacitance from it. Some of the advantages of using the technique described herein on a power device include: only one SMU with a preamplifier is required, while other methods use two SMUs; forcing current is faster than forcing voltage methods; steady-state conditions are achieved by forcing a constant DC current to the DUT, as opposed to stepping voltage; avoiding instability issues by measuring voltage while using the instrument in low output impedance mode to derive capacitance; performing open circuit correction; correcting for leakage; and working on larger capacitances greater than 20pF.

[0022] The present disclosure involves forcing a positive current to pre-set and charge the DUT, reversing the current to negative, and reversing the current back to positive. After collecting CV data (measured capacitance-voltage versus time), the leakage current measurements are used to improve the charge calculations of the leakage device.

[0023] Figure 1 is a diagram showing a circuit with a DUT coupled to an SMU for deriving quasi-static CV characteristics of the DUT according to some examples. Figure 1 As shown in FIG, circuit 100 includes an SMU 102 coupled to a DUT 104. Specifically, DUT 104 is a power MOSFET and has gate, drain, and source terminals, such as Figure 1 Therefore, in Figure 1 In the example shown in Figure 1, the Force HI terminal of SMU 102 is connected to the gate of DUT 104, and the Force LO terminal of SMU 102 is connected to the drain and source terminals of DUT 104, which are shorted together. In some examples, a single SMU can derive the quasi-static CV characteristics of a power MOSFET or capacitor. In the examples described herein, the SMU can source and measure both current and voltage.

[0024] like Figure 1 , the SMU 102 includes a controller 106. The controller 106 of the SMU 102 includes firmware that controls the SMU 102. The SMU 102 includes a current source 108 and a voltmeter 110, and the controller 106 of the SMU 102 is configured to control the current source 108 and the voltmeter 110. In some examples, the controller 106 sends instructions to the current source 108 to generate a specific current to the DUT 104 and sends instructions to the voltmeter 110 to measure the voltage across the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 for a specific time. As used herein, the term "controller" refers to a programmable circuit. This discussion refers to a controller as a processor or programmable circuit, which may include a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other type of controller that can perform those functions.

[0025] In some examples, the circuit 100 includes a computing device 112 coupled to the SMU 102. In such examples, the SMU 102 provides voltage measurements to the computing device 112, and the computing device 112 performs a quasi-static CV calculation and determines the capacitance of the DUT 104. The computing device 112 transmits the capacitance of the DUT 104 to the SMU 102 so that the SMU 102 can compensate for leakage current of the DUT 104. In other examples, the SMU 102 performs a quasi-static CV calculation and determines the capacitance of the DUT 104. As used herein, the term "computing device" refers to a programmable circuit. This discussion refers to a computing device as a processor, controller, or programmable circuit, which may include a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other type of controller that can perform the functions described herein.

[0026] As described herein, the controller 106 of the SMU 102 derives the forward and reverse capacitance of the DUT 104 as a function of voltage and compensates for leakage current. To derive capacitance, the SMU 102 is configured to force a current to the DUT 104 and measure the voltage across the Force HI and Force LO terminals of the SMU 102 at a specific time. Forcing a constant current provides accurate control of the total charge supplied to the device (Q = I * dt). Unlike voltage stepping (which can result in dynamic changes in the measurement setup), using a constant current allows the instrument to maintain a steady-state condition.

[0027] Figure 2 104 as measured by voltmeter 110 versus time, as described herein. As shown, during time period T1, SMU 102 forces a constant positive current (+I) using current source 108 and measures voltage (V) and time across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 using voltmeter 110 until SMU 102 determines that the voltage measured by voltmeter 110 has reached a first predetermined voltage level, VHigh. In some examples, the first predetermined voltage is a user-defined maximum voltage of DUT 104. In some examples, the voltage measurements taken during time period T1 are not used for capacitance measurements.

[0028] After the SMU 102 determines that the voltage as read by the voltmeter 110 has reached the first predetermined voltage level, during a time period T2, the SMU 102 changes the polarity of the current source 108 so that the current source 108 forces a constant negative current (-I) to the DUT 104. During the time period T2, the SMU 102 uses the voltmeter 110 to measure the voltage across the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 until the SMU 102 determines that the voltage as measured by the voltmeter has reached a second predetermined voltage level (VLow). In some examples, the second predetermined voltage is a user-defined minimum voltage of the DUT 104. The voltage measurement during the time period T2 can be referred to as a reverse sweep.

[0029] After the SMU 102 determines that the voltage as read by the voltmeter 110 has reached the first predetermined voltage level, during time period T3, the SMU 102 again changes the polarity of the current source so that the current source 108 forces a constant positive current (+I) to the DUT 104. During time period T3, the SMU 102 uses the voltmeter 110 to measure the voltage (V) across the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 until the SMU 102 determines that the voltage as measured by the voltmeter 110 has reached a third predetermined voltage level. In some examples, the predetermined voltage is a user-defined maximum voltage of the DUT 104. In further examples, the third predetermined voltage level can be the same as the first predetermined voltage level VHigh. The voltage measurement during time period T3 can be referred to as a forward sweep.

[0030] In some examples, depending on the polarity of the forced current, the SMU 102 may use a negative, positive, and negative current arrangement instead of the positive, negative, and positive current arrangement described above.

[0031] Once the SMU 102 has finished sending different currents to the DUT 104, as described, the SMU 102 collects voltage measurements of the DUT 104 and generates a capacitance versus voltage curve. Because the SMU 102 provides both positive and negative currents to the DUT 104 and measures the corresponding voltages for both positive and negative currents, both positive and negative CV curves can be extracted. The SMU 102 calculates the DUT capacitance (Cm) as follows:

[0032]

[0033] Where I = forced current (A), V = measured voltage (V), t = measurement time (s), and Cm = derived capacitance (F).

[0034] Figure 3304 ) and includes all currents provided by the current sources of the SMU (in the form of dashed lines). When making direct current (DC) measurements as described herein, such as to derive quasi-static CV, the leakage resistance from the DUT 304 itself and the parasitic capacitance in the cables can cause significant errors if not corrected. The gate capacitance of the DUT 304 (such as a power MOSFET or other capacitive device) can be modeled as a parallel RC circuit representing the DUT 304, as shown in FIG. Figure 3 In this example, resistor R represents the leakage resistance of capacitor Cd. In addition, capacitor Cp represents the parasitic capacitance in the cable and / or in the circuit 300.

[0035] In some examples, the SMU 302 may include an ammeter 312 (controlled by the controller 306) for measuring current and a voltage source ( Figure 3 (not shown in the figure). Therefore, when measuring the leakage current of DUT 304, SMU 302 forces the voltage to be applied and measures the current because the leakage current is a function of the applied voltage. Figure 3 As illustrated in , IR is the leakage current of the DUT 304; Id is the current due to the capacitance Cd of the DUT 304, which can be represented by Id=Cd(dV / dt); and Ip is the current due to the parasitic capacitance Cp in the system / circuit 300, which can be represented by Ip=Cp(dV / dt).

[0036] In the present disclosure, the SMU 302 can measure and compensate for unwanted currents (IR and Ip) by performing an IV sweep on the DUT 304 and subtracting the unwanted current. The voltage sweep uses actual measured voltage points from a constant forward and reverse current forced application test. According to this test, the forced applied current is:

[0037]

[0038] The forced current can also be written as:

[0039]

[0040] Where Cm is the derived capacitance.

[0041] Therefore, the combined terms are as follows:

[0042]

[0043] Where Cp = system parasitic capacitance, which includes cable parasitic capacitance and probe parasitic capacitance. Therefore, the measurement of leakage (IR) allows to compensate for it and calculate Cp + Cd from the measured value Cm.

[0044] In probes up scenarios or other open circuit scenarios, where the DUT is not coupled to the circuit, there is no Cd and what is measured is the parasitic capacitance (Cp). Subtracting this parasitic capacitance (Cd) from (Cp + Cd) provides an additional level of accuracy and yields the device capacitance to compensate for leakage and parasitic capacitance.

[0045] Figure 4A is a graph illustrating the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 versus time, and Figure 4B is a graph illustrating the resulting forward and reverse CV curves corresponding to the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 generated by the quasi-static capacitance-voltage technique described herein. Specifically, Figure 4B The graphs of QSCV and QSCV illustrate the forward and reverse capacitance versus voltage measurements extracted on a SiC power MOSFET. From these two curves, the SMU 302 may be able to extract other parameters such as trapped charge.

[0046] Figure 5 is a flow chart of the operation of the SMU as described in this article to obtain the capacitance of the DUT. Figure 1 The operation 500 is described with respect to the circuit 100, but may also be used with Figure 3 In some examples, operation 500 may occur when DUT 104 is coupled to SMU 102.

[0047] Operation 500 is to instruct a voltage sensor of a test and measurement instrument such as Figure 1Operation 502 begins by measuring a first set of voltages that vary over time while a current source of the SMU (e.g., a voltmeter) outputs a first constant current to the DUT. In some examples, the current source of the SMU outputs the first constant current to the DUT until a voltage sensor of the SMU determines that the voltage across the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 has reached a first predetermined voltage threshold. In some examples, the first constant current to the DUT is a constant positive current, and by sending the constant positive current to the DUT, the SMU charges the DUT to the first predetermined voltage threshold. In further examples, the SMU tracks the time until the DUT reaches the first predetermined voltage threshold. The first predetermined voltage threshold can be a user-defined maximum voltage for the DUT. In other examples, the first constant current to the DUT is a constant negative current, and therefore, the SMU tracks the time until the DUT reaches the first predetermined voltage threshold, which can be a user-defined minimum voltage for the DUT.

[0048] In some examples, a controller of the SMU sends an instruction to a current source of the SMU to output a first positive current to the DUT.

[0049] Operation 500 then proceeds to operation 504, where the voltage sensor is instructed to use a voltage sensor such as Figure 1 The voltmeter 110 of the SMU measures a second set of voltages that vary over time while the SMU's current source outputs a second constant current to the DUT. The second constant current has a different polarity than the first constant current to the DUT. For example, if the first constant current is positive, the second constant current is negative. Similarly, if the first constant current is negative, the second constant current is positive. In some examples, the SMU's current source outputs the second constant current to the DUT until the SMU's voltage sensor determines that the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 has reached a second predetermined voltage threshold. In some examples, the second constant current to the DUT is a constant negative current, and by sending the negative current to the DUT, the SMU discharges the DUT, and the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 reflects this. In further examples, the SMU tracks the time until the DUT reaches the second predetermined voltage threshold. The second predetermined voltage threshold can be a user-defined minimum voltage for the DUT. In other examples, the second constant current to the DUT is a constant positive current, and therefore, the SMU tracks the time until the DUT reaches a first predetermined voltage threshold, which may be a user-defined maximum voltage of the DUT.

[0050] Operation 500 then proceeds to operation 506, where the voltage sensor is instructed to measure a third set of voltages that vary over time while the current source of the SMU outputs a third constant current to the DUT. The third constant current has the same polarity as the first constant current to the DUT. For example, if the first constant current is positive, the third constant current is also positive. Similarly, if the first constant current is negative, the third constant current is also negative. In some examples, the current source of the SMU outputs the third constant current to the DUT until the voltage sensor of the SMU determines that the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 has reached a third predetermined voltage threshold. As mentioned, in some examples, the third constant current to the DUT is a constant positive current, and by sending the positive current to the DUT, the SMU charges the DUT, and the voltage across the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102 reflects this. In further examples, the SMU tracks the time until the DUT reaches the third predetermined voltage threshold. The third predetermined voltage threshold can be a user-defined maximum voltage, and in some examples, the third predetermined voltage threshold can be the same as the first predetermined voltage threshold. In other examples, the third constant current to the DUT is a constant negative current, and thus, the SMU tracks the time until the DUT reaches the third predetermined voltage threshold, which can be a user-defined minimum voltage for the DUT.

[0051] Then, operation 500 proceeds to operation 508, where the DUT capacitance is derived based on the second and third constant currents and the second and third sets of voltages as a function of time. Operation 508 involves determining the quasi-static capacitance of the DUT versus the voltage based on the second and third sets of voltages that vary over time. In some examples, operation 508 involves collecting the voltage measurements collected in operations 504 and 506 and calculating the DUT capacitance (Cm) as follows:

[0052]

[0053] Where I = forced current (A), V = measured voltage (V), t = measurement time (s), and Cm = derived capacitance (F).

[0054] Operation 500 then proceeds to operation 510 where device parameters of the DUT are determined based on the DUT quasi-static capacitance. Using the DUT capacitance, the SMU can determine other parameters of the DUT, such as mobile charge in the oxide, oxide capacitance, or interface traps.

[0055] Operation 500 then proceeds to operation 512, where the SMU and computing device compensate for the unwanted leakage current and parasitic capacitance of the DUT. As mentioned, the SMU can measure and compensate for unwanted current (IR and Ip) by performing an IV sweep on the DUT and subtracting the unwanted current. The voltage sweep uses the actual measured voltage points from the constant forward and reverse current force test, and from this, the capacitance can be derived, as described. In addition, the SMU can determine the system parasitic capacitance, which includes cable parasitic capacitance and probe parasitic capacitance, and can compensate for the unwanted current based on the previous calculation.

[0056] The quasi-static CV technique described in this article offers several advantages over other methods. Measuring voltage is faster than measuring low currents and allows more data points to be collected with good accuracy. Feedback ammeters are typically unstable under capacitive loads, and therefore measuring voltage avoids noisy measurements. The technique described in this article requires one SMU, rather than the two required by other methods. The technique in this article combines leakage measurement and correction, which enables the quasi-static technique to be applied to leaky MOS devices. Quasi-static CV measurements in both the forward and reverse directions in a single run allow for charge trap characterization.

[0057] The present disclosure relates to measuring voltage rather than current, which results in faster, more accurate, and less noisy results. The present disclosure relates to using only one SMU instead of two. The present disclosure relates to providing leakage correction at specific measurement voltage points without using differential methods that may result in noisy results.

[0058] This disclosure further describes a method for determining interface trapped and other internal charges of SiC MOS devices using a forced current QSCV measurement technique. Since SiC devices have significantly more internal charge than conventional Si devices, the measured capacitance needs to be plotted again as a function of surface potential (V s ) instead of the gate voltage (V g ) to calculate the trapped charge. From the low frequency (quasi-static) CV g The interface trapped charge of the silicon MOS device is extracted from the capacitance difference between the CMOS curve and the high-frequency (AC) curve. To observe the internal charge of the SiC MOSFET, forward and reverse quasi-static CV scans can be used to extract this charge.

[0059] The technique used to derive this interface trap capacitance can be described in five steps: First, the forward (Cf) and reverse (Cr) quasi-static capacitance versus gate voltage (V) is generated on the SiC MOSFET using the forced current quasi-static CV technique described above. g ) curve. Second, the surface potential (V s) array. Third, interpolate the forward capacitance (CfDut) and reverse capacitance (CrDut) at each surface potential point. Fourth, subtract the oxide capacitance (C ox ). Fifth, the capacitance due to trapped charge (CIT) and the density of interface traps (DIT) are calculated from the difference between the forward and reverse curves as a function of surface potential. These five steps are further explained in this article.

[0060] Although the present disclosure relates to MOSFETs, the present disclosure may be potentially applicable to other devices. In addition, although the present disclosure relates to interface charges, the present disclosure may be potentially applicable to other types of charges, including but not limited to oxide or mobile ionic charges.

[0061] The present disclosure works by generating forward and reverse CV data using a forced current quasi-static method and then extracting the interface trap density as a function of surface potential.

[0062] As mentioned above, deriving the interface trap capacitance involves generating forward and reverse quasi-static CV curves. Specifically, deriving the interface trap capacitance involves generating forward quasi-static capacitance (Cf) and reverse quasi-static capacitance (Cr) versus gate voltage (Vg) curves on a SiC MOSFET using a forced current quasi-static CV technique. The forced current QSCV technique uses an SMU to derive the quasi-static CV of a DUT (such as a SiC MOSFET or MOScap). In this test, the SMU forces a current and measures the voltage and time. The constant current provides accurate control of the total charge supplied to the DUT (Q = ∑I * dt). When a constant current is forced to the DUT, both the forward and reverse CV sweeps are derived from the forced current, voltage, and time. The capacitance (C) is calculated as follows:

[0063]

[0064] Where I is the forced current (A), V is the measured voltage (V), t is the measurement time (s), and C is the derived capacitance (F).

[0065] At this point in the test, the voltage and time have been measured. The data needs to be separated into reverse and forward CV scans to accurately represent the data. First, during the reverse scan, the reverse voltage (Vr), reverse scan time (timeR), and reverse capacitance (Cr) are output. During the forward scan, the reverse voltage (Vf), forward scan time (timeF), and capacitance (Cf) are output.

[0066] From the forward and reverse CV scans, a shift in voltage between the two curves is observed, as well as a "peak" and smaller curve features. Both the voltage shift and the "peak" are the result of internal device charge (such as trapped charge, mobile ion charge, or charge associated with the device structure). However, sometimes during high-frequency (AC) scans, the voltage shift and peak are not observed.

[0067] As mentioned above, deriving the interface trap capacitance involves deriving the surface potential (V s ) array. Usually at the same gate voltage (V g ) to compare the capacitance of the DUT under forward and reverse voltage sweeps. Since SiC MOSFETs have significant internal charge, the surface potential (V s ) function. Using V s Corrects for the "shift" seen in the gate voltage between the forward and reverse curves and allows the curves to be compared. Accurately measured charge allows correction for the voltage drop across the gate oxide to extract V s .

[0068] Figure 6 The diagram shows a circuit with an SMU connected to a SiC MOSDUT, showing the circuit potential. Figure 6 As shown in FIG, circuit 600 includes SMU 102 coupled to DUT 604 having gate 614, oxide 616, and SiC layer 618. SMU 102 includes current source 108 and voltmeter 110. Figure 6 As shown in FIG, SMU 102 applies a constant current and a voltage V to DUT 604. g and V s The voltage at the gate layer 614 of the DUT 604 is V g The voltage at the SiC / SiO2 interface is the surface potential (V s ) and is represented by the following formula:

[0069] V s =V g -V ox

[0070] Therefore, in order to derive the surface potential (V s ) array, the computing device 112 analyzes the reverse and forward capacitance arrays (Cr and Cf) to find the maximum value from either array. The maximum capacitance is defined as C ox or oxide capacitance. Then, according to each gate voltage V g , SMU 102 uses an oxide capacitor C oxand calculated charge (Q) to calculate the surface potential V s :

[0071]

[0072] For both scans, the surface potential is split into two separate arrays. Output parameter V s R represents the reverse scanning surface potential, and V s F represents the forward scanning surface potential.

[0073] As mentioned above, the interface trap capacitance is derived by considering the surface potential V at each s Interpolate the forward capacitance (CfDut) and reverse capacitance (CrDut) at each surface potential V s Interpolating the forward capacitance (CfDut) and reverse capacitance (CrDut) at different V g but the same surface potential V s To this end, the computing device 112 uses linear interpolation as follows: (1) Determine the number of voltage step points, but use the following formula And (2) run linear interpolation twice, once for the reverse scan and once for the forward scan, to extract the interpolated capacitance points. The forward and reverse interpolated capacitance arrays are CrDut and CfDut.

[0074] As mentioned above, deriving the interface trap capacitance involves subtracting the oxide capacitance (C ox Specifically, the maximum capacitance (C ox ). To this end, SMU102 measures the reverse and forward voltage surface potential values ​​V s R and V s F uses linear interpolation. The computing device 112 calculates the forward and reverse interpolated capacitance arrays (CrDut and CfDut), and in each function, the computing device 112 uses the following two equations to remove C at each point ox value:

[0075]

[0076] Figure 7 As V s Specifically, Figure 7 Both forward and reverse capacitance curves, CfDut and CrDut, are shown plotted as a function of the interface voltage rather than the gate voltage.

[0077] Figure 8 is shown as Vs The function of which removes C ox Specifically, regarding the Cf and Cr curves Figure 8 , in which C is removed ox , CrOnly and CfOnly are plotted as a function of the interface voltage, now on a logarithmic scale.

[0078] As mentioned above, deriving the interface trap capacitance involves calculating the interface trapped capacitance (CIT) and density (DIT) due to trapped charge based on the difference of the corrected forward and reverse curves as a function of surface potential. In some examples, the computing device 112 determines the interface trapped capacitance due to trapped charge of the DUT 604 using the following formula:

[0079]

[0080] In some examples, the computing device determines the interface trap density (DIT) due to trapped charge of the DUT 604 using the following formula:

[0081]

[0082] Figure 9 Shown as the surface potential (V s ). Specifically, Figure 9 shows the difference between the interpolated forward and reverse capacitance plotted against the interface voltage (V s ).

[0083] Figure 10 is a flow chart of the operation of an SMU and a computing device for deriving interface trap capacitance using the quasi-static capacitance-voltage technique as described herein. Operation 1000 refers to Figure 1 The circuit 100 is described, but it can also be used Figure 6 The circuit 600 is implemented.

[0084] Operation 1000 begins with operation 1002, where the SMU generates forward and reverse quasi-static capacitance versus gate voltage curves for the DUT. The DUT may be a SiC MOSFET. In some examples, operation 1002 includes Figure 5 Some of the operations 500 are performed to generate forward and reverse quasi-static capacitance versus gate voltage curves of the DUT.

[0085] Then, operation 1000 proceeds to operation 1004, where the computing device derives the surface potential arrays for both the forward scan and the reverse scan. s) array, the SMU analyzes the reverse and forward capacitance arrays (Cr and Cf) to find the maximum value from either array. Then, based on each gate voltage V g , computing devices use oxide capacitors C ox and calculated charge (Q) to calculate the surface potential V s For both scans, the surface potential is split into two separate arrays. Output parameter V s R represents the reverse scanning surface potential, and V s F represents the forward scanning surface potential.

[0086] Operation 1000 then proceeds to operation 1006, where the computing device interpolates the forward capacitance and the reverse capacitance at each surface potential point of the surface potential array. In operation 1006, the computing device compares the forward capacitance and the reverse capacitance at different V g but the same surface potential V s To this end, the computing device uses linear interpolation as follows: (1) The computing device determines the number of voltage step points, but uses the following formula And (2) the computing device runs linear interpolation twice, once for reverse scan and once for forward scan, to extract interpolated capacitance points. The forward and reverse interpolated capacitance arrays are CrDut and CfDut.

[0087] Operation 1000 then proceeds to operation 1008, where the computing device subtracts the oxide capacitance from the forward and reverse measurements. The computing device calculates the oxide capacitance by comparing the reverse and forward voltage surface potential values ​​V s R and V s F is calculated using linear interpolation by subtracting the maximum capacitance (C ox ). The computing device calculates the forward and reverse interpolated capacitance arrays (CrDut and CfDut), and in each function, the computing device uses the following two equations to remove C at each point ox value:

[0088]

[0089] Operation 1000 then proceeds to operation 1010, where the computing device calculates the interface trapped capacitance (CIT) and density (DIT) due to trapped charge based on the difference of the corrected forward and reverse curves as a function of the surface potential. The computing device uses the gate area of ​​the DUT, CIT, and DIT. Fonly Point and C Ronly Similarly, the calculation device uses the gate area of ​​the DUT, the charge of the DUT, C Fonly Point and C RonlyThe interface trap density (DIT) due to the trapped charge of the DUT is determined by the DIT point.

[0090] The present disclosure for counting traps in SiC MOS devices based on forward and reverse sweeps offers advantages over other solutions. For example, quasi-static CV measurements in both the forward and reverse directions can be performed in a single run, which allows charge trap characterization. Another advantage is that the present disclosure allows capacitance measurements as a function of the interface potential rather than just the gate voltage. Still another advantage is that the present disclosure involves extracting the internal charge of the device, which is not detectable by high-frequency methods. In addition, the present disclosure requires only one SMU, rather than the two required by other methods. Requiring only one SMU also avoids interruption of the measurement circuit when two instruments need to be switched to the device.

[0091] In this disclosure, the difference in forward and reverse quasi-static (low frequency) capacitance versus voltage measurements is used to calculate internal traps. Other techniques use the difference between high and low frequency CV scans to derive interface trap density.

[0092] Since the charge is measured, the interface potential can be calculated, allowing the capacitance to be characterized as a function of the interface potential. Extracting the interface potential is difficult with other techniques because measuring the oxide charge at high frequencies is difficult or impossible. Therefore, comparisons are typically made as a function of gate voltage rather than interface potential. With this technique, high-frequency CV measurements are unnecessary.

[0093] In this disclosure, the singular forms "a," "an," and "the" include plural referents unless the context dictates otherwise. The term "or" is intended to be inclusive and means any one, any one, several, or all of the listed items. The terms "comprises," "comprising," "including," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, or product that includes a list of elements does not necessarily include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Relative terms, such as "about," "approximately," "substantially," and "generally," are used to indicate a possible variation of ±10% from a stated or understood value.

[0094] Aspects of the present disclosure are susceptible to various modifications and alternative forms. Specific aspects have been illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be noted that the examples disclosed herein are presented for clarity of discussion and are not intended to limit the scope of the general concepts disclosed to the specific aspects described herein, unless expressly limited. Therefore, the present disclosure is intended to cover all modifications, equivalents, and alternatives of the aspects described in accordance with the drawings and claims.

[0095] References in the specification to aspects, examples, etc. indicate that the item may include a particular feature, structure, or characteristic. However, each disclosed aspect may or may not necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same aspect unless otherwise indicated. Furthermore, when a discussion describes a particular feature, structure, or characteristic in relation to a particular aspect, such feature, structure, or characteristic may be used in relation to another disclosed aspect, regardless of whether such feature is explicitly described in relation to such another disclosed aspect.

[0096] Aspects of the present disclosure may be operated on specially created hardware, on firmware, a digital signal processor, or on a specially programmed general-purpose computer including a processor that operates according to programmed instructions. As used herein, the term controller or processor includes a microprocessor, a microcomputer, an application-specific integrated circuit (ASIC), a cloud-based server, and a dedicated hardware controller. One or more aspects of the present disclosure may be implemented with computer-usable data and computer-executable instructions (such as one or more program modules) executed by one or more computers (including monitoring modules) or other devices. Typically, a program module includes routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer-executable instructions may be stored on a non-transitory computer-readable medium such as a hard disk, an optical disk, a removable storage medium, a solid-state memory, a random access memory (RAM), etc. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various aspects. In addition, the functions may be present in firmware or hardware equivalents (such as integrated circuits, field programmable gate arrays (FPGAs), and the like) in whole or in part. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0097] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more or non-transitory computer-readable media, which instructions may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0098] Computer storage media refers to any medium that can store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transitory forms of signal transmission.

[0099] Communication media refers to any medium that can transmit computer-readable information. By way of example, and not limitation, communication media can include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0100] In some cases, the disclosed aspects can be implemented in hardware, firmware, software, or any combination thereof. The above references to FPGAs and other integrated circuits (such as voltage regulators, etc.) can be replaced by any component that can perform the same function. The disclosed aspects can also be implemented as instructions carried or stored on one or more or non-transitory computer-readable media, which can be read and executed by one or more processors. Such instructions can be referred to as computer program products. As discussed herein, computer-readable media means any medium that can be accessed by a computing device. As an example and not a limitation, computer-readable media can include computer storage media and communication media.

[0101] Furthermore, when reference is made herein to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0102] Although specific aspects of the present disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be limited, except as by the appended claims.

[0103] Example

[0104] Illustrative examples of the disclosed technology are provided below. Implementations of the technology may include one or more of the examples described below, and any combination thereof.

[0105] Example 1 is a test and measurement instrument comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to sense a voltage of the DUT, wherein the voltage sensor is configured to: measure a first set of voltages that vary over time using the voltage sensor when the current source outputs a first constant current to the DUT; measure a second set of voltages that vary over time using the voltage sensor when the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; and measure a third set of voltages that vary over time using the voltage sensor when the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; and one or more processors configured to execute code that causes the one or more processors to derive the capacitance of the DUT based on the first, second, and third constant currents and the first, second, and third sets of voltages as a function of time.

[0106] Example 2 is the test and measurement instrument of Example 1, wherein the DUT is a power device or a metal oxide semiconductor device.

[0107] Example 3 is the test and measurement instrument of Example 1 or Example 2, wherein the voltage sensor is configured to measure a second voltage when the current source outputs a second constant current to the DUT after the first voltage reaches a predetermined threshold.

[0108] Example 4 is the test and measurement instrument of any of Examples 1-3, wherein the voltage sensor is configured to measure a third voltage when the current source outputs a third constant current to the DUT after the second set of voltages reaches a predetermined threshold.

[0109] Example 5 is the test and measurement instrument of any of Examples 1-4, wherein the voltage sensor is configured to measure the first set of voltages until the first set of voltages reaches a predetermined threshold.

[0110] Example 6 is the test and measurement instrument of any of Examples 1-5, wherein the one or more processors are further configured to determine a device parameter of the DUT based on a capacitance of the DUT.

[0111] Example 7 is the test and measurement instrument of any of Examples 1-6, wherein the capacitance is a quasi-static capacitance of the DUT.

[0112] Example 8 is the test and measurement instrument of any of Examples 1-7, wherein the one or more processors are further configured to compensate for the one or more unwanted currents based on a leakage current of the DUT and a capacitance of the test fixture and cables.

[0113] Example 9 is the test and measurement instrument of any of Examples 1-8, wherein the one or more processors configured to derive the capacitance of the DUT involves using the following formula: C_m=I / (dV / dt).

[0114] Example 10 is a method for a test and measurement instrument, comprising: instructing a voltage sensor of the test and measurement instrument to measure a first set of voltage measurement values ​​that vary with time when a current source of the test and measurement instrument outputs a first constant current to a device under test (DUT) coupled to the test and measurement instrument; instructing the voltage sensor of the test and measurement instrument to measure a second set of voltage measurement values ​​that vary with time when the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instructing the voltage sensor of the test and measurement instrument to measure a third set of voltage measurement values ​​that vary with time when the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; and deriving a quasi-static capacitance of the DUT based on the second and third constant currents and the second and third sets of voltages as a function of time.

[0115] Example 11 is the method of Example 10, wherein the DUT is a power device or a metal oxide semiconductor device.

[0116] Example 12 is the method of Example 10 or Example 11, wherein deriving the capacitance of the DUT involves using the following formula: C_m=I / (dV / dt).

[0117] Example 13 is the method described in any of Examples 10-12, wherein instructing the voltage sensor of the test and measurement instrument to measure a second set of voltages that vary over time may include instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages that vary over time when the current source outputs a second constant current to the DUT after the first set of voltages reaches a user-defined threshold.

[0118] Example 14 is a method described in any of Examples 10-13, wherein instructing the voltage sensor of the test and measurement instrument to measure a third set of voltages that vary over time may include instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages that vary over time when the current source outputs a third constant current to the DUT after the second set of voltages reaches a second defined threshold.

[0119] Example 15 is the method of any of Examples 10-14, wherein instructing a voltage sensor of the test and measurement instrument to take a measurement may include instructing the voltage sensor of the test and measurement instrument to measure a first set of voltages that vary over time until the first set of voltages reaches a user-defined threshold.

[0120] Example 16 is the method of any of Examples 10-15, further comprising determining a device parameter of the DUT based on a capacitance of the DUT.

[0121] Example 17 is the method of any of Examples 10-16, wherein the capacitance of the DUT is a quasi-static capacitance of the DUT.

[0122] Example 18 is the method of any of Examples 10-17, further comprising compensating for unwanted leakage current of the DUT and capacitance of the test fixture and cables.

[0123] Example 19 is a test and measurement system comprising: a test and measurement instrument comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to sense a voltage of the DUT; and one or more processors configured to execute code that causes the one or more processors to: instruct the voltage sensor to measure a first set of voltages that vary over time when the current source outputs a first constant current to the DUT; instruct the voltage sensor to measure a second set of voltages that vary over time when the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instruct the voltage sensor to measure a third set of voltages that vary over time when the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; and derive the quasi-static capacitance of the DUT based on the second and third constant currents and the second and third sets of voltages as a function of time.

[0124] Example 20 is the test and measurement system of Example 19, wherein the one or more processors configured to derive the capacitance of the DUT involves using the following formula: C_m=I / (dV / dt).

[0125] Example 21 is a method for driving interface trap capacitance using a test and measurement instrument, comprising: generating a forward quasi-static capacitance scan and a reverse quasi-static capacitance scan using a current source and a voltage sensor of the test and measurement instrument, wherein the test and measurement instrument is configured to sense the voltage across a connected device under test (DUT); deriving an array of surface potential voltages for the forward quasi-static capacitance scan and the reverse quasi-static capacitance scan; interpolating the forward capacitance and the reverse capacitance of the DUT at each surface potential voltage based on the array of surface potential voltages for the forward quasi-static capacitance scan and the reverse quasi-static capacitance scan; subtracting the oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances to generate a forward-only quasi-static capacitance scan and a reverse-only quasi-static capacitance scan; and calculating the capacitance and interface trap density of the DUT based on the difference between the forward-only quasi-static capacitance scan and the reverse-only quasi-static capacitance scan as a function of the surface potential voltage.

[0126] Example 22 is the method described in Example 21, wherein generating a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep may include: deriving an array of a first voltage and time measurement using a voltage sensor when a current source outputs a first constant current to the DUT; deriving an array of a second voltage and time measurement using a voltage sensor when the current source outputs a second constant current to the DUT; deriving an array of a third voltage and time measurement using a voltage sensor when the current source outputs a third constant current to the DUT; and determining the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep based on the arrays of the second and third voltage and time measurements and the second and third constant currents.

[0127] Example 23 is the method of Example 21 or Example 22, wherein the DUT is a power device or a metal oxide semiconductor device.

[0128] Example 24 is a method described in any of Examples 21-23, wherein deriving an array of surface potential voltages may include: determining the oxide capacitance for a forward quasi-static capacitance scan and a reverse quasi-static capacitance scan; and calculating the array of surface potential voltages based on the total charge and the oxide capacitance.

[0129] Example 25 is the method of any of Examples 21-24, wherein deriving the array of surface potential voltages involves the following formula: V_s=V_g-Q / C_ox.

[0130] Example 26 is a method described in any of Examples 21-25, wherein interpolating the forward capacitance and reverse capacitance of the DUT at each surface potential voltage may include: determining the number of voltage steps; and performing linear interpolation on the forward quasi-static capacitance scan and the reverse quasi-static capacitance scan to extract the interpolated capacitance points.

[0131] Example 27 is the method of any of Examples 21-26, wherein subtracting the oxide capacitance involves the following equations: CfOnly=1 / (1 / CfDut-1 / Cox), and CrOnly=1 / (1 / CrDut-1 / Cox).

[0132] Example 28 is the method of any of Examples 21-27, wherein calculating the capacitance and the interface trap density of the DUT may include calculating the capacitance due to trapped charge based on the gate area.

[0133] Example 29 is the method of any of Examples 21-28, wherein calculating the capacitance and the interface trap density of the DUT may include calculating the interface trap density based on a gate area and a total charge.

[0134] Example 30 is a test and measurement system comprising: a current source configured to output a current; a voltage sensor configured to sense a voltage through a connected device under test (DUT); and one or more processors configured to execute code that causes the one or more processors to: generate a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep using the current source and the voltage sensor; derive an array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; interpolate a forward capacitance and a reverse capacitance of the DUT at each surface potential voltage based on the array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; subtract an oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances; and calculate a capacitance and an interface trap density of the DUT based on the difference between the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep as a function of the surface potential voltage.

[0135] Example 31 is the test and measurement system of Example 30, wherein the current source is a direct current source.

[0136] Example 32 is the test and measurement system of Example 30 or Example 31, wherein the DUT is a power device or a metal oxide semiconductor device.

[0137] Example 33 is a test and measurement instrument as described in any of Examples 30-32, wherein the one or more processors configured to derive an array of surface potential voltages are further configured to: determine the oxide capacitance for a forward quasi-static capacitance scan and a reverse quasi-static capacitance scan; and calculate the array of surface potential voltages based on the total charge and the oxide capacitance.

[0138] Example 34 is a test and measurement system as described in any of Examples 30-33, wherein the one or more processors configured to interpolate the forward capacitance and reverse capacitance of the DUT at each surface potential voltage are further configured to: determine the number of voltage steps; and perform linear interpolation on the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep to extract the interpolated capacitance points.

[0139] Example 35 is the test and measurement system of any of Examples 30-34, wherein the one or more processors configured to calculate capacitance and interface trap density of the DUT are further configured to calculate capacitance due to trapped charge based on gate area.

[0140] Example 36 is the test and measurement system of any of Examples 30-35, wherein the one or more processors configured to calculate capacitance and interface trap density of the DUT are further configured to calculate the interface trap density based on gate area and total charge.

[0141] The previously described versions of the disclosed subject matter have many advantages that are described or will be apparent to those of ordinary skill in the art. Even so, these advantages or features are not required in all versions of the disclosed apparatus, system, or method.

[0142] In addition, this written description refers to specific features. It is to be understood that the disclosures in this specification include all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, that feature may also be used in the context of other aspects and examples to the extent possible.

[0143] Furthermore, when reference is made herein to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0144] Although specific examples of the present invention have been illustrated and described for purposes of illustration, it will be understood that various modifications can be made without departing from the spirit and scope of the invention. Accordingly, the present invention should not be limited except as by the appended claims.

Claims

1. A test and measurement instrument comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to sense a voltage of the DUT, wherein the voltage sensor is configured to: When the current source outputs a first constant current to the DUT, a voltage sensor is used to measure a first set of voltages that vary with time; When the current source outputs a second constant current to the DUT, the voltage sensor is used to measure a second set of voltages that vary with time, the second constant current having a different polarity than the first constant current; as well as When the current source outputs a third constant current to the DUT, using the voltage sensor to measure a third set of voltages that change with time, the third constant current having the same polarity as the first constant current; as well as One or more processors configured to execute code that causes the one or more processors to derive a capacitance of the DUT based on the first, second, and third constant currents and the first, second, and third sets of voltages as a function of time. 2 . The test and measurement instrument according to claim 1 , wherein the DUT is a power device or a metal oxide semiconductor device. 3 . The test and measurement instrument of claim 1 , wherein the voltage sensor is configured to measure the second voltage when the current source outputs a second constant current to the DUT after the first voltage reaches a predetermined threshold. 4 . The test and measurement instrument of claim 1 , wherein the voltage sensor is configured to measure a third set of voltages when the current source outputs a third constant current to the DUT after the second voltage reaches a predetermined threshold. 5 . The test and measurement instrument of claim 1 , wherein the voltage sensor is configured to measure the first set of voltages until the first set of voltages reaches a predetermined threshold. 6 . The test and measurement instrument of claim 1 , wherein the one or more processors are further configured to determine a device parameter of the DUT based on a capacitance of the DUT.

7. The test and measurement instrument of claim 1 , wherein the capacitance is a quasi-static capacitance of the DUT.

8. The test and measurement instrument of claim 1, wherein the one or more processors are further configured to compensate for the one or more unwanted currents based on a leakage current of the DUT and a capacitance of the test fixture and cables.

9. The test and measurement instrument of claim 1 , wherein the one or more processors configured to derive the capacitance of the DUT involves using the following formula:

10. A method for testing and measuring an instrument, comprising: instructing a voltage sensor of the test and measurement instrument to measure a first set of voltage versus time measurements when a current source of the test and measurement instrument outputs a first constant current to a device under test (DUT) coupled to the test and measurement instrument; instructing a voltage sensor of the test and measurement instrument to measure a second set of voltage versus time measurements when the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instructing a voltage sensor of the test and measurement instrument to measure a third set of voltage versus time measurements when the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; as well as A quasi-static capacitance of the DUT is derived based on the second and third constant currents and the second and third sets of voltages as a function of time. The method according to claim 10 , wherein the DUT is a power device or a metal oxide semiconductor device.

12. The method of claim 10 , wherein instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages that vary over time comprises instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages that vary over time when the current source outputs a second constant current to the DUT after the first voltage reaches a user-defined threshold.

13. The method of claim 10 , wherein instructing a voltage sensor of the test and measurement instrument to measure a third set of voltages that vary over time comprises instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages that vary over time when the current source outputs a third constant current to the DUT after the second set of voltages reaches a second defined threshold.

14. The method of claim 10, wherein instructing a voltage sensor of the test and measurement instrument to take a measurement comprises instructing the voltage sensor of the test and measurement instrument to measure a first set of voltages over time until the first voltage reaches a user-defined threshold.

15. The method of claim 10, further comprising determining a device parameter of the DUT based on a capacitance of the DUT. The method of claim 10 , wherein the capacitance of the DUT is a quasi-static capacitance of the DUT.

17. The method according to claim 10, further comprising: Compensate for unwanted leakage current from the DUT and the capacitance of the test fixture and cables.

18. The method of claim 11 , wherein deriving the capacitance of the DUT involves using the following formula:

19. A test and measurement system comprising: Test and measurement instruments, including: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to sense a voltage of the DUT; and One or more processors configured to execute code that causes the one or more processors to: Instructing the voltage sensor to measure a first set of voltages varying with time when the current source outputs a first constant current to the DUT; The instructing voltage sensor to measure a second set of voltages that vary with time when the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instructing the voltage sensor to measure a third set of voltages that vary with time when the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; and A quasi-static capacitance of the DUT is derived based on the second and third constant currents and the second and third sets of voltages as a function of time.

20. The test and measurement system of claim 19, wherein the one or more processors configured to derive the capacitance of the DUT involves using the following formula:

Images