Real random number generator and real random number generation method thereof
By adopting high-energy ion implantation process and anti-check disk pattern programming in memory cells, the problems of high cost and complexity of random number code generation in the existing technology are solved, random number code generation with high randomness and uniqueness is achieved, and system security is improved.
Patent Information
- Application Number
- CN202410448995.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-06
- Filing Date
- 2024-04-15
- Publication Date
- 2025-09-09
AI Technical Summary
It is difficult for existing technologies to effectively utilize physical unclonable functions to generate random number codes, and existing methods are costly and complex, making them difficult to be widely used to meet security needs.
The memory cell is manufactured by using a process with different ion implantation energies in the memory cell, and the random induced interference characteristics of the memory cell are improved by using a high-energy ion implantation process. A random number code is generated by combining the anti-check disk pattern programming operation, and is stored and generated through a memory control circuit.
The random number code generation with high randomness and uniqueness is achieved, the security of the system device is improved, and the process cost is reduced.
Smart Images
Figure CN120610682A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a random number generation technology, and in particular to a true random number generator and a true random number generation method adopted by the same. Background Art
[0002] In recent years, for security purposes, physical unclonable function (PUF) has been widely used in security product applications. Physical unclonable function is a program that can be used to create a unique random key for a physical entity (such as an integrated circuit). Generally speaking, physical unclonable function technology uses manufacturing variation in semiconductor chips to obtain a unique random code. Even if there are precise process steps to produce semiconductor chips, their random codes are almost impossible to copy and can be applied to a wide range of applications, such as component identification, security, and authentication. Therefore, how to effectively use physical unclonable function to generate random number codes is one of the key concerns of researchers in this field. Summary of the Invention
[0003] The present invention provides a true random number generator and a true random number generation method thereof, which can apply a specific bit of disturbance characteristics to a physical non-copyable function to generate a random number code.
[0004] The true random number generator of the present invention includes a random code generating element, a random code storage element, and a memory control circuit. The random code generating element includes a plurality of first memory cells for generating random code. The random code storage element includes a plurality of second memory cells for receiving and storing random code. The memory control circuit is coupled to the random code generating element and the random code storage element. The first memory cells are fabricated using a first ion implantation process, and the second memory cells are fabricated using a second ion implantation process. The first implantation energy used in the first ion implantation process is higher than the second implantation energy used in the second ion implantation process.
[0005] The present invention provides a true random number generation method applicable to a true random number generator including a random code generation element and a random code storage element. The random code generation element includes a plurality of first memory cells. The random code storage element includes a plurality of second memory cells. The true random number generation method includes the following steps: forming the plurality of first memory cells by a first ion implantation process; forming the plurality of second memory cells by a second ion implantation process, wherein a first implantation energy used in the first ion implantation process is higher than a second implantation energy used in the second ion implantation process; and storing the random code generated by the random code generation element in the random code storage element.
[0006] The present invention's true random number generator includes a random code generating element. The random code generating element comprises a plurality of memory cells. After performing a reverse check disk pattern programming operation, the logic values of some of the memory cells are randomly switched from a first logic value to a second logic value, thereby generating a random code. The memory cells are fabricated through an ion implantation process using ions that are prone to randomly inducing disturbance characteristics during programming, thereby having a high-density S / D junction.
[0007] Based on the above, the present invention's true random number generator and true random number generation method can utilize memory cell manufacturing process control to produce memory cells with higher implantation energy, thereby increasing the probability of random induced disturbance characteristics in the memory cells. This generates a random and unique random number factor code that can be used as a cryptographic key, thereby enhancing the security of the system device.
[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 A block diagram illustrating a true random number generator according to an embodiment of the present invention is shown;
[0010] Figure 2A An example of a check board bar (CKBDB) pattern according to an embodiment of the present invention is shown;
[0011] Figure 2B An example of a random number code according to an embodiment of the present invention is shown;
[0012] Figure 3 A schematic diagram showing a memory cell according to an embodiment of the present invention;
[0013] Figure 4A A schematic diagram showing a first bit line according to an embodiment of the present invention;
[0014] Figure 4B A schematic diagram showing a second bit line according to an embodiment of the present invention;
[0015] Figure 5 A flowchart showing the steps of a method for generating true random numbers according to an embodiment of the present invention. DETAILED DESCRIPTION
[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0017] Please refer to Figure 1 The true random number generator 100 of the present invention includes a random code generating element 110, a random code storing element 120, and a memory control circuit 130. The random code generating element 110 includes a plurality of first memory cells 112 arranged in an array. The first memory cells 112 are coupled to respective first bit lines BL1 and first word lines WL1.
[0018] The random code storage element 120 includes a plurality of second memory cells 122 arranged in an array. The second memory cells 122 are coupled to respective second bit lines BL2 and second word lines WL2. The second memory cells 122 can be non-volatile memory cells similar to the first memory cells 112, such as NOR flash memory cells or NAND flash memory cells. The second memory cells 122 and the first memory cells 112 can be located on the same chip, but they undergo different manufacturing processes.
[0019] The memory control circuit 130 is coupled to the random code generating element 110 and the random code storing element 120. The memory control circuit 130 may be, for example, a central processing unit (CPU), other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination thereof. Alternatively, the memory control circuit 130 may be a hardware circuit designed using a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented using a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).
[0020] In this embodiment, the memory control circuit 130 may perform an anti-check disk pattern programming operation on the first memory cell 112 of the random number code generating element 110. Specifically, the memory control circuit 130 may program the first memory cell 112 of the random number code generating element 110 in sequence from the smallest address. Figure 2AThe data of the reverse check disk pattern 200 is stored in each first memory cell 112. The reverse check disk pattern is characterized in that the data of the smallest address is "1" and the data values of two adjacent addresses are different, thus forming a data pattern of "1010101...".
[0021] However, the random number code generating element 110 is manufactured using the unique first ion implantation process of the present invention, which is prone to randomly inducing interference characteristics when being programmed. In other words, all the first memory cells 112 in the random number code generating element 110 are manufactured using the first ion implantation process using ions that are prone to randomly inducing interference characteristics when being programmed. Therefore, after performing the anti-check disk pattern programming operation, the logic values of some of the first memory cells 112 will randomly change from logic 1 to logic 0, so that the logic values of the first memory cells 112 arranged in an array will appear, for example, as follows: Figure 2B The random code 210 is shown. Accordingly, the first memory cell 112 constituting the random code generating element 110 has a characteristic of random data transition, and the random code generating element 110 can generate a random code according to the logic value of the first memory cell 112 .
[0022] Furthermore, the memory control circuit 130 can store the random code generated by the random code generation element 110 in the random code storage element 120. The random code storage element 120 can be used to receive and store the random code. In this way, the true random number generator 100 provided by the embodiment of the present invention can be used to generate a random code, which can be used as a cryptographic key to enhance the security of the system device.
[0023] The following uses the memory cell 300 to illustrate the schematic structure of the first memory cell 112 and the second memory cell 122. Figure 3 Memory cell 300 includes a gate 310, a well region 320, a source 330, and a drain 340. Gate 310 is coupled to a corresponding word line WL. A halo region 350_1 is formed near gate 310 at the end of source 330, and a halo region 350_2 is formed near gate 310 at the end of drain 340. During fabrication of memory cell 300, ion implantation is generally performed sequentially in the order of well region 320, halo regions 350_1 and 350_2, source 330, and drain 340. The structures of first memory cell 112 and second memory cell 122 can be considered to be the same as memory cell 300, for example.
[0024] In this embodiment, the first memory cell 112 is fabricated using a first ion implantation process. The second memory cell 122 is fabricated using a second ion implantation process. The first ion implantation process differs from the second ion implantation process in that a first implantation energy used in the first ion implantation process is higher than a second implantation energy used in the second ion implantation process.
[0025] Specifically, the first ion implantation process includes heavily doping the halo region of each first memory cell 112 with a first implantation energy. The first implantation energy is higher than the energy generally applied to the halo region for ion implantation. The higher the first implantation energy, the higher the randomness of the generated random number code. The dopant of the first implantation energy is, for example, a P-type trivalent element, preferably B+, and the energy range is, for example, 20 to 50 KeV. The ion concentration range in the halo region is, for example, greater than 1.2E13 cm -3 , preferably 1.2E13~1E14cm -3 , but the present invention is not limited thereto.
[0026] The second ion implantation process includes lightly doping the halo region of each second memory cell 122 with a second implantation energy. The second implantation energy is, for example, equal to the energy generally applied for ion implantation in the halo region.
[0027] In addition, the first ion implantation process further includes heavily doping the well region of each first memory cell 112 with a third implantation energy. The third implantation energy is higher than the energy generally applied to the well region for ion implantation. The higher the third implantation energy, the higher the randomness of the generated random number code. The dopant of the third implantation energy is, for example, a P-type trivalent element, preferably BF2, and the energy range is, for example, 30 to 60 KeV. The ion concentration range in the well region is, for example, greater than 1.5E13 cm -3 , preferably 1.5E13~1E14 cm -3 , but the present invention is not limited thereto.
[0028] The second ion implantation process further includes lightly doping the well region of each second memory cell 122 with a fourth implantation energy. The fourth implantation energy is, for example, equal to the energy generally applied to the well region during ion implantation.
[0029] Comparing the first memory cell 112 fabricated by the first ion implantation process with the second memory cell 122 fabricated by the second ion implantation process, the first memory cell 112 has a high-concentration S / D junction, with an ion concentration range greater than 1.2E13 cm -3 The ion concentration range in the well region is greater than 1.5E13 cm -3, so the junction leakage is large, the channel boosting capability is poor, and the probability of random induced interference characteristics increases. In addition, the second memory cell 122 has a shallower and lighter S / D junction, so the junction leakage is small, the channel boosting capability is improved, and the probability of random induced interference characteristics is reduced. In this way, the random code generation element 110 is prone to random induced interference characteristics when being programmed, and is suitable for generating random code with high randomness. The random code storage element 120 is suitable for storing data (random code).
[0030] It should be noted that since the first memory cell 112 and the second memory cell 122 can be located on the same chip, a photoresist mask can be used to shield the area surrounding the second memory cell 122 during the first ion implantation process, and a photoresist mask can be used to shield the area surrounding the first memory cell 112 during the second ion implantation process. Compared to conventional process steps, only one or two additional photoresist-related steps are required to fabricate the first memory cell 112 and the second memory cell 122, thereby reducing costs.
[0031] In addition, in one embodiment of the present invention, the probability of random induced disturbance characteristics can be increased by reducing the width of the word line coupling the memory cell, thereby generating a random number code with high randomness. Figure 4A FIG. 4 shows a schematic structure of a first word line WL1 coupled to a first memory cell 112 in the random number code generating element 110. Figure 4B FIG4 shows a schematic structure of the second word line WL2 coupled to the second memory cell 122 in the random code storage element 120. Figure 4B ,exist Figure 4A The width W1 of the first word line WL1 coupled to the gate 400 of the corresponding first memory cell 112 is significantly smaller than that in Figure 4B The width W2 of the second word line WL2 coupled to the gate 410 of the corresponding second memory cell 122 is shown in FIG. That is, when the circuits are laid out, the width W1 of the first word line WL1 is laid out to be smaller than the width W2 of the second word line WL2.
[0032] Since the width W1 of the first word line WL1 is smaller, the space between the two first word lines WL1 becomes larger. When performing the first ion implantation process, the first implantation energy E1 can more easily pass through the space between the two first word lines WL1 to dope the halo region of each first memory cell 112, thereby improving the effect of ion implantation.
[0033] In addition, since the width W2 of the second word line WL2 is larger, the space between the two second word lines WL2 becomes smaller. During the second ion implantation process, the second implantation energy E2 is less likely to pass through the space between the two second word lines WL2 to dope the halo region of each second memory cell 122, thereby reducing the effect of the ion implantation. In this way, the first memory cell 112 can also have a high-concentration S / D junction, and the ion concentration range in its halo region is greater than 1.2E13 cm -3 The ion concentration range in the well region is greater than 1.5E13 cm -3 , which also increases the probability of randomly induced interference characteristics.
[0034] Incidentally, the width W2 of the second word line WL2 is, for example, the width of a word line generally coupled to a memory cell storing data. The ratio of the width W1 to the width W2 is, for example, in the range of 0.95 to 0.8, but the present invention is not limited thereto.
[0035] Please also refer to Figure 1 and Figure 5 The true random number generation method of this embodiment can be applied to at least Figure 1 The true random number generator 100 of the embodiment includes the following steps. A plurality of first memory cells 112 are produced by a first ion implantation process (step S500). A plurality of second memory cells 122 are produced by a second ion implantation process, wherein the first implantation energy used in the first ion implantation process is higher than the second implantation energy used in the second ion implantation process (step S502). The random code generated by the random code generating element 110 is stored in the random code storage element 120 (step S504). The implementation details of the above steps S500, S502 and S504 can be referred to. Figures 1 to 4A 、 Figure 4B The embodiments of the present invention will not be described in detail here.
[0036] In summary, the present invention's true random number generator and method for generating true random numbers can be used to dope the halo and well regions of memory cells at higher implantation energies through process control of the memory cell. This allows for increased random induced disturbance (RID) characteristics in the memory cell by simply adding one or two additional photoresist-related steps. This generates random, unique codes that can be used as cryptographic keys, enhancing system security.
[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A true random number generator, characterized in that include: A random number code generating element includes a plurality of first memory cells for generating a random number code; A random number code storage element, comprising a plurality of second memory cells, for receiving and storing the random number code; as well as A memory control circuit is coupled to the random number code generating element and the random number code storing element, The plurality of first memory cells are manufactured through a first ion implantation process, and the plurality of second memory cells are manufactured through a second ion implantation process. A first implantation energy used in the first ion implantation process is higher than a second implantation energy used in the second ion implantation process.
2. The true random number generator according to claim 1, wherein The first ion implantation process includes: heavily doping the halo region of each of the plurality of first memory cells with the first implantation energy, The second ion implantation process includes: The halo region of each of the plurality of second memory cells is lightly doped with the second implantation energy.
3. The true random number generator according to claim 2, characterized in that The first ion implantation process further includes: heavily doping the well region of each of the plurality of first memory cells with a third implantation energy, The second ion implantation process further includes: The well region of each of the plurality of second memory cells is lightly doped with a fourth implantation energy, wherein the third implantation energy is higher than the fourth implantation energy.
4. The true random number generator according to claim 1, wherein: The plurality of first memory cells in the random number code generating element are respectively coupled to a plurality of first word lines, and the plurality of second memory cells in the random number code storing element are respectively coupled to a plurality of second word lines, and the widths of the plurality of first word lines are arranged to be smaller than the widths of the plurality of second word lines.
5. The true random number generator according to claim 1, wherein: The memory control circuit performs an anti-check disk pattern programming operation on the plurality of first memory cells of the random code generating element, so that the random code generating element generates the random code according to logic values of the plurality of first memory cells arranged in an array.
6. A true random number generation method, applicable to a true random number generator, wherein the true random number generator comprises a random number code generating element and a random number code storage element, the random number code generating element comprises a plurality of first memory cells, and the random number code storage element comprises a plurality of second memory cells, the true random number generation method being characterized by comprising: fabricating the plurality of first memory cells by a first ion implantation process; fabricating the plurality of second memory cells by a second ion implantation process, wherein a first implantation energy used in the first ion implantation process is higher than a second implantation energy used in the second ion implantation process; as well as The random number code generated by the random number code generating element is stored in the random number code storage element.
7. The method for generating true random numbers according to claim 6, wherein: The first ion implantation process includes: heavily doping the halo region of each of the plurality of first memory cells with the first implantation energy, The second ion implantation process includes: The halo region of each of the plurality of second memory cells is lightly doped with the second implantation energy.
8. The method for generating true random numbers according to claim 7, wherein: The first ion implantation process further includes: heavily doping the well region of each of the plurality of first memory cells with a third implantation energy, The second ion implantation process further includes: The well region of each of the plurality of second memory cells is lightly doped with a fourth implantation energy, wherein the third implantation energy is higher than the fourth implantation energy.
9. The method for generating true random numbers according to claim 6, wherein: The plurality of first memory cells in the random number code generating element are respectively coupled to a plurality of first word lines, and the plurality of second memory cells in the random number code storing element are respectively coupled to a plurality of second word lines. The true random number generating method further includes: The widths of the plurality of first word lines are arranged to be smaller than the widths of the plurality of second word lines.
10. The method for generating true random numbers according to claim 6, wherein: Also includes: An anti-check disk pattern programming operation is performed on the plurality of first memory cells of the random code generating element, so that the random code generating element generates the random code according to logic values of the plurality of first memory cells arranged in an array.
11. A true random number generator, characterized in that include: The random code generating element includes a plurality of memory cells. After performing an anti-check disk pattern programming operation, the logic values of some of the plurality of memory cells are randomly changed from a first logic value to a second logic value to generate a random code. The memory cells are manufactured by an ion implantation process using ions that are prone to randomly induce interference characteristics when being programmed, so as to have a high-concentration S / D junction.
12. The true random number generator according to claim 11, characterized in that The ion implantation process includes: The halo region of each of the plurality of memory cells is heavily doped, and the ion concentration range in the halo region of each of the plurality of memory cells is greater than 1.2E13 cm -3 .
13. The true random number generator according to claim 11, characterized in that The ion implantation process includes: The well region of each of the plurality of memory cells is heavily doped, and the ion concentration range in the well region of each of the plurality of memory cells is greater than 1.5E13 cm -3 .