Method, device and chip for supporting segmented cyclic redundancy check

Abstract

The disclosure discloses a method for supporting segmented cyclic redundancy check, comprising: in response to correctness of a first cyclic redundancy check performed on an encoding block by using a generator polynomial corresponding to the encoding block belonging to a transport block, performing a second cyclic redundancy check operation on the encoding block by using a generator polynomial corresponding to the transport block, obtaining a first result; performing third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transmission block and the length of the coding block by using a generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, and performing a fourth cyclic redundancy check operation on the result of the first operation by using a generator polynomial corresponding to the transmission block to obtain a partial result of the coding block in the cyclic redundancy check code of the whole transmission block; and performing second operation on each part result to obtain a cyclic redundancy check code of the whole transmission block.

Description

Technical Field

[0001] The present disclosure generally relates to the field of communication technology. More specifically, the present disclosure relates to a method, device, and chip that support segmented cyclic redundancy check. Background Art

[0002] Cyclic redundancy check (CRC) is a checksum technology widely used in network communications and data storage. It can detect errors that may occur during data transmission or storage, such as bit flips, bit loss, or out-of-order data. CRC adds checksums to the data so that the receiving end can verify the data for errors.

[0003] When transmitting large amounts of data, a segmented cyclic redundancy check (CRC) is often used. A transmission block is divided into multiple coded blocks, and a checksum is added to each coded block and the entire transmission block. If a coded block is transmitted incorrectly, it must be retransmitted and then rechecked upon receipt. Only after all coded blocks have passed the CRC can the transmission block be checked. This approach consumes excessive storage space and results in prolonged data transmission latency.

[0004] In view of this, there is an urgent need to provide a solution that supports segmented cyclic redundancy check to reduce the storage space occupied during data transmission and shorten the data processing time. Summary of the Invention

[0005] In order to at least solve one or more technical problems mentioned above, the present disclosure proposes a solution supporting segmented cyclic redundancy check in multiple aspects.

[0006] In a first aspect, the present disclosure provides a method for supporting segmented cyclic redundancy check, comprising: in response to a first cyclic redundancy check performed on a coding block using a generator polynomial corresponding to a transmission block being correct, performing a second cyclic redundancy check operation on the coding block using the generator polynomial corresponding to the transmission block to obtain a first result; performing a third cyclic redundancy check operation on parameters related to a position of the coding block in the transmission block and a length of the coding block itself using the generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, performing a fourth cyclic redundancy check operation on the result of the first operation using the generator polynomial corresponding to the transmission block to obtain a partial result of the cyclic redundancy check code of the coding block in the entire transmission block; and performing a second operation on each partial result to obtain a cyclic redundancy check code for the entire transmission block.

[0007] In some embodiments, in response to a first cyclic redundancy check error performed on a coding block using a generator polynomial corresponding to a coding block belonging to a transport block, the coding block with the first cyclic redundancy check error is retransmitted to perform the first cyclic redundancy check again on the retransmitted coding block; and while waiting for retransmission of the coding block with the first cyclic redundancy check error, the first cyclic redundancy check operation is continued on the next coding block following the coding block in the transport block.

[0008] In some embodiments, using a generator polynomial corresponding to the transport block, performing a third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transport block and the length of the coding block itself, to obtain a second result includes: performing a third operation on a second result of the third cyclic redundancy check operation on a previous coding block before the coding block and a second result of the third cyclic redundancy check operation on the initial coding block to obtain a third result; and performing a third cyclic redundancy check on the third result using the generator polynomial corresponding to the transport block to obtain the second result.

[0009] In some embodiments, the first operation is a modular two multiplication operation based on the first result and the second result.

[0010] In some embodiments, the second operation is a modulo-2 addition operation based on the partial results.

[0011] In some embodiments, the third operation is based on a modulo-two multiplication operation of a second result of a third cyclic redundancy check operation on a previous coded block preceding the coded block and a second result of a third cyclic redundancy check operation on an initial coded block.

[0012] In some embodiments, the second cyclic redundancy check operation and the third cyclic redundancy check operation are performed in parallel.

[0013] In a second aspect, the present disclosure provides a device supporting segmented cyclic redundancy check, including: a coding block check part, used to use a generator polynomial corresponding to a coding block belonging to a transmission block to perform a first cyclic redundancy check on the coding block; a position and length check part, used to use the generator polynomial corresponding to the transmission block to perform a third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transmission block and the length of the coding block itself, to obtain a second result; a transmission block check part, used to use the generator polynomial corresponding to the transmission block to perform a second cyclic redundancy check operation on the coding block to obtain a first result, perform a first operation on the first result and the second result, perform a fourth cyclic redundancy check operation on the result of the first operation using the generator polynomial corresponding to the transmission block, to obtain a partial result of the cyclic redundancy check code of the coding block in the entire transmission block, and perform a second operation on each partial result to obtain a cyclic redundancy check code for the entire transmission block.

[0014] In a third aspect, the present disclosure provides a chip comprising the device supporting segmented cyclic redundancy check as described above.

[0015] The above-described scheme supports segmented cyclic redundancy check (CRC). Because the CRC results for each transmission block are calculated segment by segment, compared to traditional schemes, only the intermediate CRC results of the transmission block need to be stored, rather than the entire transmission block data. This reduces the data storage capacity from millions of bits to tens of bits. Furthermore, accessing memory can be avoided, and the intermediate results can be stored directly in local registers. Local registers have extremely fast access speeds, enabling almost instant data access. In contrast, accessing memory requires additional time and power consumption, which can become a performance bottleneck for high-speed data transmission. By using local registers for storage, efficient data processing and computation can be achieved. Registers have a small footprint and low power consumption, so they do not significantly impact the chip's area and energy performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an illustrative and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0017] Figure 1 A schematic diagram showing the process of segmenting a transmission block during data transmission is shown;

[0018] Figure 2 A schematic flow chart of a method for supporting segmented cyclic redundancy check according to an embodiment of the present disclosure is shown;

[0019] Figure 3 A schematic flow chart showing a method for retransmitting a coding block according to an embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic flow chart for iteratively obtaining a second result is shown;

[0021] Figure 5 A schematic diagram of a device supporting segmented cyclic redundancy check according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0023] It should be understood that the terms “include” and “comprising” used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0025] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0026] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0027] Cyclic Redundancy Check (CRC) is a widely used checksum technology in network communications and data storage. It can be used to detect errors that may occur during data transmission or storage, such as bit flips, bit loss, or out-of-order errors. CRC adds redundant bits (also called checksums) to the data so that the receiving end can verify the data.

[0028] The CRC principle is to generate a checksum using polynomial division. Before sending data, the sender processes the data according to a pre-agreed generator polynomial to generate a checksum with a fixed number of bits. After receiving the data, the receiver divides the received data again using the same generator polynomial and compares the remainder with the received checksum. If the two are the same, it indicates that no errors occurred during data transmission or storage. If they are different, the data may have errors and require retransmission or other error handling mechanisms.

[0029] Because the amount of data to be transmitted in some data transmission scenarios is large, it is necessary to wait for the entire data block to be transmitted before performing a cyclic redundancy check. If the CRC check result indicates that an error occurred during transmission, the entire data block needs to be retransmitted, which has a certain impact on the timeliness of network communication. Therefore, for larger data blocks, in addition to performing a CRC check on the data block itself, it can be segmented and a CRC check is performed on each segment. That is, the entire data block is used as a transport block (TB) and a TB-CRC is added. In addition, the transport block is divided into multiple parts, each of which is a code block (CB), and a CB-CRC is added to each CB. In this way, if the CRC check result of a CB indicates that an error occurred during transmission, the CB can be retransmitted; if the TB-CRC check result indicates that an error occurred during transmission, the TB needs to be retransmitted, that is, all CBs of the TB need to be retransmitted. Since CRC check has been performed on each CB with a smaller amount of data and retransmission and re-CRC check are performed when the result indicates a transmission error, the accuracy of the entire data block obtained in the end is greatly improved, that is, the final TB-CRC check result shows that the probability of correct transmission is greatly improved, that is, the probability of not needing to retransmit the entire data block is greatly improved.

[0030] Figure 1 The figure shows a schematic diagram of the process of segmenting a transmission block during data transmission.

[0031] like Figure 1As shown, first, when a transmission block 201 needs to be sent, a cyclic redundancy check code: TB-CRC 202 is generated and added to the transmission block 201, and the TB-CRC 202 is added to the end of the transmission block 201. The TB-CRC 202 is used by the receiver to check whether the transmission block 201 has a transmission error.

[0032] Then, the transmission block 201 and the TB-CRC 202 are divided into three coding blocks 203-1, 203-2, and 203-3, and a cyclic redundancy check code CB-CRC 204-1, 204-2, and 204-3 is added to each coding block 203-1, 203-2, and 203-3 respectively. The CB-CRC 204-1, 204-2, and 204-3 are added to the end of the coding blocks 203-1, 203-2, and 203-3 respectively. The CB-CRC 204-1, 204-2, and 204-3 are used by the receiver to check whether the coding blocks 203-1, 203-2, and 203-3 have transmission errors.

[0033] It can be understood that dividing the transport block into three coding blocks as described above is only an example. In practice, the transport block can be divided into more coding blocks.

[0034] Generally speaking, for a transport block, the generator polynomial used to generate the TB-CRC is different from the generator polynomial used to generate the CB-CRC; the generator polynomials used to generate the CB-CRC of different coding blocks are generally the same.

[0035] Of course, those skilled in the art will appreciate that, for a transport block, the generator polynomial used to generate the TB-CRC may also be the same as the generator polynomial used to generate the CB-CRC.

[0036] Figure 2 A schematic flow chart of a method for supporting segmented cyclic redundancy check according to an embodiment of the present disclosure is shown.

[0037] like Figure 2 As shown, the method first performs a first cyclic redundancy check on a coding block using a generator polynomial corresponding to a coding block belonging to a transport block at step S210, and in response to the first cyclic redundancy check being correct, performs the next step S220.

[0038] In the disclosed embodiment, when a coding block CBn of a transport block TB is received, a first cyclic redundancy check is performed on the coding block CBn using the generator polynomial corresponding to the coding block CBn belonging to the transport block TB. When the first cyclic redundancy check is correct, the next step S220 is performed on the coding block CBn. Since each coding block may have errors during transmission, a cyclic redundancy check needs to be performed on each coding block. When the cyclic redundancy check result corresponding to the coding block is correct, the coding block no longer needs to be retransmitted. As described above, the specific CRC check process is to divide the received data using the generator polynomial to obtain the corresponding remainder. The obtained remainder is then compared with the received check code. If the two are the same, it indicates that no errors occurred during the data transmission or storage process; if the two are different, it indicates that there may be errors in the data.

[0039] Then, at step S220, a second cyclic redundancy check operation is performed on the coding block using a generator polynomial corresponding to the transmission block to obtain a first result.

[0040] In the disclosed embodiment, a second cyclic redundancy check operation is performed on the coded block CBn that passes the first cyclic redundancy check, thereby obtaining a first result. That is, a division operation is performed on the data of the coded block CBn using the generator polynomial of the transport block TB to obtain a corresponding remainder.

[0041] Next, at step S230, a generator polynomial corresponding to the transport block is used to perform a third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transport block and the length of the coding block itself to obtain a second result.

[0042] In the disclosed embodiment, 2^nk is used to represent parameters related to the position of each coding block within the entire transport block and the length of each coding block itself, where n represents the position of each coding block within the entire transport block, and k represents the length of each coding block. A third cyclic redundancy check operation is performed on 2^nk using the generator polynomial of the transport block TB to obtain the second result. Specifically, 2^nk is divided by the generator polynomial of the transport block TB to obtain the corresponding remainder.

[0043] Generally, for a transport block, the length k of each coding block therein is the same.

[0044] Next, at step S240 , a first operation is performed on the first result and the second result.

[0045] In the disclosed embodiment, a first operation is performed on the first result and the second result of the coding block CBn. For example, the first operation is a modular two multiplication operation based on the first result and the second result of the coding block CBn.

[0046] Then, at step S250, a fourth cyclic redundancy check operation is performed on the result of the first operation using a generator polynomial corresponding to the transport block to obtain a partial result of the cyclic redundancy check code of the coded block in the entire transport block.

[0047] In the disclosed embodiment, a generator polynomial corresponding to the transport block TB is used to perform a fourth cyclic redundancy check operation on the result of the modulo-two multiplication operation on the first result and the second result of the coding block CBn to obtain a partial result of the cyclic redundancy check code of the coding block CBn in the entire transport block TB.

[0048] Finally, at step S260, a second operation is performed on each partial result to obtain a cyclic redundancy check code of the entire transmission block.

[0049] For example, a modulo-2 addition operation is performed on a partial result of each coding block CB in the cyclic redundancy check code of the entire transport block TB, thereby obtaining the cyclic redundancy check code of the entire transport block TB.

[0050] In one implementation scenario, a modulo-2 addition operation can be iteratively performed on the partial result of coding block CBn and the partial result of coding blocks CB1 to CBn-1 in the cyclic redundancy check code of the entire transmission block TB, thereby obtaining the cyclic redundancy check code of the entire transmission block.

[0051] Because the cyclic redundancy check (CRC) results for each transmission block are calculated segment by segment, compared to traditional solutions, only the intermediate CRC results of the transmission block need to be stored, rather than the entire transmission block data. This reduces the data storage requirement from millions of bits to tens of bits. Furthermore, intermediate results can be stored directly in local registers, avoiding memory access. Local registers offer extremely fast access speeds, enabling almost instant data access. In contrast, accessing memory requires additional time and power consumption, which can become a performance bottleneck for high-speed data transmission. Using local registers for storage enables efficient data processing and computation. Registers have a small footprint and low power consumption, so they do not significantly impact the chip's area and energy performance.

[0052] In addition, when a coding block is transmitted incorrectly during the transmission process, a strategy is generally adopted to retransmit the coding block, and while retransmitting the coding block, a cyclic redundancy check is continued on the next coding block. This can avoid waiting for the retransmitted coding block and perform cyclic redundancy checks on other coding blocks in parallel.

[0053] Figure 3 A schematic flowchart of a method for retransmitting a coding block according to an embodiment of the present disclosure is shown.

[0054] like Figure 3As shown, at step 310, method 300, in response to a first cyclic redundancy check error performed on a coding block using a generator polynomial corresponding to the coding block belonging to a transport block, retransmits the coding block with the first cyclic redundancy check error, and performs the first cyclic redundancy check again on the retransmitted coding block. In the disclosed embodiment, when the nth coding block CBn is transmitted in error, the erroneous coding block CBn is ignored and the coding block CBn is retransmitted.

[0055] Next, at step S320, while waiting for the retransmission of the coded block with the first cyclic redundancy check error, the first cyclic redundancy check operation is continued on the next coded block following the coded block in the transport block. In the disclosed embodiment, while waiting for the retransmission of the nth coded block CBn, the first cyclic redundancy check operation is continued on the (n+1)th coded block.

[0056] While waiting for the correct coded block to be retransmitted, a first CRC check is performed on subsequent coded blocks, thereby improving the efficiency of data processing.

[0057] According to an embodiment of the present disclosure, in method 200 , the operation of obtaining the second result in step S230 is performed iteratively. Figure 4 A schematic flow chart for iteratively obtaining a second result is shown.

[0058] like Figure 4 As shown, at step S410, method 400 performs a third operation on the second result of the third cyclic redundancy check operation on the previous coded block before the coded block and the second result of the third cyclic redundancy check operation on the initial coded block to obtain a third result.

[0059] In the disclosed embodiment, a third cyclic redundancy check operation is performed on a parameter 2^k related to the position of the first coding block CB1 in the transport block TB and the length of the coding block CB1 itself, to obtain a second result 2^k_result of the coding block CB1, that is, the initial second result, and 2^k_result is stored; a third cyclic redundancy check operation is performed on a parameter 2^2k related to the position of the second coding block CB2 in the transport block TB and the length of the coding block CB2 itself, to obtain a second result 2^2k_result of the coding block CB2, and a third operation is performed on 2^k_result and 2^2k_result to obtain a third result of the third cyclic redundancy check for parameters related to the position of the third coding block in the transport block TB and the length of the coding block CB3 itself. By analogy, a third result of the third cyclic redundancy check for parameters related to the position of the nth coding block in the transport block TB and the length of the coding block CBn itself can be obtained.

[0060] The third operation is to perform a modulo-two multiplication operation on the second result 2^(n-1)k_result of the coding block CB(n-1) and the initial second result 2^k_result to obtain a third result corresponding to the nth coding block.

[0061] Next, at step S420, a third cyclic redundancy check is performed on the corresponding third result using the generator polynomial corresponding to the transport block to obtain a corresponding second result. In the disclosed embodiment, a third cyclic redundancy check is performed on the third result for the coding block CB using the generator polynomial of the transport block TB to obtain a corresponding second result.

[0062] In order to implement the above-mentioned method of supporting segmented cyclic redundancy check, in an embodiment of the present disclosure, a device supporting segmented cyclic redundancy check is also provided. Figure 5 A schematic diagram of a device 500 supporting segmented cyclic redundancy check according to an embodiment of the present disclosure is shown. The device 500 may be located in, for example, a communication processing chip. Alternatively, the device 500 may be located in, for example, a communication processing board.

[0063] like Figure 5 As shown, the device 500 includes a coding block check part 510, a transmission block check part 520, and a position and length check part 530.

[0064] Among them, the coding block check part 510 is a cyclic redundancy check unit CRC_unit, called the first cyclic redundancy check unit, which is used to perform a first cyclic redundancy check on the coding block. When the coding block CBn is received, the first cyclic redundancy check is performed on the coding block CBn using the generating polynomial corresponding to the coding block CBn belonging to a transport block. In response to the first cyclic redundancy check being correct, the coding block CBn is output to perform the next operation on the coding block CBn.

[0065] More specifically, the position and length check section 530 is configured to perform a third cyclic redundancy check (CRC) operation on parameters related to the position of the coding block CBn within the transport block TB and the length of the coding block CBn itself. This third CRC operation is performed using a generator polynomial corresponding to the transport block TB to obtain a corresponding second result. The position and length check section 530 includes a second CRC check unit 531, an initial second result storage unit 532, an iterative second result storage unit 533, and a second modulo-2 multiplier 534.

[0066] The second cyclic redundancy check unit 531 is configured to perform a third cyclic redundancy check to obtain a corresponding second result. The initial second result storage unit 532 is configured to store the CRC second result of the position and length information (e.g., 2^k) of the first coding block CB1 to provide the 2^k second result when calculating the CRC second results of other coding blocks.

[0067] The iterative second result storage unit 533 is used to store the corresponding second result of each coding block. In addition, the second result of the previous coding block of the coding block that does not need to be retransmitted can be deleted. The second modulo-2 multiplier 534 is used to perform a modulo-2 multiplication on the second result stored in the initial second result storage unit 532 and the corresponding second result stored in the iterative second result storage unit 533 to obtain a corresponding third result, and output the third result as the input of the second cyclic redundancy check unit 531. For example, the second modulo-2 multiplier 534 performs a modulo-2 multiplication on the second result 2^(n-1)k_result of the coding block CB(n-1) and the initial second result 2^k_result to obtain the third result corresponding to the nth coding block, and uses it as the input of the second cyclic redundancy check unit 531 to generate the second result corresponding to the coding block CBn.

[0068] The transport block TB check part 520 is used to use a generating polynomial corresponding to the transport block to perform a second cyclic redundancy check operation on the coding block to obtain a first result, perform a first operation on the first result and the second result, use the generating polynomial corresponding to the transport block to perform a fourth cyclic redundancy check operation on the result of the first operation to obtain a partial result of the cyclic redundancy check code of the coding block in the entire transport block; and perform a second operation on each partial result to obtain a cyclic redundancy check code for the entire transport block.

[0069] More specifically, the transport block TB check section 520 includes a third cyclic redundancy check (CRC) unit 521, a first modulo-2 multiplier 522, a fourth CRC unit 525, a modulo-2 adder 523, and a partial result buffer unit 524. The third CRC unit 521 is configured to perform a second CRC operation on the coded block CBn using a generator polynomial corresponding to the transport block TB to obtain a first result. The first modulo-2 multiplier 522 is configured to perform a modular-2 multiplication operation (i.e., a first operation) on the first result generated by the third CRC unit 521 and the corresponding second result output by the iterative second result storage unit 533, thereby obtaining a result of the first operation. The fourth CRC unit 525 is configured to perform a fourth CRC operation on the result of the first operation using a generator polynomial corresponding to the transport block TB to obtain a partial result of each coded block in the CRC code of the entire transport block. The modulo-2 adder 523 is used to perform a modulo-2 addition operation, that is, a second operation, on the partial result of a coding block generated each time by the fourth cyclic redundancy check unit 525 in the cyclic redundancy check code of the entire transmission block and the partial result in the partial result cache unit 524, and store the result of the second operation in the partial result cache unit 524 for use each time the modulo-2 adder 523 performs the second operation.

[0070] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many modifications, changes, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for supporting segmented cyclic redundancy check, comprising: In response to a first cyclic redundancy check performed on a coding block belonging to a transport block using a generator polynomial corresponding to the coding block being correct, performing a second cyclic redundancy check operation on the coding block using a generator polynomial corresponding to the transport block to obtain a first result; performing a third cyclic redundancy check operation on parameters respectively related to a position of the coding block in the transmission block and a length of the coding block using a generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, and performing a fourth cyclic redundancy check operation on the result of the first operation using a generator polynomial corresponding to the transport block to obtain a partial result of a cyclic redundancy check code of the coded block in the entire transport block; as well as A second operation is performed on each partial result to obtain a cyclic redundancy check code of the entire transmission block.

2. The method according to claim 1, further comprising: In response to a first cyclic redundancy check error on a coding block using a generator polynomial corresponding to the coding block belonging to a transport block, retransmitting the coding block with the first cyclic redundancy check error to perform the first cyclic redundancy check again on the retransmitted coding block; as well as While waiting for the retransmission of the coded block with the first cyclic redundancy check error, the first cyclic redundancy check operation is continued to be performed on the next coded block following the coded block in the transmission block.

3. The method according to claim 1, wherein Performing a third cyclic redundancy check operation on parameters respectively related to a position of the coding block in the transmission block and a length of the coding block using a generator polynomial corresponding to the transmission block, to obtain a second result includes: performing a third operation on a second result of the third cyclic redundancy check operation performed on a previous coded block before the coded block and a second result of the third cyclic redundancy check operation performed on the initial coded block to obtain a third result; A third cyclic redundancy check is performed on the third result using a generator polynomial corresponding to the transmission block to obtain the second result.

4. The method according to claim 1, wherein The first operation is a modular two multiplication operation based on the first result and the second result.

5. The method according to claim 1, wherein The second operation is a modulo-2 addition operation based on each partial result.

6. The method according to claim 3, wherein: The third operation is based on a modulo-two multiplication operation of a second result of a third cyclic redundancy check operation performed on a previous coded block before the coded block and a second result of a third cyclic redundancy check operation performed on an initial coded block.

7. The method according to claim 1, wherein The second cyclic redundancy check operation and the third cyclic redundancy check operation are performed in parallel.

8. A device supporting segmented cyclic redundancy check, comprising: A coding block check unit, configured to perform a first cyclic redundancy check on a coding block using a generator polynomial corresponding to a coding block belonging to a transport block; a position and length check unit, configured to perform a third cyclic redundancy check operation on parameters respectively related to a position of the coding block in the transmission block and a length of the coding block itself, using a generator polynomial corresponding to the transmission block, to obtain a second result; The transport block check section is configured to perform a second cyclic redundancy check operation on the coded block using a generator polynomial corresponding to the transport block to obtain a first result, perform a first operation on the first result and the second result, perform a fourth cyclic redundancy check operation on the result of the first operation using a generator polynomial corresponding to the transport block to obtain a partial result of the cyclic redundancy check code of the coded block in the entire transport block, and perform a second operation on each partial result to obtain a cyclic redundancy check code for the entire transport block.

9. A chip comprising the device supporting segmented cyclic redundancy check according to claim 8.

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