Program control flow protection system and method based on stack data confidentiality and integrity

Abstract

The application belongs to the technical field of information security of embedded systems, and specifically discloses a program control flow protection system and method based on stack data confidentiality and integrity. The application generates and manages a key stream while the special hardware is accessing the memory at the micro-architecture level, and realizes the fast encryption and decryption calculation of the key data of the stack through the XOR operation of the key stream and the stack data. The stack data confidentiality protection supports the burst transmission property of the AHB-Lite bus which depends on the stack data transmission, and reduces the execution overhead of the program control flow protection method. On the basis of data encryption, the stack data integrity verification architecture based on the MAC code calculates and checks the MAC code when the stack data is written and read, realizes the real-time detection of the tampering of the key data of the stack, and discovers the program control flow anomaly in time. The application realizes the protection of the program control flow from the perspective of the stack data protection through the parallel encryption and decryption and integrity verification of the stack data.

Description

Technical Field

[0001] The present invention belongs to the technical field of embedded system information security, and in particular relates to a program control flow protection system and method based on stack data confidentiality and integrity. Background Art

[0002] Embedded systems have been widely used in numerous fields due to their numerous advantages, including low power consumption, high real-time performance, and miniaturization. However, due to the frequent interaction between embedded devices and the physical world, the probability of encountering security risks has greatly increased, and the consequences of attacks and damage have become increasingly serious. Therefore, the information security of embedded systems has become a focus of public attention.

[0003] Most embedded device programs are written in C, but C lacks support for program memory edge detection. This allows attackers to exploit stack overflows, integer overflows, and format character overflows to analyze stack storage data, maliciously tamper with program control flow data, and change the program execution sequence, thereby launching malicious attacks on critical devices and systems. This type of attack, which exploits stack overflows to change the program execution sequence, is called a control flow hijacking attack.

[0004] There are currently two main approaches to control flow hijacking attacks: software-based and hardware-based. The greater the security of software-based control flow protection, the greater the performance overhead. Furthermore, software-based control flow protection relies on program source code, making it less universal. The code instrumentation tools they use inherently carry certain security risks, posing a potential threat to software-implemented control flow protection.

[0005] Hardware-based control flow protection methods overcome some of the shortcomings of software-based control flow protection methods. Hardware-implemented control flow protection methods not only effectively reduce processor performance overhead but also enhance security. Some solutions can also eliminate reliance on program source code, demonstrating good universal applicability. However, hardware-based control flow protection carries significant hardware resource overhead, and related research still relies on source code and executable binaries. Furthermore, these methods typically only respond to control flow hijacking attacks and cannot proactively defend against unknown risks.

[0006] In this context, it becomes particularly important to design a program control flow protection method that is independent of source code dependence, has low performance and resource overhead, and can monitor program control flow anomalies in real time. Summary of the Invention

[0007] The purpose of the present invention is to propose a program control flow protection system based on the confidentiality and integrity of stack data, aiming to achieve program control flow protection with low performance and resource overhead. Through parallel encryption and decryption and integrity verification of stack data, it gets rid of the dependence on source code and can monitor program control flow anomalies in real time.

[0008] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0009] A program control flow protection system based on stack data confidentiality and integrity, including a processor, an AHB-Lite bus, a stack, a stack data confidentiality protection unit, and a stack data integrity verification unit;

[0010] The processor is used to access data addresses, read and write control signals, write stack data and transmit them to the stack data confidentiality protection unit and the stack data integrity verification unit;

[0011] The stack data confidentiality protection unit determines the base address of the memory data accessed based on the read / write burst control signal sent by the processor. The stack data confidentiality protection unit generates an encryption algorithm key internally to encrypt the stack data written on the AHB-Lite bus and decrypt the stack data read out.

[0012] The decrypted read stack data and the encryption algorithm key are simultaneously transmitted to the stack data integrity verification unit. The stack data integrity verification unit verifies the integrity of the stack data by calculating the MAC during writing and checking the MAC during reading. When an error is detected, the program execution is suspended.

[0013] In addition, the present invention also proposes a program control flow protection method based on stack data confidentiality and integrity, which corresponds to the above-mentioned program control flow protection system based on stack data confidentiality and integrity. The method adopts the following technical solutions:

[0014] A program control flow protection method based on stack data confidentiality and integrity includes the following steps:

[0015] Step 1. Configure the startup file, enable the processor's data cache, and set the write policy and capacity.

[0016] Step 2. After power-on initialization, the random number generator module uses the Arbiter PUF structure to generate keys for the stack data confidentiality protection unit and the stack data integrity verification unit.

[0017] Step 3. Collect the bus control signals and data addresses of the processor accessing the stack, analyze the read and write burst control signals of the memory access, and calculate the base address of the memory access data;

[0018] Step 4. Determine encryption or decryption of the accessed data based on the bus control signal. Calculate the key stream using the base address of the accessed data. If the operation is encryption, proceed to step 5. If the operation is decryption, proceed to step 6. Otherwise, proceed to step 7.

[0019] Step 5. After the key stream is calculated, the written stack data is marked, compressed, and sent to the FIFO buffer module, which then encrypts the written stack data.

[0020] Step 6. After the key stream is calculated, the read stack data is marked, decrypted, and compressed before being sent to the FIFO buffer module.

[0021] Step 7. Execute step 3 and determine whether the FIFO buffer module is not empty. If it is not empty, execute step 8; otherwise, execute step 7.

[0022] Step 8. Calculate the MAC code for the decoded data to obtain the MAC code read / write flag of the decoded data. If the MAC code read / write flag indicates write is valid, proceed to step 9. If the MAC code read / write flag indicates read is valid, proceed to step 10.

[0023] Step 9. Store the calculated MAC code into the MAC code storage module according to the address of the decoded data;

[0024] Step 10. Verify the calculated MAC code with the MAC code stored in the MAC code storage module according to the address of the decoded data. If the verification passes, continue to step 3; otherwise, pause the processor execution.

[0025] The present invention has the following advantages:

[0026] As described above, the present invention proposes a program control flow protection system and method based on stack data confidentiality and integrity. This system protects the confidentiality of key stack data through a stack data confidentiality protection unit, effectively preventing malicious analysis of key control flow data. Furthermore, a stack data integrity verification unit verifies the integrity of key stack data, enabling real-time monitoring of program control flow anomalies. The present invention designs an Arbiter PUF structure for generating high-quality random numbers to enhance the computational security of the key stream. It supports and optimizes burst transmission of stack data over the AHB-Lite bus, effectively reducing the performance overhead of the protection method. By calculating the MAC code when writing stack data and verifying the MAC code when reading stack data, real-time detection of tampering with key stack data is achieved, thereby identifying possible program control flow anomalies. To further reduce the hardware overhead of the protection method, the present invention utilizes a lightweight hash algorithm based on a sponge structure for MAC calculation and generation. Computational efficiency and throughput are improved through round function reuse and a pipelined hash calculation design. The pipeline design significantly improves computational efficiency and data throughput, while round function reuse effectively optimizes hardware resource usage and reduces area overhead. The program control flow protection method based on stack data confidentiality and integrity proposed by the present invention can protect the program control flow with lower performance and implementation overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a structural diagram of the program control flow protection system based on stack data confidentiality and integrity of the present invention.

[0028] Figure 2 2 is a structural diagram of a stack data confidentiality protection unit in an embodiment of the present invention.

[0029] Figure 3 2 is a structural diagram of a stack data integrity verification unit in an embodiment of the present invention.

[0030] Figure 4 This is a flow chart of the program control flow protection method based on stack data confidentiality and integrity of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0032] Example 1

[0033] This embodiment 1 describes a program control flow protection system based on stack data confidentiality and integrity, which ensures program control flow security by protecting stack key data. By building dedicated hardware on the RISC-V processor SoC chip, the confidentiality of stack key data is protected, effectively preventing malicious analysis of control flow key data; and by verifying the integrity of stack key data, program control flow anomalies are monitored in real time.

[0034] The inventive concept of the program control flow protection system based on stack data confidentiality and integrity is as follows: To address the problem of stack data being maliciously analyzed and then used to launch control flow hijacking attacks, the present invention proposes a stack data confidentiality protection unit, which designs dedicated hardware at the micro-architecture level to realize the generation and management of the key stream while accessing the memory, and realizes the rapid encryption and decryption calculation of the stack key data through the XOR operation of the key stream and the stack data. In order to enhance the randomness of the key stream, an on-chip Arbiter PUF structure is designed to generate high-quality random numbers as the key of the encryption algorithm, thereby enhancing the calculation security of the key stream. To address the problem of program control flow attacks carried out by maliciously tampering with stack data, a stack data integrity verification unit based on MAC code is proposed. By calculating the MAC code when writing the stack data and verifying the MAC when reading it, real-time detection of stack key data tampering is achieved, thereby discovering possible program control flow anomalies.

[0035] The following is a detailed introduction to the program control flow protection system based on stack data confidentiality and integrity.

[0036] like Figure 1 As shown, the program control flow protection system based on stack data confidentiality and integrity in this embodiment 1 includes a processor, an AHB-Lite bus, a stack, a stack data confidentiality protection unit, and a stack data integrity verification unit.

[0037] The processor is used to access data addresses, read and write control signals, write stack data and transmit them to the stack data confidentiality protection unit and the stack data integrity verification unit.

[0038] The stack data confidentiality protection unit determines the base address of the memory data accessed according to the read / write burst control signal issued by the processor. The stack data confidentiality protection unit generates an encryption algorithm key internally to encrypt the written stack data on the AHB-Lite bus and decrypt the read stack data.

[0039] The decrypted read stack data and the encryption algorithm key are simultaneously transmitted to the stack data integrity verification unit. The stack data integrity verification unit verifies the integrity of the stack data by calculating the MAC during writing and checking the MAC during reading. When an error is detected, the program execution is suspended.

[0040] Specifically, such as Figure 2 As shown, the stack data confidentiality protection unit includes an address marking unit, a control state machine, a symmetric encryption algorithm module, a random number generator module and an incentive generation module.

[0041] The address tag unit is used to capture the data address and read / write burst control signals transmitted on the AHB-Lite bus, intercept the high 27-bit base address and expand it to 128 bits to mark the read and write operations.

[0042] The control state machine receives read / write control signals and determines encryption / decryption operations. It calculates the base address of the accessed data based on the address tag unit and generates control signals to activate the symmetric encryption algorithm module. This ultimately generates a key stream to encrypt data written to the stack and decrypt data read from the stack. The encryption algorithm key for the symmetric encryption algorithm module is generated by the random number generator module, whose input is derived from the round constant of the stimulus generation module.

[0043] Specifically, such as Figure 3 As shown, the stack data integrity verification unit includes a data compression module, a FIFO buffer module, a decoding unit, a MAC code calculation unit, a MAC code storage module and a MAC code verification module.

[0044] The data compression module receives read / write data and control signals, uses a counter to mark burst transmissions, and compresses them. The FIFO buffer module temporarily stores compressed data packets to address the mismatch between MAC calculations and AHB-Lite bus transmission rates.

[0045] The decoding unit reads and parses data from the FIFO buffer module and determines whether to execute the MAC code storage or verification process based on the MAC code read / write flag, i.e., the two most significant bits. In this embodiment, when the two most significant bits are 01, it indicates a write operation, and when the two most significant bits are 10, it indicates a read operation.

[0046] The MAC code calculation unit uses a lightweight hashing algorithm based on a sponge structure to concatenate the input data with the key to generate a MAC code. The MAC code storage module stores the MAC code of the written data according to the decoded address. The MAC code verification module compares the calculated MAC code with the corresponding value in the MAC code storage module. If they do not match, a detection error signal is triggered and CPU execution is suspended via the AHB-Lite bus, enabling real-time detection of stack data tampering.

[0047] Example 2

[0048] This embodiment 2 describes a program control flow protection method based on stack data confidentiality and integrity, which is implemented based on the program control flow protection system based on stack data confidentiality and integrity in the above embodiment 1.

[0049] like Figure 4 As shown, the program control flow protection method based on stack data confidentiality and integrity includes the following steps:

[0050] Step 1. Configure the startup file, enable the processor's data cache, and set the write policy and capacity.

[0051] This paper focuses on data cache capacity planning, with a preset capacity of 4KB. The data cache write strategy uses two strategies: write-back and write-allocate. The combination of these two strategies aims to optimize cache performance, reduce the number of data transfers between the cache and main memory, and ensure data consistency and integrity.

[0052] Taking the RISC-V processor implementation as an example, the RISC-V processor includes an extended status register and a hardware control register. For the RISC-V processor, the specific process of configuring the startup file is as follows:

[0053] Configure the processor's data cache and the extended status register, setting the PM bit of the extended status register to "1." When the PM bit is set to "1," the processor enters machine mode to execute programs. In machine mode, hardware control registers are configured to enable or disable the instruction and data caches, as well as configure write-back and write-allocate. Setting the data cache enable bits "DE," "WA," and "WB" to "1" turns on the data cache and enables write-back and write-allocate policies, respectively.

[0054] Step 2. After power-on initialization, the random number generator module uses the Arbiter PUF structure to generate keys for the stack data confidentiality protection unit and the stack data integrity verification unit.

[0055] The random number generator module uses the Arbiter PUF structure to generate random numbers. Using the Arbiter PUF structure as a random number generator can enhance the computational security of the key stream.

[0056] The process of using the random number generator module to generate the keys for the stack data confidentiality protection unit and the stack data integrity verification unit is as follows: the arbiter PUF structure generates round constants based on the excitation generation module, namely the Galvaro linear feedback shift register, and collects four round constants through a counter as the excitation input of the arbiter PUF structure. The output of the arbiter PUF structure is then collected through the counter and spliced ​​into a 128-bit wide output as the security key of the symmetric encryption algorithm AES, namely the key for the stack data confidentiality protection unit and the stack data integrity verification unit.

[0057] Specifically, the Arbiter PUF structure consists of multiple delay lines and an arbiter module. After power-on, the Galois linear feedback shift register serves as an excitation generation module to generate a random number with a bit width of 16 bits. Subsequently, a counter is used as the input of the selector to select a random number, which is latched by a latch and used as the excitation input of the arbiter module. Afterwards, the output result of the initial selector and the selection signal corresponding to the next selector serve as the input of the next-level selector, and are cascaded through the selectors of each level. When the number of levels is equal to 15, its output result is filtered by the D latch to obtain a final output result. The present invention selects the output results of the excitation generation module twice through a counter as the two excitation inputs of the subsequent arbiter module. The output data is selected by a counter, and the output results of the two arbiter modules are spliced ​​together to finally obtain a 32-bit wide random number. The output of the Arbiter PUF structure is then collected by the counter and spliced ​​into a 128-bit wide output as the key for the symmetric encryption algorithm AES.

[0058] Step 3. Collect the bus control signals and data addresses of the processor accessing the stack, analyze the read and write burst control signals of the memory access, and calculate the base address of the memory access data.

[0059] In step 3 of this embodiment, the write flag, data address, and burst transfer control bit of the processor accessing the stack data are obtained, the current processor reading and writing is determined based on the write flag and the burst transfer mode, and the high bit of the data memory access address is intercepted to obtain the memory access data address base address.

[0060] Specifically, the address tagging unit collects the bus control signals CPU_Write, CPU_Burst, and CPU_Wdata, as well as the data address CPU_Addr, sent by the processor. To ensure correct data encryption and decryption during continuous data transmission initiated by the AHB-Lite bus, the present invention incorporates a counter module into the address tagging unit to mark the data during burst transmission. After the key stream is generated, an XOR operation is performed on the marked data to achieve parallel and fast encryption and decryption operations.

[0061] First, the processor transfer operation is determined based on the high and low levels of CPU_Write and the value of CPU_Burst. When CPU_Write is high and CPU_Burst is 3'b101, the processor performs an 8-beat incremental burst write transfer operation on the stack data; when CPU_Write is low and CPU_Burst is 3'b100, the processor performs an 8-beat wraparound burst read transfer operation. If it is determined that the processor is performing an 8-beat incremental burst write transfer operation on the stack data, the address tag unit obtains the upper 27 bits of CPU_Addr as the base address for accessing the memory data, adds 5 bits of all 1 to the lower bits of the base address to expand it to 32 bits of data, and then repeatedly splices the data four times to expand it to 128 bits as the data input for the AES encryption algorithm to calculate the key stream of the data address.

[0062] At the same time, the data compression module in the stack data integrity verification module compresses the data using the read / write flags calculated by the address tag module. The compressed data is sent to the FIFO buffer module, and then the decoding module reads the data from the FIFO buffer module and decodes the buffered data.

[0063] Step 4. Determine the encryption or decryption operation of the accessed data based on the bus control signal, and calculate the key stream using the base address of the accessed data. If it is an encryption operation, execute step 5; if it is a decryption operation, execute step 6; otherwise, execute step 7.

[0064] In step 4 of this embodiment, the AES algorithm is used as the output function for key stream generation, a 32-bit random number generated by the ArbiterPUF structure is expanded to a 128-bit AES security key, and the key stream is calculated according to the access data base address.

[0065] A control state machine is defined to control the encryption and decryption operations of memory access data. The control state machine has three states: the initial state AES_IDL, the write data encryption state AES_En, and the read data decryption state AES_De.

[0066] The write enable flag and read enable flag are triggered based on the bus control signal sent by the processor. When the processor issues a write operation, the write enable flag is valid, the write data encryption state is entered, and step 5 is executed. When the processor issues a read operation, the read enable flag is valid, the read data decryption state is entered, and step 6 is executed. Otherwise, step 7 is executed.

[0067] Specifically, when encrypting bus data, a keystream must first be calculated for the data address sent by the processor. The AES encryption algorithm requires 12 clock cycles to complete a keystream calculation. Afterward, the read and write data is decrypted and encrypted to obtain the correct data. Therefore, data expansion support is required for data transmitted on the bus to allow for keystream calculation.

[0068] The present invention designs a control state machine to implement a key stream prefetch mechanism. By pulling down the HREADY signal of the AHB-Lite bus, a data transmission wait state is inserted, and the bus transmission cycle is automatically extended when the control state machine is not ready. The AHB-Lite bus adopts a master-slave architecture, and when the memory is used as a slave device, transmission flow control is implemented through the hready signal. According to the protocol specification, when the hready signal output by the slave device remains at a high level, it indicates that the current transmission cycle is completed normally. If the slave device sets the hready signal to a low level, the bus extension transmission mechanism is triggered. At this time, the AHB-Lite bus will automatically insert a wait cycle until the hready signal is pulled high again before continuing subsequent operations.

[0069] For the design of extended data encryption and decryption operations, the control state machine in the keystream generation controls the hready signal on the AHB-Lite bus. The control state machine has three states: the initial state AES_IDL, the write data encryption state AES_En, and the read data decryption state AES_De.

[0070] The specific process of encryption and decryption operations is as follows:

[0071] When the processor issues a read / write burst control signal, the address marking unit marks the access address of the current read / write data, performs data bit expansion on the access address of the current read / write data to 128 bits, and sends the read / write flag of the current read / write data to the control state machine; performs an XOR operation on the key stream and the access address of the current read / write data to complete the encryption and decryption of the data.

[0072] Step 5. After the key stream is calculated, the written stack data is marked, compressed, and sent to the FIFO buffer module, and then the written stack data is encrypted.

[0073] In the initial state, the hready signal = 1, and the aes_ld signal controlling the state machine calculation is 0. When the processor issues a write data operation, the write enable flag is enabled, and the write data encryption state is entered. At this time, the aes_ld signal is pulled high for one clock, and hready = 0, triggering the bus extension transmission mechanism, and AES performs key stream calculation operations. After key stream generation is completed, when aes_done_r = 2′b10, the hready signal is pulled high to terminate the bus extension transmission. The generated key stream is then XORed with the processor write data to complete the data encryption. After the hready signal is pulled high, the extended transmission mechanism ends, and the state machine enters the initial state AES_IDL.

[0074] Step 6. After the key stream calculation is completed, the read stack data is marked, decrypted, compressed, and sent to the FIFO buffer module.

[0075] The transition to the read data decryption extension is similar to the write data encryption state transition. When the processor issues a read data, the read enable flag is valid, and the read data decryption state is entered. At this time, the aes_ld signal is pulled high for one clock cycle, hready = 0, and AES calculates the key stream. After the key stream generation is completed, when aes_done_r == 2′b10, the hready signal is pulled high, and the generated key stream is XORed with the encrypted read data to complete the data decryption. At the same time, the hready signal is pulled high, indicating that the bus extension transfer operation has ended, and the state machine then enters the initial state AES_IDL.

[0076] Step 7. Execute step 3 and determine whether the FIFO buffer module is not empty. If it is not empty, execute step 8; otherwise, execute step 7.

[0077] The data compression module is responsible for compressing stack data accessed by the processor in burst mode via the AHB-Lite bus. When the stack data integrity verification unit begins operation, two counters, En_count and De_count, are defined to mark the unencrypted write data CPU_Wdata and decrypted read data CPU_Rdata transmitted by the processor during AHB-Lite bus burst transfers. The En_count and De_count-marked data, along with the data read and write flags, En_count, and De_count signals issued by the processor, are then fed into the data compression module as input. The data compression module uses the two counters to perform compression calculations on the marked write and read data in the burst transfers. The compression calculation results, combined with the read and write flags and the data address, are then concatenated and fed into the FIFO buffer module.

[0078] Step 8. Calculate the MAC code for the decoded data to obtain the MAC code read / write flag of the decoded data. If the MAC code read / write flag indicates that write is valid, execute step 9. If the MAC code read / write flag indicates that read is valid, execute step 10.

[0079] In this embodiment, in step 8, the first 32 bits of the decoded data are the compressed data to be calculated or verified, and bits 32 to 47 of the decoded data are the MAC code storage data address bits. The most significant two bits of the MAC code storage data address are used as the MAC code read / write flag bits. When the high bit of the MAC code read / write flag bit is 0 and the low bit is 1, it indicates that write is valid, and step 9 is executed. When the high bit of the MAC code read / write flag bit is 1 and the low bit is 0, it indicates that read is valid, and step 10 is executed.

[0080] Specifically, when the two most significant bits are 2'b01, it indicates write-valid, indicating that the MAC code of the data needs to be calculated and stored in the MAC code storage module. When the two most significant bits are 2'b10, it indicates read-valid, indicating that the MAC code of the current data is calculated and verified against the corresponding MAC code retrieved from the MAC code storage module.

[0081] Specifically, the MAC code calculation unit uses a lightweight hash algorithm to concatenate the input calculation data and the encryption algorithm key generated by the Arbiter PUF structure, and then extracts the hash value of the current transmitted data as the MAC code. This invention uses a lightweight hash algorithm based on a sponge structure, using the hash value as the MAC code for stack data integrity verification. This algorithm divides the hash calculation process into two stages: data absorption and data compression, efficiently completing MAC code calculation.

[0082] In the process of verifying the integrity of stack data, in order to avoid data loss caused by delays in lightweight hash calculations, the present invention introduces a cache mechanism. Specifically, the data that needs to be MAC calculated and verified is first cached, and then the MAC calculation is performed on the cached data. Therefore, the input data of the lightweight hash algorithm is mostly continuous input, which provides a basis for the pipeline design of the hash calculation. Registers are inserted between the absorption phase and the compression phase of the algorithm to cache the data signals calculated in the absorption phase. This allows the algorithm to immediately enter the absorption phase of the next hash value calculation after completing the calculation in the data absorption phase and absorb other input data, thereby realizing the pipeline calculation process.

[0083] Step 9. Store the calculated MAC code into the MAC code storage module according to the address of the decoded data.

[0084] Step 10. Verify the calculated MAC code with the MAC code stored in the MAC code storage module according to the address of the decoded data. If the verification passes, continue to step 3; otherwise, pause the processor execution.

[0085] In the MAC code verification module, the corresponding MAC code is retrieved from the MAC code storage module according to the MAC code storage address of the decoded data. The MAC code of the decoded data is compared with the MAC code retrieved from the MAC code storage module to detect whether the current stack data has been tampered with.

[0086] If the MAC values ​​of the two are equal, the verification passes and the process continues to step 3. If the MAC values ​​of the two are not equal, the stack data integrity verification unit will issue a detection error signal and transmit it to the AHB-Lite bus. The AHB-Lite bus will notify the CPU that the current stack data has been tampered with, thereby suspending the CPU operation.

[0087] The method of the present invention is particularly suitable for protecting embedded system programs from control flow hijacking attacks. It utilizes dedicated hardware designed at the microarchitecture level to generate and manage key streams while accessing memory. This allows for rapid encryption and decryption of critical stack data through exclusive-OR operations between the key stream and stack data. Furthermore, an on-chip arbiter PUF structure generates high-quality random numbers, which serve as the encryption algorithm's key, enhancing the security of key stream calculations. Stack data confidentiality protection leverages the bursty nature of the AHB-Lite bus, upon which stack data transmission relies, reducing the execution overhead of program control flow protection methods.

[0088] Based on data encryption, the present invention also proposes a MAC code-based stack data integrity verification architecture. MAC codes are calculated and verified when stack data is written and read, enabling real-time detection of tampering with critical stack data and timely detection of program control flow anomalies. Through parallel encryption and decryption of stack data and integrity verification, the present invention protects program control flow from the perspective of stack data protection.

[0089] Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above-mentioned embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any technician familiar with this field under the guidance of this specification fall within the substantive scope of this specification and should be protected by the present invention.

Claims

1. A program control flow protection system based on stack data confidentiality and integrity, characterized in that: Includes processor, AHB-Lite bus, stack, stack data confidentiality protection unit and stack data integrity verification unit; The processor is used to access data addresses, read and write control signals, write stack data and transmit them to the stack data confidentiality protection unit and the stack data integrity verification unit; The stack data confidentiality protection unit determines the base address of the memory data accessed based on the read / write burst control signal sent by the processor. The stack data confidentiality protection unit generates an encryption algorithm key internally to encrypt the stack data written on the AHB-Lite bus and decrypt the stack data read out. The decrypted read stack data and the encryption algorithm key are simultaneously passed to the stack data integrity verification unit. The stack data integrity verification unit verifies the integrity of the stack data by calculating the MAC when writing and checking the MAC when reading. If an error is detected, the program execution is suspended. The stack data confidentiality protection unit includes an address marking unit, a control state machine, a symmetric encryption algorithm module, a random number generator module and an incentive generation module; The address marking unit is used to capture the data address and read / write burst control signals transmitted on the AHB-Lite bus, intercept the high 27-bit base address and expand it to 128 bits to mark the read / write operation; The control state machine is used to receive read and write control signals and determine encryption and decryption operations. It calculates the base address of the accessed data according to the address tag unit, generates a control signal to start the symmetric encryption algorithm module, and finally generates a key stream to encrypt the data written to the stack and decrypt the data read from the stack. Among them, the encryption algorithm key of the symmetric encryption algorithm module is generated by the random number generator module, and the input of the random number generator module comes from the round constant of the incentive generation module.

2. The program control flow protection system based on stack data confidentiality and integrity according to claim 1, characterized in that: The stack data integrity verification unit includes a data compression module, a FIFO buffer module, a decoding unit, a MAC code calculation unit, a MAC code storage module and a MAC code verification module; The data compression module is used to receive read and write data and read and write control signals, mark burst transmission data through a counter and perform compression processing; The FIFO buffer module is used to temporarily store compressed data packets to solve the problem of mismatch between MAC calculation and AHB-Lite bus transmission rate; The decoding unit reads and parses data from the FIFO buffer module, and determines whether to execute the MAC code storage or verification process based on the MAC code read and write flag bit; The MAC code calculation unit uses a lightweight hash algorithm based on a sponge structure to concatenate the input data with the key to generate a MAC code; The MAC code storage module stores the MAC code of the written data according to the decoded address; The MAC code verification module compares the calculated MAC code with the corresponding value in the MAC code storage module. If they are inconsistent, it triggers a detection error signal and suspends CPU execution through the AHB-Lite bus to achieve real-time detection of stack data tampering.

3. A program control flow protection method based on stack data confidentiality and integrity, implemented based on the program control flow protection system based on stack data confidentiality and integrity according to any one of claims 1 to 2, characterized in that: The steps include: Step 1. Configure the startup file, enable the processor's data cache, and set the write policy and capacity. Step 2. After power-on initialization, the random number generator module uses the Arbiter PUF structure to generate keys for the stack data confidentiality protection unit and the stack data integrity verification unit. Step 3. Collect the bus control signals and data addresses of the processor accessing the stack, analyze the read and write burst control signals of the memory access, and calculate the base address of the memory access data; Step 4. Determine encryption or decryption of the accessed data based on the bus control signal. Calculate the key stream using the base address of the accessed data. If the operation is encryption, proceed to step 5. If the operation is decryption, proceed to step 6. Otherwise, proceed to step 7. Step 5. After the key stream is calculated, the written stack data is marked, compressed, and sent to the FIFO buffer module, which then encrypts the written stack data. Step 6. After the key stream is calculated, the read stack data is marked, decrypted, and compressed before being sent to the FIFO buffer module. Step 7. Execute step 3 and determine whether the FIFO buffer module is not empty. If it is not empty, execute step 8; otherwise, execute step 7. Step 8. Calculate the MAC code for the decoded data to obtain the MAC code read / write flag of the decoded data. If the MAC code read / write flag indicates write is valid, proceed to step 9. If the MAC code read / write flag indicates read is valid, proceed to step 10. Step 9. Store the calculated MAC code into the MAC code storage module according to the address of the decoded data; Step 10. Verify the calculated MAC code with the MAC code stored in the MAC code storage module according to the address of the decoded data. If the verification passes, continue to step 3; otherwise, pause the processor execution.

4. The program control flow protection method based on stack data confidentiality and integrity according to claim 3, characterized in that: The step 1 is specifically as follows: The processor uses a RISC-V processor, which includes an extended status register and a hardware control register; Configure the data cache of the processor, set the PM bit of the extended status register to "1", and the processor enters machine mode to execute the program. Then configure the hardware control register, set the data cache switch bits "DE", "WA", and "WB" to "1", turn on the data cache, and configure the write policy to write back and write allocate.

5. The program control flow protection method based on stack data confidentiality and integrity according to claim 3, characterized in that: In step 2, the process of using the random number generator module to generate the key of the stack data confidentiality protection unit and the stack data integrity verification unit is specifically as follows: The random number generator module uses the Arbiter PUF structure to generate random numbers; The Arbiter PUF structure generates round constants based on the stimulus generation module, namely the Galvaro linear feedback shift register. The counter collects four round constants as the stimulus input of the Arbiter PUF structure. The counter then collects the output of the Arbiter PUF structure and splices it into a 128-bit wide output as the security key of the symmetric encryption algorithm AES, which is the key for the stack data confidentiality protection unit and the stack data integrity verification unit.

6. The program control flow protection method based on stack data confidentiality and integrity according to claim 5, characterized in that: The step 4 is specifically as follows: The AES algorithm is used as the output function for key stream generation. The 32-bit random number generated by the Arbiter PUF structure is expanded into a 128-bit AES security key. The key stream is calculated based on the base address of the accessed data. Define a control state machine to control the encryption and decryption operations of memory access data. The control state machine has three states: initial state AES_IDL, write data encryption state AES_En, and read data decryption state AES_De. According to the bus control signal sent by the processor, the write enable flag and the read enable flag are triggered; when the processor sends a write data operation, the write enable flag is valid, the write data encryption state is entered, and step 5 is executed; when the processor sends a read data, the read enable flag is valid, the read data decryption state is entered and step 6 is executed; otherwise, step 7 is executed.

7. The program control flow protection method based on stack data confidentiality and integrity according to claim 3, characterized in that: The specific process of encryption and decryption operations is as follows: When the processor issues a read / write burst control signal, the address marking unit marks the access address of the current read / write data, performs data bit expansion on the access address of the current read / write data to 128 bits, and sends the read / write flag of the current read / write data to the control state machine; performs an XOR operation on the key stream and the access address of the current read / write data to complete the encryption and decryption of the data.

8. The program control flow protection method based on stack data confidentiality and integrity according to claim 3, characterized in that: The step 8 is specifically as follows: The first 32 bits of the decoded data are the compressed data to be calculated or verified, and bits 32 to 47 of the decoded data are the MAC code storage data address; The highest two bits in the MAC code storage data address are used as the MAC code read and write flag bits; When the high bit of the MAC code read / write flag is 0 and the low bit is 1, it indicates that writing is valid, and then execute step 9; when the high bit of the MAC code read / write flag is 1 and the low bit is 0, it indicates that reading is valid, and then execute step 10.

9. The program control flow protection method based on stack data confidentiality and integrity according to claim 3, characterized in that: The step 10 is specifically as follows: In the MAC code verification module, the MAC code stored in the MAC code storage module is retrieved according to the address of the decoded data; Compare the MAC code of the decoded data with the MAC code retrieved from the MAC code storage module to detect whether the current stack data has been tampered with; if the MAC values ​​are equal, the verification passes and proceeds to step 3; If the MAC values ​​are not equal, the stack data integrity verification unit will issue a detection error signal and transmit it to the AHB-Lite bus. The AHB-Lite bus will notify the CPU that the current stack data has been tampered with, thereby suspending the CPU operation.

Images