Memory device and manufacturing method of memory device

Abstract

According to one embodiment, a memory device includes a first substrate, a first transistor on the first substrate, a second substrate disposed over the first transistor, an external connection terminal disposed over the second substrate, a second transistor on the second substrate, a first conductor, a first separation structure, and a memory cell array. The first conductor penetrates through the second substrate and electrically connects the first transistor and the external connection terminal. When viewed from the first direction, the first separation structure is in a ring shape surrounding the first conductor, penetrates through the second substrate, and separates the second substrate. The memory cell array is electrically connected with the first transistor and the second transistor.

Description

Technical Field

[0001] Embodiments generally relate to memory devices and methods of manufacturing memory devices. Background Art

[0002] A memory device including memory cells arranged three-dimensionally is known. To achieve a large storage capacity, a memory device may have a structure in which structures including elements formed in independent processes are bonded onto different substrates. Summary of the Invention

[0003] A storage device according to one embodiment includes: a first substrate, a first transistor on the first substrate, a second substrate disposed above the first transistor, an external connection terminal disposed above the second substrate, a second transistor on the second substrate, a first conductor, a first separation structure, and a memory cell array. The first conductor passes through the second substrate and electrically connects the first transistor to the external connection terminal. When viewed from a first direction, the first separation structure is annular, surrounding the first conductor, and passes through the second substrate to separate the second substrate. The memory cell array is electrically connected to the first transistor and the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An example of components of the storage device according to the first embodiment and connections of the components is shown.

[0005] Figure 2 Components of one block of the storage device according to the first embodiment and connections between the components are shown.

[0006] Figure 3 The external appearance of the storage device according to the first embodiment is shown.

[0007] Figure 4 An example of the surface structure of a portion of the storage device according to the first embodiment is shown.

[0008] Figure 5 An example of a cross-sectional structure of a portion of the storage device according to the first embodiment is shown.

[0009] Figure 6 An example of a cross section of a memory column of the memory device according to the first embodiment is shown.

[0010] Figure 7 An example of a cross-sectional structure of a portion of the storage device according to the first embodiment is shown.

[0011] Figure 8 This is a plan view of a portion of the storage device according to the first embodiment.

[0012] Figure 9 An example of the flow of the method for manufacturing the storage device according to the first embodiment is shown.

[0013] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 as well as Figure 15 An example of a state in which a part of the storage device according to the first embodiment is being manufactured is shown.

[0014] Figure 16 This is a plan view of a portion of the storage device according to the first embodiment.

[0015] Figure 17 This is a plan view of a portion of a storage device according to a first modification of the first embodiment.

[0016] Figure 18 An example of a cross-sectional structure of a portion of a storage device according to a second modification of the first embodiment is shown.

[0017] Figure 19 An example of a cross-sectional structure of a portion of a storage device according to a third modified example of the first embodiment is shown.

[0018] Figure 20 An example of a cross-sectional structure of a portion of the storage device according to the second embodiment is shown.

[0019] Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 as well as Figure 25 An example of a state in which a part of the storage device according to the second embodiment is being manufactured is shown.

[0020] Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 as well as Figure 31 An example of a state in which a part of a storage device according to a modification of the second embodiment is being manufactured is shown.

[0021] Figure 32 and Figure 33 An example of a cross-sectional structure of a portion of a storage device according to the third embodiment is shown.

[0022] Figure 34 and Figure 35 An example of a cross-sectional structure of a portion of a storage device according to a fourth embodiment is shown.

[0023] Figure 36An example of a cross-sectional structure of a portion of a storage device according to a modified example is shown. DETAILED DESCRIPTION

[0024] The following describes the embodiments with reference to the accompanying drawings. For multiple components having substantially the same function and configuration within a particular embodiment or different embodiments, additional numbers or letters may be added to the end of the reference numerals to distinguish them from one another. The description of a particular embodiment also applies to the description of other embodiments unless explicitly or obviously excluded.

[0025] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from reality. In addition, the drawings may also include portions where the relationship and ratio of dimensions differ from each other.

[0026] Any steps in the flow of the method of the embodiment are not limited to the order illustrated, and unless otherwise stated, they may occur in an order different from the illustrated order and / or in parallel with other steps.

[0027] In this specification and claims, a first element being “connected” to a second element includes the case where the first element is connected to the second element directly, always, or selectively via a conductive element.

[0028] The following describes the embodiments using an XYZ orthogonal coordinate system. The x-axis extends along the X direction, the y-axis extends along the Y direction, and the z-axis extends along the Z direction.

[0029] 1. First Implementation

[0030] 1.1. Composition (Structure)

[0031] Figure 1 This figure shows an example of the components and connections of a storage device according to the first embodiment. Storage device 1 uses memory cells to store data. Storage device 1 operates based on commands CMD and address information ADD received from an external memory controller. Storage device 1 receives data DAT to be written and outputs the data stored in storage device 1.

[0032] The storage device 1 includes components such as a memory cell array 10, an input / output circuit 11, a logic controller 12, a register 13, a sequencer 14, a voltage generating circuit 15, a driver 16, a row decoder 17, a sense amplifier 18, a data register (data buffer) 19, and multiple external connection terminals (pads) PD.

[0033] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (BLK). Each block BLK includes a plurality of memory cell transistors MT. The region in which the memory cell array 10 is provided also includes wiring such as word lines WL (not shown) and bit lines BL (not shown).

[0034] The input / output circuit 11 transmits and receives various signals to and from an external device, such as a memory controller, outside the memory device 1. The input / output circuit 11 is connected to the external connection terminal PD. The input / output circuit 11 transmits and receives input / output signals DQ_0, DQ_1, DQ_2, DQ_3, DQ_4, DQ_5, DQ_6, and DQ_7 at the external connection terminals PD_D0, PD_D1, PD_D2, PD_D3, PD_D4, PD_D5, PD_D6, and PD_D7, respectively. The input / output circuit 11 transmits and receives signals DQS and -DQS at the external connection terminal PD. The "-" symbol indicates the inverse logic of a signal without the "-" symbol, and a signal with a "-" symbol indicates that it is enabled when at a low ("L") level. The input / output signals DQ_0 to DQ_7 transmit a command (CMD), write data or read data (DAT), address information (ADD), and status (STA). Signals DQS and -DQS indicate the timing of inputting and outputting signals DQ_0 to DQ_7.

[0035] The logic controller 12 transmits and receives signals to and from an external portion of the storage device 1, such as a memory controller. The logic controller 12 is connected to the external connection terminal PD and transmits and receives the signals -CE, CLE, ALE, -WE, RE, -RE, -WP, and RY / BY at the external connection terminal PD. The -CE signal enables the storage device 1. The CLE signal notifies the storage device 1 of the transmission of a command based on the input / output signal DQ. The ALE signal notifies the storage device 1 of the transmission of address information ADD based on the input / output signal DQ. The -WE signal instructs the storage device 1 to receive the input / output signal DQ. The -RE signal instructs the storage device 1 to output the input / output signal DQ. The ready / busy signal RY / BY indicates whether the storage device 1 is in the ready state or the busy state, with a low level indicating the busy state. The storage device 1 accepts commands when in the ready state and does not accept commands when in the busy state.

[0036] Register 13 is a circuit that stores commands CMD and address information ADD received by memory device 1. Command CMD instructs sequencer 14 on various operations, including data read, data write, and data erase. In one example, address information ADD includes a block address, a page address, and a column address. The block address, page address, and column address specify a block BLK, a word line WL, and a bit line BL, respectively.

[0037] The sequencer 14 is a circuit that controls the entire operation of the memory device 1. Based on the command CMD received from the register 13, the sequencer 14 controls the voltage generating circuit 15, the row decoder 17, and the sense amplifier 18 to perform various operations including data reading, data writing, and data erasing.

[0038] The voltage generating circuit 15 generates a plurality of voltages of different magnitudes. The voltage generating circuit 15 receives a power supply voltage from outside the memory device 1 and generates a plurality of voltages based on the power supply voltage. The generated voltages are supplied to the driver 16.

[0039] The driver 16 is a circuit that applies various voltages required for the operation of the memory device 1 to some components. The driver 16 receives multiple voltages from the voltage generating circuit 15 and supplies the received voltages to the memory cell array 10 , the row decoder 17 , and the sense amplifier 18 .

[0040] The row decoder 17 is a circuit for selecting a block BLK and transmits a voltage supplied from the driver 16 to one block BLK selected based on a block address received from the register 13 .

[0041] The sense amplifier 18 is a circuit for determining data stored in the memory cell array 10. The sense amplifier 18 senses the state of the memory cell transistor MT and generates read data according to the sensed state or transmits write data to the memory cell transistor MT.

[0042] The data register 19 is a circuit that holds data used for input and output of the memory device 1. The data register 19 receives data DAT received by the memory device 1 and supplies data based on the received data DAT to the sense amplifier 18. The data register 19 receives data from the sense amplifier 18 and supplies data DAT based on the received data to the input / output circuit 11.

[0043] 1.1.1. Memory Cell Array

[0044] Figure 2 The components of one block of the storage device of the first embodiment and the connections of the components are shown. A plurality of blocks BLK, for example, all blocks BLK include Figure 2 The components and connections shown.

[0045] One block BLK includes a plurality of string units SU. Figure 2 An example of five string units SU_0 to SU_4 is shown.

[0046] like Figure 2As shown, m bit lines BL_0 to BL_m-1 are connected to one NAND string NS from each string unit SU_0 to SU_4 in each block BLK, respectively. m is a positive integer.

[0047] Each NAND string NS includes one select gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT0, DT1, DT2, DT3, or DT4). n is a positive integer. The memory cell transistor MT is an element that stores data nonvolatilely. The memory cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings. The memory cell transistor MT stores data nonvolatilely based on the charge in the charge storage film. Data is written to the memory cell transistor MT by injecting electrons into the charge storage film.

[0048] The select gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series in this order between the source line SL and one bit line BL.

[0049] Multiple NAND strings NS, each connected to a plurality of different bit lines BL, form a string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. The group of memory cell transistors MT that share a word line WL in a string unit SU is called a cell unit CU.

[0050] The selection gate transistors DT0 to DT4 belong to the string units SU_0 to SU_4 respectively. Figure 2 In the figure, the select gate transistors DT2, DT3, and DT4 are omitted. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS of the string unit SU_0 is connected to the select gate line SGDL0. Similarly, the gates of the select gate transistors DT1, DT2, DT3, and DT4 of each of the multiple NAND strings NS of the string units SU_1, SU_2, SU_3, and SU_4 are connected to the select gate lines SGDL1, SGDL2, SGDL3, and SGDL4.

[0051] The gate of the select gate transistor ST is connected to a select gate line SGSL.

[0052] 1.1.2. Storage Device Structure

[0053] Figure 3 FIG. 2 shows the appearance of the storage device of the first embodiment. Figure 3As shown, the storage device 1 includes a first structure 100, a second structure 200, and a third structure 300 arranged along the z-axis. The first structure 100, the second structure 200, and the third structure 300 extend along the xy plane and are arranged along the z-axis. The second structure 200 is located on the upper surface of the first structure 100. The third structure 300 is located on the upper surface of the second structure 200.

[0054] The first structure 100, the second structure 200, and the third structure 300 each include a plurality of semiconductors, a plurality of different electrical conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100, the second structure 200, and the third structure 300 each include a plurality of elements and wirings implemented by the semiconductors, electrical conductors, and insulators. The first structure 100, the second structure 200, and the third structure 300 each include a circuit containing elements and wirings. The elements and wirings in the first structure 100, the elements and wirings in the second structure 200, and the elements and wirings in the third structure 300 are electrically connected to each other.

[0055] The set of the first structure 100 and the second structure 200 includes an input-output circuit 11, a logic controller 12, a register 13, a sequencer 14, a voltage generating circuit 15, a driver 16, a row decoder 17, a sense amplifier 18, and a data register 19. The first structure 100 may include any of the input-output circuit 11, the logic controller 12, the register 13, the sequencer 14, the voltage generating circuit 15, the driver 16, the row decoder 17, the sense amplifier 18, and the data register 19. The second structure 200 may include any of the input-output circuit 11, the logic controller 12, the register 13, the sequencer 14, the voltage generating circuit 15, the driver 16, the row decoder 17, the sense amplifier 18, and the data register 19.

[0056] The third structure 300 includes the memory cell array 10 and a plurality of external connection terminals PD. The external connection terminals PD are exposed on the upper surface of the third structure 300.

[0057] Figure 4 An example of the surface structure of a portion of the storage device according to the first embodiment is shown. Figure 4 Decomposed to show Figure 3 structure.

[0058] like Figure 4 As shown, the first structure 100 includes a plurality of conductive bonding terminals BD1 . The bonding terminals BD1 are exposed on the upper surface of the first structure 100 . The bonding terminals BD1 are connected to the elements in the first structure 100 .

[0059] The second structure 200 includes a plurality of conductive bonding terminals BD2L and a plurality of conductive bonding terminals BD2U. The bonding terminals BD2L are exposed on the bottom surface of the second structure 200. The bonding terminals BD2L are connected to components in the second structure 200. The bonding terminals BD2L have the same layout as the bonding terminals BD1 of the first structure 100. The bonding terminals BD2L are arranged so that when the first structure 100 and the second structure 200 are bonded, each bonding terminal BD2L contacts the corresponding one of the bonding terminals BD1 of the first structure 100. A particular bonding terminal BD2L and the corresponding one of the bonding terminals BD1 of the first structure 100 function as the same node in the circuit.

[0060] The joining terminals BD2U are exposed on the upper surface of the second structure 200. The joining terminals BD2U are connected to the elements in the second structure 200.

[0061] The third structure 300 includes a plurality of conductive bonding terminals BD3. The bonding terminals BD3 are exposed on the bottom surface of the third structure 300. The bonding terminals BD3 are connected to components in the third structure 300. The bonding terminals BD3 have a layout identical to that of the bonding terminals BD2U in the second structure 200. The bonding terminals BD3 are arranged so that, when the second structure 200 and the third structure 300 are bonded, each bonding terminal BD3 contacts the corresponding one of the bonding terminals BD2U in the second structure 200. A particular bonding terminal BD3 and the corresponding one of the bonding terminals BD2U in the second structure 200 function as the same node in the circuit.

[0062] Figure 5 An example of a cross-sectional structure of a portion of the storage device of the first embodiment is shown. Figure 5 As shown, the memory device 1 includes a connection area PA. The connection area PA is a region where a conductor electrically connected to the external connection terminal PD is located. The connection area PA extends along the x-axis, the y-axis, and the z-axis.

[0063] First structure 100 further includes substrate W1, structure STI, transistor Tr1, contacts CS1, C0, C1, C2, and C3, conductors L0, L1, and L2, and insulators 21 and 22. In the following description, conductors also include semiconductors that have conductivity due to the presence of impurities. In one example, substrate W1 is made of silicon. In one example, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 are made of copper or tungsten. In one example, insulators 21 and 22 are made of silicon oxide.

[0064] The STI structure is hereinafter referred to as STI. The STI extends from the upper surface of the substrate W1 along the z-axis. In one example, the STI comprises silicon oxide.

[0065] The transistor Tr1 is located above and near the upper surface of the substrate W1 and includes a gate insulator on the upper surface of the substrate W1, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching a region below the gate electrode.

[0066] Each contact C0 is in contact with the upper surface of the gate electrode of one transistor Tr1 at its lower surface, and each contact CS1 is in contact with one source / drain region at its lower surface.

[0067] Each conductor L0 is in contact with one contact C0 or CS1 on its lower surface.

[0068] Each contact C1 is in contact with the upper surface of one conductor L0 at its lower surface. The plurality of contacts C1 in the connection area PA are in contact with the upper surface of one conductor L0 at their respective lower surfaces.

[0069] The lower surface of each conductor L1 is in contact with the upper surface of one contact C1. The lower surface of one conductor L1 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C1.

[0070] Each contact C2 is in contact with the upper surface of one conductor L1 at its lower surface. The plurality of contacts C2 in the connection area PA are in contact with the upper surface of one conductor L1 at their respective lower surfaces.

[0071] The lower surface of each conductor L2 is in contact with the upper surface of one contact C2. The lower surface of one conductor L2 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C2.

[0072] Each contact C3 is in contact with the upper surface of one conductor L2 at its lower surface. The plurality of contacts C3 in the connection area PA are in contact with the upper surface of one conductor L2 at their respective lower surfaces.

[0073] The group of transistor Tr1, contacts CS1, C0, C1, C2, and C3, and electrical conductors L0, L1, and L2 implements the circuit included in the first configuration 100. Therefore, the first configuration 100 has transistor Tr1, contacts CS1, C0, C1, C2, and C3, and electrical conductors L0, L1, and L2 of any shape and configuration that implements the circuit included in the first configuration 100.

[0074] The insulator 21 extends from the top surface of the substrate W1 to the top surface of the contact C3. The insulator 21 fills the region of the first structure 100 where no components are provided, that is, the region where the transistor Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 are not provided.

[0075] Each of the connecting terminals BD1 is in contact with the upper surface of one contact C3 at its lower surface. The insulator 22 fills the region where the connecting terminal BD1 is not provided in the layer where the connecting terminal BD1 is located.

[0076] Second structure 200 further includes substrate W2, structure ST2, transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, conductors L3, L4, L5, and L6, and insulators 24, 25, 26, and 27. In one example, substrate W2 comprises silicon. In one example, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and conductors L3, L4, L5, and L6 comprise copper or tungsten. In one example, insulators 24, 25, 26, and 27 comprise silicon oxide.

[0077] Each joining terminal BD2L is located in the lowermost layer of the second structure 200. The insulator 24 fills the region where the joining terminal BD2L is located in the layer where the joining terminal BD2L is located and where no joining terminal BD2L is provided.

[0078] The lower surface of each contact C4 is in contact with the upper surface of one connecting terminal BD2L.

[0079] The lower surface of each conductor L3 is in contact with the upper surface of one contact C1. The lower surface of one conductor L3 in the connection area PA is in contact with the upper surface of each of the plurality of contacts C4.

[0080] Each contact C5 is in contact with the upper surface of one conductor L3 at its lower surface. The plurality of contacts C5 in the connection area PA are in contact with the upper surface of one conductor L3 at their lower surfaces.

[0081] Insulator 25 extends from the top surface of bonding terminal BD2L and the top surface of insulator 24 to the top surface of contact C5. Insulator 25 fills the area above bonding terminal BD2L and insulator 24 where contacts C4 and C5 and conductor L3 are not provided. In one example, insulator 25 comprises silicon oxide.

[0082] The substrate W2 is located on the upper surface of the insulator 25. The STI penetrates the substrate W2 through the upper and lower surfaces of the substrate W2.

[0083] The passage TS penetrates the substrate W2 through the upper and lower surfaces of the substrate W2. Each passage TS is in contact with the upper surface of one contact C5 at its lower surface.

[0084] The insulator SP1 penetrates the substrate W2 through the upper and lower surfaces of the substrate W2. Each insulator SP1 covers the side surface of one via TS.

[0085] The isolation structure DS electrically isolates the area of ​​the substrate W2 surrounded by the isolation structure DS from the area outside the area. The isolation structure DS surrounds multiple groups of vias TS and insulators SP1 in the connection area PA. The isolation structure DS penetrates the substrate W2, passing through both the upper and lower surfaces. The isolation structure DS comprises an insulator, in one example, silicon oxide.

[0086] The transistor Tr2 is located above and near the upper surface of the substrate W2 and includes a gate insulator on the upper surface of the substrate W2, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching a region below the gate electrode.

[0087] Each contact C7 is in contact with the upper surface of the gate electrode of one transistor Tr2 at its lower surface. Each contact CS2 is in contact with one source / drain region at its lower surface. Each contact CS5 is in contact with the upper surface of one via TS at its lower surface.

[0088] Each conductor L4 is in contact with the upper surface of one contact C7, CS2, or CS5 at its lower surface. One conductor L4 in the connection area PA is in contact with the upper surface of each of the plurality of contacts CS5 at its lower surface.

[0089] Each contact C8 is in contact with the upper surface of one conductor L4 at its lower surface. The plurality of contacts C8 in the connection area PA are in contact with the upper surface of one conductor L4 at their lower surfaces.

[0090] The lower surface of each conductor L5 is in contact with the upper surface of one contact C8. The lower surface of one conductor L5 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C8.

[0091] Each contact C9 is in contact with the upper surface of one conductor L5 at its lower surface. The plurality of contacts C9 in the connection area PA are in contact with the upper surface of one conductor L5 at their lower surfaces.

[0092] The lower surface of each conductor L6 is in contact with the upper surface of one contact C9. The lower surface of one conductor L6 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C9.

[0093] Each contact C10 is in contact with the upper surface of one conductor L6 at its lower surface. The plurality of contacts C10 in the connection area PA are in contact with the upper surface of one conductor L6 at their lower surfaces.

[0094] The group of transistor Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and electrical conductors L4, L5, and L6 implements the circuit included in the second configuration 200. Therefore, the second configuration 200 has transistor Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and electrical conductors L4, L5, and L6 of any shape and configuration that implements the circuit included in the second configuration 200.

[0095] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 fills the area from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no components are provided, that is, the area where the transistor Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and conductors L4, L5, and L6 are not provided.

[0096] Each of the joining terminals BD2U is in contact with the upper surface of one contact C10 at its lower surface. The insulator 27 fills the region where the joining terminals BD2U are located in the layer where the joining terminals BD2U are located.

[0097] The third structure 300 further includes contacts C11 , C12 , and C13 , conductors L7 , L8 , 31 , 33 , 36 , and 38 , insulators 29 , 34 , 35 , 37 , 40 , and 41 , and a memory pillar MP.

[0098] Each joining terminal BD3 is located in the lowermost layer of the third structure 300. The insulator 29 fills the region where the joining terminal BD3 is located in the layer where the joining terminal BD3 is located and where no joining terminal BD3 is provided.

[0099] The lower surface of each contact C11 is in contact with the upper surface of one connecting terminal BD3.

[0100] The lower surface of each conductor L7 is in contact with the upper surface of one contact C11. The lower surface of one conductor L7 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C11.

[0101] Each contact C12 is in contact with the upper surface of one conductor L7 at its lower surface. The plurality of contacts C12 in the connection area PA are in contact with the upper surface of one conductor L7 at their lower surfaces.

[0102] The lower surface of each conductor L8 is in contact with the upper surface of one contact C12. The lower surface of one conductor L8 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C12.

[0103] Conductor 31 is located above conductor L8. Conductor 31 has a plate-like shape along the xy plane. Conductor 31 functions as at least a portion of select gate line SGDL. The lower surface of conductor 31 is exposed at its end and has a terrace.

[0104] The insulator 32 is located on the upper surface of the conductor 31. The insulator 32 has a plate-like shape along the xy plane.

[0105] Conductors 33 and insulators 34 are alternately stacked one by one on the upper surface of insulator 32. Conductors 33 and insulators 34 have plate-like shapes along the xy plane. Each conductor 33 functions as at least a portion of word line WL. Figure 5 In the example shown, n, or the number of memory cell transistors MT, is 8. Conductors 33 function as at least a portion of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7, sequentially from the bottom. The bottom surface of each conductor 33 is exposed at its end and has a terrace.

[0106] The insulator 35 is located on the upper surface of the uppermost conductor 33 .

[0107] The conductor 36 is located on the upper surface of the insulator 35. The conductor 36 functions as at least a portion of the selection gate line SGSL.

[0108] Insulator 37 is located on the upper surface of conductor 36. Conductor 38 is located on the upper surface of insulator 37. The lower surface of conductor 38 is exposed at the end and has a terrace.

[0109] The storage pillar MP extends along the z-axis, passing through the group of conductors 31, 33, and 36 and insulators 32, 34, 35, and 37. Each storage pillar MP includes an insulator CI, a semiconductor SM, and a stacked body SS. The semiconductor SM covers the side surfaces of the insulator CI. The stacked body SS covers the side surfaces of the semiconductor SM. The stacked body SS is open at the upper end of the storage pillar MP. A portion of the semiconductor SM is located in the opening and is in contact with the conductor 38 on its upper surface.

[0110] Alternatively, the upper portion of the memory pillar MP may be located in the conductor 38 , the stacked body SS may be opened at a portion facing the conductor 38 , and a portion of the semiconductor SM may be located in the opening.

[0111] Figure 6 An example of the structure of a cross section of the memory column of the memory device according to the first embodiment along the xy plane is shown. Figure 6 As shown, in one example, the stacked body SS includes a tunnel insulator TI, a charge storage film CA, and a blocking insulator BI.

[0112] The tunnel insulator TI surrounds the side surfaces of the semiconductor SM. The charge storage film CA surrounds the side surfaces of the tunnel insulator TI. The blocking insulator BI surrounds the side surfaces of the charge storage film CA. The conductor 31, 33, or 36 surrounds the side surfaces of the blocking insulator BI.

[0113] The semiconductor SM functions as a channel (current path) for the memory cell transistor MT and the select gate transistors DT and ST. The tunnel insulator TI and the blocking insulator BI each comprise, for example, silicon oxide. The charge storage film CA stores charge. The charge storage film CA comprises, for example, silicon nitride.

[0114] return Figure 5 The portion of each storage column MP facing the conductor 31 functions as a selection gate transistor DT. The portion of the storage column MP facing the conductor 33 functions as a memory cell transistor MT. The portion of the storage column MP facing the conductor 36 functions as a selection gate transistor ST. The lower surface of the semiconductor SM is exposed at the lower surface of each storage column MP. The upper surface of the semiconductor SM is exposed at the upper surface of each storage column MP.

[0115] Each contact C13 contacts the upper surface of one conductor L8 at its lower surface. Multiple contacts C13 in the connection area PA contact the upper surface of one conductor L8 at their lower surfaces. Some contacts C13 contact the lower surface of the semiconductor SM of one memory pillar MP at their upper surfaces. Some contacts C13 contact the lower surface of the platform portion of one of the conductors 31, 33, and 37 at their upper surfaces.

[0116] Insulator 40 extends from the height of the upper surface of insulator 29 to the height of the upper surface of conductor 38. Insulator 40 fills the area of ​​third structure 300 where no components are provided, that is, the area where contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, and 38, insulators 40, 32, 34, 35, and 37, and memory pillar MP are not provided.

[0117] Insulator 41 is located on the upper surface of each of conductors 38 and 40. Insulator 41 has an opening OG in connection area PA. Opening OG extends from the upper surface of insulator 41 to the lower surface. Opening OG reaches multiple contacts C13 in connection area PA. Opening OG has an external connection terminal PD inside. In one example, external connection terminal PD is one of external connection terminals PD_D0, PD_D1, PD_D2, PD_D3, PD_D4, PD_D5, PD_D6, and PD_D7 for transmitting and receiving input / output signals DQ. External connection terminal PD is connected to the upper surface of each of multiple contacts C13 on its lower surface.

[0118] Hereinafter, the portion of the third structure 300 from the layer of the insulator 29 and the bonding terminal BD3 to the layer of the conductor 38 may be referred to as a first portion 300 a of the third structure 300 .

[0119] 1.1.3. Construction of the connection area

[0120] Figure 7 An example of a cross-sectional structure of a portion of the storage device according to the first embodiment is shown. Figure 7 Enlarged view Figure 5 The area of ​​the middle substrate W2 where the via TS is provided (ie, the connection area PA) and the areas above and below it.

[0121] like Figure 7 As shown, conductor L3 and contact C5 have an inverted tapered shape. A component having an inverted tapered shape means that the length (or width) of the component along the xy plane increases from the top end toward the bottom end. In other words, the length (or width) of the component along an imaginary line at the top end is greater than the length (or width) of the component along the imaginary line at the bottom end.

[0122] The separation structure DS has an inverted cone shape. Figure 8 As will be described later, the separation structure DS extends along the xy plane, and the length of the separation structure DS along a direction (X direction or Y direction) intersecting the direction in which the separation structure DS extends increases from the upper end toward the lower end.

[0123] The passage TS has a tapered shape. A component having a tapered shape means that the length (or width) of the component along the xy plane decreases from the upper end to the lower end of the component. In other words, the length (or width) of the upper end of the component along an imaginary straight line is smaller than the length (or width) of the lower end of the component along the imaginary straight line.

[0124] The contact CS5 and the electrical conductor L4 have a tapered shape.

[0125] Figure 8 This is a plan view of a portion of the storage device according to the first embodiment. Figure 8 The structure of the region where the passage TS is provided in the substrate W2 (ie, the connection region PA) is shown when viewed from the Z direction.

[0126] As reference Figure 6 The above and Figure 8 As shown in FIG, a plurality of sets of passages TS and insulators SP1 are provided. As an example, Figure 8 A group of matrices arranged into 5 rows along the x-axis and 5 columns along the y-axis is shown.

[0127] The separation structure DS surrounds the group of the passage TS and the insulator SP1 along the xy plane. The separation structure DS has a linear shape and extends continuously along the xy plane. Due to this structure of the separation structure DS, the separation structure DS electrically separates the portion of the substrate W2 that is surrounded by the separation structure (i.e., the inner side) from the portion of the substrate W2 that is outside the separation structure. The width of the separation structure DS, that is, the length (or width) of the imaginary straight line that intersects the direction in which the separation structure extends, has a size that can fully suppress the capacitance (electrostatic capacitance) between the inner and outer areas of the separation structure DS. The larger the width, the more the capacitance is suppressed, which results in an increase in the area of ​​the storage device 1. Therefore, the separation structure DS has a width determined based on the suppression of the capacitance by the separation structure DS and the allowable area of ​​the separation structure WS.

[0128] Manufacturing method

[0129] Figure 9 An example of the flow of the method for manufacturing the storage device of the first embodiment is shown. Figure 9 As shown, the first structure 100, a structure including a portion of the second structure 200, and the first portion 300a of the third structure 300 are formed (step ST1). The first structure 100, a structure including a portion of the second structure 200, and the first portion 300a of the third structure 300 are formed through separate processes.

[0130] In one example, the first structure 100 is formed by sequentially forming components located closer to the substrate W1 in the Z direction on the substrate W1 in the Z direction.

[0131] The structure including a portion of the second structure 200 includes the structure from the substrate W2 to the connecting terminal BD2L and the insulator 24. In one example, the structure including a portion of the second structure 200 is formed by the following method. Figure 5 The orientation shown is reversed relative to the xy plane, i.e. Figure 5 Then, the substrate W2 is prepared with the upper side of the substrate W2 facing downward. Figure 5 A structure from the substrate W2 to the connecting terminal BD2L and the insulator 24 is formed on the lower surface of the substrate W2.

[0132] In one example, the first portion 300a of the third structure 300 is formed by the following method. First, a substrate W3 (not shown) is prepared. Next, the first portion 300a is formed on the upper surface of the substrate W3. Figure 5 The structure shown is reversed relative to the xy plane, i.e. Figure 5 The structure shown has its upper side facing downward. In one example, the portion of the structure closer to the substrate W3 is formed earlier.

[0133] The first structure 100 is bonded or attached to a structure including a portion of the second structure 200 (step ST2). The bonding is performed with the structure including a portion of the second structure 200 inverted relative to the xy plane so that the bonding terminal BD1 of the first structure 100 and the bonding terminal BD2L of the structure including a portion of the second structure 200 are in contact with each other.

[0134] The remaining portion of the second structure 200 is formed (step ST3 ). The method for forming the remaining portion of the second structure 200 will be described in detail later. The forming method includes forming the bonding terminals BD2U of the second structure 200 .

[0135] The second structure 200 is bonded (or attached) to the first portion 300a of the third structure 300 (step ST4). The bonding is performed with the first portion 300a of the third structure 300 inverted relative to the xy plane so that the bonding terminals BD2U of the second structure 200 come into contact with the bonding terminals BD3 of the first portion 300a of the third structure 300.

[0136] The substrate W3 on which the third structure 300 is formed is removed (step ST5). Examples of removal include CMP (Chemical Mechanical Polishing). The substrate W3 may not be removed but may remain thinly.

[0137] The remaining portion of the third structure 300 is formed (step ST6). Figure 5 The structure shown.

[0138] 1.2.1. Manufacturing method of the second structure

[0139] Figures 10 to 15 An example of a state during the manufacture of a part of the storage device according to the first embodiment will be described in sequence. Figures 10 to 15 An example of the state during the production of the second structure 200 is shown in sequence.

[0140] Figure 10 Shown as Figure 9 The process is performed as part of step ST1 of the process. Figure 10 As shown, from Figure 5 The orientation shown is reversed relative to the xy plane, i.e. Figure 5 The substrate W2 is prepared in a state where the upper side is facing downward. Figure 5STI and separation structure DS are formed in an area (the lower surface of the substrate W2). In one example, STI and separation structure DS are formed by a common process. That is, in an area including the upper surface of substrate W2, a trench is formed by a combination of a photolithography process and anisotropic etching. Examples of etching methods include RIE (Reactive Ion Etching). Then, the trench is filled with the material of STI and separation structure DS. Due to the use of anisotropic etching, STI and separation structure DS have a tapered shape.

[0141] A structure from the upper surface of the substrate W2 to the layer of the joining terminals BD2L and the insulator 24 , ie, the contacts C5 and C4 , the conductor L3 , the joining terminals BD2L, and the insulators 25 and 24 is formed above the substrate W2 .

[0142] Figures 11 to 15 Shown as Figure 9 The process is performed as part of step ST3 of the process. Figure 11 As shown, the structure formed by the steps thus far, namely, the structure including a portion of the second structure 200, is inverted relative to the xy plane. As a result, the isolation structure DS has an inverted tapered shape. Next, the substrate W2 is thinned by partially removing the upper surface (the surface opposite to the side where the insulator 25 is located). Examples of removal methods include CMP (Chemical Mechanical Polishing). This removal is continued until the STI and isolation structure DS are exposed.

[0143] like Figure 12 As shown, transistor Tr2 is formed.

[0144] like Figure 13 As shown, openings OP1 are formed by partially removing the substrate W2. Each opening OP1 is formed in a region where each set of vias TS and insulator SP1 is to be formed. Each opening OP1 extends from the upper surface of the substrate W2 to the lower surface. Each opening OP1 exposes a portion of the upper surface of each contact C5 and the upper surface of the insulator 25. Examples of methods for forming openings OP1 include photolithography and anisotropic etching such as RIE. The use of anisotropic etching gives openings OP1 a tapered shape.

[0145] like Figure 14As shown, the insulator SP1 is formed on the side surfaces of the opening OP1, that is, on the portion of the substrate W2 surface exposed by the opening OP1. Specifically, the insulator SP1 is first deposited continuously on the side surfaces and bottom surface of the opening OP1, that is, on the portion of the substrate W2 surface and the insulator 25 surface exposed by the opening OP1, and on the upper surface of the contact C5. Examples of deposition methods include CVD (Chemical Vapor Deposition). Next, the bottom surface portion of the opening OP1 in the insulator SP1 is removed through a combination of photolithography and anisotropic etching such as RIE.

[0146] like Figure 15 As shown, the remaining portion of the opening OP1 is filled with the via TS. According to the shape of the opening OP1, each set of the via TS and the insulator SP1 has a tapered shape.

[0147] Afterwards, if Figure 5 The remaining portion of the second structure 200 is formed as shown, that is, the structure from the substrate W to the layer of the bonding terminals BD2U and the insulator 27. In this way, the second structure 200 is obtained.

[0148] 1.3. Advantages (Effects)

[0149] According to the first embodiment, as described below, a storage device capable of high-speed operation can be provided.

[0150] In order to increase the capacity of the storage device, the storage device may include a plurality of structures joined together, such as the first structure 100, the second structure 200, and the third structure 300. In such a structure, in order to electrically connect the components in the separate structures to each other, each structure needs to include a path such as the path TS that passes through the substrate. These paths will form parasitic capacitance between the path and the substrate around the path. The parasitic capacitance will reduce the speed of the signal passing through the path. The requirements for high-speed operation of the storage device, especially the requirements for the input and output signals of the storage device, are high, and the influence of parasitic capacitance is large. In the case where a separate structure DS as in the first embodiment is not provided, each path TS has a parasitic capacitance formed between the path and the remaining part of the substrate W2. In addition, since the insulator SP1 is thin, the parasitic capacitance of each path TS is large. The parasitic capacitance can be reduced by thickening the insulator SP1 around the path TS, but in order to achieve sufficient parasitic capacitance suppression, the area of ​​the insulator SP1 needs to be significantly increased. In order to thicken the insulator SP1, it is also necessary to increase the spacing between the paths TS.

[0151] According to the first embodiment, a separation structure DS is provided that surrounds multiple parallel-connected channels TS. Consequently, the area inside the separation structure DS (i.e., where the channels TS are located) in the substrate W2 is electrically isolated from the area outside. Consequently, the capacitance formed by the area outside the separation structure DS is isolated from the area inside. Consequently, the parasitic capacitance of the channels TS is suppressed. Consequently, a storage device 1 capable of high-speed operation can be provided.

[0152] Furthermore, according to the first embodiment, the separation structure DS surrounds multiple vias TS. Therefore, by providing a single separation structure DS, the parasitic capacitance of the multiple vias TS can be reduced. Therefore, by providing a wide separation structure DS while suppressing the area increase caused by the addition of the separation structure DS, parasitic capacitance can be significantly reduced.

[0153] 1.4. Modifications

[0154] 1.4.1. First Modification

[0155] Figure 16 and Figure 17 This is a plan view of a portion of a storage device according to a first modification of the first embodiment. Figure 16 and Figure 17 The structure of the region where the passage TS is provided in the substrate W2 (ie, the connection region PA) is shown when viewed from the Z direction.

[0156] like Figure 16 and Figure 17 As shown in FIG, the separation structure DS can also be configured with multiple layers. Figure 16 In the example, a separation structure DS2 is further provided, and the separation structure DS2 surrounds the separation structure DS along the xy plane. Figure 17 In the example, one separation structure DS2 surrounds multiple separation structures DS along the xy plane. Figure 17 In the example of , some groups of the via TS and the insulator SP1 are surrounded by one separation structure DS2 but are not surrounded by the separation structure DS.

[0157] 1.4.2. Second Modification

[0158] The orientations of the first structure 100, the second structure 200, and the third structure 300 are not limited to Figure 3 and Figure 5 The orientation shown can be arbitrary.

[0159] Figure 18 An example of a cross-sectional structure of a portion of a storage device according to a second modification of the first embodiment is shown. Figure 18 As shown, the second configuration 200 has a Figure 5That is, the lower surface of each conductor L4 contacts the upper surface of each contact C5. The lower surface of one conductor L4 in the connection area PA contacts the upper surface of each of the plurality of contacts C5.

[0160] Each contact C6 is in contact with the upper surface of one conductor L4 at its lower surface. The plurality of contacts C6 in the connection area PA are in contact with the upper surface of one conductor L4 at their lower surfaces.

[0161] The lower surface of each conductor L5 is in contact with the upper surface of one contact C6. The lower surface of one conductor L5 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C6.

[0162] Each contact CS2 contacts the upper surface of one conductor L5 at its lower surface. Each contact CS5 contacts the upper surface of one conductor L5 at its lower surface. The multiple contacts CS5 in the connection area PA contact the upper surface of one conductor L4 at their lower surfaces.

[0163] The substrate W2 is located at a layer above the layers of the contacts CS2 and CS5.

[0164] Transistor Tr2 is located below and near the lower surface of substrate W2. Transistor Tr2 includes a gate insulator on the lower surface of substrate W2, a gate electrode on the lower surface of the gate insulator, and a pair of source / drain regions sandwiching the region above the gate electrode. Each gate electrode is connected to the upper surface of a contact C7 on its lower surface. Each source / drain region is connected to the upper surface of a contact CS2 on its lower surface.

[0165] Each path TS is in contact with the upper surface of one contact CS5 at its lower surface.

[0166] Insulator 25 extends from the top surface of bonding terminal BD2L and the top surface of insulator 24 to the top surface of contact C8. Insulator 25 fills the area above bonding terminal BD2L and insulator 24 where contacts C4, C5, C6, C7, CS2, and CS5, conductors L3, L4, and L5, and transistor Tr2 are not provided.

[0167] The lower surface of each contact C9 is in contact with the upper surface of one path TS.

[0168] The lower surface of each conductor L6 is in contact with the upper surface of one contact C9. The lower surface of one conductor L6 in the connection area PA is in contact with the upper surfaces of the plurality of contacts C9.

[0169] Each contact C10 is in contact with the upper surface of one conductor L6 at its lower surface. The plurality of contacts C10 in the connection area PA are in contact with the upper surface of one conductor L6 at their lower surfaces.

[0170] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 fills the area from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no components are provided, that is, the area where the contacts C9 and C10 and the conductor L6 are not provided.

[0171] Each of the joining terminals BD2U is in contact with the upper surface of one contact C10 at its lower surface.

[0172] 1.4.3. Third Modification

[0173] The arrangement of the first structure 100, the second structure 200 and the third structure 300 is not limited to Figure 3 and Figure 5 The arrangement shown can be arbitrary.

[0174] Figure 19 An example of a cross-sectional structure of a portion of a storage device according to a third modified example of the first embodiment is shown. Figure 19 As shown, the third structure 300 is located on the upper surface of the first structure 100, and the second structure 200 is located on the upper surface of the third structure 300. The second structure 200 has the same orientation as the second structure 200 in the second modification.

[0175] The third structure 300 includes a connecting terminal BD3L instead of the connecting terminal BD3 and a connecting terminal BD3U instead of the external connection terminal PD. The third structure 300 further includes a contact C15 , a conductor L10 , and an insulator 45 .

[0176] The lower surface of each contact C11 is in contact with the upper surface of one connecting terminal BD3L.

[0177] The upper surfaces of the plurality of contacts C13 in the connection area PA are in contact with the lower surface of one conductor L8 instead of being in contact with the external connection terminal PD.

[0178] The contact C15 is in contact with the upper surface of one conductor L10 at its lower surface. The plurality of contacts C15 in the connection area PA are in contact with one conductor L10 at their lower surfaces.

[0179] The upper surface of each contact C15 is in contact with the lower surface of one connecting terminal BD3U.

[0180] The insulator 45 fills a region in the layer where the joining terminals BD3U are located and where no joining terminals BD3U are provided.

[0181] The upper surface of each connecting terminal BD3U is in contact with the lower surface of one connecting terminal BD2L.

[0182] The second structure 200 further includes external connection terminals PD and an insulator 41. Each external connection terminal PD is in contact with the upper surface of each of the plurality of contacts C10 at its lower surface.

[0183] 2. Second Implementation

[0184] Figure 20 An example of a cross-sectional structure of a portion of the second embodiment is shown. Figure 20 Shown with the first embodiment Figure 7 Same area.

[0185] like Figure 20 As shown, each separation structure DS includes a first portion DSA and a second portion DSB. The first portion DSA occupies the lower portion of the lower surface of the separation structure DS. The second portion DSB is located on the upper surface of the first portion DSA. The second portion DSB occupies a portion of the upper surface of the separation structure DS. The first portion DSA has an inverted tapered shape. The second portion DSB has a tapered shape. In one example, the first portion DSA and the second portion DSB include silicon oxide.

[0186] The entire process of the manufacturing method of the storage device structure of the second embodiment is the same as that of the first embodiment. Figure 9 The process is the same.

[0187] Figures 21 to 25 An example of a state during the manufacture of a part of the storage device according to the second embodiment will be described in sequence. Figures 21 to 25 An example of the state during the manufacture of the second structure 200 will be sequentially shown. The following describes the differences from the first embodiment.

[0188] Figure 21 Shown as Figure 9 A process that is performed as part of step ST1 of the process. Figure 21 In the process shown, in the connection area PA, instead of Figure 5 The isolation structure DS in the process shown is formed to form the first portion DSA of the isolation structure DS. The formation method is similar to that of STI, including trench formation using a combination of photolithography and anisotropic etching, and burying the trench with the material of the first portion DSA. Due to the use of anisotropic etching, the first portion DSA of the isolation structure DS has a tapered shape.

[0189] Figures 22 to 25 Shown as Figure 9 The process is performed as part of step ST3 of the process. Figure 22As shown, the structure formed by the steps up to this point, that is, the structure including a portion of the second structure 200, is inverted relative to the xy plane and bonded to the first structure 100. As a result, the first portion DSA of the isolation structure DS has an inverted tapered shape. Next, the transistor Tr2 is formed.

[0190] like Figure 23 As shown, the via TS and the insulator SP1 are formed. The method of forming the via TS and the insulator SP1 is the same as that described in the first embodiment. Figures 13 to 15 The method described is the same.

[0191] like Figure 24 As shown, openings OP2 are formed by partially removing the substrate W2. Each opening OP2 is formed in a region where the second portion DSB of the separation structure DS is to be formed. Each opening OP2 extends from the upper surface of the substrate W2 to the upper surface of the first portion DSA of the separation structure DS. Examples of methods for forming the openings OP2 include photolithography and anisotropic etching such as RIE. The use of anisotropic etching gives the openings OP2 a tapered shape.

[0192] like Figure 25 As shown, the opening OP2 is filled with the material of the second portion DSB of the separation structure DS, thereby completing the separation structure DS.

[0193] The subsequent steps are the same as those in the first embodiment.

[0194] Reference Figure 24 The process can also be referred to Figure 23 That is, the opening OP2 is formed, and then the via TS and the insulator SP1 are formed.

[0195] The separated structure DS may include only the second portion DSB. Figure 26 An example of a cross-sectional structure of a portion of a storage device according to a modification of the second embodiment is shown. Figure 26 Shown with Figure 20 And the first embodiment Figure 7 Same area. Figure 26 As shown, the separation structure DS includes the second portion DSB extending from the upper surface to the lower surface of the substrate W2.

[0196] Figure 26 The structure can be formed through the following manufacturing steps. Figures 27 to 31 An example of a state during the manufacture of a part of a storage device according to a modification of the second embodiment will be described in sequence. Figures 27 to 31 An example of a state during the production of the second structure 200 of the modified example will be sequentially described.

[0197] Figure 27 Shown as Figure 9 A process that is performed as part of step ST1 of the process. Figure 27 In the illustrated process, the separation structure DS is not formed in the connection region PA, but is a structure including a portion of the second structure 200 .

[0198] Figures 28 to 31 Shown as Figure 9 The process is performed as part of step ST3 of the process. Figure 28 As shown, the structure formed by the steps up to this point, that is, the structure including a portion of the second structure 200, is inverted with respect to the xy plane and bonded to the first structure 100. Next, the transistor Tr2 is formed.

[0199] like Figure 29 As shown, the via TS and the insulator SP1 are formed. The method of forming the via TS and the insulator SP1 is the same as that described in the first embodiment. Figures 13 to 15 The method described is the same.

[0200] like Figure 30 As shown, openings OP3 are formed by partially removing the substrate W2. Each opening OP3 is formed in a region where the second portion DSB of the separation structure DS is to be formed. Each opening OP3 extends from the upper surface of the substrate W2 to the lower surface. Examples of methods for forming the openings OP3 include photolithography and anisotropic etching such as RIE. The use of anisotropic etching gives the openings OP3 a tapered shape.

[0201] like Figure 31 As shown, the opening OP3 is filled with the material of the second portion DSB of the separation structure DS, thereby completing the separation structure DS.

[0202] The subsequent steps are the same as those in the first embodiment.

[0203] Reference Figure 30 The process can also be referred to Figure 29 That is, the opening OP3 is formed, and then the via TS and the insulator SP1 are formed.

[0204] The first, second, or third modification of the first embodiment may also be applied to the second embodiment.

[0205] In reference Figure 25 In the above-described steps, the opening OP2 may be filled by forming the insulator 26 . In this case, the second portion DSB of the separation structure DS is made of the same material as the insulator 26 .

[0206] The insulator SP1 and the second portion DSB can also be formed by a common process. Figure 25After the above-mentioned steps, the opening OP2 is further formed in the step of forming the opening for the via TS and the insulator SP1. In the next step of forming the insulator SP1, the opening OP2 is filled.

[0207] According to the second embodiment as well, the same advantages as those obtained according to the first embodiment can be obtained.

[0208] 3. Third Implementation

[0209] The third embodiment is based on the second embodiment. The third embodiment is different from the second embodiment in the structure of the second portion DSB of the separation structure DS.

[0210] Figure 32 An example of a cross section of a part of the third embodiment is shown. Figure 32 Shown with the first embodiment Figure 7 Same area.

[0211] like Figure 32 As shown, the second portion DSB includes a conductive body DSB1 and an insulator DSB2. The conductive body DSB1 extends along the z-axis and occupies a region including the center of the second portion DSB2. In one example, the conductive body DSB1 comprises the same material as the via TS. The insulator DSB2 covers the sides of the conductive body DSB1.

[0212] Figure 32 The structure shown can be formed by the same process as the process for forming the set of the via TS and the insulator SP1. Figure 23 In the above process, before the via TS and the insulator SP1 are embedded, the reference Figure 24 The opening OP2 is formed by a process different from or in the same process as the process for forming the opening for the set of the via TS and the insulator SP1. Subsequently, the insulator DSB2 is formed by the same process as that for forming the insulator SP1, and the conductive body DSB1 is formed by the same process as that for forming the via TS.

[0213] The modified example of the second embodiment can also be applied to the third embodiment. Figure 33 As shown, the separation structure DS includes a second portion DSB extending from the upper surface to the lower surface of the substrate W2 , and the second portion DSB includes a conductor DSB1 and an insulator DSB2 .

[0214] The first, second, or third modification of the first embodiment may also be applied to the third embodiment.

[0215] According to the third embodiment as well, the same advantages as those of the first embodiment can be obtained.

[0216] 4. Fourth embodiment

[0217] Figure 34 and Figure 35 An example of a cross-sectional structure of a portion of the fourth embodiment is shown. Figure 34 and Figure 35 The first embodiment is shown Figure 7 Same area.

[0218] like Figure 34 As shown, the isolation structure DS is composed of a diffusion region of p-type impurities. The substrate W2 contains n-type impurities. Examples of p-type impurities include boron (B). Examples of n-type impurities include arsenic (As).

[0219] You can also Figure 35 As shown, the isolation structure DS is composed of an n-type impurity diffusion region, and the substrate W2 contains p-type impurities.

[0220] In one example, the separation structure DS can be referred to in the first embodiment. Figure 10 In the above-mentioned process, the contact C5 is formed by ion implantation before formation.

[0221] The first, second, or third modification of the first embodiment may also be applied to the fourth embodiment.

[0222] According to the fourth embodiment as well, the same advantages as those obtained according to the first embodiment can be obtained.

[0223] 5. Other variations

[0224] The storage device 1 may further include one or more fourth structures that are the same as the second structure 200 .

[0225] The configuration of the via TS and the insulator SP1 is not limited to Figure 7 The structure shown can also have Figure 36 The structure shown in FIG. That is, the upper portion of the passage TS and the upper portion of the insulator SP1 protrude from the upper surface of the substrate W2. Such a structure is produced, for example, by the following process. Figure 13 In the process shown, a mask is formed on the upper surface of the substrate W2, and the mask is used to refer to Figure 13 The above-mentioned photolithography process and anisotropic etching are performed to form the opening OP. Next, the via TS and the insulator SP1 are formed with the mask remaining, and then the mask is removed. As a result, the via TS and the insulator SP1 protrude from the upper surface of the substrate W2 by an amount corresponding to the thickness of the area where the mask was previously present. Figure 36 The structure shown is based on the basic mode of the first embodiment. Figure 7 However, Figure 36 The structure shown can also be applied to the modification of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment.

[0226] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Indeed, the novel embodiments described herein may be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and variations in the form of the embodiments described herein may be made without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as are within the scope and spirit of the invention.

Claims

1. A storage device comprising: a first substrate; a first transistor on the first substrate; a second substrate disposed above the first transistor; external connection terminals disposed above the second substrate; a second transistor on the second substrate; a first conductor penetrating the second substrate and electrically connecting the first transistor to the external connection terminal; a first separation structure, wherein the first separation structure is annular and surrounds the first conductor when viewed from the first direction, penetrates the second substrate, and separates the second substrate; as well as A memory cell array is electrically connected to the first transistor and the second transistor.

2. The storage device according to claim 1, wherein The first separation structure includes a first insulator that penetrates the second substrate in the first direction.

3. The storage device according to claim 2, wherein: The second substrate includes a first surface and a second surface that are parallel to each other in the first direction. A length of the first insulator along a second direction intersecting a direction in which the first insulator extends increases from the first surface side of the second substrate toward the second surface side of the second substrate. The storage device according to claim 3 , wherein: further comprising a second insulator provided in the second substrate and surrounding the second transistor, A length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate.

5. The storage device according to claim 4, wherein: The length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate. The storage device according to claim 1 , wherein: The first separation structure comprises: third insulator; as well as A fourth insulator is provided on the first direction side of the third insulator.

7. The storage device according to claim 6, wherein: The second substrate includes a first surface and a second surface that are parallel to each other in the first direction. The length of the third insulator along a second direction intersecting the direction in which the third insulator extends increases from the first surface side of the second substrate toward the second surface side of the second substrate. A length of the fourth insulator along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate. The storage device according to claim 7 , wherein: further comprising a second insulator provided in the second substrate and surrounding the second transistor, A length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate.

9. The storage device according to claim 8, wherein: The length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate.

10. The storage device according to claim 6, wherein: The first separation structure further includes a second conductor, The third insulator surrounds the second conductor. The storage device according to claim 10 , wherein: The second substrate includes a first surface and a second surface that are parallel to each other in the first direction. A length of the second conductor along a second direction intersecting the direction in which the second conductor extends decreases from the first surface side of the second substrate toward the second surface side of the second substrate.

12. The storage device according to claim 11, wherein further comprising a second insulator provided in the second substrate and surrounding the second transistor, A length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate.

13. The storage device according to claim 12, wherein: The length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate.

14. The storage device according to claim 1, wherein The second substrate contains impurities of the first conductivity type, The first isolation structure contains impurities of a second conductivity type different from the first conductivity type.

15. The storage device according to claim 1, wherein A second separation structure is further provided, and when viewed from the first direction, the second separation structure surrounds the first separation structure.

16. The storage device according to claim 1, wherein Also features: a first configuration comprising a first terminal; a second structure connected to the first structure on the first direction side of the first structure, comprising a second terminal connected to the first terminal and a third terminal electrically connected to the second terminal; as well as The third structure is connected to the second structure on the first direction side of the second structure and includes a fourth terminal connected to the third terminal and electrically connected to the external connection terminal.

17. The storage device according to claim 1, wherein The device includes the first conductor and further comprises a plurality of first conductors that penetrate the second substrate and electrically connect the first transistor to the external connection terminal.

18. A method for manufacturing a storage device, comprising: forming a first structure comprising a first substrate, a first transistor on the first substrate, and a first conductor in contact with the first substrate, the first structure forming comprising forming a first annular separation structure in the first substrate surrounding a first region of the first substrate; a process of bonding a second structure to the first structure, the second structure comprising a second substrate and a second transistor on the second substrate; forming a second conductor, the second conductor penetrating the first substrate in the first region and being in contact with the first conductor; as well as A process of forming a third structure including a memory cell array electrically connected to the first transistor and the second transistor, and an external connection terminal electrically connected to the second conductor.

19. The method for manufacturing a storage device according to claim 18, wherein: The process of forming the first separate structure includes forming a first insulator in an opening extending from the first surface of the first substrate.

20. The method for manufacturing a memory device according to claim 19, wherein: The method further includes forming a second separate structure in the first substrate after the second structure and the first structure are bonded together, the second separate structure extending from a surface opposite to the first surface and contacting the first separate structure.

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