Memory device, operating method thereof, memory system, and computer readable storage medium

Abstract

The invention provides a memory device and an operation method thereof, a memory system and a computer readable storage medium. The memory device comprises a memory array and a peripheral circuit coupled with the memory array; the memory array comprises a plurality of memory cell strings and conductive wires coupled with one ends of the memory cell strings; the peripheral circuit is configured to apply a first pre-charge voltage to the conductive line during a pre-charge phase of a first program cycle; applying a second pre-charging voltage to the conductor wire in a pre-charging stage of a second programming cycle after the first programming cycle; wherein the second pre-charge voltage is greater than the first pre-charge voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory device and an operating method thereof, a memory system, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems, such as solid-state drives (SSDs), are appearing in electronic devices. SSDs, due to their fast read and write speeds, vibration resistance, low power consumption, quiet operation, low heat generation, and lightweight design, have found widespread application in military, automotive, industrial, medical, and aviation applications. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof, a memory system, and a computer-readable storage medium to solve at least one problem existing in the prior art.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory device comprising: a memory array and a peripheral circuit coupled to the memory array; the memory array comprises a plurality of memory cell strings and a conductive line coupled to one end of the memory cell strings; the peripheral circuit is configured to: apply a first precharge voltage to the conductive line in a precharge phase of a first programming loop; apply a second precharge voltage to the conductive line in a precharge phase of a second programming loop following the first programming loop; wherein the second precharge voltage is greater than the first precharge voltage.

[0005] In an optional embodiment, the peripheral circuit is further configured to: apply a third pre-charge voltage to the conductive line in a pre-charge phase of a third programming loop after the second programming loop; the third pre-charge voltage is greater than the second pre-charge voltage.

[0006] In an optional embodiment, the first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

[0007] In an optional embodiment, the peripheral circuit is further configured to: apply a first voltage to the word line coupled to the target memory cell during the precharge phase of the first programming loop; apply a second voltage to the word line coupled to the target memory cell during the precharge phase of the second programming loop; and the second voltage is greater than the first voltage.

[0008] In an optional embodiment, the memory array also includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group includes at least one first word line and at least one second word line, the first word line is close to the word line coupled to the target memory cell, and the second word line is away from the word line coupled to the target memory cell; the peripheral circuit is further configured to: in the pre-charge stage of the first programming loop, apply a third voltage to the first word line; the third voltage is less than or equal to the first voltage; and / or, in the pre-charge stage of the second programming loop, apply a fourth voltage to the first word line; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

[0009] In an optional embodiment, the peripheral circuit is further configured to: apply a fifth voltage to the second word line in the pre-charge phase of the first programming loop; the fifth voltage is less than the third voltage; and / or, apply a sixth voltage to the second word line in the pre-charge phase of the second programming loop; the sixth voltage is less than the fourth voltage, and the sixth voltage is greater than the fifth voltage.

[0010] In an optional embodiment, the first programming loop includes at least one first pulse stage, and the second programming loop includes at least one second pulse stage; the peripheral circuit is specifically configured to: apply the corresponding first pre-charge voltage to the conductive line in each first pulse stage; apply the corresponding second pre-charge voltage to the conductive line in each second pulse stage; wherein, in the first programming loop, the first pre-charge voltage applied in the first pulse stage arranged in sequence is less than or equal to the first pre-charge voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second pre-charge voltage applied in the second pulse stage arranged in sequence is less than or equal to the second pre-charge voltage applied in the second pulse stage arranged in sequence.

[0011] In an optional embodiment, the corresponding multiple first pre-charge voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second pre-charge voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0012] In an optional embodiment, the peripheral circuit is specifically configured to: apply the corresponding first voltage to the word line coupled to the target memory cell in each first pulse stage; apply the corresponding second voltage to the word line coupled to the target memory cell in each second pulse stage; wherein, in the first programming loop, the first voltage applied in the first pulse stage arranged in sequence is less than or equal to the first voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second voltage applied in the second pulse stage arranged in sequence is less than or equal to the second voltage applied in the second pulse stage arranged in sequence.

[0013] In an optional embodiment, the corresponding multiple first voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0014] In an optional embodiment, the conductive line includes a bit line or a common source line.

[0015] In an optional embodiment, the memory array also includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; the peripheral circuit is further configured to: apply a seventh voltage to the third word line in the pre-charge stage of the first programming loop; apply an eighth voltage to the third word line in the pre-charge stage of the second programming loop; the seventh voltage is less than the eighth voltage.

[0016] In an optional embodiment, the memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; the peripheral circuit is further configured to: connect the fourth word line to the ground voltage during the precharge phase of the first programming loop and the precharge phase of the second programming loop.

[0017] In an optional embodiment, the peripheral circuit is further configured to: apply a first programming voltage to the word line coupled to the target memory cell during the programming voltage application phase of the first programming loop; apply a second programming voltage to the word line coupled to the target memory cell during the programming voltage application phase of the second programming loop; and the second programming voltage is greater than the first programming voltage.

[0018] In an optional embodiment, the conductive line includes a common source line, and the memory array further includes a bit line coupled to the other end of the memory cell string; the peripheral circuit is further configured to: apply a programming inhibit voltage to the bit lines other than the bit line coupled to the target memory cell in the precharge phase and the programming voltage application phase of the first programming cycle, and in the precharge phase and the programming voltage application phase of the second programming cycle.

[0019] In a second aspect, an embodiment of the present disclosure provides a memory system, comprising a memory controller and a memory device as described in any of the above embodiments; the memory controller is coupled to the memory device and is configured to control the memory device.

[0020] In a third aspect, an embodiment of the present disclosure provides an operating method for a memory device, wherein the memory device includes a plurality of memory cell strings and a conductive line coupled to one end of the memory cell strings; the operating method includes: applying a first pre-charge voltage to the conductive line in a pre-charge stage of a first programming loop; applying a second pre-charge voltage to the conductive line in a pre-charge stage of a second programming loop after the first programming loop; the second pre-charge voltage is greater than the first pre-charge voltage.

[0021] In an optional embodiment, the operating method further includes: applying a third pre-charge voltage to the conductive line during a pre-charge phase of a third programming loop after the second programming loop.

[0022] In an optional embodiment, the third pre-charge voltage is greater than the second pre-charge voltage; the first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

[0023] In an optional embodiment, the operating method further includes: applying a first voltage to the word line coupled to the target memory cell during the precharge phase of the first programming loop; applying a second voltage to the word line coupled to the target memory cell during the precharge phase of the second programming loop; and the second voltage is greater than the first voltage.

[0024] In an optional embodiment, the memory array also includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group includes at least one first word line and at least one second word line, the first word line is close to the word line coupled to the target memory cell, and the second word line is away from the word line coupled to the target memory cell; the operating method also includes: in the pre-charge stage of the first programming loop, applying a third voltage to the first word line; the third voltage is less than or equal to the first voltage; and / or, in the pre-charge stage of the second programming loop, applying a fourth voltage to the first word line; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

[0025] In an optional embodiment, the operating method further includes: applying a fifth voltage to the second word line during the pre-charge phase of the first programming loop; the fifth voltage is less than the third voltage; and / or, applying a sixth voltage to the second word line during the pre-charge phase of the second programming loop; the sixth voltage is less than the fourth voltage, and the sixth voltage is greater than the fifth voltage.

[0026] In an optional embodiment, the first programming loop includes at least one first pulse stage arranged in sequence, and the second programming loop includes at least one second pulse stage arranged in sequence; the first pre-charging voltage is applied to the conductive line in the pre-charging stage of the first programming loop, and the second pre-charging voltage is applied to the conductive line in the pre-charging stage of the second programming loop after the first programming loop, including: applying the corresponding first pre-charging voltage to the conductive line in each first pulse stage, and applying the corresponding second pre-charging voltage to the conductive line in each second pulse stage; wherein, in the first programming loop, the first pre-charging voltage applied in the first pulse stage arranged in sequence is less than or equal to the first pre-charging voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second pre-charging voltage applied in the second pulse stage arranged in sequence is less than or equal to the second pre-charging voltage applied in the second pulse stage arranged in sequence.

[0027] In an optional embodiment, the corresponding multiple first pre-charge voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second pre-charge voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0028] In an optional embodiment, applying a first voltage to the word line coupled to the target memory cell in the precharge phase of the first programming loop, and applying a second voltage to the word line coupled to the target memory cell in the precharge phase of the second programming loop, include: applying the corresponding first voltage to the word line coupled to the target memory cell in each first pulse phase; applying the corresponding second voltage to the word line coupled to the target memory cell in each second pulse phase; wherein, in the first programming loop, the first voltage applied in the first pulse phase arranged in sequence is less than or equal to the first voltage applied in the first pulse phase arranged in sequence; in the second programming loop, the second voltage applied in the first pulse phase arranged in sequence is less than or equal to the second voltage applied in the second pulse phase arranged in sequence.

[0029] In an optional embodiment, the corresponding multiple first voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0030] In an optional embodiment, the memory array also includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; the operating method also includes: in the pre-charge stage of the first programming loop, applying a seventh voltage to the third word line; in the pre-charge stage of the second programming loop, applying an eighth voltage to the third word line; the seventh voltage is less than the eighth voltage.

[0031] In an optional embodiment, the memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; the operating method further includes: in the precharge stage of the first programming loop and the precharge stage of the second programming loop, connecting the fourth word line to the ground voltage.

[0032] In an optional embodiment, the operating method further includes: applying a first programming voltage to a word line coupled to a target memory cell during a programming voltage application phase of the first programming loop; applying a second programming voltage to a word line coupled to the target memory cell during a programming voltage application phase of the second programming loop; and the second programming voltage is greater than the first programming voltage.

[0033] In an optional embodiment, the conductive line includes a common source line, and the memory array also includes a bit line coupled to the other end of the memory cell string; the operating method also includes: in the pre-charging stage and the programming voltage application stage of the first programming cycle, and in the pre-charging stage and the programming voltage application stage of the second programming cycle, applying a programming inhibit voltage to the bit lines other than the bit lines coupled to the target memory cell.

[0034] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method as described in any of the above embodiments can be implemented.

[0035] In the technical solution provided in the embodiment of the present disclosure, a first pre-charge voltage is applied to the conductive line in the pre-charge stage of the first programming loop, and a second pre-charge voltage is applied to the conductive line in the pre-charge stage of the second programming loop after the first programming loop, and the second pre-charge voltage is greater than the first pre-charge voltage. This effectively improves the Fowler-Nordheim tunneling effect and the hot carrier effect in the entire programming process, thereby effectively suppressing programming interference and improving the performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of an exemplary system having a memory system provided for embodiments of the present disclosure.

[0037] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for embodiments of the present disclosure.

[0038] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure.

[0039] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for embodiments of the present disclosure.

[0040] Figure 5 A schematic cross-sectional view of a memory array including memory cell strings provided in an embodiment of the present disclosure.

[0041] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for embodiments of the present disclosure.

[0042] Figure 7 A schematic structural diagram of a memory device provided in an embodiment of the present disclosure.

[0043] Figure 8 A schematic diagram of the relationship between the number of memory cells and threshold voltage provided by an embodiment of the present disclosure.

[0044] Figure 9 A flowchart of the operating method provided in an embodiment of the present disclosure.

[0045] Figure 10 A schematic diagram of dividing a programming process into multiple programming loops according to an embodiment of the present disclosure is provided.

[0046] Figure 11 A schematic diagram of voltage application during the step-by-step pulse programming process provided in an embodiment of the present disclosure.

[0047] Figure 12 A schematic diagram of a voltage waveform change provided in an embodiment of the present disclosure Figure 1 .

[0048] Figure 13 Schematic diagram of the channel potential waveform at each corresponding position in the channel during the pre-charging phase provided by an embodiment of the present disclosure.

[0049] Figure 14 A schematic diagram illustrating the relationship between the pre-charge voltage, the Fowler-Nordheim tunneling effect, and the hot carrier injection effect provided in an embodiment of the present disclosure.

[0050] Figure 15 Schematic diagram of channel potential waveforms at corresponding positions in the channel during the voltage raising stage provided by an embodiment of the present disclosure.

[0051] Figure 16 A schematic diagram of the relationship between pre-charge voltages in different programming cycles provided by an embodiment of the present disclosure.

[0052] Figure 17 A schematic diagram of a voltage waveform change provided in an embodiment of the present disclosure Figure 2 .

[0053] Figure 18 A schematic diagram of a voltage waveform change provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0054] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0056] In the drawings, like reference numerals refer to like elements throughout.

[0057] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system of a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking a memory system including a three-dimensional NAND memory as an example.

[0060] Figure 1Schematic diagram of an exemplary system with a memory system provided in an embodiment of the present disclosure. In an embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host device 101 and a memory system 102. Memory system 102 may include one or more memory devices 103 and a memory controller 104. Host device 101 may include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host device 101 may be configured to send data to or receive data from memory system 102.

[0061] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (CFC), a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as in a solid-state drive or an embedded multi-media card (eMMC).

[0062] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of memory devices. That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0063] In such Figure 2In one example shown in FIG, the memory controller 104 and the single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash memory card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1 The host device 101 in FIG. 1 is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0064] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided in accordance with an embodiment of the present disclosure. The memory device 300 may be Figure 1 3. An example of a memory device 103 in FIG. Memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to memory array 301. Memory array 301 is described as a three-dimensional NAND memory array, wherein memory cells 305 are NAND memory cells, and memory cells 305 are provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0065] The following describes the principle of data writing to a floating gate type memory cell, taking a floating gate type memory cell as an example. When writing data to a memory cell, a programming voltage can be applied to the control gate of the floating gate field effect transistor (FET) to cause electrons in the channel of the FET to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the magnitude of the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that when the threshold voltage Vth of the floating gate FET is different, the voltage required to be applied to the control gate of the FET to control the conduction of the FET is different. Therefore, the magnitude of the threshold voltage Vth of the FET can reflect the content of the stored data.

[0066] In some embodiments, each memory cell 305 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) that stores two bits per cell, a triple-level cell (TLC) that stores three bits per cell, or a quad-level cell (QLC) that stores four bits per cell.

[0067] like Figure 4As shown in FIG, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of the memory cell strings 304 in the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, and data can be read from or written to the bit line 311 via an output bus (not shown). In some embodiments, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0068] like Figure 4 As shown in FIG, a memory cell string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory cell strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0069] Figure 5 A cross-sectional schematic diagram of a memory array including a memory cell string provided in an embodiment of the present disclosure. Figure 5As shown, a memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 alternately stacked in sequence, and a channel structure 403 vertically extending through the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, with two adjacent gate layers 401 separated by an insulating layer 402. The number of memory cells included in the memory array is primarily related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0070] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory cell string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as an upper selection gate line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a lower selection gate line, and the gate layer 401 extending laterally between the upper selection gate line and the lower selection gate line can serve as a word line layer.

[0071] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0072] It should be noted that, in some other embodiments, the memory array may only include the stacked structure 400 but not a substrate. The present disclosure does not limit whether the memory array includes a substrate.

[0073] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polysilicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (for example, a pillar shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0074] Return Reference Figure 4 , the peripheral circuit 302 can be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309 and the upper selection line 308. The peripheral circuit 302 may include any suitable analog, digital and mixed signal circuits to apply a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309 and the upper selection line 308, and sense the voltage signal and / or the current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0075] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic unit 505 and select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 504.

[0076] The row decoder / word line driver 503 can be configured to be controlled by the control logic unit 505 and select / deselect memory blocks of the memory array 301 and select / deselect word lines of the memory blocks. The row decoder / word line driver 508 can also be configured to drive word lines using word line voltages generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 can also select / deselect and drive lower select lines and upper select lines. As described in detail below, the row decoder / word line driver 503 is configured to perform programming operations on memory cells coupled to (one or more) selected word lines. The voltage generator 504 can be configured to be controlled by the control logic unit 505 and generate word line voltages (e.g., read voltage, program voltage, precharge voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0077] The control logic unit 505 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 506 can be coupled to the control logic unit 505 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The flash memory interface 507 can be coupled to the control logic unit 505 and act as a control buffer to buffer control commands received from a host device (not shown) and relay them to the control logic unit 505, as well as buffer status information received from the control logic unit 505 and relay it to the memory controller. The flash memory interface 507 can also be coupled to the column decoder / bit line driver 502 via the data bus 508 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0078] In pursuit of higher storage density, the number of stacked layers in 3D flash memory is getting higher and higher, and the number of storage bits of storage units is increasing, including TLC that can achieve three-bit storage and QLC that can achieve four-bit storage. For QLC, a page must be divided into 16 states, which makes the programming interference during the programming process more serious. In order to reduce costs, reference Figure 7As shown in (1) to (2), the number of stacked layers of the three-dimensional flash memory continues to increase. In order to reduce the difficulty of channel etching, the ratio of the distance Ls between the word line layers and the thickness Lg of the word line layers (Ls / Lg) in the stacked structure shown in (2) to (3) continues to decrease. As Ls / Lg continues to decrease and the number of stacked layers continues to increase, Fowler-Nordheim tunneling (FN) and hot carrier injection (Hot Carrier Injection) become more and more serious, resulting in serious programming crosstalk. Figure 8 As shown, the threshold voltage width of the L0 state (erased state) is widened, which greatly challenges the reliability of the flash memory. How to suppress program disturb and widen the threshold voltage window has become an urgent problem to be solved at this stage.

[0079] The present disclosure provides an operating method for a memory device. Figure 9 A flowchart of the operating method provided in the embodiment of the present disclosure is shown in FIG. Figure 9 As shown, the operating method of the memory device includes the following steps: step S10: applying a first precharge voltage to the conductive line in the precharge stage of the first programming cycle; step S20: applying a second precharge voltage to the conductive line in the precharge stage of the second programming cycle after the first programming cycle; wherein the second precharge voltage is greater than the first precharge voltage.

[0080] In the embodiment of the present disclosure, a first pre-charge voltage is applied to the conductive line in the pre-charge stage of the first programming loop, and a second pre-charge voltage is applied to the conductive line in the pre-charge stage of the second programming loop after the first programming loop, and the second pre-charge voltage is greater than the first pre-charge voltage. This effectively improves the Fowler-Nordheim tunneling effect and the hot carrier effect in the entire programming process, thereby effectively suppressing program interference and improving the performance of the memory device.

[0081] In some embodiments, the programming of the three-dimensional flash memory device is mainly performed by Incremental Step Pulse Program (ISPP). During the programming process, when applying the programming voltage, the voltage is not applied all at once, but is increased step by step until the voltage reaches the programming requirement. Figure 10 As shown, the programming process includes multiple programming loops, such as the first programming loop, the second programming loop, the third programming loop...the nth programming loop, each programming loop includes at least one pulse phase, and each pulse phase includes a verification phase, a precharge phase, and a programming voltage application phase.

[0082] It should be noted that the number of pulse phases included in each programming loop may be the same or different. For example, the number of pulse phases included in the first programming loop may be greater than, equal to, or less than the number of pulse phases included in the second programming loop.

[0083] Figure 11 FIG. 1 shows a schematic diagram of ISPP programming provided by an embodiment of the present disclosure. Figure 11 As shown, during the programming process, first, an initial programming voltage (Vpgm) is applied to the word line coupled to the target memory cell; then, in the first pulse phase, it is verified whether the initial programming voltage reaches the required programming voltage. If not, a voltage step length Vispp is added to the initial programming voltage to obtain a programming voltage (Vpgm+Vispp), and the programming voltage (Vpgm+Vispp) is applied to the word line coupled to the target memory cell; in the second pulse phase, it is further verified whether the programming voltage (Vpgm+Vispp) reaches the required programming voltage. The above process is repeated until the programming voltage applied to the word line coupled to the target memory cell reaches the required programming voltage, and then programming is stopped. It should be noted that, Figure 11 The pre-charge phase in each pulse phase is not shown.

[0084] In some specific examples, the memory device includes a memory array and a peripheral circuit coupled to the memory array; the memory array includes a plurality of memory cell strings and a conductive line coupled to one end of the memory cell strings.

[0085] In some specific examples, the conductive line includes a bit line or a common source line.

[0086] In some specific examples, programming can be forward programming or reverse programming. For example, forward programming can refer to a bottom-up programming sequence, and reverse programming can refer to a top-down programming sequence, but the present disclosure is not limited thereto. In forward programming, the conductive line can be a bit line, that is, the bit line terminal can be precharged; in reverse programming, the conductive line can be a common source line, that is, the common source line can be precharged.

[0087] The following description will first be made by taking the reverse programming as the programming sequence and the precharging through the common source line ACS as an example.

[0088] It should be noted that, whether it is forward programming or reverse programming, the WL numbering can start from WL0 to WLn+x+m (assuming that the memory device contains n+y+1 word lines in total), and the word lines arranged from top to bottom in the stacked structure are numbered continuously, wherein during programming, programming operations are performed in sequence from the WL with a smaller number to the WL with a larger number, and WL0 is the first WL to be programmed, that is, in the same memory cell string, programming is performed in sequence from the memory cell coupled to the WL with a smaller number to the memory cell coupled to the WL with a larger number. Figure 12 In the reverse programming shown in FIG, WL0 starts programming first, and among the multiple word lines in the stacked structure, WL0 is closest to the upper selection line TSL. Figure 18 In the forward programming shown, WL0 starts programming first, and among the multiple word lines in the stack structure, WL0 is closest to the lower selection line BSL. Figure 12 as well as Figure 18 In the illustrated embodiment, Sel and WLn are both word lines coupled to the target memory cells.

[0089] like Figure 12 As shown, in the precharge phase of the first programming loop, a first precharge voltage Vacs is applied to the common source line, and in the precharge phase of the second programming loop after the first programming loop, a second precharge voltage Vacs+x1 is applied to the common source line.

[0090] Figure 13 Schematic diagram of the channel potential waveform at each corresponding position in the channel during the pre-charging stage; Figure 14 Figure 1 is a diagram showing the relationship between the pre-charge voltage and the Fowler-Nordheim tunneling effect and the hot carrier injection effect, wherein the solid line is the relationship curve between the pre-charge voltage and the Fowler-Nordheim tunneling effect, and the dotted line is the relationship curve between the pre-charge voltage and the hot carrier injection effect. Figure 13 as well as Figure 14 As shown in FIG. 1 , the HCI interference becomes more serious in the pre-charge stage of the pulse stage, and the greater the pre-charge voltage applied to the common source line or the bit line in the pre-charge stage, the more serious the HCI interference. Figure 15 Schematic diagram of the channel potential waveform at each corresponding position in the channel during the voltage raising stage, wherein the dotted line is a schematic diagram of the channel potential under a low pre-charge voltage, and the solid line is a schematic diagram of the channel potential under a high pre-charge voltage. Figure 15 As shown, during the voltage boosting phase, it is hoped that the boost potential of the channel near the word line coupled to the target memory cell reaches a certain level, in order to reduce the word line-channel voltage difference and reduce the L0 interference caused by FN tunneling. The program interference caused by FN tunneling is more serious in the subsequent programming loops, and it is generally required that the pre-charge voltage in the pre-charge phase be higher. However, as Figure 14 as well as Figure 15As shown in the figure, the higher the precharge voltage, the more serious the FN interference. For program interference, if the local boosting is too high, HCI is likely to occur, and if the local boosting is not enough, FN is likely to occur. These two mechanisms balance each other. Figure 14 As shown, HCI interference in the precharge phase and interference caused by FN tunneling in the voltage rise phase have opposite precharge voltage requirements. Because interference caused by FN tunneling is most severe in the later programming cycles, the disclosed embodiment applies a relatively high precharge voltage to the common source line or bit line in the precharge phase of the subsequent programming cycles, while using a relatively low precharge voltage in the earlier programming cycles. This effectively reduces program interference caused by FN tunneling and hot carrier effects throughout the entire programming process.

[0091] The sequential arrangement in the embodiments of the present disclosure can be specifically understood as arrangement in chronological order.

[0092] In some embodiments, as Figure 12 As shown, the operating method further includes: applying a third pre-charge voltage Vacs+x1+x2 to the conductive line in a pre-charge phase of a third programming loop after the second programming loop.

[0093] It should be noted that this disclosure uses only three programming loops as an example. The disclosed embodiments do not limit the number of programming loops and may include more programming loops. However, the precharge voltage applied in a subsequent programming loop is greater than the precharge voltage applied in an earlier programming loop.

[0094] In some embodiments, the third pre-charge voltage is greater than the second pre-charge voltage; the first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

[0095] Figure 16 FIG. 1 shows a schematic diagram of the relationship between the precharge voltage in different programming cycles. Figure 16 As shown, the precharge voltages applied in each pulse stage in a programming loop can be the same, and the precharge voltages in different programming loops can increase in a linear increasing trend during the programming process.

[0096] In some embodiments, the first programming loop includes at least one first pulse stage arranged in sequence, and the second programming loop includes at least one second pulse stage arranged in sequence; the first pre-charge voltage is applied to the conductive line in the pre-charge stage of the first programming loop, and the second pre-charge voltage is applied to the conductive line in the pre-charge stage of the second programming loop after the first programming loop, including: applying the corresponding first pre-charge voltage to the conductive line in each first pulse stage, and applying the corresponding second pre-charge voltage to the conductive line in each second pulse stage; wherein, in the first programming loop, the first pre-charge voltage applied in the first pulse stage arranged in sequence is less than or equal to the first pre-charge voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second pre-charge voltage applied in the second pulse stage arranged in sequence is less than or equal to the second pre-charge voltage applied in the second pulse stage arranged in sequence.

[0097] The first programming loop may include one or more first pulse stages; the second programming loop may include one or more first pulse stages. Each first pulse stage includes a precharge stage and a programming voltage application stage. When the first programming loop includes multiple first pulse stages, a corresponding first precharge voltage is applied in each first pulse stage, and the first precharge voltage applied to the first pulse stage arranged earlier in the first programming loop in chronological order may be less than or equal to the first precharge voltage applied to the first pulse stage arranged later in chronological order.

[0098] It is understood that in the solution provided by the embodiments of the present disclosure, the pre-charge voltages of each pulse phase within a programming loop can be equal. The pre-charge voltages of each pulse phase within a programming loop can also be unequal, but the pre-charge voltage of the pulse phase arranged later in time is greater than the pre-charge voltage of the pulse phase arranged earlier in time. The pre-charge voltages of each pulse phase within a programming loop can also be partially equal and partially unequal.

[0099] In some embodiments, the corresponding multiple first pre-charge voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second pre-charge voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0100] It is understandable that when the pre-charge voltages of each pulse stage in a programming loop are not equal, the pre-charge voltages applied corresponding to multiple pulse stages in a programming loop can be set in two ways: a step-by-step increasing trend or a linear increasing trend.

[0101] In some embodiments, the operating method further includes: applying a first voltage to a word line coupled to a target memory cell during a precharge phase of the first programming loop; applying a second voltage to a word line coupled to the target memory cell during a precharge phase of the second programming loop; and the second voltage is greater than the first voltage.

[0102] like Figure 12 As shown, a first voltage (Vpre1) is applied to the word line (Sel WLn) coupled to the target memory cell in the first programming loop, and a second voltage (Vpre1+y1) is applied to Sel WLn in the precharge phase of the second programming loop.

[0103] In some specific examples, such as Figure 12 As shown, the method further includes: applying Vpre1+y1+y2 to Sel WLn during the precharge phase of the third programming loop.

[0104] In some embodiments, the corresponding multiple first voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0105] It can be understood that in order to further improve the HCI interference in the pre-charge stage of the subsequent programming loop, the embodiment of the present disclosure applies different voltages to the word line coupled to the target memory cell in different programming loops, and the voltage applied to the word line coupled to the target memory cell in the subsequent programming loop is greater than the voltage applied to the word line coupled to the target memory cell in the previous programming loop. The voltage applied to the word line coupled to the target memory cell is changed in accordance with the change of the pre-charge voltage, so that the potential difference between the corresponding channel potential under the target memory cell and the corresponding channel potential under the unprogrammed memory cell can be reduced, thereby effectively improving the HCI interference problem in the subsequent programming loop.

[0106] In an embodiment of the present disclosure, the number of pulse phases included in the first programming loop can be greater than the number of pulse phases included in the second programming loop and the number of pulse phases included in the third programming loop, and the multiple precharge voltages applied corresponding to the multiple pulse phases included in the first programming loop can be equal. In this case, it can be considered that the precharge voltage begins to increase in the latter several pulse phases of the entire programming process, and specifically, the precharge voltage can be increased when programming to a certain programming state. In other embodiments, the precharge voltage and the voltage applied to the word line coupled to the target memory cell can also be increased simultaneously in the precharge phases of the latter several pulse phases of the programming process.

[0107] In other embodiments, the number of pulse stages included in the first programming loop may be equal to the number of pulse stages included in the second programming loop and the number of pulse stages included in the third programming loop, and the multiple pre-charge voltages applied corresponding to the multiple pulse stages included in the first programming loop may be equal. In this case, it can be considered that the pre-charge voltage is increased starting from the pulse stage in the middle of the entire programming process. In this case, the multiple pre-charge voltages applied corresponding to the multiple pulse stages included in the second programming loop may be unequal, and the pre-charge voltage applied in the pulse stage arranged later in time sequence within the second programming loop is greater than the pre-charge voltage applied in the pulse stage arranged earlier, and the increase trend may include a step-by-step increase trend or a linear increase trend. The multiple pre-charge voltages applied corresponding to the multiple pulse stages included in the third programming loop may be unequal or equal.

[0108] In some embodiments, applying a first voltage to the word line coupled to the target memory cell in the precharge phase of the first programming loop, and applying a second voltage to the word line coupled to the target memory cell in the precharge phase of the second programming loop, include: applying the corresponding first voltage to the word line coupled to the target memory cell in each first pulse phase; applying the corresponding second voltage to the word line coupled to the target memory cell in each second pulse phase; wherein, in the first programming loop, the first voltage applied in the first pulse phase arranged in sequence is less than or equal to the first voltage applied in the first pulse phase arranged in sequence; in the second programming loop, the second voltage applied in the first pulse phase arranged in sequence is less than or equal to the second voltage applied in the second pulse phase arranged in sequence.

[0109] In some embodiments, the memory array further includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group includes at least one first word line and at least one second word line, the first word line is close to the word line coupled to the target memory cell, and the second word line is away from the word line coupled to the target memory cell; the operating method further includes: in the pre-charge stage of the first programming loop, applying a third voltage to the first word line; the third voltage is less than or equal to the first voltage; and / or, in the pre-charge stage of the second programming loop, applying a fourth voltage to the first word line; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

[0110] like Figure 12As shown, the word line (Sel WLn) coupled to the target memory cell is located between the ACS and the first word line group (WLn-1 to WLn-xm), the first word line group includes at least one first word line (WLn-1 to WLn-x) and at least one second word line (WLn-x-1 to WLn-xm), in the pre-charge phase of the first programming loop, a third voltage (Vpre2) is applied to WLn-1 to WLn-x; Vpre2 is less than or equal to Vpre1; and / or, in the pre-charge phase of the second programming loop, a fourth voltage (Vpre2+a1) is applied to WLn-1 to WLn-x; and / or, in the pre-charge phase of the third programming loop, a voltage Vpre2+p1+a2 is applied to WLn-1 to WLn-x.

[0111] It is understood that in the disclosed embodiments, applying voltage to WLn-1 to WLn-x during the pre-charge phase can reduce the potential difference between WLn and WLn-1, thereby reducing HCI interference during the pre-charge phase. Furthermore, in the disclosed embodiments, while the voltage applied to WLn increases with programming cycles, the voltage applied to WLn-1 to WLn-x also increases with programming cycles, thereby further reducing the potential difference between WLn and WLn-1, thereby further reducing HCI interference during the pre-charge phase.

[0112] In some embodiments, the operating method further includes: applying a fifth voltage to the second word line during the precharge phase of the first programming loop; the fifth voltage is less than the third voltage; and / or, applying a sixth voltage to the second word line during the precharge phase of the second programming loop; the sixth voltage is less than the fourth voltage, and the sixth voltage is greater than the fifth voltage.

[0113] like Figure 12 As shown, in the pre-charge stage of the first programming loop, the fifth voltage (Vpre3) is applied to the second word line (WLn-x-1~WLn-xm); and / or, in the pre-charge stage of the second programming loop, the sixth voltage (Vpre3+z1) is applied to WLn-x-1~WLn-xm; and / or, in the pre-charge stage of the third programming loop, Vpre3+z1+z2 is applied to WLn-x-1~WLn-xm.

[0114] It can be understood that in the embodiments of the present disclosure, applying a voltage to WLn-x-1 to WLn-xm during the pre-charge phase can reduce the potential difference between WLn-1 to WLn-x and WLn-x-1 to WLn-xm, thereby reducing HCI interference during the pre-charge phase. Furthermore, in the embodiments of the present disclosure, based on the fact that the voltage applied to WLn-1 to WLn-x increases with programming cycles, the voltage applied to WLn-x-1 to WLn-xm also increases with programming cycles, thereby further reducing the potential difference between WLn-1 to WLn-x and WLn-x-1 to WLn-xm, thereby further reducing HCI interference during the pre-charge phase.

[0115] In some specific examples, such as Figure 12 As shown, the ground voltage Vss may be applied to WLn+1 to WLn+y in the precharge phase of the first programming loop, the precharge phase of the second programming loop, and the precharge phase of the third programming loop.

[0116] In some embodiments, the memory array further includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; the operating method further includes: in the pre-charge stage of the first programming loop, applying a seventh voltage to the third word line; in the pre-charge stage of the second programming loop, applying an eighth voltage to the third word line; the seventh voltage is less than the eighth voltage.

[0117] like Figure 17 As shown, the second word line group (WLn+1~WLn+p) includes at least one third word line. In the pre-charge stage of the first programming loop, the seventh voltage (V1) is applied to the third word line; in the pre-charge stage of the second programming loop, the eighth voltage (V1+p1) is applied to the third word line; in the pre-charge stage of the third programming loop, V1+p1+p2 is applied to the third word line.

[0118] In some specific examples, the programming method includes one-step programming and multi-step programming. One-step programming refers to an ISPP programming operation, which includes multiple pulse stages, each pulse stage applying a corresponding programming voltage. Multi-step programming refers to multiple ISPP programming operations, each ISPP operation includes multiple pulse stages, and each pulse stage applies a corresponding programming voltage. Multi-step programming can specifically include a coarse programming operation and a fine programming operation. The coarse programming operation can form a coarse threshold voltage distribution. The fine programming operation can finely narrow the threshold voltage distribution formed by the coarse programming operation. The coarse programming operation can include multiple programming loops, each programming loop includes at least one pulse stage, each pulse stage includes a verification stage, a precharge stage, and a programming voltage application stage; the fine programming operation can also include multiple programming loops, each programming loop includes at least one pulse stage, each pulse stage includes a verification stage, a precharge stage, and a programming voltage application stage. The multi-step programming method can make the final threshold voltage distribution narrower and the interval between states wider, so that the performance of the memory device can be improved.

[0119] In the multi-step programming method of the embodiment of the present disclosure, the voltage applied to the third word line in different programming loops of each step of programming can be made different. For example, in coarse programming (or fine programming), the voltage applied to the third word line in the programming loop arranged in sequence is lower than the voltage applied to the third word line in the programming loop arranged in sequence, thereby reducing the potential difference between the word line coupled to the target memory cell and the corresponding channel potential under the third word line, thereby further reducing HCI, suppressing program interference, and improving the performance of the memory device.

[0120] In some embodiments, the memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; the operating method further includes: connecting the fourth word line to a ground voltage during a precharge phase of the first programming loop and a precharge phase of the second programming loop.

[0121] like Figure 17 As shown, the third word line group (WLn+p+1~WLn+y) includes at least one fourth word line, and the fourth word line is connected to the ground voltage (Vss) in the precharge stage of the first programming loop, the precharge stage of the second programming loop, and the precharge stage of the third programming loop.

[0122] In some embodiments, as Figure 12As shown, the operating method also includes: in the programming voltage application phase of the first programming loop, applying a first programming voltage (Vpgm1) to the word line coupled to the target memory cell; in the programming voltage application phase of the second programming loop, applying a second programming voltage (Vpgm2) to the word line coupled to the target memory cell; the second programming voltage is greater than the first programming voltage.

[0123] In some specific examples, such as Figure 12 As shown, the method further includes: in the programming voltage application phase of the third programming loop, applying a third programming voltage (Vpgm3) to the word line coupled to the target memory cell; the third programming voltage is greater than the second programming voltage.

[0124] In some embodiments, the conductive line includes a common source line, and the memory array further includes a bit line coupled to the other end of the memory cell string; the operating method further includes: in the precharge stage and the programming voltage application stage of the first programming loop, and in the precharge stage and the programming voltage application stage of the second programming loop, applying a programming inhibit voltage to the bit lines other than the bit lines coupled to the target memory cell.

[0125] In some specific examples, such as Figure 12 As shown, the method further includes: applying corresponding voltages to the bottom select gate (BSG) in the precharge phase of the first programming loop, in the precharge phase of the second programming loop, and in the precharge phase of the third programming loop.

[0126] In the above embodiment, the programming sequence is reverse programming, precharging is performed through the common source line ACS, and the conductive line is ACS. Figure 18 , the programming sequence is forward programming, precharging is performed through BL, and the conductive line is BL as an example for further explanation.

[0127] like Figure 18 As shown, the conductive line is the bit line BL, a first pre-charge voltage Vbl is applied to BL in the pre-charge stage of the first programming loop, a second pre-charge voltage Vbl+x1 is applied to BL in the pre-charge stage of the second programming loop, and a third pre-charge voltage Vbl+x1+x2 is applied to BL in the pre-charge stage of the third programming loop, and Vbl<Vbl+x1<Vbl+x1+x2.

[0128] In some specific examples, such as Figure 18 As shown, the method further includes: applying corresponding voltages to the top select gate (TSG) in the precharge phase of the first programming loop, in the precharge phase of the second programming loop, and in the precharge phase of the third programming loop.

[0129] In some embodiments, as Figure 18 As shown, the method further includes: applying corresponding programming inhibit voltages to the bit lines in the programming voltage application phase of the first programming loop, the programming voltage application phase of the second programming loop, and the programming voltage application phase of the third programming loop.

[0130] Figure 18 Other voltage application conditions are similar to Figure 12 The application of medium voltage is similar and will not be described here.

[0131] Based on a concept similar to the operating method of the above-mentioned memory device, the present disclosure provides a memory device, including: a memory array and a peripheral circuit coupled to the memory array; the memory array includes a plurality of memory cell strings and a conductive line coupled to one end of the memory cell string; the peripheral circuit is configured to: apply a first precharge voltage to the conductive line in the precharge stage of a first programming loop; apply a second precharge voltage to the conductive line in the precharge stage of a second programming loop after the first programming loop; wherein the second precharge voltage is greater than the first precharge voltage.

[0132] In some embodiments, the peripheral circuit is further configured to: apply a third precharge voltage to the conductive line during a precharge phase of a third programming loop after the second programming loop; the third precharge voltage is greater than the second precharge voltage.

[0133] In some embodiments, the first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

[0134] In some embodiments, the peripheral circuit is further configured to: apply a first voltage to the word line coupled to the target memory cell during the precharge phase of the first programming loop; apply a second voltage to the word line coupled to the target memory cell during the precharge phase of the second programming loop; and the second voltage is greater than the first voltage.

[0135] In some embodiments, the memory array also includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group includes at least one first word line and at least one second word line, the first word line is close to the word line coupled to the target memory cell, and the second word line is away from the word line coupled to the target memory cell; the peripheral circuit is also configured to: apply a third voltage to the first word line in the precharge stage of the first programming loop; the third voltage is less than or equal to the first voltage; and / or, apply a fourth voltage to the first word line in the precharge stage of the second programming loop; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

[0136] In some embodiments, the peripheral circuit is further configured to: apply a fifth voltage to the second word line in the precharge phase of the first programming loop; the fifth voltage is less than the third voltage; and / or, apply a sixth voltage to the second word line in the precharge phase of the second programming loop; the sixth voltage is less than the fourth voltage, and the sixth voltage is greater than the fifth voltage.

[0137] In some embodiments, the first programming loop includes at least one first pulse stage, and the second programming loop includes at least one second pulse stage; the peripheral circuit is specifically configured to: apply the corresponding first pre-charge voltage to the conductive line in each first pulse stage; apply the corresponding second pre-charge voltage to the conductive line in each second pulse stage; wherein, in the first programming loop, the first pre-charge voltage applied in the first pulse stage arranged in sequence is less than or equal to the first pre-charge voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second pre-charge voltage applied in the second pulse stage arranged in sequence is less than or equal to the second pre-charge voltage applied in the second pulse stage arranged in sequence.

[0138] In some embodiments, the corresponding multiple first pre-charge voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second pre-charge voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0139] In some embodiments, the peripheral circuit is specifically configured to: apply the corresponding first voltage to the word line coupled to the target memory cell in each first pulse stage; apply the corresponding second voltage to the word line coupled to the target memory cell in each second pulse stage; wherein, in the first programming loop, the first voltage applied in the first pulse stage arranged in sequence is less than or equal to the first voltage applied in the first pulse stage arranged in sequence; in the second programming loop, the second voltage applied in the second pulse stage arranged in sequence is less than or equal to the second voltage applied in the second pulse stage arranged in sequence.

[0140] In some embodiments, the corresponding multiple first voltages applied in the multiple first pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend; and / or, the corresponding multiple second voltages applied in the multiple second pulse stages arranged in sequence show a step-by-step increasing trend or a linear increasing trend.

[0141] In some embodiments, the conductive line includes a bit line or a common source line.

[0142] In some embodiments, the memory array further includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; the peripheral circuit is further configured to: apply a seventh voltage to the third word line in the precharge stage of the first programming loop; apply an eighth voltage to the third word line in the precharge stage of the second programming loop; the seventh voltage is less than the eighth voltage.

[0143] In some embodiments, the memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; the peripheral circuit is further configured to: connect the fourth word line to the ground voltage during the precharge phase of the first programming loop and the precharge phase of the second programming loop.

[0144] In some embodiments, the peripheral circuit is further configured to: apply a first programming voltage to the word line coupled to the target memory cell during the programming voltage application phase of the first programming loop; apply a second programming voltage to the word line coupled to the target memory cell during the programming voltage application phase of the second programming loop; and the second programming voltage is greater than the first programming voltage.

[0145] In some embodiments, the conductive line includes a common source line, and the memory array further includes a bit line coupled to the other end of the memory cell string; the peripheral circuit is further configured to: apply a programming inhibit voltage to the bit lines other than the bit lines coupled to the target memory cell during the precharge phase and the programming voltage application phase of the first programming cycle, and the precharge phase and the programming voltage application phase of the second programming cycle.

[0146] Based on a concept similar to the operating method of the above-mentioned memory device, the present disclosure also provides a memory system, including a memory controller and a memory device as described in any of the above-mentioned embodiments; the memory controller is coupled to the memory device and is configured to control the memory device.

[0147] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. The computer-readable storage medium stores the computer program, and when the computer program is executed, the operating method described in any of the above embodiments can be implemented.

[0148] Here, to implement all or part of the processes in the operating methods of the above embodiments, the processes may be completed by hardware related to computer program instructions. The computer program may be stored in a computer-readable storage medium. The execution of the computer program may include the processes of the operating methods in any of the above embodiments. The computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive, etc. The computer-readable storage medium may also include a combination of multiple storage media.

[0149] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0150] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0151] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory device, characterized in that: include: a memory array and a peripheral circuit coupled to the memory array; The memory array includes a plurality of memory cell strings and a conductive line coupled to one end of the memory cell strings; The peripheral circuit is configured as follows: In a precharge phase of a first programming loop, applying a first precharge voltage to the conductive line; applying a second precharge voltage to the conductive line during a precharge phase of a second programming cycle following the first programming cycle; The second pre-charge voltage is greater than the first pre-charge voltage.

2. The memory device according to claim 1, wherein The peripheral circuit is further configured to: In a precharge phase of a third programming loop following the second programming loop, a third precharge voltage is applied to the conductive line; the third precharge voltage is greater than the second precharge voltage.

3. The memory device according to claim 2, wherein: The first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

4. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: In a precharge phase of the first programming loop, applying a first voltage to a word line coupled to the target memory cell; During the precharge phase of the second programming loop, a second voltage is applied to the word line coupled to the target memory cell; the second voltage is greater than the first voltage.

5. The memory device according to claim 4, wherein: The memory array further includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group includes at least one first word line and at least one second word line, the first word line is close to the word line coupled to the target memory cell, and the second word line is far from the word line coupled to the target memory cell; the peripheral circuit is further configured to: During a precharge phase of the first programming loop, a third voltage is applied to the first word line; the third voltage is less than or equal to the first voltage; and / or, During the precharge phase of the second programming loop, a fourth voltage is applied to the first word line; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

6. The memory device according to claim 5, wherein: The peripheral circuit is further configured to: In a precharge phase of the first programming loop, a fifth voltage is applied to the second word line; the fifth voltage is lower than the third voltage; and / or, During the precharge phase of the second programming loop, a sixth voltage is applied to the second word line; the sixth voltage is lower than the fourth voltage and higher than the fifth voltage.

7. The memory device according to claim 4, wherein: The first programming loop includes at least one first pulse phase, and the second programming loop includes at least one second pulse phase; the peripheral circuit is specifically configured to: apply the corresponding first pre-charge voltage to the conductive line in each first pulse phase; apply the corresponding second pre-charge voltage to the conductive line in each second pulse phase; wherein, In the first programming loop, the first precharge voltage applied in the first pulse phase arranged in sequence is less than or equal to the first precharge voltage applied in the first pulse phase arranged in sequence; In the second programming loop, the second precharge voltage applied in a second pulse phase sequentially arranged earlier is less than or equal to the second precharge voltage applied in a second pulse phase sequentially arranged later.

8. The memory device according to claim 7, wherein: The first pre-charge voltages applied corresponding to the plurality of first pulse stages arranged sequentially are in a step-wise increasing trend or a linear increasing trend; and / or, The second pre-charge voltages correspondingly applied in the plurality of second pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend.

9. The memory device according to claim 7, wherein: The peripheral circuit is specifically configured to: apply the corresponding first voltage to the word line coupled to the target memory cell in each first pulse phase; apply the corresponding second voltage to the word line coupled to the target memory cell in each second pulse phase; wherein, In the first programming loop, the first voltage applied in the first pulse phase arranged in sequence is less than or equal to the first voltage applied in the first pulse phase arranged in sequence; In the second programming loop, the second voltage applied in the first second pulse phase is less than or equal to the second voltage applied in the second pulse phase.

10. The memory device according to claim 9, wherein: The first voltages applied corresponding to the first pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend; and / or, The second voltages correspondingly applied in the second pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend.

11. The memory device according to claim 1, wherein The conductive line includes a bit line or a common source line.

12. The memory device according to claim 1, wherein The memory array further includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; the peripheral circuit is further configured to: During a precharge phase of the first programming loop, applying a seventh voltage to the third word line; During the precharge phase of the second programming loop, an eighth voltage is applied to the third word line; and the seventh voltage is lower than the eighth voltage.

13. The memory device according to claim 12, wherein: The memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; the peripheral circuit is further configured to: During the precharge phase of the first programming loop and the precharge phase of the second programming loop, the fourth word line is connected to a ground voltage.

14. The memory device according to claim 1, wherein The peripheral circuit is further configured to: In a program voltage application phase of the first program loop, applying a first program voltage to a word line coupled to a target memory cell; In a program voltage application phase of the second program loop, applying a second program voltage to a word line coupled to the target memory cell; The second programming voltage is greater than the first programming voltage.

15. The memory device according to claim 1, wherein The conductive line includes a common source line, and the memory array further includes a bit line coupled to the other end of the memory cell string; The peripheral circuit is further configured to: In the precharge phase and the program voltage application phase of the first program loop and the precharge phase and the program voltage application phase of the second program loop, a program inhibit voltage is applied to bit lines other than the bit line coupled to the target memory cell.

16. A memory system, characterized in that: The invention comprises a memory controller and the memory device according to any one of claims 1 to 15; the memory controller is coupled to the memory device and is configured to control the memory device.

17. A method for operating a memory device, characterized in that: The memory device includes a plurality of memory cell strings and a conductive line coupled to one end of the memory cell strings; the operating method includes: In a precharge phase of a first programming loop, applying a first precharge voltage to the conductive line; In a precharge phase of a second programming loop following the first programming loop, a second precharge voltage is applied to the conductive line; the second precharge voltage is greater than the first precharge voltage.

18. The operating method according to claim 17, characterized in that: The operation method further includes: In a precharge phase of a third programming loop following the second programming loop, a third precharge voltage is applied to the conductive line.

19. The operating method according to claim 18, characterized in that: The third pre-charge voltage is greater than the second pre-charge voltage; the first pre-charge voltage, the second pre-charge voltage, and the third pre-charge voltage increase in a step-by-step manner or in a linear manner.

20. The operating method according to claim 17, characterized in that: The operation method further includes: In a precharge phase of the first programming loop, applying a first voltage to a word line coupled to the target memory cell; During the precharge phase of the second programming loop, a second voltage is applied to the word line coupled to the target memory cell; the second voltage is greater than the first voltage.

21. The operating method according to claim 20, characterized in that: The memory array further includes a first word line group adjacent to the word line coupled to the target memory cell; the word line coupled to the target memory cell is located between the conductive line and the first word line group, the first word line group including at least one first word line and at least one second word line, the first word line being close to the word line coupled to the target memory cell, and the second word line being far from the word line coupled to the target memory cell; The operation method further includes: During a precharge phase of the first programming loop, a third voltage is applied to the first word line; the third voltage is less than or equal to the first voltage; and / or, During the precharge phase of the second programming loop, a fourth voltage is applied to the first word line; the fourth voltage is less than or equal to the second voltage, and the fourth voltage is greater than the third voltage.

22. The operating method according to claim 21, characterized in that: The operation method further includes: In a precharge phase of the first programming loop, a fifth voltage is applied to the second word line; the fifth voltage is lower than the third voltage; and / or, During the precharge phase of the second programming loop, a sixth voltage is applied to the second word line; the sixth voltage is lower than the fourth voltage and higher than the fifth voltage.

23. The operating method according to claim 20, characterized in that: The first programming loop includes at least one first pulse phase arranged in sequence, and the second programming loop includes at least one second pulse phase arranged in sequence; The step of applying a first precharge voltage to the conductive line in a precharge phase of a first programming loop, and applying a second precharge voltage to the conductive line in a precharge phase of a second programming loop after the first programming loop, comprises: The first pre-charge voltage is applied to the conductive line in each of the first pulse stages, and the second pre-charge voltage is applied to the conductive line in each of the second pulse stages; wherein, In the first programming loop, the first precharge voltage applied in the first pulse phase arranged in sequence is less than or equal to the first precharge voltage applied in the first pulse phase arranged in sequence; In the second programming loop, the second precharge voltage applied in a second pulse phase sequentially arranged earlier is less than or equal to the second precharge voltage applied in a second pulse phase sequentially arranged later.

24. The operating method according to claim 23, characterized in that: The first pre-charge voltages applied corresponding to the plurality of first pulse stages arranged sequentially are in a step-wise increasing trend or a linear increasing trend; and / or, The second pre-charge voltages correspondingly applied in the plurality of second pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend.

25. The operating method according to claim 23, characterized in that: The step of applying a first voltage to a word line coupled to a target memory cell during a precharge phase of the first programming loop, and applying a second voltage to a word line coupled to the target memory cell during a precharge phase of the second programming loop, comprises: In each of the first pulse phases, the corresponding first voltage is applied to the word line coupled to the target memory cell; in each of the second pulse phases, the corresponding second voltage is applied to the word line coupled to the target memory cell; wherein, In the first programming loop, the first voltage applied in the first pulse phase arranged in sequence is less than or equal to the first voltage applied in the first pulse phase arranged in sequence; In the second programming loop, the second voltage applied in the first pulse phase arranged in sequence is less than or equal to the second voltage applied in the second pulse phase arranged in sequence.

26. The operating method according to claim 25, characterized in that: The first voltages applied corresponding to the first pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend; and / or, The second voltages correspondingly applied in the second pulse stages arranged sequentially present a step-wise increasing trend or a linear increasing trend.

27. The operating method according to claim 17, characterized in that: The memory array further includes a second word line group; the second word line group includes at least one third word line, the second word line group is adjacent to the word line coupled to the target memory cell and is located between the word line coupled to the target memory cell and the conductive line; The operation method further includes: During a precharge phase of the first programming loop, applying a seventh voltage to the third word line; During the precharge phase of the second programming loop, an eighth voltage is applied to the third word line; and the seventh voltage is lower than the eighth voltage.

28. The operating method according to claim 27, characterized in that: The memory array further includes a third word line group; the third word line group includes at least one fourth word line, and the third word line group is located between the second word line group and the conductive line; The operation method further includes: During the precharge phase of the first programming loop and the precharge phase of the second programming loop, the fourth word line is connected to a ground voltage.

29. The operating method according to claim 17, characterized in that: The operation method further includes: In a program voltage application phase of the first program loop, applying a first program voltage to a word line coupled to a target memory cell; During the program voltage application phase of the second program loop, a second program voltage is applied to the word line coupled to the target memory cell; the second program voltage is greater than the first program voltage.

30. The operating method according to claim 17, characterized in that: The conductive line includes a common source line, and the memory array further includes a bit line coupled to the other end of the memory cell string; the operating method further includes: In the precharge phase and the program voltage application phase of the first program loop and the precharge phase and the program voltage application phase of the second program loop, a program inhibit voltage is applied to bit lines other than the bit line coupled to the target memory cell.

31. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 17 to 30 can be implemented.

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