Semiconductor structure
By embedding integrated passive components into the substrate and redistribution layer in the semiconductor structure, the problem of integrated passive components occupying the interposer area is solved, and the freedom and flexibility of package design are improved while reducing costs.
Patent Information
- Application Number
- CN202410341900.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-06
- Filing Date
- 2024-03-25
- Publication Date
- 2025-09-09
AI Technical Summary
Integrated passive components occupy the interposer area in the semiconductor structure, resulting in reduced package design freedom and flexibility.
The first integrated passive component is embedded in the substrate, and the second integrated passive component is embedded in the redistribution layer. Electrical connection or insulation is achieved through the interconnection structure to avoid occupying the area of the intermediate layer.
It improves the freedom and flexibility of package design and reduces the difficulty and cost of the back-end package manufacturing process.
Smart Images
Figure CN120613338A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including an integrated passive device (IPD). Background Art
[0002] Currently, integrated passive components are widely used in semiconductor structures and are mounted on an interposer next to the main die. Since the integrated passive components occupy the area on the interposer used to mount the die, this reduces the freedom and flexibility of the package design. Summary of the Invention
[0003] The present invention provides a semiconductor structure, which can improve the freedom and flexibility of packaging design.
[0004] The present invention provides a semiconductor structure comprising an interposer. The interposer includes a substrate, a redistribution layer (RDL), a first integrated passive component, and a second integrated passive component. The RDL is located on the substrate. The first integrated passive component is located in the substrate. The second integrated passive component is located in the RDL.
[0005] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device may be electrically connected to each other.
[0006] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device may be connected in series.
[0007] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device may be connected in parallel.
[0008] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device may be electrically insulated from each other.
[0009] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device can be separated from each other.
[0010] According to an embodiment of the present invention, in the semiconductor structure, the second integrated passive device may overlap the first integrated passive device.
[0011] According to an embodiment of the present invention, in the semiconductor structure, the second integrated passive device does not overlap with the first integrated passive device.
[0012] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive component may be a capacitor.
[0013] According to an embodiment of the present invention, in the semiconductor structure, the second integrated passive component may be a capacitor.
[0014] According to one embodiment of the present invention, in the semiconductor structure described above, the redistribution layer may include a dielectric layer, an interconnect structure, and a pad. The dielectric layer is located on the substrate. The interconnect structure is located in the dielectric layer. The pad is located above the interconnect structure and in the dielectric layer.
[0015] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device may be electrically connected to the interconnect structure.
[0016] According to an embodiment of the present invention, in the semiconductor structure, the second integrated passive device may be electrically connected to the interconnect structure.
[0017] According to an embodiment of the present invention, in the semiconductor structure, the second integrated passive component may be located in the dielectric layer.
[0018] According to an embodiment of the present invention, in the semiconductor structure, the dielectric layer may include a first surface and a second surface opposite to each other. The first surface may be adjacent to the substrate.
[0019] According to an embodiment of the present invention, in the semiconductor structure, the first integrated passive device and the second integrated passive device may be adjacent to the first surface, and the pad may be adjacent to the second surface.
[0020] According to an embodiment of the present invention, the semiconductor structure may further include a die. The die is located on the second surface and may be electrically connected to the pad.
[0021] According to an embodiment of the present invention, the semiconductor structure may further include a connection terminal located between the die and the pad.
[0022] According to an embodiment of the present invention, in the semiconductor structure, the interposer may further include a through-substrate via (TSV), which penetrates the substrate.
[0023] According to an embodiment of the present invention, in the semiconductor structure, the through substrate via may extend into the dielectric layer.
[0024] Based on the above, in the semiconductor structure proposed by the present invention, the first integrated passive component is located in the substrate, and the second integrated passive component is located in the redistribution layer. Therefore, the first and second integrated passive components do not occupy the area on the interposer used for mounting the die. This increases the freedom and flexibility of package design and reduces the difficulty and cost of back-end package manufacturing processes.
[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 are cross-sectional views of semiconductor structures according to some embodiments of the present invention;
[0027] Figure 2 are cross-sectional views of semiconductor structures according to other embodiments of the present invention;
[0028] Figure 3 are cross-sectional views of semiconductor structures according to other embodiments of the present invention.
[0029] Explanation of symbols
[0030] 100:Semiconductor structure
[0031] 102: Intermediary layer
[0032] 104: Base
[0033] 106: Rewiring layer
[0034] 108, 108A, 108B, 110, 110A, 110B: Integrated passive components
[0035] 112: dielectric layer
[0036] 114:Internal connection structure
[0037] 114a: Wire
[0038] 114b: Plug
[0039] 116: pad
[0040] 118: Base perforation
[0041] 120: Grain
[0042] 122: Connecting terminal
[0043] S1: Side 1
[0044] S2: Side 2 DETAILED DESCRIPTION
[0045] The following examples are illustrated in detail with accompanying figures. However, these examples are not intended to limit the scope of the present invention. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description. Furthermore, the figures are for illustrative purposes only and are not drawn to scale. The dimensions of various features may be arbitrarily increased or decreased for clarity.
[0046] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 2 are cross-sectional views of semiconductor structures according to some other embodiments of the present invention. Figure 3 are cross-sectional views of semiconductor structures according to some other embodiments of the present invention.
[0047] Please refer to Figures 1 to 3 The semiconductor structure 100 includes an interposer 102. In some embodiments, the interposer 102 may be a silicon interposer. The interposer 102 includes a substrate 104, a redistribution layer 106, an integrated passive device 108, and an integrated passive device 110. In some embodiments, the substrate 104 may be a semiconductor substrate, such as a silicon substrate.
[0048] The redistribution layer 106 is located on the substrate 104. The redistribution layer 106 may include a dielectric layer 112, an interconnect structure 114, and a pad 116. The dielectric layer 112 is located on the substrate 104. The dielectric layer 112 may include a first surface S1 and a second surface S2 opposite to each other. The first surface S1 may be adjacent to the substrate 104. In some embodiments, the dielectric layer 112 may be a multilayer structure. In some embodiments, the material of the dielectric layer 112 is, for example, silicon oxide, silicon nitride, or a combination thereof. The interconnect structure 114 is located in the dielectric layer 112. The interconnect structure 114 may include a conductive line 114a, a plug 114b, or a combination thereof. In some embodiments, the plug 114b may be a contact plug or a via plug. In some embodiments, the material of the interconnect structure 114 is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. The pads 116 are located above the interconnect structures 114 and in the dielectric layer 112. The pads 116 may be adjacent to the second surface S2 and electrically connected to the corresponding interconnect structures 114. The pads 116 are made of a conductive material such as metal (eg, copper, aluminum, or tungsten).
[0049] The integrated passive component 108 is located in the substrate 104. That is, the integrated passive component 108 may be embedded in the substrate 104. The integrated passive component 108 may be adjacent to the first surface S1. The integrated passive component 108 may be electrically connected to the interconnect structure 114. In some embodiments, the integrated passive component 108 may be a capacitor. In some embodiments, the integrated passive component 108 may be, for example, a trench capacitor.
[0050] The integrated passive component 110 is located in the redistribution layer 106. That is, the integrated passive component 110 can be embedded in the redistribution layer 106. Because the integrated passive component 108 is located in the substrate 104 and the integrated passive component 110 is located in the redistribution layer 106, the integrated passive component 108 and the integrated passive component 110 do not occupy the area on the interposer 102 used for mounting the die. In some embodiments, the integrated passive component 110 can be located in the dielectric layer 112. The integrated passive component 110 can be adjacent to the first surface S1. The integrated passive component 110 can be electrically connected to the interconnect structure 114. The integrated passive component 108 and the integrated passive component 110 can be separated from each other. In some embodiments, the integrated passive component 108 and the integrated passive component 110 can be separated from each other by the dielectric layer 112. In some embodiments, the integrated passive component 110 can be a capacitor. In some embodiments, the integrated passive component 110 is, for example, a trench capacitor.
[0051] In some embodiments, as Figure 1 As shown, the integrated passive component 108A and the integrated passive component 110A may be electrically connected to each other, but the present invention is not limited thereto. In other embodiments, such as Figure 2 and Figure 3 As shown, the integrated passive component 108A and the integrated passive component 110A may be electrically insulated from each other. Figure 1 As shown, the integrated passive component 108A and the integrated passive component 110A can be electrically connected to each other via the interconnect structure 114. In some embodiments, the integrated passive component 108A and the integrated passive component 110A can be connected in series. In some embodiments, the integrated passive component 108A and the integrated passive component 110A can be connected in parallel. In some embodiments, as Figure 1 As shown, the integrated passive device 108A and the integrated passive device 110A may be connected in series or in parallel via the interconnect structure 114 .
[0052] In some embodiments, as Figures 1 to 3 As shown, the integrated passive component 108B and the integrated passive component 110B may be electrically insulated from each other, but the present invention is not limited thereto. In other embodiments, although not shown in the figures, the integrated passive component 108B and the integrated passive component 110B may be electrically connected to each other.
[0053] In some embodiments, as Figure 1 As shown, the integrated passive component 110A may overlap the integrated passive component 108A, and the integrated passive component 110B may overlap the integrated passive component 108B. In other embodiments, such as Figure 2As shown, the integrated passive component 110A does not overlap the integrated passive component 108A, and the integrated passive component 110B may overlap the integrated passive component 108B. In other embodiments, such as Figure 3 As shown, the integrated passive component 110A does not overlap the integrated passive component 108A, and the integrated passive component 110B does not overlap the integrated passive component 108B.
[0054] Interposer 102 may further include through-substrate vias 118. The through-substrate vias 118 extend through substrate 104 and into dielectric layer 112. The through-substrate vias 118 may be electrically connected to corresponding interconnect structures 114. In some embodiments, the material of the through-substrate vias 118 may be copper, tantalum, tantalum nitride, or a combination thereof.
[0055] The semiconductor structure 100 may further include a die 120. The die 120 is located on the second surface S2. The die 120 may be electrically connected to the pad 116. In some embodiments, the die 120 may be a high bandwidth memory (HBM) die or a system on chip (SOC) die. If there are multiple dies 120, the multiple dies 120 may include high bandwidth memory dies, SOC dies, or a combination thereof.
[0056] The semiconductor structure 100 may further include a connection terminal 122. The connection terminal 122 is located between the die 120 and the pad 116. The die 120 may be electrically connected to the pad 116 via the connection terminal 122. In some embodiments, the integrated passive component 108 may be electrically connected to the corresponding die 120 via the corresponding interconnect structure 114, the corresponding pad 116, and the corresponding connection terminal 122. In some embodiments, the integrated passive component 110 may be electrically connected to the corresponding die 120 via the corresponding interconnect structure 114, the corresponding pad 116, and the corresponding connection terminal 122. The connection terminal 122 may be a bump (e.g., a solder ball), but the present invention is not limited thereto.
[0057] Based on the above embodiment, it can be seen that in the semiconductor structure 100, the integrated passive component 108 is located in the substrate 104, and the integrated passive component 110 is located in the redistribution layer 106. Therefore, the integrated passive component does not occupy the area on the interposer 102 used to mount the die 120. This increases the freedom and flexibility of package design and reduces the difficulty and cost of back-end package manufacturing processes.
[0058] In summary, in the semiconductor structure of the above embodiment, since the integrated passive components do not occupy the area on the interposer for mounting the die, the freedom and flexibility of the package design can be improved, and the difficulty and cost of the back-end package manufacturing process can be reduced.
[0059] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the appended claims.
Claims
1. A semiconductor structure comprising: The intermediary layer includes: substrate; a redistribution layer located on the substrate; A first integrated passive component is located in the substrate; and The second integrated passive component is located in the redistribution layer. 2 . The semiconductor structure as claimed in claim 1 , wherein the first integrated passive device and the second integrated passive device are electrically connected to each other. 3 . The semiconductor structure as claimed in claim 2 , wherein the first integrated passive device and the second integrated passive device are connected in series. 4 . The semiconductor structure according to claim 2 , wherein the first integrated passive device and the second integrated passive device are connected in parallel. 5 . The semiconductor structure as claimed in claim 1 , wherein the first integrated passive device and the second integrated passive device are electrically insulated from each other. The semiconductor structure as claimed in claim 1 , wherein the first integrated passive device and the second integrated passive device are separated from each other. The semiconductor structure as claimed in claim 1 , wherein the second integrated passive device overlaps the first integrated passive device. 8 . The semiconductor structure of claim 1 , wherein the second integrated passive device does not overlap with the first integrated passive device.
9. The semiconductor structure of claim 1, wherein the first integrated passive device comprises a capacitor.
10. The semiconductor structure of claim 1, wherein the second integrated passive device comprises a capacitor.
11. The semiconductor structure of claim 1 , wherein the redistribution layer comprises: a dielectric layer located on the substrate; an interconnect structure located in the dielectric layer; as well as The pad is located above the interconnect structure and in the dielectric layer. 12 . The semiconductor structure of claim 11 , wherein the first integrated passive device is electrically connected to the interconnect structure. 13 . The semiconductor structure according to claim 11 , wherein the second integrated passive device is electrically connected to the interconnect structure. 14 . The semiconductor structure of claim 11 , wherein the second integrated passive device is located in the dielectric layer. 15 . The semiconductor structure of claim 11 , wherein the dielectric layer comprises a first surface and a second surface opposite to each other, and the first surface is adjacent to the substrate. 16 . The semiconductor structure of claim 15 , wherein the first integrated passive device and the second integrated passive device are adjacent to the first surface, and the pad is adjacent to the second surface.
17. The semiconductor structure of claim 15, further comprising: The die is located on the second surface and is electrically connected to the pad.
18. The semiconductor structure of claim 17, further comprising: The connecting terminal is located between the die and the pad.
19. The semiconductor structure of claim 11, wherein the interposer further comprises: The substrate is perforated, extending through the substrate.
20. The semiconductor structure of claim 19, wherein the through substrate via extends into the dielectric layer.