Power factor correction (PFC) circuit based on active current control mode and correction method

Abstract

The invention provides a power factor correction (PFC) circuit based on an active current control mode and a correction method, and belongs to the technical field of integrated circuits, the PFC circuit comprises a non-winding Boost PFC topological structure and a control chip; the winding-free Boost PFC topological structure comprises an input voltage source, an input filter capacitor, an inductor, a resistor, a switch, a diode and an output filter capacitor; the control chip comprises a zero current detection module circuit, a zero current detection delay and leading edge blanking circuit, a fast response error amplifier, a multi-stage protection integrated circuit and a demagnetization detection circuit. Dynamic and steady-state overvoltage protection dual mechanisms are realized based on output feedback voltage FB representing output voltage of a boost switching power supply circuit; the control chip provides an efficient and reliable solution for a high-power-density PD charger, and meanwhile, the circuit meets strict requirements of energy efficiency regulations such as IEC 61000-3-2 on harmonic suppression and electric energy quality, and has a wide application prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a power factor correction (PFC) circuit based on an active current control mode and a correction method. Background Art

[0002] Power supplies are core components in electronic devices, and their performance directly impacts system safety and reliability. Switching power supplies, with their high efficiency, low losses, and compact design, are widely used in computers, communications equipment, and household appliances. Due to the varying power requirements of various devices, conversion between AC / DC, DC / DC, and DC / AC becomes particularly important. Current power systems utilize a three-phase, four-wire system with a voltage level of 380 / 220V and a frequency of 50Hz, with AC / DC conversion playing a dominant role in switching power supplies.

[0003] Traditional AC / DC power supplies are typically connected to the grid through a rectifier. These rectifiers are typically diode-based, nonlinear circuits that introduce significant harmonics and reactive power into the grid. This not only reduces energy efficiency but can also cause equipment overheating, failures, and even shorten its lifespan. These power supplies generally have a low power factor (0.45–0.75), and the amplitudes of the third and fifth harmonics can approach or exceed the fundamental harmonic, making them a major source of harmonic pollution. To control the hazards of harmonics, international and domestic standards, such as IEC61000-3-2 and GB / T14549-93, have been introduced since the 1990s, imposing higher requirements on rectifiers.

[0004] There are two main approaches to addressing harmonics: passive filtering, which uses passive or active filters to bypass harmonics; and active filtering, which involves designing high-performance rectifiers with sinusoidal input current, low harmonics, and a high power factor. This is known as power factor correction (PFC). With advances in power supply and semiconductor technology, integrated PFC control chips have rapidly developed and become a popular high-tech product.

[0005] Traditional PFC controllers rely on a sensing coil for zero-current detection, which increases circuit complexity and cost. Furthermore, existing solutions lack dynamic overvoltage protection and feedback failure handling, potentially leading to uncontrolled output voltage or component damage.

[0006] There are two control methods for the critical conduction mode of APFC based on the Boost structure. One is the control method with a multiplier, which is achieved by sampling the input voltage. Figure 1 A topological diagram of a typical Boost switching power supply using a multiplier structure and a circuit schematic diagram of a control chip are shown, wherein part of the circuit schematic diagram of the control chip is shown in the dotted box.

[0007] This method controls the peak inductor current by sampling the rectified input voltage and multiplying it with the error amplifier output signal. Because the error amplifier output remains essentially constant when the load remains unchanged, the inductor current follows the input voltage. However, when the load changes, fluctuations in the output voltage cause changes in the error amplifier output, which in turn adjusts the multiplier output, achieving dynamic current regulation to meet energy requirements under varying loads.

[0008] The other is a control method without a multiplier, which does not sample the input voltage. Figure 2 A typical topology diagram of a boost switching power supply without a multiplier structure and a schematic diagram of the control chip are shown, with the portion of the control chip schematic shown within the dashed box. This method eliminates the need for input voltage sampling and a multiplier, resulting in a simpler structure. Current regulation is achieved by comparing the error amplifier output with a sawtooth waveform with a fixed slope. When the sawtooth voltage reaches a set threshold, the control circuit turns off the power switch, thus achieving current regulation. Because the on-time is fixed, the inductor current can still vary with the input voltage, thus achieving power factor correction.

[0009] The control scheme with multiplier has a complex structure, many components, and the linearity design of the analog multiplier is difficult; while the scheme without multiplier has a simple circuit, is easy to implement, and has higher practicality. Summary of the Invention

[0010] The purpose of the present invention is to provide a power factor correction (PFC) circuit based on active current control mode, which significantly improves system reliability and efficiency by integrating demagnetization detection, primary current detection, dynamic protection mechanism and optimized control logic.

[0011] The purpose of the present invention is achieved through the following technical solutions:

[0012] A power factor correction (PFC) circuit based on an active current control mode, characterized by comprising: a winding-free Boost type PFC topology structure and a control chip;

[0013] The winding-less Boost PFC topology includes an input voltage source, an input filter capacitor, an inductor, a resistor, a switch, a diode, and an output filter capacitor;

[0014] The control chip includes a zero current detection module circuit, a zero current detection delay and leading edge blanking circuit, a fast response error amplifier, a multi-stage protection integrated circuit, and a demagnetization detection circuit.

[0015] Furthermore, the winding-less Boost PFC topology structure includes an AC power input terminal, which is connected to a DC bus via a bridge rectifier diode array;

[0016] The DC bus positive electrode is connected in parallel with a filter capacitor C1;

[0017] The positive electrode of the DC bus is connected to the positive electrode of the inductor L1;

[0018] The cathode of the inductor L1 is connected to the drain of the power tube Q1 and the anode of the diode D1 respectively;

[0019] The negative pole of the DC bus is connected to the first section of the current detection resistor Rsense, the resistor R CS The first end of

[0020] The resistor R CS The second end of is grounded;

[0021] The second section of the current detection resistor Rsense is connected to the CS / ZCD pin of the control chip;

[0022] The gate of the power tube Q1 is connected to the GATE pin of the invented control chip;

[0023] The source of the power tube Q1 is grounded;

[0024] The inductor L1, power tube Q1, current detection resistor R CS Constitute a BOOST type circuit charging loop;

[0025] The cathode of the diode D1 is connected to the first end of the resistor R1, the anode of the output filter capacitor C2, and the anode of the output voltage respectively;

[0026] The second end of the resistor R1 is connected to the first end of the resistor R2, the positive electrode of the capacitor C3, and the FB pin of the invented control chip respectively;

[0027] The second end of the resistor R2 is grounded;

[0028] The negative electrode of the capacitor C3 is grounded;

[0029] The negative end of the output filter capacitor C2 is grounded;

[0030] The VCC pin of the control chip is connected to an external power supply;

[0031] The GND pin of the control chip is grounded;

[0032] The COMP pin of the control chip is respectively connected to the first end of the resistor R3 and the positive electrode of the capacitor C4 in the compensation network;

[0033] The second section of the resistor R3 is connected to the positive electrode of the capacitor C5;

[0034] The negative electrode of the capacitor C4 is grounded;

[0035] The negative electrode of the capacitor C5 is grounded.

[0036] Furthermore, the multi-stage protection integrated circuit includes a cycle-by-cycle current limiting module, an inductor short-circuit protection module, a feedback loop open-loop protection module, an over-temperature protection module, a system overvoltage protection module, and an under-voltage lockout module. The multi-stage protection integrated circuit has a multi-stage protection mechanism, including under-voltage lockout, multi-stage cycle-by-cycle current limiting protection, dual-mechanism dynamic / static overvoltage protection, inductor short-circuit protection, feedback loop fault handling, and over-temperature protection.

[0037] Furthermore, the zero current detection module circuit includes a PMOS tube, and the source of the PMOS tube M2 is connected to a reference current of 10uA;

[0038] The gate of the PMOS tube M2 is connected to the node ZCD_ENB;

[0039] The drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4 and the input end of the inverter respectively;

[0040] The output end of the inverter is connected to the node ZCD_PRI;

[0041] The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M5 and the output end of the operational amplifier AMP respectively;

[0042] The source of the NMOS transistor M4 is connected to the collector of the NPN transistor Q1;

[0043] The base of the NPN transistor Q1 is connected to the base of the NPN transistor Q2, the drain of the NMOS transistor M8, the drain of the PMOS transistor M2, and a reference current of 4uA respectively;

[0044] The emitter of the NPN transistor Q1 is connected to the first end of the first resistor R0;

[0045] The second end of the first resistor R0 is connected to the CS / ZCD pin of the control chip;

[0046] The CS / ZCD pin of the control chip is connected to the first section of the current detection resistor Rsense;

[0047] The second section of the current detection resistor Rsense is connected to the first end of the resistor RCS;

[0048] The second end of the resistor RCS is grounded;

[0049] The drain of the NMOS tube M5 is connected to a reference current of 10uA and the gate of the NMOS tube M3 respectively;

[0050] The source of the NMOS transistor M5 is connected to the collector of the NPN transistor Q2;

[0051] The emitter of Q2 is connected to the first end of the second resistor R1 and the source of the NMOS transistor M7 respectively;

[0052] The second end of the second resistor R1 is connected to the GND pin of the control chip;

[0053] The GND pin of the control chip is grounded;

[0054] The gate and drain of the NMOS tube M6 are connected together, and are connected to a 2uA reference current and the gate of M7;

[0055] The source of M6 is connected to the drain of M7;

[0056] The gate of M8 is connected to the node ZCD_ENB;

[0057] The source of M8 is grounded;

[0058] The gate of M1 is connected to the node ZCD_ENB;

[0059] The source of M1 is connected to the power supply VDD.

[0060] Furthermore, the zero current detection delay and leading edge blanking circuit includes two input terminals of a NAND gate A1, and the two input terminals of the NAND gate A1 are connected to nodes ZCD_EN and ZCD_PRI respectively;

[0061] The output end of the NAND gate A1 is connected to the input end of the inverter A2;

[0062] The output end of the inverter A2 is connected to the input end of the inverter A3 and the input end 1 of the NAND gate A4 respectively;

[0063] The output end of the inverter A3 is connected to the gate of the PMOS tube M1;

[0064] The source of the PMOS tube M1 is connected to the reference current of IREF1;

[0065] The gate of the PMOS transistor M1 is connected to the source of the NMOS transistor M2, the positive electrode of the capacitor C1, the drain of the NMOS transistor M3, and the positive terminal of the comparator CMP respectively;

[0066] The positive terminal of the operational amplifier AMP is connected to a reference voltage of 2V;

[0067] The negative terminal and the output terminal of the operational amplifier AMP are connected together and connected to the drain of M2;

[0068] The gate of M2 is connected to the node MOS_ON;

[0069] The negative electrode of the capacitor C1 is grounded;

[0070] The gate of the NMOS transistor M3 is connected to the node VDD_ON;

[0071] The source of the NMOS tube M3 is grounded;

[0072] The reference current IREF2 is connected to the FB pin of the control chip and the first end of the resistor R1;

[0073] The FB pin of the control chip is connected to the positive electrode of the capacitor C2;

[0074] The negative electrode of the capacitor C2 is grounded;

[0075] The second end of the resistor R1 is connected to the positive electrode of the capacitor C3 and the negative end of CMP respectively;

[0076] The negative electrode of the capacitor C3 is grounded;

[0077] The negative terminal of the operational amplifier AMP is connected to the input terminal 2 of the NAND gate A4;

[0078] The output end of the NAND gate A4 is connected to the gate of the PMOS transistor M4 and the gate of the NMOS transistor M5 respectively;

[0079] The source of the PMOS tube M4 is connected to the reference current IREF3;

[0080] The drain of the PMOS tube M4 is connected to the drain of M5, the gate of the NMOS tube M6, and the input end of the inverter A5 respectively;

[0081] The source and drain of the NMOS tube M5 are grounded;

[0082] The output end of the inverter A5 is connected to the input end of the inverter A6;

[0083] The output end of the inverter A6 is connected to the node ZCD.

[0084] Furthermore, the fast response error amplifier adopts a multi-vector error amplifier to avoid the influence of sudden load changes on the stability of the system output voltage.

[0085] Furthermore, the fast response error amplifier includes the positive terminal of the comparator CMP1, and the FB pin of the control chip is respectively connected to the positive terminal of the comparator CMP1, the negative terminal of the error amplifier EA, and the positive terminal of the comparator CMP2;

[0086] The negative terminal of the comparator CMP1 is connected to a reference voltage of 2.35V;

[0087] The negative terminal of the comparator CMP2 is connected to a reference voltage of 2.60V;

[0088] The positive terminal of the error amplifier EA is connected to a reference voltage of 2.50V;

[0089] The output end of the comparator CMP1 is connected to the starting end of the reference current I1;

[0090] The output end of the error amplifier EA is connected to the COMP pin of the control chip;

[0091] The output end of the CMP2 is connected to the starting end of the reference current I2;

[0092] The output end of the error amplifier EA is connected to the control chip COMP pin which is respectively connected to the reference current I1, the reference current I2, the first end of the resistor R1, and the positive electrode of the capacitor C2;

[0093] The second end of the resistor R1 is connected to the positive electrode of the capacitor C1;

[0094] The negative electrode of the capacitor C1 is grounded;

[0095] The negative electrode of the capacitor C2 is grounded.

[0096] The present invention also includes:

[0097] A correction method for a power factor correction (PFC) circuit based on the active current control mode as described above, the method comprising:

[0098] The output voltage Vout of the winding-less Boost PFC topology is divided by resistors R4 and R5 and sent to the inverting input of the fast response error amplifier.

[0099] The positive input terminal of the fast response error amplifier is connected to an internally generated 2.5V reference voltage;

[0100] The output of the fast response error amplifier is connected to a type II filter, which reduces its bandwidth to a very low level and filters out the AC component superimposed on Vout. Therefore, the output Vea_out of the error amplifier remains unchanged when the load remains unchanged.

[0101] The control chip contains a sawtooth signal with a fixed slope. Each time the power tube is turned on, the initial value of the sawtooth signal is controlled according to the detected ICS current. The sawtooth signal starts at a fixed voltage and then slowly increases after the start signal is triggered. Once the signal reaches the output Vea_out of the error amplifier, the PWM module generates a shutdown signal to turn off the power tube. Under constant load conditions, the Vea_out signal remains stable, and therefore the on-time also remains stable.

[0102] From the Boost topology characteristics, it can be seen that when the on-time is fixed, the inductor current changes with the input voltage, so power factor correction can be achieved.

[0103] The beneficial effects of the present invention are:

[0104] The present invention is an active current-controlled PFC circuit with a single inductor and no detection coil required. By integrating demagnetization detection, primary current detection, dynamic protection mechanism and optimized control logic, it significantly improves system reliability and efficiency, effectively protects against various abnormal situations, and ensures good system stability and robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] Attachment Figure 1 This is a typical topology diagram of a Boost switching power supply using a multiplier structure and a circuit schematic diagram of a control chip, wherein part of the circuit schematic diagram of the control chip is shown in the dotted box.

[0106] Attachment Figure 2 This is a typical topology diagram of a Boost switching power supply that does not use a multiplier structure and a circuit schematic diagram of a control chip, wherein part of the circuit schematic diagram of the control chip is shown in the dotted box.

[0107] Attachment Figure 3 It is a structural schematic diagram of the winding-free Boost type PFC topology structure of the present invention.

[0108] Attachment Figure 4 It is a functional block diagram of the PFC chip of the present invention.

[0109] Attachment Figure 5 This is the zero current detection module circuit of the present invention.

[0110] Attachment Figure 6 The invention relates to a zero current detection delay and leading edge blanking circuit.

[0111] Attachment Figure 7 It is a fast response error amplifier of the present invention.

[0112] Attachment Figure 8 It is the voltage and current condition of the input terminal when the control chip of the present invention works normally. DETAILED DESCRIPTION

[0113] The present invention will be further described below with reference to the accompanying drawings.

[0114] The present invention provides a power factor correction PFC circuit based on active current control mode, as shown in the attached Figure 3-7 As shown, it includes: winding-free Boost type PFC topology structure and control chip;

[0115] The winding-less Boost PFC topology includes an input voltage source, an input filter capacitor, an inductor, a resistor, a switch, a diode, and an output filter capacitor;

[0116] The control chip includes a zero current detection module circuit, a zero current detection delay and leading edge blanking circuit, a fast response error amplifier, a multi-stage protection integrated circuit, and a demagnetization detection circuit.

[0117] The present invention is an improvement based on the control method of APFC critical conduction mode without multiplier. It does not sample the input voltage to avoid complex circuit structure and linearity problem.

[0118] As attached Figure 3 As shown, the winding-less Boost type PFC topology structure includes: an AC power input end, which is connected to a DC bus via a bridge rectifier diode array;

[0119] The DC bus positive electrode is connected in parallel with a filter capacitor C1;

[0120] The positive electrode of the DC bus is connected to the positive electrode of the inductor L1;

[0121] The cathode of the inductor L1 is connected to the drain of the power tube Q1 and the anode of the diode D1 respectively;

[0122] The negative pole of the DC bus is connected to the first section of the current detection resistor Rsense, the resistor R CS The first end of

[0123] The resistor R CS The second end of is grounded;

[0124] The second section of the current detection resistor Rsense is connected to the CS / ZCD pin of the control chip;

[0125] The gate of the power tube Q1 is connected to the GATE pin of the invented control chip;

[0126] The source of the power tube Q1 is grounded;

[0127] The inductor L1, power tube Q1, current detection resistor R CS Constitute a BOOST type circuit charging loop;

[0128] The cathode of the diode D1 is connected to the first end of the resistor R1, the anode of the output filter capacitor C2, and the anode of the output voltage respectively;

[0129] The second end of the resistor R1 is connected to the first end of the resistor R2, the positive electrode of the capacitor C3, and the FB pin of the invented control chip respectively;

[0130] The second end of the resistor R2 is grounded;

[0131] The negative electrode of the capacitor C3 is grounded;

[0132] The negative end of the output filter capacitor C2 is grounded;

[0133] The VCC pin of the control chip is connected to an external power supply;

[0134] The GND pin of the control chip is grounded;

[0135] The COMP pin of the control chip is respectively connected to the first end of the resistor R3 and the positive electrode of the capacitor C4 in the compensation network;

[0136] The second section of the resistor R3 is connected to the positive electrode of the capacitor C5;

[0137] The negative electrode of the capacitor C4 is grounded;

[0138] The negative electrode of the capacitor C5 is grounded.

[0139] Furthermore, the multi-stage protection integrated circuit includes a cycle-by-cycle current limiting module, an inductor short-circuit protection module, a feedback loop open-loop protection module, an over-temperature protection module, a system overvoltage protection module, and an under-voltage lockout module. The multi-stage protection integrated circuit has a multi-stage protection mechanism, including under-voltage lockout, multi-stage cycle-by-cycle current limiting protection, dual-mechanism dynamic / static overvoltage protection, inductor short-circuit protection, feedback loop fault handling, and over-temperature protection.

[0140] As attached Figure 4 As shown, the present invention is a system overvoltage protection module (OVP) for suppressing abnormal increase in output voltage in the event of a sudden load change (e.g., sudden removal of the load);

[0141] The present invention is used for a VCC undervoltage lockout module (UVLO) to prevent malfunction when the chip power supply voltage is lower than a set threshold;

[0142] The present invention is used for limiting the current peak value in each switching cycle by cycle current limiting module (IL_OCP);

[0143] The present invention is an inductor short circuit protection module (IL_ISP) for detecting an inductor short circuit condition;

[0144] The present invention is used for shutting down the system to prevent damage when the chip temperature exceeds a preset value. Over-temperature protection module (OTP);

[0145] The present invention is a feedback loop open loop protection module (SOP) for closing a system output when a feedback loop is abnormally interrupted.

[0146] In addition, the present invention also has a dual overvoltage protection mechanism based on the change of the output feedback voltage, which can achieve dynamic response and steady-state maintenance, thereby effectively improving the operating safety of the boost switching power supply.

[0147] The present invention further optimizes the design of the above functional modules to ensure that the system has good stability and robustness.

[0148] High-precision research of the present invention:

[0149] In critical conduction mode, the output voltage of the PFC driver chip is unstable and has large ripples. This is basically due to the inaccurate control of the MOS tube's on and off time. The main reason for this inaccuracy is the inaccurate detection of the inductor current zero crossing point. Therefore, this design will use a new circuit structure to achieve high-precision control of the inductor current, thereby achieving high precision of the PFC chip and improving efficiency.

[0150] To keep a PFC chip in critical conduction mode, the current control module is essential. The accuracy of current control directly impacts chip performance. Most PFC chips use two pins to detect the inductor's charge and discharge status: CS (current sensing) and ZCD (zero current detection).

[0151] The present invention uses a similar circuit structure and one pin to detect the inductor current while ensuring high precision of current control.

[0152] As attached Figure 5 As shown, the zero current detection module circuit includes a PMOS tube, and the source of the PMOS tube M2 is connected to a reference current of 10uA;

[0153] The gate of the PMOS tube M2 is connected to the node ZCD_ENB;

[0154] The drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4 and the input end of the inverter respectively;

[0155] The output end of the inverter is connected to the node ZCD_PRI;

[0156] The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M5 and the output end of the operational amplifier AMP respectively;

[0157] The source of the NMOS transistor M4 is connected to the collector of the NPN transistor Q1;

[0158] The base of the NPN transistor Q1 is connected to the base of the NPN transistor Q2, the drain of the NMOS transistor M8, the drain of the PMOS transistor M2, and a reference current of 4uA respectively;

[0159] The emitter of the NPN transistor Q1 is connected to the first end of the first resistor R0;

[0160] The second end of the first resistor R0 is connected to the CS / ZCD pin of the control chip;

[0161] The CS / ZCD pin of the control chip is connected to the first section of the current detection resistor Rsense;

[0162] The second section of the current detection resistor Rsense is connected to the first end of the resistor RCS;

[0163] The second end of the resistor RCS is grounded;

[0164] The drain of the NMOS tube M5 is connected to a reference current of 10uA and the gate of the NMOS tube M3 respectively;

[0165] The source of the NMOS transistor M5 is connected to the collector of the NPN transistor Q2;

[0166] The emitter of Q2 is connected to the first end of the second resistor R1 and the source of the NMOS transistor M7 respectively;

[0167] The second end of the second resistor R1 is connected to the GND pin of the control chip;

[0168] The GND pin of the control chip is grounded;

[0169] The gate and drain of the NMOS tube M6 are connected together, and are connected to a 2uA reference current and the gate of M7;

[0170] The source of M6 is connected to the drain of M7;

[0171] The gate of M8 is connected to the node ZCD_ENB;

[0172] The source of M8 is grounded;

[0173] The gate of M1 is connected to the node ZCD_ENB;

[0174] The source of M1 is connected to the power supply VDD.

[0175] The present invention clamps the pin voltage through an internal operational amplifier and collects the peripheral inductor current through resistor shunt.

[0176] The present invention outputs a control signal according to the collected current, detects the inductor current of the boost switch power supply circuit and detects the charging status, and realizes current threshold control and voltage / time conversion.

[0177] Specifically:

[0178] When the external power tube is turned off, the magnetic energy stored in the inductor and the input voltage are directly provided to the output voltage, and the inductor current gradually decreases. According to the flow direction of the inductor current, the voltage between Rsense and Rcs is negative at this time. At this time, the base of Q1 will have a current of nanoamperes, and after the voltage is positive, there will be a stable current, which is IB0, which is about 100 nanoamperes. When the comparator reaches the reversal point, that is, the emitter voltage of the transistor Q1 reaches the emitter voltage of Q2, which is V E1 =V E2 ,but

[0179]

[0180] V E2 =V E1 =12uA×R0 (2)

[0181] Simplified

[0182] I BO ×(R0+R SENSE )+10uA×R SENSE -2uA×R0=I L ×R CS (3)

[0183] Right now

[0184] (2uA-I BO )×R0-(I BO +10uA)×R SENSE =-I L ×R CS (4)

[0185] At this time, if I L =0, Rsense / Rcs=K, then the specific resistance value of R0 can be obtained, that is, zero current detection is achieved.

[0186] As attached Figure 6 As shown, the zero current detection delay and leading edge blanking circuit includes two input terminals of a NAND gate A1, and the two input terminals of the NAND gate A1 are connected to nodes ZCD_EN and ZCD_PRI respectively;

[0187] The output end of the NAND gate A1 is connected to the input end of the inverter A2;

[0188] The output end of the inverter A2 is connected to the input end of the inverter A3 and the input end 1 of the NAND gate A4 respectively;

[0189] The output end of the inverter A3 is connected to the gate of the PMOS tube M1;

[0190] The source of the PMOS tube M1 is connected to the reference current of IREF1;

[0191] The gate of the PMOS transistor M1 is connected to the source of the NMOS transistor M2, the positive electrode of the capacitor C1, the drain of the NMOS transistor M3, and the positive terminal of the comparator CMP respectively;

[0192] The positive terminal of the operational amplifier AMP is connected to a reference voltage of 2V;

[0193] The negative terminal and the output terminal of the operational amplifier AMP are connected together and connected to the drain of M2;

[0194] The gate of M2 is connected to the node MOS_ON;

[0195] The negative electrode of the capacitor C1 is grounded;

[0196] The gate of the NMOS transistor M3 is connected to the node VDD_ON;

[0197] The source of the NMOS tube M3 is grounded;

[0198] The reference current IREF2 is connected to the FB pin of the control chip and the first end of the resistor R1;

[0199] The FB pin of the control chip is connected to the positive electrode of the capacitor C2;

[0200] The negative electrode of the capacitor C2 is grounded;

[0201] The second end of the resistor R1 is connected to the positive electrode of the capacitor C3 and the negative end of CMP respectively;

[0202] The negative electrode of the capacitor C3 is grounded;

[0203] The negative terminal of the operational amplifier AMP is connected to the input terminal 2 of the NAND gate A4;

[0204] The output end of the NAND gate A4 is connected to the gate of the PMOS transistor M4 and the gate of the NMOS transistor M5 respectively;

[0205] The source of the PMOS tube M4 is connected to the reference current IREF3;

[0206] The drain of the PMOS tube M4 is connected to the drain of M5, the gate of the NMOS tube M6, and the input end of the inverter A5 respectively;

[0207] The source and drain of the NMOS tube M5 are grounded;

[0208] The output end of the inverter A5 is connected to the input end of the inverter A6;

[0209] The output end of the inverter A6 is connected to the node ZCD.

[0210] The present invention uses a demagnetization detection module to monitor the inductor current zero crossing detection (ZCD) in real time with high precision. The module does not require an external zero current detection coil.

[0211] The leading edge blanking circuit (LEB) of the present invention eliminates the power-on spike, and another additional function is to limit the minimum time of the system, thereby reducing the THD of the system under light load.

[0212] The present invention can realize different startup time delays according to the capacitors around the FB pin, and realize the mode switching from BCM to DCM. Figure 6 The zero current detection delay and leading edge blanking circuit are shown.

[0213] Specifically:

[0214] After the demagnetization detection module generates the ZCD_PRI signal, it controls the current to charge capacitor C1, causing the comparator to transition from "0" to "1," thus transmitting the ZCD signal. The negative terminal of the comparator is connected to the FB pin. The reference voltage at the negative terminal can be adjusted based on the value of external capacitor C2 to achieve varying delay times. The subsequent LEB circuit provides a delay of several hundred nanoseconds, eliminating power-on spikes and limiting the system's minimum operating time, thereby reducing the system's total distortion (THD) under light loads.

[0215] Research on response speed of the present invention:

[0216] In the multiplier-less PFC drive circuit employed in this invention, the performance of the error amplifier plays a crucial role in determining the stability of the system's output voltage and its response speed to sudden load changes. Because the power transistor's on-time is directly determined by the error amplifier's output, the error amplifier's output must remain stable throughout a complete power frequency cycle to ensure a high power factor.

[0217] However, because the PFC control system has an AC input voltage, its output voltage inevitably contains harmonic components at twice the power frequency. If this AC component is not effectively filtered out and fed back into the system, it will adversely affect the system's power factor. Therefore, a clear requirement is placed on the error amplifier's bandwidth: its bandwidth should be less than 20Hz to effectively filter out the AC component in the output voltage and improve the system's power factor control accuracy.

[0218] However, too low a bandwidth will limit the system's response speed when the load changes suddenly.

[0219] Specifically:

[0220] When the load suddenly changes from heavy to light, the inductor current should decrease rapidly to prevent output voltage overshoot. However, due to the low bandwidth of the error amplifier, its output remains at its original value for several power frequency cycles. This prevents the power tube's on-time from being shortened in a timely manner, causing the output voltage to rise or even exceed the safety threshold, potentially damaging the filter capacitor and reducing system stability. Conversely, when the load suddenly changes from light to heavy, the error amplifier's slow response prevents the inductor current from rising quickly, resulting in a significant drop in output voltage and an inability to meet load requirements.

[0221] Therefore, in order to improve the comprehensive performance of the system under steady-state and dynamic load conditions, an error amplifier design scheme with adaptive bandwidth adjustment is proposed: when the system load is stable, the error amplifier operates in low-bandwidth mode to filter out high-frequency interference and enhance voltage stability; when the system detects a sudden load change, the error amplifier automatically increases the bandwidth to enhance the transient response capability, thereby ensuring the stable operation of the system while improving the overall response speed and dynamic adjustment capability.

[0222] As attached Figure 7 As shown, the fast response error amplifier adopts a multi-vector error amplifier to avoid the influence of sudden load changes on the stability of the system output voltage.

[0223] The fast response error amplifier includes the positive terminal of the comparator CMP1, and the FB pin of the control chip is respectively connected to the positive terminal of the comparator CMP1, the negative terminal of the error amplifier EA, and the positive terminal of the comparator CMP2;

[0224] The negative terminal of the comparator CMP1 is connected to a reference voltage of 2.35V;

[0225] The negative terminal of the comparator CMP2 is connected to a reference voltage of 2.60V;

[0226] The positive terminal of the error amplifier EA is connected to a reference voltage of 2.50V;

[0227] The output end of the comparator CMP1 is connected to the starting end of the reference current I1;

[0228] The output end of the error amplifier EA is connected to the COMP pin of the control chip;

[0229] The output end of the CMP2 is connected to the starting end of the reference current I2;

[0230] The output end of the error amplifier EA is connected to the control chip COMP pin which is respectively connected to the reference current I1, the reference current I2, the first end of the resistor R1, and the positive electrode of the capacitor C2;

[0231] The second end of the resistor R1 is connected to the positive electrode of the capacitor C1;

[0232] The negative electrode of the capacitor C1 is grounded;

[0233] The negative electrode of the capacitor C2 is grounded.

[0234] Specifically, the present invention adds two current source branches, each controlled by the outputs of comparators CMP1 and CMP2, respectively. When the system is stable, both branches are inactive, and the error amplifier maintains a low bandwidth. When the load suddenly changes from heavy to light, and the output sampling voltage FB exceeds 2.65V, comparator CMP2 outputs a high level, turning on current source I2. The error amplifier output discharges to ground through the current source, rapidly reducing the output voltage, immediately reducing the power tube on-time, and consequently reducing the inductor current. The loop then reaches stability, preventing output voltage overcharge. When the load suddenly changes from light to heavy, and the output sampling voltage FB falls below 2.35V, comparator CMP1 outputs a high level, turning on current source I1. This immediately pulls up the error amplifier output, increasing the power tube on-time, rapidly increasing the inductor current, and consequently increasing the energy delivered to the load, preventing the output voltage from being pulled too low. This circuit structure achieves fast circuit response and enhances circuit stability.

[0235] This embodiment also includes:

[0236] A correction method for a power factor correction (PFC) circuit based on the active current control mode, the method comprising:

[0237] The output voltage Vout of the winding-less Boost PFC topology is divided by resistors R4 and R5 and sent to the inverting input of the fast response error amplifier.

[0238] The positive input terminal of the fast response error amplifier is connected to an internally generated 2.5V reference voltage;

[0239] The output of the fast response error amplifier is connected to a type II filter, which reduces its bandwidth to a very low level and filters out the AC component superimposed on Vout. Therefore, the output Vea_out of the error amplifier remains unchanged when the load remains unchanged.

[0240] The control chip contains a sawtooth signal with a fixed slope. Each time the power tube is turned on, the initial value of the sawtooth signal is controlled according to the detected ICS current. The sawtooth signal starts at a fixed voltage and then slowly increases after the start signal is triggered. Once the signal reaches the output Vea_out of the error amplifier, the PWM module generates a shutdown signal to turn off the power tube. Under constant load conditions, the Vea_out signal remains stable, and therefore the on-time also remains stable.

[0241] From the Boost topology characteristics, it can be seen that when the on-time is fixed, the inductor current changes with the input voltage, so power factor correction can be achieved.

[0242] Finally, the present invention realizes a dual mechanism of dynamic and steady-state overvoltage protection based on the output feedback voltage FB representing the output voltage of the boost switching power supply circuit;

[0243] The oscillator outputs a periodic square wave which is frequency-adjusted by a frequency divider to limit the maximum and minimum switching time of the MOS tube, and the CRM and DCM mode switching is achieved through frequency limitation to avoid current mutation.

[0244] The final experimental results of the active current control boost PFC circuit show that in an AC-DC system with an input voltage of 90-264V and an output power of 100W, the power factor (PF) is ≥0.97 and the total harmonic distortion (THD) is <5%. Figure 8 The figure shows the voltage and current at the input end when the chip is working normally. At this time, the PF is about 0.99367.

[0245] The present invention proposes an active conversion mode active flow control PFC chip based on Boost topology for a 100-watt AC-DC switching power supply system.

[0246] The control chip of the present invention meets the requirements of high power factor (PF), low harmonic distortion (THD) and compact design. The chip integrates a demagnetization detection module and primary current detection technology. The chip does not require an external zero current detection (ZCD) coil, and while simplifying the circuit structure and reducing costs, it realizes real-time high-precision monitoring of the inductor current zero crossing point (ZCD). It combines dynamic and steady-state overvoltage protection dual mechanisms, multi-level protection integration (OCP / ISP / SOP / OTP) and CRM / DCM mode switching strategies. The above strategies effectively solve the problems of insufficient harmonic suppression, poor dynamic load adaptability and low system reliability in traditional solutions.

[0247] Compared with existing 100-watt PFC chips, the present invention reduces circuit volume by eliminating the external ZCD detection coil, and significantly reduces the risk of output voltage loss of control or device damage by virtue of optimized control logic and protection mechanism.

[0248] The control chip of this invention provides an efficient and reliable solution for high-power density PD chargers. The circuit also complies with the stringent harmonic suppression and power quality requirements of energy efficiency regulations such as IEC 61000-3-2, and has broad application prospects.

[0249] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0250] The descriptions in this specification refer only to preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Furthermore, reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" implies that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, those skilled in the art may combine and integrate the different embodiments or examples described in this specification, as well as features from different embodiments or examples, unless otherwise specified. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance or to implicitly specify the number of the technical features indicated. Therefore, features designated "first" or "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined. Any process or method description in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code comprising one or more executable instructions for implementing a custom logic function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed in a different order than shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which the embodiments of the present invention pertain. The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logic function, can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in conjunction with such instruction execution systems, apparatuses, or devices. For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such instruction execution systems, apparatuses, or devices. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or N wirings (electronic devices), a portable computer disk cartridge (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM).In addition, the computer-readable medium may even be paper or other suitable medium on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, then editing, interpreting, or processing in other suitable ways as necessary, and then storing it in a computer memory. It should be understood that the various parts of the present invention can be implemented with hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented with hardware, as in another embodiment, any one of the following technologies known in the art or their combination can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0251] Those skilled in the art will appreciate that all or part of the steps carried out in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment. In addition, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

Claims

1. A power factor correction (PFC) circuit based on active current control mode, characterized in that: include: Winding-free Boost PFC topology and control chip; The winding-less Boost PFC topology includes an input voltage source, an input filter capacitor, an inductor, a resistor, a switch, a diode, and an output filter capacitor; The control chip includes a zero current detection module circuit, a zero current detection delay and leading edge blanking circuit, a fast response error amplifier, a multi-stage protection integrated circuit, and a demagnetization detection circuit.

2. The power factor correction (PFC) circuit based on active current control mode according to claim 1, characterized in that: The winding-less Boost PFC topology structure includes an AC power input terminal, which is connected to a DC bus via a bridge rectifier diode array; The DC bus positive electrode is connected in parallel with a filter capacitor C1; The positive electrode of the DC bus is connected to the positive electrode of the inductor L1; The cathode of the inductor L1 is connected to the drain of the power tube Q1 and the anode of the diode D1 respectively; The negative pole of the DC bus is connected to the first section of the current detection resistor Rsense, the resistor R CS The first end of The resistor R CS The second end of is grounded; The second section of the current detection resistor Rsense is connected to the CS / ZCD pin of the control chip; The gate of the power tube Q1 is connected to the GATE pin of the invented control chip; The source of the power tube Q1 is grounded; The inductor L1, power tube Q1, current detection resistor R CS Constitute a BOOST type circuit charging loop; The cathode of the diode D1 is connected to the first end of the resistor R1, the anode of the output filter capacitor C2, and the anode of the output voltage respectively; The second end of the resistor R1 is connected to the first end of the resistor R2, the positive electrode of the capacitor C3, and the FB pin of the invented control chip respectively; The second end of the resistor R2 is grounded; The negative electrode of the capacitor C3 is grounded; The negative end of the output filter capacitor C2 is grounded; The VCC pin of the control chip is connected to an external power supply; The GND pin of the control chip is grounded; The COMP pin of the control chip is respectively connected to the first end of the resistor R3 and the positive electrode of the capacitor C4 in the compensation network; The second section of the resistor R3 is connected to the positive electrode of the capacitor C5; The negative electrode of the capacitor C4 is grounded; The negative electrode of the capacitor C5 is grounded.

3. The power factor correction (PFC) circuit based on active current control mode according to claim 1 or 2, characterized in that: The multi-stage protection integrated circuit includes a cycle-by-cycle current limiting module, an inductor short-circuit protection module, a feedback loop open-loop protection module, an over-temperature protection module, a system overvoltage protection module, and an under-voltage lockout module. The multi-stage protection integrated circuit has a multi-stage protection mechanism, including under-voltage lockout, multi-stage cycle-by-cycle current limiting protection, dual-mechanism dynamic / static overvoltage protection, inductor short-circuit protection, feedback loop fault handling, and over-temperature protection.

4. The power factor correction (PFC) circuit based on active current control mode according to claim 1, characterized in that: The zero current detection module circuit includes a PMOS tube, and the source of the PMOS tube M2 is connected to a reference current of 10uA; The gate of the PMOS tube M2 is connected to the node ZCD_ENB; The drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4 and the input end of the inverter respectively; The output end of the inverter is connected to the node ZCD_PRI; The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M5 and the output end of the operational amplifier AMP respectively; The source of the NMOS transistor M4 is connected to the collector of the NPN transistor Q1; The base of the NPN transistor Q1 is connected to the base of the NPN transistor Q2, the drain of the NMOS transistor M8, the drain of the PMOS transistor M2, and a reference current of 4uA respectively; The emitter of the NPN transistor Q1 is connected to the first end of the first resistor R0; The second end of the first resistor R0 is connected to the CS / ZCD pin of the control chip; The CS / ZCD pin of the control chip is connected to the first section of the current detection resistor Rsense; The second section of the current detection resistor Rsense is connected to the first end of the resistor RCS; The second end of the resistor RCS is grounded; The drain of the NMOS tube M5 is connected to a reference current of 10uA and the gate of the NMOS tube M3 respectively; The source of the NMOS transistor M5 is connected to the collector of the NPN transistor Q2; The emitter of Q2 is connected to the first end of the second resistor R1 and the source of the NMOS transistor M7 respectively; The second end of the second resistor R1 is connected to the GND pin of the control chip; The GND pin of the control chip is grounded; The gate and drain of the NMOS tube M6 are connected together, and are connected to a 2uA reference current and the gate of M7; The source of M6 is connected to the drain of M7; The gate of M8 is connected to the node ZCD_ENB; The source of M8 is grounded; The gate of M1 is connected to the node ZCD_ENB; The source of M1 is connected to the power supply VDD.

5. The power factor correction (PFC) circuit based on active current control mode according to claim 1, characterized in that: The zero current detection delay and leading edge blanking circuit includes two input terminals of a NAND gate A1, and the two input terminals of the NAND gate A1 are connected to nodes ZCD_EN and ZCD_PRI respectively; The output end of the NAND gate A1 is connected to the input end of the inverter A2; The output end of the inverter A2 is connected to the input end of the inverter A3 and the input end 1 of the NAND gate A4 respectively; The output end of the inverter A3 is connected to the gate of the PMOS tube M1; The source of the PMOS tube M1 is connected to the reference current of IREF1; The gate of the PMOS transistor M1 is connected to the source of the NMOS transistor M2, the positive electrode of the capacitor C1, the drain of the NMOS transistor M3, and the positive terminal of the comparator CMP respectively; The positive terminal of the operational amplifier AMP is connected to a reference voltage of 2V; The negative terminal and the output terminal of the operational amplifier AMP are connected together and connected to the drain of M2; The gate of M2 is connected to the node MOS_ON; The negative electrode of the capacitor C1 is grounded; The gate of the NMOS transistor M3 is connected to the node VDD_ON; The source of the NMOS tube M3 is grounded; The reference current IREF2 is connected to the FB pin of the control chip and the first end of the resistor R1; The FB pin of the control chip is connected to the positive electrode of the capacitor C2; The negative electrode of the capacitor C2 is grounded; The second end of the resistor R1 is connected to the positive electrode of the capacitor C3 and the negative end of CMP respectively; The negative electrode of the capacitor C3 is grounded; The negative terminal of the operational amplifier AMP is connected to the input terminal 2 of the NAND gate A4; The output end of the NAND gate A4 is connected to the gate of the PMOS transistor M4 and the gate of the NMOS transistor M5 respectively; The source of the PMOS tube M4 is connected to the reference current IREF3; The drain of the PMOS tube M4 is connected to the drain of M5, the gate of the NMOS tube M6, and the input end of the inverter A5 respectively; The source and drain of the NMOS tube M5 are grounded; The output end of the inverter A5 is connected to the input end of the inverter A6; The output end of the inverter A6 is connected to the node ZCD.

6. The power factor correction (PFC) circuit based on active current control mode according to claim 1, characterized in that: The fast response error amplifier adopts a multi-vector error amplifier to avoid the influence of sudden load changes on the stability of the system output voltage.

7. The power factor correction (PFC) circuit based on active current control mode according to claim 1 or 6, characterized in that: The fast response error amplifier includes the positive terminal of the comparator CMP1, and the FB pin of the control chip is respectively connected to the positive terminal of the comparator CMP1, the negative terminal of the error amplifier EA, and the positive terminal of the comparator CMP2; The negative terminal of the comparator CMP1 is connected to a reference voltage of 2.35V; The negative terminal of the comparator CMP2 is connected to a reference voltage of 2.60V; The positive terminal of the error amplifier EA is connected to a reference voltage of 2.50V; The output end of the comparator CMP1 is connected to the starting end of the reference current I1; The output end of the error amplifier EA is connected to the COMP pin of the control chip; The output end of the CMP2 is connected to the starting end of the reference current I2; The output end of the error amplifier EA is connected to the control chip COMP pin which is respectively connected to the reference current I1, the reference current I2, the first end of the resistor R1, and the positive electrode of the capacitor C2; The second end of the resistor R1 is connected to the positive electrode of the capacitor C1; The negative electrode of the capacitor C1 is grounded; The negative electrode of the capacitor C2 is grounded.

8. A correction method for a power factor correction (PFC) circuit based on an active current control mode according to any one of claims 1 to 7, characterized in that: The method includes: The output voltage Vout of the winding-less Boost PFC topology is divided by resistors R4 and R5 and then sent to the inverting input of the fast response error amplifier. The positive input terminal of the fast response error amplifier is connected to an internally generated 2.5V reference voltage; The output of the fast response error amplifier is connected to a type II filter, which reduces its bandwidth to a very low level and filters out the AC component superimposed on Vout. Therefore, the output Vea_out of the error amplifier remains unchanged when the load remains unchanged. The control chip contains a sawtooth signal with a fixed slope. Each time the power tube is turned on, the initial value of the sawtooth signal is controlled according to the detected ICS current. The sawtooth signal starts at a fixed voltage and then slowly increases after the start signal is triggered. Once the signal reaches the output Vea_out of the error amplifier, the PWM module generates a shutdown signal to turn off the power tube. Under constant load conditions, the Vea_out signal remains stable, and therefore the on-time also remains stable. From the Boost topology characteristics, it can be seen that when the on-time is fixed, the inductor current changes with the input voltage, so power factor correction can be achieved.

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