Phase change memory

Abstract

The invention discloses a phase change memory, which can be used in the field of semiconductor devices, and comprises a memory cell, a linear barrier layer, a first signal line and a second signal line, wherein the first signal line is located on the first side of the storage unit, and the second signal line is located on the second side of the storage unit; the linear barrier layer covers the side wall of the storage unit, and the side wall of the storage unit is perpendicular to the first signal line and the second signal line; the linear barrier layer comprises a first barrier layer in contact with the side wall of the memory unit and a second barrier layer deviating from the side wall of the memory unit; the thermal conductivity of the second barrier layer is higher than that of the first barrier layer. Therefore, heat generated by RESET current is prevented from being transmitted to the periphery through the first barrier layer with low thermal conductivity; the heat overflowing from the first barrier layer is quickly conducted away through the second barrier layer with high thermal conductivity, so that the frequency of crystalline-amorphous inversion of the surrounding memory units is reduced, the write-in error is reduced, and the reliability of the phase change memory is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a phase change memory. Background Art

[0002] Phase Change Memory (PCM) is a new type of non-volatile memory. As PCM is gradually widely used in various fields such as high-performance computing and mobile devices, the reliability of PCM is receiving increasing attention.

[0003] Phase change memory relies on the Joule heat of electric current to convert the phase change memory cell material between the crystalline low resistance and the amorphous high resistance, thereby realizing the switching between the set (SET) state and the reset (RESET) state to complete data storage. At present, in order to improve the storage density of phase change memory, phase change memory usually adopts a storage array structure including multiple memory cells. Since there are key dimension deviations between different memory cells during the manufacturing process of phase change memory, in order to ensure that the SET state and RESET state of each memory cell with different key dimensions can be significantly distinguished in resistance value, a larger RESET current is required during the operation of phase change memory. However, the Joule heat generated by the larger RESET current will cause thermal disturbance to the surrounding memory cells, causing crystalline-amorphous state inversion in the surrounding memory cells, causing write errors (write disturb, WD), and reducing the reliability of phase change memory.

[0004] Therefore, how to improve the reliability of phase change memory has become a problem that needs to be solved. Summary of the Invention

[0005] Based on the above problems, the present application provides a phase change memory, which can improve the reliability of the phase change memory.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] An embodiment of the present application provides a phase change memory, the phase change memory comprising: a memory unit, a linear barrier layer, a first signal line, and a second signal line;

[0008] The first signal line is located at a first side of the storage unit, and the second signal line is located at a second side of the storage unit;

[0009] The linear barrier layer covers the sidewalls of the memory cell, and the sidewalls of the memory cell are perpendicular to the first signal line and the second signal line;

[0010] The linear barrier layer includes a first barrier layer contacting the sidewall of the memory cell and a second barrier layer away from the sidewall of the memory cell; the thermal conductivity of the second barrier layer is higher than that of the first barrier layer.

[0011] Optionally, a plurality of intermediate barrier layers are provided between the first barrier layer and the second barrier layer; and the thermal conductivity of the second barrier layer is higher than that of the intermediate barrier layer.

[0012] Optionally, the plurality of intermediate barrier layers include a first intermediate barrier layer and a second intermediate barrier layer;

[0013] The first barrier layer at least covers the top electrode and the phase change memory layer in the memory cell and is connected to the first signal line;

[0014] The first intermediate barrier layer covers the first barrier layer and is connected to the first signal line;

[0015] The second intermediate barrier layer covers the first intermediate barrier layer and the exposed sidewalls of the memory cell, and is perpendicular to and connected to the first signal line and the second signal line;

[0016] The second barrier layer covers the second intermediate barrier layer and is perpendicular to and connected to the first signal line and the second signal line.

[0017] Optionally, a side of the first intermediate barrier layer facing away from the first signal line is flush with a side of the gate layer in the memory unit close to the first signal line.

[0018] Optionally, the second barrier layer is parallel to an extension direction of the first signal line.

[0019] Optionally, the second barrier layer includes a first sub-barrier layer and a second sub-barrier layer;

[0020] The first sub-blocking layer is parallel to an extending direction of the first signal line; and the second sub-blocking layer is parallel to an extending direction of the second signal line.

[0021] Optionally, a material of the second barrier layer is selected from any one of boron nitride, aluminum nitride, aluminum oxide and magnesium oxide.

[0022] Optionally, the thermal conductivity of the second barrier layer is not less than 20 W / m·K.

[0023] Optionally, the thermal conductivity of the first barrier layer is not higher than 1.5 W / m·K.

[0024] Optionally, the electrical conductivity of the second barrier layer is not higher than 1×e -11 S / m.

[0025] Compared with the existing technology, this application has the following beneficial effects:

[0026] The present invention provides a phase-change memory (PCM) comprising a memory cell, a linear barrier layer, a first signal line, and a second signal line. The first signal line is located on a first side of the memory cell, and the second signal line is located on a second side of the memory cell. The linear barrier layer covers the sidewalls of the memory cell, and the sidewalls of the memory cell are perpendicular to the first and second signal lines. The linear barrier layer comprises a first barrier layer contacting the sidewalls of the memory cell and a second barrier layer facing away from the sidewalls of the memory cell. The thermal conductivity of the second barrier layer is higher than that of the first barrier layer. Thus, a linear barrier layer with anisotropic thermal conductivity is employed in the PCM. The first barrier layer contacting the sidewalls of the memory cell has a lower thermal conductivity, thereby blocking heat generated by the RESET current from being transferred to the surrounding area during a RESET operation. The second barrier layer facing away from the sidewalls of the memory cell has a higher thermal conductivity, thereby quickly conducting away heat that escapes from the first barrier layer, thereby reducing thermal disturbances experienced by adjacent memory cells and the frequency of crystalline-amorphous state inversion in the surrounding memory cells. This reduces write errors and improves the reliability of the PCM. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A side cross-sectional view of a phase change memory provided in an embodiment of the present application;

[0029] Figure 2 A plan view of a phase change memory provided in an embodiment of the present application;

[0030] Figure 3 A plan view of temperature distribution in a phase change memory provided in an embodiment of the present application;

[0031] Figure 4 A plan view of temperature distribution in another phase change memory provided in an embodiment of the present application;

[0032] Figure 5 A plan view of temperature distribution in another phase change memory provided in an embodiment of the present application;

[0033] Figure 6 A plan view of another phase change memory provided in an embodiment of the present application;

[0034] Figure 7 A side cross-sectional view of another phase change memory provided in an embodiment of the present application;

[0035] Figure 8 A side cross-sectional view of another phase change memory provided in an embodiment of the present application;

[0036] Figure 9 A side cross-sectional view of another phase change memory provided in an embodiment of the present application;

[0037] Figure 10 A structural diagram of a three-dimensional stacked phase change memory provided in an embodiment of the present application;

[0038] Figure 11 This is another structural diagram of a three-dimensional stacked phase change memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The phase change memory provided in the present application can be used in the field of semiconductor devices. The above is only an example and does not limit the application field of the phase change memory provided in the present application.

[0040] The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0041] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in the embodiments of this application as "as an example" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0043] As mentioned above, Phase Change Memory (PCM) is a new type of non-volatile memory that relies on Joule heating of electric current to convert the phase change memory cell material between crystalline low resistance and amorphous high resistance, thereby realizing the switching between the set (SET) state and the reset (RESET) state to complete data storage.

[0044] When using low thermal conductivity materials, such as silicon nitride or silicon oxide with a thermal conductivity between 0.5 and 1.5 W / m·K, as linear barrier layers on the stack and memory cell sidewalls, the inventors conducted experimental simulations and found that in a memory array consisting of 3×3 memory cells, the temperature of the aggressive cell performing a RESET operation reached a steady state after approximately 10 ns, while the temperature of the surrounding victim cells also reached a steady state after approximately 13 ns.

[0045] Due to the thermal insulation effect of the linear barrier layer on the sidewalls, heat conduction is delayed. If the linear barrier layer can effectively block temperature conduction, the active memory cell will begin to cool down before the affected memory cells around it reach the theoretical maximum temperature limit, and the temperature of the affected memory cells around it will not be observed to reach a steady state. However, in the experimental simulation results, the temperature of the affected memory cells around it reaches a steady state. This shows that when using low thermal conductivity materials as linear barrier layers, it is impossible to produce sufficient delay in heat transfer and it is difficult to completely suppress the maximum temperature of the surrounding memory cells. The Joule heat generated by the RESET current will cause thermal disturbances in the surrounding memory cells, causing crystalline-amorphous inversion in the surrounding memory cells, causing write disturbances (WD), and reducing the reliability of the phase change memory.

[0046] In view of this, an embodiment of the present application provides a phase-change memory, wherein the linear barrier layer in the phase-change memory includes a first barrier layer contacting the sidewalls of the memory cell and a second barrier layer facing away from the sidewalls of the memory cell; wherein the thermal conductivity of the second barrier layer is higher than that of the first barrier layer. As a result, the first barrier layer contacting the sidewalls of the memory cell has a lower thermal conductivity, thereby preventing heat generated by the RESET current from being transferred to the surrounding area during a RESET operation; while the second barrier layer facing away from the sidewalls of the memory cell has a higher thermal conductivity, thereby quickly conducting away heat that escapes from the first barrier layer, thereby reducing thermal disturbances experienced by adjacent memory cells and the frequency of crystalline-amorphous state inversion in surrounding memory cells, thereby reducing write errors and improving the reliability of the phase-change memory.

[0047] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0048] See also Figure 1, this figure is a side sectional view of a phase change memory provided in an embodiment of the present application, the phase change memory comprising: a storage unit 101, a linear barrier layer 102, a first signal line 103 and a second signal line 104.

[0049] The first signal line 103 may be a bit line (BL) or a word line (WL); correspondingly, the second signal line may be a word line or a bit line.

[0050] The first signal line 103 is located at a first side of the memory cell 101 , and the second signal line 104 is located at a second side of the memory cell 101 .

[0051] The linear barrier layer 102 covers the sidewalls of the memory cell 101 , and the sidewalls of the memory cell 101 are perpendicular to the first signal line 103 and the second signal line 104 .

[0052] The linear barrier layer 102 includes a first barrier layer 1021 contacting the sidewall of the memory cell 101 and a second barrier layer 1022 away from the sidewall of the memory cell 101 ; the thermal conductivity of the second barrier layer 1022 is higher than that of the first barrier layer 1021 .

[0053] Exemplarily, the material of the first barrier layer 1021 can be a material with low thermal conductivity such as silicon oxide (SiOx) or silicon nitride (SiNx); the material of the second barrier layer 1022 can be selected from materials with high thermal conductivity such as boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3) and magnesium oxide (MgO).

[0054] Therefore, in an embodiment of the present application, a linear barrier layer with anisotropic thermal conductivity is applied in a phase change memory, wherein the first barrier layer contacting the side wall of the memory cell has a low thermal conductivity, which can block the heat generated by the RESET current from being transferred to the surroundings during the RESET operation; the second barrier layer away from the side wall of the memory cell has a high thermal conductivity, which can quickly conduct away the heat overflowing from the first barrier layer, thereby reducing the thermal disturbance of adjacent memory cells and reducing the frequency of crystalline-amorphous inversion in surrounding memory cells, thereby reducing write errors and improving the reliability of the phase change memory.

[0055] See also Figure 2 , this figure is a plan cross-sectional view of a phase change memory provided by an embodiment of the present application, wherein the second barrier layer 1022 is parallel to the extension direction of the first signal line 103 .

[0056] Specifically, a linear barrier layer 102 having a first barrier layer 1021 and a second barrier layer 1022 is provided only for the side walls of the memory cell 101 parallel to the word line extension direction or the bit line extension direction; correspondingly, a linear barrier layer 102 having a first barrier layer 1021 and a third barrier layer 1023 can be provided for the side walls of the memory cell 101 parallel to the bit line extension direction or the word line extension direction, wherein the material of the third barrier layer 1023 can be a material with low thermal conductivity such as Si-O or Si-N.

[0057] See also Figure 3 , which is a plan view of the temperature distribution in a phase change memory provided by an embodiment of the present application, Figure 3 In the corresponding phase change memory, the linear barrier layer 102 includes a first barrier layer 1021 and a third barrier layer 1023 .

[0058] It can be seen that when only low thermal conductivity material is used as the linear barrier layer (baseline), a RESET operation is performed on a memory cell in the phase change memory. After the temperatures of the active memory cell (aggressive cell) and the surrounding affected memory cells (victim cells) reach a steady state, the temperature of the aggressive cell is 1070K, the temperatures of the victim cells above and below the aggressive cell are both 490K, and the temperatures of the victim cells to the left and right of the aggressive cell are both 466K. The range of the 200°C isotherm has already connected to the edges of the surrounding memory cells.

[0059] See also Figure 4 , which is a plan view of the temperature distribution in another phase change memory provided by an embodiment of the present application, Figure 4 In the corresponding phase change memory, the linear barrier layer 102 parallel to the extension direction of the first signal line includes a first barrier layer 1021 and a second barrier layer 1022 , and the linear barrier layer 102 parallel to the extension direction of the second signal line includes a first barrier layer 1021 and a third barrier layer 1023 .

[0060] As an example, the linear barrier layer 102 parallel to the word line WL extension direction includes a first barrier layer 1021 and a second barrier layer 1022 (WL liner TC+). A RESET operation is performed on a memory cell in a phase-change memory. After the temperatures of the active memory cell (aggressive cell) and the surrounding victim cells (victim cells) reach a steady state, the temperature of the aggressive cell is 1079K, the temperatures of the victim cells above and below the aggressive cell are both 439K, and the temperatures of the victim cells to the left and right of the aggressive cell are both 464K. The range of the 200°C isothermal line is significantly reduced on both sides of the word line WL extension direction.

[0061] Compared to Figure 3 The corresponding instance, Figure 4 In the corresponding example, the temperature of the victim cells located above and below the aggressive cell decreased by 51K, which significantly improved the thermal distribution in the phase-change memory and reduced the crystalline-amorphous state inversion in the surrounding memory cells, thereby reducing write errors and improving the reliability of the phase-change memory.

[0062] Thus, a linear barrier layer comprising a first barrier layer and a second barrier layer is provided only on the sidewalls of the memory cells parallel to the direction in which the first signal line extends. During a RESET operation, the second barrier layer, facing away from the memory cell sidewall, can quickly and directionally conduct away heat that escapes from the corresponding first barrier layer, thereby reducing the frequency of crystalline-amorphous state reversal in the memory cells located on both sides of the first signal line. This solution requires less expensive high-thermal conductivity material, reduces write errors, and improves the reliability of the phase-change memory without significantly increasing overall manufacturing costs.

[0063] See also Figure 5 , which is a plan view of temperature distribution in another phase change memory provided by an embodiment of the present application, Figure 5 The corresponding cross-sectional view of the phase change memory is as follows: Figure 6 As shown, the second blocking layer 1022 includes a first sub-blocking layer 01 and a second sub-blocking layer 02 , wherein the first sub-blocking layer 01 is parallel to the extension direction of the first signal line 103 ; the second sub-blocking layer 02 is parallel to the extension direction of the second signal line 104 .

[0064] As an example, the linear barrier layer 102 parallel to the word line WL and the linear barrier layer 102 parallel to the bit line BL both have a first barrier layer 1021 and a second barrier layer 1022 (WL / BL liner TC+). A RESET operation is performed on a memory cell in a phase-change memory. After the temperatures of the active memory cell (aggressive cell) and the surrounding victim cells (victim cells) reach a steady state, the temperature of the aggressive cell is 1068K, the temperatures of the victim cells above and below the aggressive cell are both 424K, and the temperatures of the victim cells to the left and right of the aggressive cell are both 449K. The range of the 200°C isotherm is significantly reduced around the aggressive cell.

[0065] Compared to Figure 3 The corresponding instance, Figure 5 In the corresponding example, the temperature of the victim cells located above and below the aggressive cell decreased by 66K, and the temperature of the victim cells located to the left and right of the aggressive cell decreased by 17K. This significantly improves the thermal distribution in the phase-change memory and can significantly reduce the occurrence of crystalline-amorphous state inversion in the surrounding storage cells, thereby reducing write errors and improving the reliability of the phase-change memory.

[0066] Therefore, the side walls of the memory cell parallel to the extension direction of the first signal line and the side walls of the memory cell parallel to the extension direction of the second signal line are both provided with a linear barrier layer having a first barrier layer and a second barrier layer. During the RESET operation, the second barrier layer away from the side wall of the memory cell can be used to quickly and directionally conduct away the heat overflowing from the corresponding first barrier layer, thereby more significantly reducing the frequency of crystalline-amorphous state inversion in other surrounding memory cells that have not performed the RESET operation, reducing write errors, and improving the reliability of the phase change memory.

[0067] See also Figure 7 , this figure is a side cross-sectional view of another phase change memory provided in an embodiment of the present application, wherein the memory cell 101 includes: a bottom electrode 1011, a gating layer 1012, an intermediate electrode 1013, a phase change memory layer 1014 and a top electrode 1015 stacked in sequence; the bottom electrode 1011 is in contact with the first signal line 103, and the top electrode 1015 is in contact with the second signal line 104.

[0068] As an example, the linear barrier layer 102 may further include multiple intermediate barrier layers between the first barrier layer 1021 and the second barrier layer 1022, where the thermal conductivity of the second barrier layer 1022 is higher than that of the intermediate barrier layers. Thus, the multiple low-thermal-conductivity barrier layers can better prevent heat generated by the RESET current from being transferred to the surrounding area, while any excess heat can be quickly conducted away through the high-thermal-conductivity second barrier layer 1022, thereby reducing thermal disturbances experienced by adjacent memory cells and improving the reliability of the phase-change memory.

[0069] For example, the linear barrier layer 102 may be composed of four barrier layers: a first barrier layer 1021, a first intermediate barrier layer 112, a second intermediate barrier layer 122, and a second barrier layer 1022. The first barrier layer 1021 is the innermost barrier layer (close to the side of the memory cell 101), the second barrier layer 1022 is the outermost barrier layer (away from the memory cell 101), and the intermediate barrier layer includes the first intermediate barrier layer 112 and the second intermediate barrier layer 122.

[0070] The first barrier layer 1021 covers at least the top electrode 1015 and the phase-change memory layer 1014 in the memory cell 101 and is connected to the first signal line 103. The first intermediate barrier layer 112 covers the first barrier layer 2021 and is connected to the first signal line 103. The first barrier layer 1021 and the first intermediate barrier layer 112 are of the same size and overlap.

[0071] As an example, the side of the first intermediate barrier layer 112 facing away from the memory cell 101 is flush with the side of the gating layer 1012 in the memory cell 101 in the vertical direction. For example, in the phase change memory provided in this embodiment, the first barrier layer 1021 can cover the top electrode 1015 in the memory cell 101 and the sidewall of the phase change memory layer 1014, as shown in FIG. Figure 8 shown.

[0072] The second intermediate barrier layer 122 covers the first intermediate barrier layer 112 and the exposed sidewalls of the memory cell 101, and the second intermediate barrier layer 122 is perpendicular to and connected to the first signal line 103 and the second signal line 104. The second barrier layer 1022 covers the second intermediate barrier layer 122, and is perpendicular to and connected to the first signal line 103 and the second signal line 104. The second barrier layer 1022 is the same size as the second intermediate barrier layer 122 and overlaps with it. For example, the second intermediate barrier layer 122 can cover the first intermediate barrier layer 112 and the sidewalls of the bottom electrode 1011, the gate layer 1012, and the intermediate electrode 1013 in the memory cell 101, as shown in FIG. Figure 8 shown.

[0073] As another example, the side of the first intermediate barrier layer 112 facing away from the first signal line 103 is flush with the side of the gating layer 1012 in the memory cell 101 close to the first signal line 103; the side of the first intermediate barrier layer 112 facing away from the memory cell 101 is flush with the side of the gating layer 1012 in the memory cell 101 in the vertical direction. For example, in the phase change memory provided in this embodiment, the first barrier layer 1021 can cover the sidewalls of the top electrode 1015, the phase change memory layer 1014, and the intermediate electrode 1013 in the memory cell 101, as shown in FIG. Figure 9 shown.

[0074] The second intermediate barrier layer 122 covers the first intermediate barrier layer 112 and the exposed sidewalls of the memory cell 101, and the second intermediate barrier layer 122 is perpendicular to and connected to the first signal line 103 and the second signal line 104. The second barrier layer 1022 covers the second intermediate barrier layer 122, and is perpendicular to and connected to the first signal line 103 and the second signal line 104. The second barrier layer 1022 and the second intermediate barrier layer 122 have the same size and overlap. For example, the second intermediate barrier layer 122 can cover the first intermediate barrier layer 112 and the sidewalls of the bottom electrode 1011 and the gate layer 1012 in the memory cell 101, as shown in FIG. Figure 9 shown.

[0075] The first signal line 103 and the second signal line 104 can be made of a material with high thermal conductivity, such as tungsten. Ideally, excess heat from the memory cell 101 performing a RESET operation can be conducted away through the first signal line 103 and the second signal line 104 to avoid affecting other surrounding memory cells. However, in the memory cell 101 provided in this embodiment, the bottom electrode 1011, the gate layer 1012, the middle electrode 1013, and the top electrode 1015 have relatively low thermal conductivity, which hinders the heat dissipation of the phase-change memory layer 1014 in the vertical direction. The excess heat will be conducted laterally, causing the temperature of other surrounding memory cells to rise, resulting in write errors.

[0076] In this embodiment, the linear barrier layer 102 consists of a first barrier layer 1021 with low thermal conductivity located near the memory cell 101, an intermediate barrier layer, and a second barrier layer 1022 with high thermal conductivity located away from the memory cell 101. During a RESET operation, the first barrier layer 1021 and the intermediate barrier layer, with their thicker, low-thermal-conductivity layers, effectively block the heat generated by the RESET current from being transferred to the surrounding area. The second barrier layer 1022, with its higher thermal conductivity, quickly conducts away any excess heat. This significantly reduces the thermal disturbance experienced by adjacent memory cells, lowering the frequency of crystalline-amorphous state reversal in surrounding memory cells, significantly reducing write errors, and improving the reliability of the phase-change memory.

[0077] In some embodiments, the thermal conductivity of the second barrier layer 1022 is not less than 20 W / m·K to quickly conduct away the heat that escapes from the first barrier layer 1021. For example, the material of the second barrier layer 1022 can be selected from at least one of aluminum oxide with a thermal conductivity of approximately 30 W / m·K, magnesium oxide with a thermal conductivity of approximately 35 W / m·K, boron nitride with a thermal conductivity greater than 30 W / m·K, and aluminum nitride with a thermal conductivity greater than 100 W / m·K.

[0078] In some embodiments, the thermal conductivity of the first barrier layer 1021 is no greater than 1.5 W / m·K to minimize heat transfer from the RESET current. For example, the material of the first barrier layer 1021 can be selected from at least one of silicon oxide and silicon nitride, each having a thermal conductivity between 0.5 and 1.5 W / m·K.

[0079] Optionally, the first barrier layer 1021 may include multiple sub-barrier layers to provide better thermal insulation. For example, if the linear barrier layer 102 has a total of four sub-barrier layers in the stacking direction of the first barrier layer 1021 and the second barrier layer 1022, the three sub-barrier layers on the side closest to the memory cell 101 together constitute the first barrier layer 1021, and the outermost sub-barrier layer facing away from the memory cell 101 constitutes the second barrier layer 1022.

[0080] In some embodiments, the electrical conductivity of the second barrier layer 1022 and / or the electrical conductivity of the first barrier layer 1021 is no greater than 1×e -11 S / m. Therefore, using a low conductivity material in the linear barrier layer 102 can avoid the first signal line 103 and the second signal line 104 being directly connected to each other and causing a short circuit, thereby improving the reliability of the phase change memory. For example, the material of the first barrier layer 1021 can be selected from a material with a conductivity of about 1×e -14 S / m of silicon oxide and silicon nitride; the material of the second barrier layer 1022 can be selected from the conductivity of about 1 × e -12 S / m of aluminum oxide, conductivity less than 1×e -12 S / m of magnesium oxide, the conductivity is about 1×e -14 S / m of boron nitride and a conductivity of about 1×e -13 At least one of S / m of aluminum nitride.

[0081] Optionally, the preparation process of the linear blocking layer 102 can be selected from at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), ion-assisted pulsed laser deposition (IA-PLD) and ion beam deposition (IBD).

[0082] Taking the example of selecting boron nitride as the material for the second barrier layer 1022 and using a CVD method to form the second barrier layer 1022, gaseous raw materials containing boron and nitrogen can be introduced into the reaction chamber of the CVD equipment via a carrier gas. Under high temperature conditions, a chemical reaction occurs between the gaseous raw materials to produce boron nitride. The boron nitride is then deposited on the side of the first barrier layer 1021 facing away from the memory cell 101, forming the second barrier layer 1022. The gaseous raw material containing boron can be any boron-containing compound such as boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), and diborane (B2H6); the gaseous raw material containing nitrogen can be any nitrogen-containing gas such as ammonia (NH3) and nitrogen (N2).

[0083] Taking boron nitride as the material of the second barrier layer 1022 and using PVD to prepare the second barrier layer 1022 as an example, a boron nitride target can be used and sputtered in a nitrogen atmosphere to form the second barrier layer 1022 on the side of the first barrier layer 1021 away from the storage unit 101.

[0084] As an example, the phase change memory in each embodiment of the present application may be a three-dimensional stacked phase change memory, wherein, for example Figure 1 The storage unit 101 , the linear barrier layer 102 , the first signal line 103 and the second signal line 104 shown in the figure form a one-layer storage structure. The multi-layer storage structure is stacked in sequence along the arrangement direction of the first signal line 103 and the storage unit 101 .

[0085] For example, Figure 10 As shown, the figure is a structural diagram of a three-dimensional stacked phase change memory provided in an embodiment of the present application. The three-dimensional stacked phase change memory has a two-layer storage structure, and the two-layer storage structure is stacked in a vertical direction to form a three-dimensional stacked phase change memory.

[0086] For example, Figure 11 As shown, this figure is a structural diagram of another three-dimensional stacked phase change memory provided in an embodiment of the present application. The three-dimensional stacked phase change memory has a four-layer storage structure, and the four-layer storage structure is stacked in sequence in the vertical direction to form a three-dimensional stacked phase change memory.

[0087] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. Those of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0088] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A phase change memory, characterized in that: The phase change memory comprises: a memory unit, a linear barrier layer, a first signal line and a second signal line; The first signal line is located at a first side of the storage unit, and the second signal line is located at a second side of the storage unit; The linear barrier layer covers the sidewalls of the memory cell, and the sidewalls of the memory cell are perpendicular to the first signal line and the second signal line; The linear barrier layer includes a first barrier layer contacting the sidewall of the memory cell and a second barrier layer away from the sidewall of the memory cell; the thermal conductivity of the second barrier layer is higher than that of the first barrier layer.

2. The phase change memory according to claim 1, wherein: There are multiple intermediate barrier layers between the first barrier layer and the second barrier layer; the thermal conductivity of the second barrier layer is higher than that of the intermediate barrier layer.

3. The phase change memory according to claim 2, wherein: The plurality of intermediate barrier layers include a first intermediate barrier layer and a second intermediate barrier layer; The first barrier layer at least covers the top electrode and the phase change memory layer in the memory cell and is connected to the first signal line; The first intermediate barrier layer covers the first barrier layer and is connected to the first signal line; The second intermediate barrier layer covers the first intermediate barrier layer and the exposed sidewalls of the memory cell, and is perpendicular to and connected to the first signal line and the second signal line; The second barrier layer covers the second intermediate barrier layer and is perpendicular to and connected to the first signal line and the second signal line.

4. The phase change memory according to claim 3, wherein: The side of the first intermediate barrier layer facing away from the first signal line is flush with the side of the gating layer in the memory unit close to the first signal line.

5. The phase change memory according to claim 1, wherein: The second barrier layer is parallel to an extending direction of the first signal line.

6. The phase change memory according to claim 1, wherein: The second barrier layer includes a first sub-barrier layer and a second sub-barrier layer; The first sub-blocking layer is parallel to an extending direction of the first signal line; and the second sub-blocking layer is parallel to an extending direction of the second signal line.

7. The phase change memory according to claim 1, wherein: The material of the second barrier layer is selected from any one of boron nitride, aluminum nitride, aluminum oxide and magnesium oxide.

8. The phase change memory according to claim 1, wherein: The thermal conductivity of the second barrier layer is not less than 20 W / m·K.

9. The phase change memory according to claim 1, wherein: The thermal conductivity of the first barrier layer is no higher than 1.5 W / m·K.

10. The phase change memory according to claim 1, wherein: The electrical conductivity of the second barrier layer is not higher than 1×e -11 S / m.

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