Gate structure forming method

Abstract

The embodiment of the invention provides a gate structure forming method, which comprises the following steps of: providing a semiconductor substrate which comprises a first region and a second region; forming a polycrystalline silicon layer on the semiconductor substrate; etching the polycrystalline silicon layer in a mixed gas atmosphere of oxygen, sulfur hexafluoride and carbon tetrafluoride to obtain a gate structure, and obtaining a gaseous intermediate product silicon oxyfluoride in the etching process; wherein the density of the gate structure of the first region is greater than that of the gate structure of the second region. By adopting the technical scheme, the polycrystalline silicon etching rate of a region with small grid structure distribution density and a region with large grid structure distribution density can be balanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a gate structure. Background Art

[0002] During the polysilicon gate etching process, the main etching of the polysilicon gate using a hard mask causes differences in the polysilicon etching rate due to the different densities of the gate structure distribution, resulting in different product stripping states. That is, the polysilicon etching rate in areas with a low gate structure distribution density is higher than the polysilicon etching rate in areas with a high gate structure distribution density. This can lead to polysilicon residue in dense areas (areas with high gate structure density), poor polysilicon bottom morphology in isolated areas (areas with low gate structure density), and / or exposure of the silicon substrate in isolated areas (areas with low gate structure density).

[0003] Therefore, how to provide a technical solution to balance the polysilicon etching rate in the area with a low gate structure distribution density and the area with a high gate structure distribution density has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In view of this, an embodiment of the present invention provides a method for forming a gate structure, which can balance the polysilicon etching rate in an area with a low gate structure distribution density and an area with a high gate structure distribution density.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a gate structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region; forming a polysilicon layer on the semiconductor substrate; etching the polysilicon layer in a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride to obtain a gate structure, and obtaining a gaseous intermediate product, silicon oxyfluoride, during the etching process; wherein the density of the gate structure in the first region is greater than the density of the gate structure in the second region.

[0006] Optionally, waste gas is discharged from the reaction chamber by a vacuum pump; wherein the waste gas includes unreacted mixed gas and the intermediate product silicon oxyfluoride, and the mixed gas injection and the exhaust gas are carried out simultaneously to maintain a stable reaction environment in the reaction chamber.

[0007] Optionally, the molar ratio of oxygen, sulfur hexafluoride and carbon tetrafluoride in the mixed gas is 1:1:10 to 1:1:15.

[0008] Optionally, the step of forming a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride includes: injecting the oxygen, sulfur hexafluoride, and carbon tetrafluoride into a mixed gas chamber and fully mixing them into the mixed gas; and injecting the mixed gas in the mixed gas chamber into the reaction chamber.

[0009] Optionally, the step of forming a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride further includes one or more of the following: injecting the oxygen, sulfur hexafluoride, and carbon tetrafluoride into a reaction chamber to form the mixed gas; applying radio frequency energy through a radio frequency electrode and / or radio frequency coil in the reaction chamber to ionize the mixed gas to form a plasma, wherein the process of etching the polysilicon layer is a plasma etching process; the gas flow rate ranges of the oxygen, sulfur hexafluoride, and carbon tetrafluoride injected into the reaction chamber are [10 sccm, 15 sccm], [10 sccm, 15 sccm], and [100 sccm, 150 sccm], respectively.

[0010] Optionally, the power of the radio frequency electrode and / or radio frequency coil is selected from 400 to 800W.

[0011] Optionally, the step of forming a polysilicon layer on the semiconductor substrate includes: forming a gate oxide layer by thermal oxidation, wherein the gate oxide layer covers the surface of the semiconductor substrate; forming a polysilicon layer by chemical vapor deposition, wherein the polysilicon layer covers the gate oxide layer;

[0012] Optionally, the step of forming a polysilicon layer on the semiconductor substrate includes: forming a gate oxide layer by thermal oxidation, wherein the gate oxide layer covers the surface of the semiconductor substrate; forming a polysilicon layer by chemical vapor deposition, wherein the polysilicon layer covers the gate oxide layer; forming a hard mask layer by plasma enhanced chemical vapor deposition, wherein the hard mask layer covers the polysilicon layer; forming a gate pattern by coating photoresist, exposing and developing; transferring the gate pattern from the photoresist to the hard mask layer by dry etching; wherein, in the step of etching the polysilicon layer, the hard mask layer serves as a protective layer.

[0013] Optionally, the hard mask layer is made of amorphous carbon.

[0014] Optionally, the gate structure has sidewalls, and the sidewalls are perpendicular to the surface of the semiconductor substrate; wherein the carbon tetrafluoride forms a passivation layer on the sidewalls of the gate structure.

[0015] Optionally, when a mixed gas of oxygen, sulfur hexafluoride and carbon tetrafluoride is provided, the gas pressure in the reaction chamber is 3 to 5 mTorr; and / or, when a mixed gas of oxygen, sulfur hexafluoride and carbon tetrafluoride is provided, the temperature in the reaction chamber is 45 to 90 degrees Celsius.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0017] In the gate structure formation method provided by an embodiment of the present invention, the polysilicon layer is etched in a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride to form the gate structure. Oxygen reacts with the polysilicon layer to form silicon dioxide, which forms a sidewall passivation layer, inhibiting lateral etching and balancing the polysilicon etch rate in areas with different gate structure distribution densities. Sulfur hexafluoride and carbon tetrafluoride provide a large amount of fluorine to etch the polysilicon layer, and carbon tetrafluoride reacts with the polysilicon layer to form a fluorocarbon polymer, further improving the sidewall morphology of the gate structure. Therefore, the method can balance the polysilicon etch rate in areas with low gate structure distribution density and areas with high gate structure distribution density. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the invention of this specification, the following briefly introduces the drawings required for use in the embodiments of the invention of this specification or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 The present invention is a schematic diagram of a device cross-sectional structure of a gate structure forming method;

[0020] Figure 2 is a schematic diagram of a device cross-sectional structure of another gate structure forming method;

[0021] Figure 3 It is a schematic diagram of a device cross-sectional structure of another method for forming a gate structure;

[0022] Figure 4 is a schematic flow chart of a method for forming a gate structure according to an embodiment of the present invention;

[0023] Figures 5 to 8 It is a schematic diagram of the device cross-sectional structure disclosed in each step of a gate structure forming method in an embodiment of the present invention.

[0024] Description of reference numerals:

[0025] Figures 1 to 3 Middle: semiconductor substrate 100, gate oxide layer 110, gate structure 120, polysilicon residue 121, side over-etched region 122, bottom over-etched region 123, sidewall 124, hard mask layer 130, dense region 141, isolated region 142;

[0026] Figures 5 to 8 Middle: semiconductor substrate 200 , gate oxide layer 210 , polysilicon layer 220 , gate structure 221 , sidewalls 224 , hard mask layer 230 , first region 241 , and second region 242 . DETAILED DESCRIPTION

[0027] The technical solutions of the present invention are described in detail below in conjunction with specific embodiments and the accompanying drawings. The embodiments described herein are specific embodiments of the present invention and are used to illustrate the concept of the present invention. These descriptions are all illustrative and exemplary and should not be construed as limiting the embodiments of the present invention and the scope of protection of the present invention. In addition to the embodiments described herein, those skilled in the art can also adopt obvious other technical solutions based on the contents disclosed in the claims of this application and the specification thereof, including technical solutions that adopt any obvious replacements and modifications to the embodiments described herein.

[0028] It should be noted that the drawings in this embodiment are schematic diagrams to assist in illustrating the concept of the present invention and schematically illustrate the shapes of the various components and their interrelationships. It should be understood that in order to clearly illustrate the structure of the various components of the present invention, the drawings are not drawn to the same scale, and the same reference numerals are used to represent the same parts in the drawings.

[0029] As described in the background art, during the polysilicon gate etching process, the main etching of the polysilicon gate using a hard mask can lead to differences in the polysilicon etching rate due to the different densities of the gate structure distribution, resulting in differences in the state of product stripping. That is, the polysilicon etching rate in areas with a low gate structure distribution density is higher than the polysilicon etching rate in areas with a high gate structure distribution density. This can result in polysilicon residue in dense areas (areas with high gate structure density), poor polysilicon bottom morphology in isolated areas (areas with low gate structure density), and / or exposure of the silicon substrate in isolated areas (areas with low gate structure density).

[0030] See also Figure 1 , Figure 1 The present invention is a schematic diagram of a device cross-sectional structure of a gate structure forming method.

[0031] As shown in the figure, a semiconductor substrate 100 is covered with a gate oxide layer 110, on which a gate structure 120 is formed. The gate structure 120 is obtained by etching according to the pattern of the hard mask layer 130 formed on the gate structure 120. The distribution density of the gate structures 120 in the dense area 141 is greater than the distribution density of the gate structures 120 in the isolated area 142. Therefore, the polysilicon etching rates of the dense area 141 and the isolated area 142 differ due to the different states of product stripping, that is, the polysilicon etching rate of the isolated area 142 is greater than the etching rate of the dense area 141. As a result, when the etching of the polysilicon gate structure in the isolated area 142 is completed, polysilicon residues 121 are still present between the gate structures 120 in the dense area 141.

[0032] See also Figure 2 , Figure 2 This is a schematic diagram of a device cross-section structure for another gate structure formation method. As shown, the distribution density of gate structures 120 in dense region 141 is greater than that in isolated region 142. Therefore, due to the different states of product stripping, the polysilicon etching rates in dense region 141 and isolated region 142 differ, i.e., the polysilicon etching rate in isolated region 142 is greater than that in dense region 141. As a result, when the polysilicon gate structure etching in dense region 141 is completed, the sidewalls 124 of the gate structure 120 in isolated region 142 have been overetched, resulting in side overetched regions 122.

[0033] See also Figure 3 , Figure 3 This is a schematic diagram of a device cross-section structure for another gate structure formation method. As shown, the distribution density of gate structures 120 in dense region 141 is greater than that in isolated region 142. Therefore, due to the different states of product stripping, the polysilicon etching rates in dense region 141 and isolated region 142 differ, i.e., the polysilicon etching rate in isolated region 142 is greater than that in dense region 141. As a result, when the polysilicon gate structure in dense region 141 is completely etched, the areas between the gate structures 120 in isolated region 142 are over-etched, forming a bottom over-etched region 123 that exposes the surface of semiconductor substrate 100.

[0034] After analyzing the cause of this phenomenon, the inventors discovered that during the patterning of the polysilicon layer, the layout structure is fixed, causing the resulting gate pattern to follow the layout structure. However, when the layout structure has dense and sparse areas, under the same environment, the gate structures in the dense and sparse areas will differ significantly.

[0035] To address the aforementioned technical issues, an embodiment of the present invention provides a method for forming a gate structure, wherein the polysilicon layer is etched in a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride to obtain the gate structure. Oxygen reacts with the polysilicon layer to form silicon dioxide, which forms a sidewall passivation layer, inhibiting lateral etching and balancing the polysilicon etch rate in regions with different gate structure distribution densities. Sulfur hexafluoride and carbon tetrafluoride provide a large amount of fluorine to etch the polysilicon layer, and carbon tetrafluoride reacts with the polysilicon layer to form a fluorocarbon polymer, further improving the sidewall morphology of the gate structure. Therefore, the method can balance the polysilicon etch rate in regions with low gate structure distribution density and those with high gate structure distribution density.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is described clearly and completely below with reference to the accompanying drawings.

[0037] See also Figure 4 , Figure 4 FIG4 is a flow chart of a method for forming a gate structure according to an embodiment of the present invention. The method may perform steps S41 to S43, each of which is described below.

[0038] In step S41 , a semiconductor substrate is provided, wherein the semiconductor substrate includes a first region and a second region.

[0039] In step S42 , a polysilicon layer is formed on the semiconductor substrate.

[0040] In step S43, the polysilicon layer is etched in a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride to obtain a gate structure, and a gaseous intermediate product, silicon oxyfluoride, is obtained during the etching process.

[0041] In this embodiment of the present invention, oxygen reacts with the polysilicon layer to form silicon dioxide, forming a sidewall passivation layer that inhibits lateral etching and balances the polysilicon etch rate in areas with different gate structure density distributions. Sulfur hexafluoride and carbon tetrafluoride provide a large amount of fluorine to etch the polysilicon layer, and carbon tetrafluoride reacts with the polysilicon layer to form a fluorocarbon polymer, further improving the sidewall morphology of the gate structure. Therefore, the method can balance the polysilicon etch rate in areas with low gate structure density and areas with high gate structure density.

[0042] The following combination Figures 5 to 8 , the above method is explained.

[0043] Figures 5 to 8 It is a schematic diagram of the device cross-sectional structure disclosed in each step of a gate structure forming method in an embodiment of the present invention.

[0044] See also Figure 5 , providing a semiconductor substrate 200 , wherein the semiconductor substrate 200 includes a first region 241 and a second region 242 , and forming a gate oxide layer 210 on the semiconductor substrate 200 .

[0045] The semiconductor substrate 200 may provide a process operation basis for a semiconductor structure formation process.

[0046] The semiconductor structure may include a memory cell, such as a static random access memory (SRAM). In some other embodiments, the semiconductor structure may also include other types of memory cells.

[0047] In this embodiment, the material of the semiconductor substrate 200 is silicon. In other embodiments, the semiconductor substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy to integrate.

[0048] The semiconductor substrate may also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), or a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate on which an epitaxial layer is grown.

[0049] Specifically, the semiconductor substrate 200 is divided into two regions based on the density of the gate structures to be formed subsequently, namely a first region 241 and a second region 242. The density of the gate structures in the first region 241 is greater than the density of the gate structures in the second region 242, that is, the gate structures in the first region 241 are denser than the gate structures in the second region 242.

[0050] It should be noted that the first region 241 and the second region 242 are not necessarily located on the same semiconductor device. The first region 241 and the second region 242 can be manually selected to compare and detect the morphological features of the gate structure subsequently formed in the first region 241 and the second region 242 to determine whether the entire wafer is qualified or the qualified rate of the entire wafer.

[0051] The gate oxide layer 210 prevents direct contact between the gate and the channel, preventing current leakage. By applying a gate voltage, the channel carrier concentration (electrons or holes) can be regulated to form a conductive path. The gate oxide layer 210 also has high dielectric strength (voltage resistance) to prevent breakdown, and low leakage current to reduce power consumption.

[0052] In this embodiment, the gate oxide layer 210 is formed by thermal oxidation, that is, the silicon substrate is placed in a high temperature (about 800-1200° C.) oxidizing atmosphere (such as oxygen or water vapor), and silicon reacts with the oxidant to generate silicon dioxide.

[0053] In some other embodiments, the gate oxide layer 210 is formed by atomic layer deposition or physical vapor deposition.

[0054] In some embodiments, the gate oxide layer 210 may be made of one or more of hafnium dioxide, aluminum oxide, and lanthanum oxide.

[0055] Reference Figure 6 The step of forming a polysilicon layer 220 on the semiconductor substrate 200 further includes: forming a polysilicon layer 220 , wherein the polysilicon layer 220 covers the gate oxide layer 210 .

[0056] In some embodiments, the polysilicon layer 220 may be formed by chemical vapor deposition.

[0057] In one specific embodiment, low-pressure chemical vapor deposition (LPCVD) can be used to decompose silane (SiH4) or disilane (Si2H6) at low pressure (0.1-10 Torr) and high temperature (550-650°C) to deposit polysilicon. Specifically, silane or disilane generates silicon and hydrogen at high temperature and low pressure. The polysilicon layer 220 obtained using this method has good film uniformity and high purity, making it suitable for the production of gate polysilicon layers.

[0058] In another specific embodiment, a plasma-enhanced chemical vapor deposition method can also be used, with a temperature range of (200-400°C), silane and hydrogen are mixed, and a plasma-excited reaction is performed. This method is suitable for complex structures, and the polysilicon layer 220 thin film obtained by this method has greater stress and higher resistivity than the polysilicon layer 220 obtained by the low-pressure chemical vapor deposition method.

[0059] See also Figures 6 to 8 , showing the step of etching the polysilicon layer 220 to obtain the gate structure 221.

[0060] See also Figure 6 , a hard mask layer 230 is formed on the polysilicon layer 220 , and the hard mask layer 230 covers the polysilicon layer 220 .

[0061] In this embodiment, the hard mask layer 230 is formed by plasma enhanced chemical vapor deposition.

[0062] The hard mask layer 230 is used in semiconductor manufacturing to replace or enhance traditional photoresist, provide higher etching resistance and pattern fidelity, protect the underlying material during the etching process, and ensure the precise transfer of nanometer-scale patterns defined by lithography, which is especially indispensable in advanced processes and high aspect ratio structures.

[0063] In this embodiment, amorphous carbon is used as the material of the hard mask layer 230 .

[0064] Specifically, the plasma-enhanced chemical vapor deposition method is used to crack hydrocarbon gases (such as CH4, C2H2) at high temperatures (600–1000°C) to generate carbon deposits, or decompose them in Ar / H2 plasma.

[0065] In some embodiments, a liquid carbon material is spin-coated into a film by spin-coating carbon, and then cured at a low temperature (<200° C.) to form the hard mask layer 230 .

[0066] In some embodiments, the material of the hard mask layer 230 is selected from silicon nitride, silicon oxide (SiO2), titanium nitride, and tantalum nitride, and the hard mask layer 230 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0067] In addition, after the hard mask layer 230 is formed, a photoresist is coated on the hard mask layer 230 .

[0068] Specifically, a photoresist is coated on the hard mask layer 230 , and then exposed and developed to form a gate pattern. The gate pattern has different pattern densities in the first region and the second region.

[0069] Next, see Figure 7 , the gate pattern is transferred from the photoresist to the hard mask layer 230 by dry etching to form a patterned hard mask layer 230.

[0070] In other words, during the manufacturing process of the semiconductor device, the formation of the gate pattern on the hard mask layer 230 needs to be achieved through a precise photolithography process.

[0071] First, a layer of positive or negative photoresist is evenly coated on the surface of the hard mask layer 230 using a spin coating or spray coating process. The thickness of the photoresist is controlled within the range of 100-500 nanometers based on the critical dimensions of the target gate pattern. A soft bake process (e.g., hot plate baking at 90-120°C for 60-180 seconds) is then performed to remove solvents and enhance adhesion between the photoresist and the hard mask layer 230. The coated wafer is then transferred to an exposure machine for pattern exposure under a light source of a specific wavelength (e.g., EUV 13.5nm, KrF excimer laser 248nm, or i-line 365nm). By precisely controlling the exposure dose (e.g., 50-500mJ / cm2) and the mask alignment accuracy, the photoresist undergoes chemical crosslinking or decomposition, forming a latent image structure corresponding to the target gate pattern. The exposed photoresist is then developed using a developer (such as an aqueous sodium hydroxide solution or a tetramethylammonium hydroxide solution). The pattern development is achieved by adjusting the developer concentration (0.1%-5%) and the immersion time (30-120 seconds). The photoresist in the unexposed area is selectively removed, thereby forming a three-dimensional gate pattern with vertical sidewalls on the surface of the hard mask layer 230. Finally, the photoresist pattern is transferred to the hard mask layer 230 through a dry etching process (such as reactive ion etching (RIE) or high-density plasma (HDP) etching), wherein a mixed plasma of a fluorine-based gas (such as CF4, SF6) and an inert gas (such as Ar, He) is used to perform anisotropic etching under conditions of a radio frequency power of 200-1000W and a chamber pressure of 1-100mTorr. By optimizing the etching rate ratio (etching selectivity ratio of the hard mask layer to the photoresist >100:1) and endpoint detection (such as OES real-time monitoring of the fluorine-based composite ion concentration), high-fidelity transfer of the photoresist pattern is ensured while avoiding damage to the underlying polysilicon layer 220. Finally, a gate structure hard mask pattern with nanometer-level precision is formed, providing a precise process template for the subsequent etching of the polysilicon layer 220.

[0072] See also Figure 8 , using the hard mask layer 230 as a mask, the polysilicon layer 220 is etched to obtain the gate structure 221.

[0073] In other words, in the step of etching the polysilicon layer 220 , the hard mask layer 230 is used as a mask.

[0074] In some embodiments, a dry etching method may be used to etch the polysilicon layer 220 to obtain the gate structure 221 , and then exhaust gas is exhausted from the reaction chamber through a vacuum pump.

[0075] In addition, the exhaust gas includes the unreacted mixed gas and the intermediate product silicon oxyfluoride.

[0076] In some embodiments, the injection of the mixed gas and the exhaust of the waste gas are performed simultaneously to maintain a stable reaction environment in the reaction chamber.

[0077] In some embodiments, after the mixed gas is injected into the reaction chamber and fully reacts with the polysilicon layer 220 , the waste gas is discharged.

[0078] Specifically, the mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride is injected into the reaction chamber for etching the gate structure under a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride. In other words, the mixed gas is formed by injecting the oxygen, sulfur hexafluoride, and carbon tetrafluoride into the reaction chamber.

[0079] In some embodiments, the molar ratio of oxygen, sulfur hexafluoride, and carbon tetrafluoride in the mixed gas is 1:1:10 to 1:1:15.

[0080] In some other embodiments, the volume ratio of oxygen, sulfur hexafluoride, and carbon tetrafluoride in the mixed gas is 1:1:10 to 1:1:15.

[0081] It is understood that under the conditions of the same pressure and temperature, the molar ratio and volume ratio of each gas in the mixed gas can be consistent.

[0082] In other embodiments, the gas flow rates of oxygen, sulfur hexafluoride, and carbon tetrafluoride injected into the reaction chamber are in the ranges of [10 sccm, 15 sccm], [10 sccm, 15 sccm], and [100 sccm, 150 sccm], respectively.

[0083] In a specific embodiment, the gas flow rates of oxygen, sulfur hexafluoride, and carbon tetrafluoride injected into the reaction chamber are 10 sccm, 10 sccm, and 150 sccm, respectively, to maximize the flow rate of carbon tetrafluoride and further enhance the protective property of carbon tetrafluoride.

[0084] Specifically, by setting an appropriate gas flow range to control the amount of injected gas, the feasibility and controllability of actual production can be improved and management costs can be reduced.

[0085] By adding oxygen to the mixed gas, the polysilicon etching rates of the first region 241 and the second region 242 can be balanced, and a passivation layer (silicon oxide) can be formed on the sidewalls 224 of the gate structure 221. In addition, using a large amount of carbon tetrafluoride can also produce fluorocarbon polymers, etc., to form a passivation layer on the sidewalls 224 of the gate structure 221 to protect the sidewall morphology.

[0086] In some embodiments, the oxygen, sulfur hexafluoride, and carbon tetrafluoride are first mixed before being injected into the reaction chamber. Specifically, the oxygen, sulfur hexafluoride, and carbon tetrafluoride are injected into a mixed gas chamber. Specifically, the oxygen, sulfur hexafluoride, and carbon tetrafluoride are first injected into the mixed gas chamber in a predetermined ratio and thoroughly mixed to form a mixed gas. The mixed gas in the mixed gas chamber is then injected into the reaction chamber.

[0087] When a mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride is provided, the gas pressure in the reaction chamber is 3-5 mTorr.

[0088] When a mixed gas of oxygen, sulfur hexafluoride and carbon tetrafluoride is provided, the temperature in the reaction chamber is 45 to 90 degrees Celsius.

[0089] In some embodiments, the gate structure 221 of the polysilicon layer 220 is etched using a purely chemical mechanism.

[0090] Specifically, the etching gas enters the reaction chamber, that is, the mixed gas is injected into the reaction chamber, and the mixed gas is not excited by the electric field and exists directly in the form of molecules. The gas molecules (or after thermal decomposition or natural dissociation) contact the surface of the polysilicon and erode the silicon atoms through chemical reactions. Part of the silicon reacts with fluorine free radicals to generate volatile SiF4, and the waste gas is discharged from the reaction chamber through a vacuum pump. Due to the addition of oxygen, part of the silicon obtains a gaseous intermediate product, silicon oxyfluoride, during the etching process in a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride. In the subsequent process, it is extracted from the reaction chamber or further forms silicon oxide (SiO2). Silicon oxide (SiO2) can form a passivation layer on the side wall 224 of the gate structure 221 to protect the side wall morphology. After SiF4 and other gaseous by-products are extracted by the vacuum system, the reaction chamber is purged with an inert gas and then restored to normal pressure.

[0091] In some embodiments, the polysilicon layer 220 is etched using a plasma etching process.

[0092] Specifically, radio frequency energy is applied through radio frequency electrodes and / or radio frequency coils in the reaction chamber to ionize the mixed gas to form plasma. The power of the radio frequency electrodes and / or radio frequency coils is selected from 400 to 800W.

[0093] In other words, the etching gas enters the reaction chamber, that is, the mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride is injected into the reaction chamber. The mixed gas is decomposed by an electric field, and the electric field accelerates the electrons to collide with the gas molecules to generate plasma. Under the acceleration of the electric field, the plasma vertically bombards the surface of the polysilicon layer 220, removes the passivation layer and strips off atoms. The whole process is a chemical-physical synergistic reaction. Through fluorine radical chemical corrosion, the fluorine radicals react with silicon to generate volatile products such as silicon fluoride SiF4; the surface of the polysilicon layer 220 is bombarded by physical sputtering plasma to enhance anisotropy and form vertical sidewalls. The sidewalls 224 are perpendicular to the surface of the semiconductor substrate 200. Among them, the reaction products of oxygen and carbon tetrafluoride (silicon oxide, fluorocarbon polymer, etc.) can form a passivation layer on the sidewalls 224 of the gate structure 221 to protect the sidewall morphology, which is conducive to the formation of vertical sidewalls.

[0094] It can be understood that the above describes multiple embodiments of the gate structure formation method. The various optional methods introduced in each embodiment can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiments, which can all be considered as embodiments disclosed and open to the public by the present invention.

[0095] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.

[0096] The term "plurality" used in the embodiments of the present application refers to two or more.

[0097] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0098] It should be noted that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0099] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a gate structure, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region; forming a polysilicon layer on the semiconductor substrate; In an atmosphere of a mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride, etching the polysilicon layer to obtain a gate structure, and obtaining a gaseous intermediate product, silicon oxyfluoride, during the etching process; The density of the gate structure in the first region is greater than the density of the gate structure in the second region.

2. The method according to claim 1, characterized in that Also includes: Exhaust gas is discharged from the reaction chamber through a vacuum pump; The waste gas includes the unreacted mixed gas and the intermediate product silicon oxyfluoride, and the injection of the mixed gas and the exhaust of the waste gas are performed simultaneously to maintain a stable reaction environment in the reaction chamber.

3. The method according to claim 1, characterized in that The molar ratio of oxygen, sulfur hexafluoride and carbon tetrafluoride in the mixed gas is 1:1:10 to 1:1:

15.

4. The method according to claim 3, characterized in that The step of forming a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride comprises: injecting the oxygen, sulfur hexafluoride, and carbon tetrafluoride into a mixed gas chamber and fully mixing them into the mixed gas; The mixed gas in the mixed gas chamber is injected into a reaction chamber.

5. The method according to claim 1, wherein The step of forming a mixed gas atmosphere of oxygen, sulfur hexafluoride, and carbon tetrafluoride further includes one or more of the following: injecting the oxygen, sulfur hexafluoride, and carbon tetrafluoride into the reaction chamber to form the mixed gas; Applying radio frequency energy through a radio frequency electrode and / or a radio frequency coil in the reaction chamber to ionize the mixed gas to form plasma, wherein the process of etching the polysilicon layer is a plasma etching process; The gas flow rates of oxygen, sulfur hexafluoride, and carbon tetrafluoride injected into the reaction chamber are in the ranges of [10 sccm, 15 sccm], [10 sccm, 15 sccm], and [100 sccm, 150 sccm], respectively.

6. The method according to claim 5, characterized in that The power of the radio frequency electrode and / or radio frequency coil is selected from 400 to 800W.

7. The method according to claim 1, characterized in that The step of forming a polysilicon layer on the semiconductor substrate comprises: forming a gate oxide layer by thermal oxidation, wherein the gate oxide layer covers the surface of the semiconductor substrate; forming a polysilicon layer by chemical vapor deposition, wherein the polysilicon layer covers the gate oxide layer; forming a hard mask layer by plasma enhanced chemical vapor deposition, wherein the hard mask layer covers the polysilicon layer; A gate pattern is formed by coating a photoresist, exposing and developing the photoresist; Transferring the gate pattern from the photoresist to the hard mask layer by dry etching; Wherein, in the step of etching the polysilicon layer, the hard mask layer is used as a protection layer.

8. The method according to claim 7, characterized in that The material of the hard mask layer is amorphous carbon.

9. The method according to claim 1, characterized in that The gate structure has a sidewall, and the sidewall is perpendicular to the surface of the semiconductor substrate; The carbon tetrafluoride forms a passivation layer on the sidewall of the gate structure.

10. The method according to claim 1, characterized in that When a mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride is provided, the pressure in the reaction chamber is 3 to 5 mTorr; and / or, when a mixed gas of oxygen, sulfur hexafluoride, and carbon tetrafluoride is provided, the temperature in the reaction chamber is 45 to 90 degrees Celsius.

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