Integrated circuit (IC), method of manufacturing same, and method of generating integrated circuit (IC) layout

Abstract

An integrated circuit (IC), a method of manufacturing the same, and a method of generating an integrated circuit (IC) layout are provided. An integrated circuit (IC) includes a voltage source configured to generate a first voltage having a temperature dependent voltage level; and a voltage controlled oscillator (VCO) including a feedback path and a first VCO unit configured to receive the first voltage. The first VCO cell includes a series of stages, a first stage of the series of stages configured to output a first signal inside the first VCO cell based on a voltage level of a first voltage and an oscillating signal propagating on a feedback path, and a last stage of the series of stages is configured to output a second signal external to the first VCO unit based on the first signal and a voltage level of the first voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an integrated circuit (IC) and a method for manufacturing the same, as well as a method for generating an integrated circuit (IC) layout diagram. Background Art

[0002] The ongoing trend toward miniaturization of integrated circuits (ICs) has resulted in increasingly smaller devices that consume less power than previous technologies while providing more functionality at higher speeds. To monitor power consumption, ICs sometimes include circuits with characteristics that vary with power-related heat generation. Such circuits can include voltage-controlled oscillators (VCOs), in which a temperature-dependent voltage is used to control the oscillation frequency. The resulting frequency acts as a temperature sensor, which can be used to generate a temperature profile that can provide feedback on IC design and manufacturing efforts, or as a signoff tool for products built using various manufacturing processes. Summary of the Invention

[0003] In one aspect, an embodiment of the present application provides an integrated circuit (IC) comprising: a voltage source configured to generate a first voltage having a temperature-dependent voltage level; and a voltage-controlled oscillator (VCO) comprising a feedback path and a first VCO unit configured to receive the first voltage, wherein the first VCO unit comprises a series of stages, a first stage in the series of stages being configured to output a first signal inside the first VCO unit based on a voltage level of the first voltage and an oscillation signal propagating on the feedback path, and a last stage in the series of stages being configured to output a second signal outside the first VCO unit based on the first signal and the voltage level of the first voltage.

[0004] In one aspect, an embodiment of the present application provides a method of manufacturing an integrated circuit (IC), the method comprising: constructing a plurality of gate structures on a plurality of transistor features located in a semiconductor substrate, thereby forming a multi-stage voltage-controlled oscillator (VCO) cell between a first dummy gate structure and a second dummy gate structure of the plurality of gate structures; and forming an electrical connection including a feedback path and a connection from each of the plurality of stages to a temperature-dependent voltage source, thereby forming a VCO including the VCO cell; wherein forming the multi-stage VCO cell comprises: forming an array of inverters between the first dummy gate structure and the second dummy gate structure, and the array comprises a total number of rows equal to 1, 2, or 4.

[0005] In one aspect, an embodiment of the present application provides a method for generating an integrated circuit (IC) layout diagram, the method comprising: arranging a multi-stage VCO cell in the IC layout diagram, wherein the multi-stage VCO cell comprises an array of inverters located between a first dummy gate region and a second dummy gate region, and the array comprises a total number of rows equal to 1, 2, or 4; configuring electrical connections from a temperature-dependent voltage source to each stage of the VCO cell; and storing the IC layout diagram in a memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following specific implementations when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an IC according to some embodiments.

[0008] Figures 2A to 2C is a plan view of an IC layout and corresponding multi-stage voltage controlled oscillator (VCO) cell according to some embodiments.

[0009] Figures 3A to 3E is a plan view of an IC layout and corresponding VCO circuit according to some embodiments.

[0010] Figure 4 is a schematic diagram of a voltage source according to some embodiments.

[0011] Figure 5 is a schematic diagram of a VCO stage according to some embodiments.

[0012] Figure 6 is a schematic diagram of a multi-stage VCO cell according to some embodiments.

[0013] Figure 7 is a schematic diagram of a multi-stage VCO cell according to some embodiments.

[0014] Figure 8 is a schematic diagram of a multi-bit VCO cell according to some embodiments.

[0015] Figure 9 is a schematic diagram of an IC according to some embodiments.

[0016] Figure 10 is a flow chart of a method of operating an IC according to some embodiments.

[0017] Figure 11 is a flow chart of a method of manufacturing an IC according to some embodiments.

[0018] Figure 12 is a flow chart of a method for generating an IC layout diagram according to some embodiments.

[0019] Figure 13 is a block diagram of an IC layout generation system according to some embodiments.

[0020] Figure 14 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. In order to simplify the present disclosure, specific examples of components, numerical values, steps, operations, materials, arrangements, etc. are described below. Of course, these are merely examples and are not intended to be limiting. Other components, numerical values, operations, materials, arrangements, etc. may also be considered. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0023] In various embodiments, an oscillator integrated circuit (IC), layout, and method include a temperature-dependent voltage source and a voltage-controlled oscillator (VCO) comprising one or more multi-stage VCO cells and a feedback path. Each multi-stage VCO cell receives a temperature-dependent voltage, and the VCO outputs a signal having a frequency that indicates the temperature of the voltage source. Compared to approaches not based on multi-stage VCO cells, the IC can use a smaller area to output the signal while maintaining thermal linearity sensitivity.

[0024] As described below, in some embodiments, Figure 1 is a schematic diagram of an oscillator IC including a VCO, Figures 2A to 3EDepicts the IC layout and the corresponding VCO circuit plan. Figures 4 to 8 This is a schematic diagram of the VCO circuit. Figures 2A to 3E Each of the figures is a circuit / layout diagram in which reference designators represent IC features and IC layout features used in a manufacturing process (e.g., reference below). Figure 11 Method 1100 discussed and / or with reference to the following Figure 14 In some embodiments, the corresponding IC features are at least partially defined in the IC manufacturing process associated with the IC manufacturing system 1400 discussed above. Figures 2A to 3E One or more of the diagrams is referenced by executing the following Figure 12

[0066] Accordingly, some or all of the IC layout diagrams generated by some or all of the operations of the method 1200 discussed herein may be used. Figures 2A to 3E Each figure in represents an IC layout diagram and a plan view of a corresponding IC device.

[0025] Each figure in this paper (e.g. Figures 2A to 3E ) are simplified for illustrative purposes. The accompanying drawings are views of IC structures and devices with various features included and various features excluded to facilitate the following discussion. In various embodiments, except for Figures 2A to 3E In addition to the features shown, the IC structure, device and / or layout diagram includes one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures or other transistor elements, isolation structures, etc.

[0026] Figures 2A to 3E The positioning and relative sizes of the various features shown are non-limiting examples provided for illustrative purposes. In various embodiments, Figures 2A to 3E The illustrated IC layouts / circuits may include features that are otherwise positioned and / or have other dimensions within the corresponding IC layouts / circuits.

[0027] Figure 1 is a schematic diagram of an IC 100 according to some embodiments. In some embodiments, IC 100 is referred to as an oscillator circuit 100 , a temperature sensor 100 , a thermal loop 100 , or a VCO circuit 100 .

[0028] IC 100 includes a voltage source 110, a switching circuit 120, VCO cells 130-1 to 130-N (collectively referred to as VCO cells 130), buffers 140 and 150, and a frequency measurement circuit 160. In some embodiments, as Figure 1As shown, the voltage source 110 is referred to as TDCELL 110 , the switching circuit 120 is referred to as CKND2 120 , the VCO cells 130 - 1 to 130 -N are referred to as VCODEL 130 - 1 to 130 -N, and / or the buffers 140 and 150 are referred to as CKB 140 and 150 .

[0029] Each of the voltage source 110 and the switching circuit 120 is configured to receive an enable signal EN from an external circuit (not shown) (e.g., a control circuit) at a signal node ENN. The feedback path FDBK is configured to propagate the oscillation signal OSC from the output terminal (not labeled) of the VCO unit 130-N to the input terminal (not labeled) of the VCO unit 130-1, and the feedback path FDBK is included in Figure 1 Switching circuit 120 in the illustrated embodiment. In some embodiments, IC 100 and feedback path FDBK do not include switching circuit 120, but rather feedback path FDBK is configured to directly couple the output terminal of VCO cell 130-N to the input terminal of VCO cell 130-1.

[0030] exist Figure 1 In the illustrated embodiment, buffers 140 and 150 are coupled in series between the output terminal of VCO cell 130-N and frequency measurement circuit 160, thereby being configured to output signal FOUT to frequency measurement circuit 160 at output node OUT. In some embodiments, IC 100 does not include buffers 140 and 150, but rather feedback path FDBK is directly coupled to output node OUT, thereby being configured to output oscillation signal OSC as signal FOUT at output node OUT. In some embodiments, IC 100 does not include one of buffers 140 or 150, or includes one or more buffers (not shown) in addition to buffers 140 and 150, thereby being configured to output signal FOUT at output node OUT.

[0031] In some embodiments, VCO cell 130 and feedback path FDBK (including switching circuit 120 if present) and buffers 140 and 150 (if present) are referred to as a VCO that is configured to output a signal FOUT in response to voltage VCTL received on voltage node VCTLN.

[0032] The voltage source 110 (also referred to as a temperature-dependent (TD) voltage source 110 in some embodiments) is an electronic circuit configured to output a voltage VCTL having a predefined voltage level or a temperature-dependent voltage level on a voltage node VCTLN in response to an enable signal EN.

[0033] The enable signal EN is configured to have a first logic level (e.g., a high logic level) and a second logic level (e.g., a low logic level), wherein the first logic level is configured to cause the voltage source 110 to output the voltage VCTL having a temperature-dependent voltage level, and the second logic level is configured to cause the voltage source 110 to output the voltage VCTL having a predetermined voltage level, which is one of the first logic level or the second logic level (e.g., a low logic level).

[0034] In some embodiments, the low logic level is a voltage level within a predetermined range of a reference voltage of IC 100 (e.g., reference voltage VSS discussed below), and the high logic level is a voltage level within a predetermined range of a power supply voltage of IC 100 (e.g., power supply voltage VDD discussed below).

[0035] In some embodiments, the voltage source 110 is configured to output the voltage VCTL having a temperature-dependent voltage level that is configured to increase as a function of increasing temperature. In some embodiments, the voltage source 110 is configured to output the voltage VCTL having a temperature-dependent voltage level that is configured to decrease as a function of increasing temperature.

[0036] In some embodiments, the voltage source 110 includes the following reference Figure 4 The voltage source 400 is discussed.

[0037] In some embodiments, IC 100 does not include voltage source 110, but instead includes one or more VCO cells 130 (e.g., as described below). Figure 9 The VCO unit 130 - 1 of the IC 900 discussed herein includes a voltage source component configured to output a voltage VCTL in response to an enable signal EN discussed herein.

[0038] The switching circuit 120 is an electronic circuit configured to, in response to the enable signal EN, connect the output terminal of the VCO cell 130-N to the input terminal of the VCO cell 130-1 when the voltage source 110 is configured to output the voltage VCTL having the temperature-dependent voltage level, and disconnect the output terminal of the VCO cell 130-N from the input terminal of the VCO cell 130-1 when the voltage source 110 is configured to output the voltage VCTL having the predetermined voltage level.

[0039] The VCO unit 130 includes a total of N VCO units 130-1 to 130-N. Each of the VCO units 130-1 to 130-N is an electronic circuit including a plurality of stages ( Figure 1(not shown in FIG), each stage is configured to receive a voltage VCTL on a voltage node VCTLN and perform a signal delay in response to a voltage level of the voltage VCTL.

[0040] In some embodiments, the signal delay performed by a given stage of instances of VCO cells 130-1 through 130-N is configured to decrease as a function of increasing voltage levels of voltage VCTL, thereby increasing the propagation speed. In some embodiments, the signal delay performed by a given stage of instances of VCO cells 130-1 through 130-N is configured to increase as a function of increasing voltage levels of voltage VCTL, thereby decreasing the propagation speed.

[0041] Each stage of the instances of the VCO cells 130-1 to 130-N is configured to receive a first signal (e.g., signal OSC on feedback path FDBK, an internal signal output from another stage of the same instance of the VCO cells 130-1 to 130-N, or an external signal output from another stage of another instance of the VCO cells 130-1 to 130-N) and output a second signal (e.g., signal OSC on feedback path FDBK, an internal signal to another stage of the same instance of the VCO cells 130-1 to 130-N, or an external signal to another stage of another instance of the VCO cells 130-1 to 130-N) in response to the first signal and a voltage level of voltage VCTL.

[0042] In various embodiments, one or more instances of VCO cells 130-1 to 130-N include one of the following: Figures 2A to 2C The VCO units 200A to 200C discussed below refer to Figures 3A to 3E The VCO units 300A to 300C discussed below refer to Figure 6 The VCO unit 600 discussed below refers to Figure 7 The VCO unit 700 discussed below refers to Figure 8 The VCO unit 800 is discussed.

[0043] As the total number N of VCO cells 130 increases, the area occupied by VCO cells 130 increases, thereby increasing the total area occupied by IC 100. In some embodiments, IC 100 includes VCO cells 130 with a number N less than or equal to 10. In some embodiments, IC 100 includes VCO cells 130 with a number N equal to 1, 2, 3, 4, 5, 6, or 7.

[0044] The series arrangement of buffers 140 and 150 is configured to receive an oscillating signal OSC from a feedback path FDBK and output a signal FOUT on an output node OUT. In various embodiments, buffers 140 and 150 are configured to output a signal FOUT that is phase-matched or complementary to the oscillating signal OSC.

[0045] A buffer (e.g., buffer 140 and / or 150) is an electronic circuit that includes an input terminal (not labeled) configured to have a high input impedance to minimize loading on adjacent circuits (e.g., the output terminal of VCO cell 130-N or buffer 140) and an output terminal (not labeled) configured to have a low output impedance to enable driving adjacent circuits (e.g., frequency measurement circuit 160 or buffer 150). In some embodiments, the buffer includes an inverter.

[0046] The frequency measurement circuit 160 is an electronic circuit configured to receive the signal FOUT, detect the frequency of the signal FOUT, and generate an output signal (not shown) indicating the frequency. In some embodiments, the frequency measurement circuit 160 includes a frequency counter.

[0047] In some embodiments, IC 100 does not include frequency measurement circuit 160, and buffers 140 and 150 are configured to output signal FOUT to a circuit (not shown) external to IC 100. In some embodiments, IC 100 does not include frequency measurement circuit 160 or buffers 140 and 150, and feedback path FDBK (e.g., switching circuit 120) is configured to output oscillation signal OSC to a circuit (not shown) external to IC 100.

[0048] Through the above configuration, IC 100 includes a temperature-dependent voltage source 110 and a VCO including one or more multi-stage VCO cells 130-1 to 130-N and a feedback path FDBK, and each of VCO cells 130-1 to 130-N receives a temperature-dependent voltage VCTL, so that the VCO outputs a signal OSC or FOUT having a frequency indicating the temperature of voltage source 110. Compared to a method not based on multi-stage VCO cells, IC 100 is thus able to use a smaller area to output signal OSC or FOUT while maintaining thermal linear sensitivity.

[0049] Figures 2A to 2C 200A-200C and corresponding multi-stage VCO cells 200A-200C according to some embodiments. Each of the IC layouts / cells 200A-200C may be used as a reference for the above Figure 1 One or more of the VCO cells 130-1 to 130-N in question.

[0050] Each of the IC layouts / cells 200A- 200C includes an array of stages S1 - S8 / S16 arranged between two instances of a dummy gate DG, also referred to as a dummy gate region DG or a dummy gate structure DG in some embodiments.

[0051] Each of stages S1 through S8 / S16 includes an inverter configured as discussed above with reference to VCO cells 130-1 through 130-N. In some embodiments, a given stage of stages S1 through S8 / S16 includes the following with reference to Figure 5 The VCO stage 500 in question.

[0052] Each inverter of stages S1 to S8 / S16 includes one or more PMOS transistors and / or NMOS transistors including various features (e.g., active regions / areas, gate regions / structures, source / drain (S / D) regions / structures, conductive regions / structures, and / or isolation regions / structures), which are not described or discussed further for the sake of clarity. In various embodiments, the various features correspond to one or more PMOS transistors and / or NMOS transistors including field effect transistors (FETs), fin transistors, gate-all-around (GAA) transistors, or other suitable transistor types.

[0053] A gate region / structure is an area of ​​an IC layout that is included as part of the manufacturing process to define a gate structure. A gate structure is a volume that includes one or more conductive segments (e.g., gate electrodes) comprising one or more conductive materials, such as polysilicon (poly), copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, the one or more conductive segments being configured to control a voltage provided at an adjacent gate dielectric layer.

[0054] The dielectric layer (e.g., a gate dielectric layer) is a bulk material including one or more insulating materials (e.g., silicon dioxide, silicon nitride (Si3N4)) and / or one or more other suitable materials (e.g., a low-k material having a k value less than 3.8 or a high-k material having a k value greater than 3.8, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2)), suitable for providing high resistance between IC structural elements, i.e., a resistance level above a predetermined threshold corresponding to one or more tolerance levels based on the impact of resistance on circuit performance.

[0055] In various embodiments, the gate dielectric layer has a generally planar shape (e.g., as part of a planar transistor), has a shape corresponding to the transistor topography (e.g., as part of a FinFET), or has a generally cylindrical shape (e.g., as part of a GAA transistor), such that the gate electrode is separated from the corresponding channel region by a distance that is large enough to limit current flow to a specified level and small enough to enable an electric field having a specified field strength to be generated in the channel.

[0056] In some embodiments, in contrast to a gate region / structure that intersects / overlaps an active region / area (as part of a transistor whose definition includes multiple portions of the active region / area adjacent to the gate region / structure), a dummy gate region / structure is located on or adjacent to an edge of the gate region / structure. Accordingly, only a single portion of the corresponding active region / area is adjacent to the dummy gate / region; the dummy gate is thus external to the transistor structure of the IC, but can be adjacent to a transistor that includes the portion of the active region / area adjacent to the dummy gate region / structure.

[0057] exist Figures 2A to 2C In the embodiment shown, the gate region / structure and the dummy gate region / structure DG extend in parallel in the vertical direction. In some embodiments, the gate region / structure and the dummy gate region / structure DG extend in parallel in the horizontal direction.

[0058] In some embodiments, the parallel gate regions / structures and dummy gate regions / structures are spaced apart at locations corresponding to a gate pitch (also referred to as a contact poly pitch (CPP) in some embodiments). In some embodiments, a minimum percentage or all of the gate pitch locations include either a gate region / structure or a dummy gate region / structure, depending on load uniformity requirements of one or more fabrication tools used to construct the gate / dummy gate structures corresponding to the gate / dummy gate regions.

[0059] In some embodiments, the active region / region is referred to as an oxide diffusion (OD) region / region, and the dummy gate region / structure is referred to as a continuous OD polysilicon on edge (CPODE) region / structure.

[0060] In some embodiments, IC layouts 200A to 200C include one or more cut gate regions that intersect one or more of the dummy gate regions DG such that corresponding dummy gate regions / structures DG (e.g., Figures 2A to 2C ) includes multiple portions referred to herein as individual dummy gate regions / structures DG.

[0061] A cut gate region (also referred to as a cut polysilicon region in some embodiments) is a region in an IC layout diagram that is included in the manufacturing process as part of defining a discontinuity in the gate electrode of a given gate structure, e.g., a portion that is etched away after the gate electrode is deposited, thereby electrically isolating corresponding adjacent portions of the gate electrode from each other.

[0062] like Figures 2A to 2C As shown, each of the stages S1 to S8 / S16 includes an input terminal and an output terminal, wherein the input terminal is configured to receive a voltage T0, the above reference voltage T1, and the output terminal. Figure 1 The voltage VCTL in question, the signal INx (x=1 . . . 16) corresponding to the first signal discussed above with reference to the VCO unit 130 , the output terminal is configured to output a signal ZNx corresponding to the second signal discussed above with reference to the VCO unit 130 .

[0063] The voltage T0 is a voltage received by each of the stages S1 to S8 / S16, which has a voltage level corresponding to or higher than the reference voltage VSS. Figure 1 In some embodiments, each of stages S1 to S8 / S16 is configured to receive voltage T0 from a reference voltage node as reference voltage VSS. In some embodiments, each of stages S1 to S8 / S16 is configured to receive voltage T0 as a buffer voltage from a circuit (not shown) external to VCO cells 200A to 200C (e.g., a tie cell or a clamp low cell).

[0064] exist Figures 2A to 2C In the illustrated embodiment, each of stages S1 to S8 / S16 is configured to be activated (e.g., enable signal propagation) in response to a low logic level or reference voltage level of voltage T0, and otherwise configured to be deactivated (e.g., configured to have a high impedance output). In some embodiments, each of stages S1 to S8 / S16 includes a PMOS transistor having a gate configured to receive voltage T0.

[0065] In some embodiments, one or more of stages S1 to S8 / S1 to S16 are configured to be activated in response to a voltage T0 having a high logic level or a power supply voltage VDD, and otherwise be deactivated, for example by including an NMOS transistor including a gate configured to receive a voltage T0, for example, from a clamp (high) unit or a power supply voltage node.

[0066] like Figures 2A to 2CAs shown, IC layout / VCO cell 200A includes an array of stages S1 to S8 arranged in a single row between two instances of dummy gate region / structure DG, IC layout / VCO cell 200B includes an array of stages S1 to S8 arranged in two rows between two instances of dummy gate region / structure DG, and IC layout / VCO cell 200C includes an array of stages S1 to S16 arranged in four rows between two instances of dummy gate region / structure DG.

[0067] Each of the IC layout / VCO cells 200A to 200C includes respective stages S1 to S8 / S16 adjacent to each other in both the row direction and the column direction (if applicable), such that each of the IC layout / VCO cells 200A to 200C has a corresponding Figures 2A to 2C 200A to 200C. In some embodiments, the two instances of dummy gate region / structure DG are included in a cell boundary (not shown) of the corresponding IC layouts 200A to 200C. In some embodiments, the two instances of dummy gate region / structure DG are referred to as boundary dummy gate region / structures.

[0068] By not including additional instances of dummy gate regions / structures DG between boundary dummy gate regions / structures DG, each of the IC layouts / VCO cells 200A to 200C can require less space than other approaches that include additional instances of dummy gate regions / structures (e.g., approaches in which the VCO cell includes a single stage such that each stage is separated from another stage by instances of boundary dummy gate regions / structures).

[0069] Figures 2A to 2C and discussed below Figures 3A to 3C The number of array rows and stages S1 to S8 / S16 shown is a non-limiting example provided for illustration purposes. Other numbers of array rows and stages similarly located between two instances of dummy gate regions / structures DG are also within the scope of the present disclosure.

[0070] Figures 3A to 3E 300A-300C and corresponding multi-stage VCO circuits 300A-300C according to some embodiments. Each of the IC layouts / circuits 300A-300C may be used as a reference above. Figure 1 The voltage source 110 in question and some or all of one or more of the VCO cells 130-1 to 130-N.

[0071] Each of the IC layouts / circuits 300A-300C includes the above referenced Figures 2A to 2CThe stages S1 to S8 / S16 discussed are arranged between two boundary dummy gate regions / structures DG. Compared to the IC layouts / VCO cells 200A to 200C, each of the IC layouts / circuits 300A to 300C also includes a voltage source 110 and an additional instance of a dummy gate region / structure DG located between the two boundary dummy gate regions / structures DG.

[0072] exist Figures 3A to 3C In the illustrated embodiment, each of the IC layouts / circuits 300A to 300C includes a voltage source 110 and two additional instances of a dummy gate region / structure DG located between the first and second portions of stages S1 to S8 / S16. The voltage source 110 is separated from each of the first and second portions by a single instance of the dummy gate region / structure DG, and each of the first and second portions includes half of the total number of stages S1 to S8 / S16.

[0073] At least one of the first portion or the second portion of stages S1 to S8 / S16 includes more than one stage, and each of the first portion and the second portion of stages S1 to S8 / S16 does not include an instance of a dummy gate region / structure DG. In some embodiments, the first portion and the second portion include more than half of the total number of stages S1 to S8 / S16.

[0074] exist Figure 3B and Figure 3C In the illustrated embodiment, each of the IC layouts / circuits 300B and 300C includes a voltage source 110 separated from each of the first and second portions by a dummy gate region / structure DG extending across each of the plurality of rows of stages S1 to S8 / S16. In some embodiments, the voltage source 110 is separated from the first and second portions by instances of the dummy gate region / structure DG extending across a subset of the plurality of rows of stages S1 to S8 / S16, for example, based on a third portion extending continuously between two boundary dummy gate regions / structures of stages S1 to S8 / S16.

[0075] Compared to IC layouts / circuits 200A-200C in which voltage VCTL is received from a source (e.g., voltage source 110) located outside the two boundary dummy gate regions / structures DG, IC layouts / circuits 300A-300C including voltage source 110 located between the two boundary dummy gate regions / structures DG can increase the uniformity of parasitic effects (e.g., resistance-capacitance (RC) effects) and reduce voltage level variations of voltage VCTL across the IC or IC die. This performance enhancement comes at the expense of the improvements to circuit area requirements discussed above with reference to IC layouts / circuits 200A-200C due to the two additional instances of dummy gate regions / structures DG.

[0076] Figure 3D and Figure 3E Each of the figures in depicts an embodiment in which the voltage source 110 is separated from a given portion of the stages S1 to S8 / S16 by one or more additional instances of the dummy gate region / structure DG. Figure 3D depicts an embodiment in which additional instances of dummy gate regions / structures DG are included in the voltage source 110, while Figure 3E Embodiments are depicted in which additional instances of dummy gate regions / structures DG are included in given portions of stages S1 through S8 / S16 .

[0077] and Figures 3A to 3C Compared to the embodiment shown, Figure 3D and Figure 3E The illustrated embodiment is capable of reducing IC process-related (ICD) effects, such as uncertainty in the voltage level of voltage VCTL, based on the voltage source 110 being separated from a given portion of stages S1 to S8 / S16 by an increased distance via one or more additional instances of the dummy gate region / structure DG. This performance enhancement comes at the expense of further reducing the improvements to the circuit area requirements discussed above with reference to IC layouts / circuits 200A to 200C due to the additional instances of the dummy gate region / structure DG.

[0078] exist Figure 3D and Figure 3E In each of the illustrated embodiments, a total of two instances of dummy gate region / structure DG separate voltage source 110 from a given portion of stages S1 to S8 / S16 and are separated from each other by a multiple of the gate pitch xGP. In some embodiments, two instances of gate region / structure DG are separated from each other by two or more instances of gate region / structure DG located at positions corresponding to the gate pitch, and outermost instances of the instances of gate region / structure DG are separated from each other by a multiple of the gate pitch xGP.

[0079] As the number of multiples x of the gate pitch GP increases, the reduction in ICD effects increases at the expense of further reductions in circuit area improvements. In some embodiments, two instances of the gate region / structure DG are separated from each other by a gate pitch multiple ranging from 3 to 8. In some embodiments, two instances of the gate region / structure DG are separated from each other by a gate pitch multiple equal to 7.

[0080] Figure 4 is a schematic diagram of a voltage source 400 according to some embodiments. The voltage source 400 may be used as the reference Figures 1 to 3E The voltage source 110 in question.

[0081] Voltage source 400 includes a first branch (not labeled) including NMOS transistors N1 and N2, and a second branch (not labeled) including PMOS transistor P1 and NMOS transistors N3 through N5. NMOS transistors N1 and N2 are coupled in series between the gate of PMOS transistor P1 and a reference voltage node / reference voltage VSS, wherein NMOS transistor N1 is configured as a diode, and NMOS transistor N2 includes a gate configured to receive an enable signal EN. PMOS transistors and NMOS transistors N3 through N5 are coupled in series between a power supply voltage node / power supply voltage VDD and a reference voltage node / reference voltage VSS, wherein PMOS transistor P1 is configured as a diode, and each of NMOS transistors N3 through N5 includes a gate configured to receive an enable signal EN. Output terminal Z is located between NMOS transistors N3 and N4 and is coupled to the aforementioned voltage node VCTLN.

[0082] The voltage source 400 is therefore configured to, in operation, respond to the enable signal EN having a high logic level by turning on each of the NMOS transistors N2 to N5, thereby allowing current to flow through each of the first branch and the second branch, and respond to the enable signal EN having a low logic level by turning off each of the NMOS transistors N2 to N5, thereby limiting the current flow.

[0083] The current flowing through each of the first and second branches causes current to flow through the series connection of PMOS transistor P1 and NMOS transistor N1. Due to the diode configuration of PMOS transistor P1 and NMOS transistor N1, this current flow generates a temperature-dependent voltage drop across PMOS transistor P1. The difference between the power supply voltage VDD and this voltage drop appears across NMOS transistors N3 to N5, which function to divide this difference to generate voltage VCTL at output terminal Z.

[0084] The voltage source 400 is thus configured to output a voltage VCTL on the voltage node VCTLN having a voltage level that increases with increasing temperature, enabling a circuit (eg, IC 100 ) including the voltage source 400 to achieve the benefits described above.

[0085] Figure 5 is a schematic diagram of a VCO stage 500 according to some embodiments. The VCO stage 500 may be used as a reference for the above Figures 1 to 3E The stages of the multi-stage VCO unit 130 in question are, for example, stages S1 to S8 / S16 .

[0086] The VCO stage 500 includes PMOS transistors P2 and P3 coupled in series with NMOS transistors N6 and N7 between a power supply voltage node / power supply voltage VDD and a reference voltage node / reference voltage VSS. The PMOS transistor P2 includes a gate configured to receive a voltage T0, transistors P3 and N6 include gates coupled to an input terminal INS configured to receive a first signal, and the NMOS transistor N7 includes a gate configured to receive a voltage VCTL, each of which is referenced by a reference voltage. Figures 1 to 3E The output terminal ZNS is located between the PMOS transistor P3 and the NMOS transistor N6 and is configured to output the above reference Figures 1 to 3E The second signal in question.

[0087] VCO stage 500 is therefore configured to, in operation, turn on PMOS transistor P2 in response to voltage T0 having a low logic level or reference voltage VSS, and to cause NMOS transistor N7 to have a transconductance based on a voltage level of voltage VCTL. Transistors P3 and N6 receive a first signal at input terminal INS, invert the first signal, and transmit it as a second signal at output terminal ZNS. The speed at which transistors P3 and N6 transmit the inverted first signal is controlled by the transconductance of NMOS transistor N7.

[0088] VCO stage 500 is thus configured to output the second signal based on the first signal at a rate that increases as the voltage level of voltage VCTL increases, enabling a circuit (eg, IC 100 ) including VCO stage 500 to achieve the above-described benefits.

[0089] Figure 6 and Figure 7 is a schematic diagram of each of the VCO cells 600 and 700 according to some embodiments. Each of the VCO cells 600 and 700 may be used as a reference. Figures 1 to 3E In some embodiments, one or both of the VCO cells 600 or 700 are referred to as delay cells 600 or 700 , VCO delay cells 600 or 700 , or multi-stage VCO cells 600 or 700 .

[0090] exist Figure 6 and Figure 7 In the illustrated embodiment, the VCO cells 600 and 700 respectively include four stages S1 to S4 and L stages S1 to SL coupled in series between the input terminal INC and the output terminal OUTC, each stage including the above-referenced Figure 5 Transistors P2, P3, N6, and N7 are configured as discussed (a single stage is labeled S1 for clarity). Other numbers of stages are also within the scope of the present invention.

[0091] Each of the VCO cells 600 and 700 is thus configured to receive, in operation, a first signal from stage S1 at input terminal INC from a source external to the VCO cell 600 or 700, e.g., a signal output from another instance of the VCO cell 600 or 700 or as an oscillation signal OSC on the aforementioned feedback path FDBK. Stage S1 inverts the first signal and transmits it as a second signal, which is internal signal O1 corresponding to the first signal of stage S2. In turn, successive stages S2 through S4 / SL-1 invert the corresponding first signals and transmit the corresponding second signals as internal signals O2, O3 (or OL-1 in the case of VCO cell 700). The final stage S4 or SL inverts the first signal (which is signal O3 or OL-1) and transmits it at output terminal OUTC as a second signal external to the VCO cell 600 or 700 (e.g., external to another instance of the VCO cell 600 or 700) or as an oscillation signal OSC on the aforementioned feedback path FDBK.

[0092] like Figure 7 As shown, VCO cell 700 includes each of stages S2 through SL-1, each of which further includes a PMOS transistor P4 coupled between PMOS transistors P2 and P3, and an NMOS transistor N8 coupled between NMOS transistors N6 and N7. Each of transistors P4 and N8 includes a gate coupled to the gates of transistors P3 and N6, thereby being configured to receive the first signal. The drain terminals of each of transistors P4 and N8 are coupled to each other and to the source terminals of each of transistors P3 and N6.

[0093] Compared to stages S1 and SL, stages S2 to SL-1 are therefore configured to propagate the first signal with greater delay (and thus slower speed) for a given voltage level of voltage VCTL in operation. In some embodiments, stages S2 to SL-1 are referred to as inner stages S2 to SL-1.

[0094] In some embodiments, one or both of the VCO cells 600 or 700A are based on the above references. Figures 2A to 3E The embodiments in question may be configured, for example, as a stage array located between two instances of a dummy gate region / structure DG.

[0095] Each of the VCO cells 600 and 700 is thus configured to include a plurality of stages S1 to S4 / SL that are configured to receive the voltage VCTL on the voltage node VCTLN and perform signal propagation delay in response to the voltage level of the voltage VCTL, enabling a circuit (e.g., IC 100) including the VCO cell 600 or 700 to achieve the above-described benefits.

[0096] As the number of stages (e.g., stages S1 to S4 of VCO cell 600 or stages S1 to SL of VCO cell 700 including internal stages S2 to SL-1) increases, the total signal propagation delay increases, while the oscillation frequency decreases. In some embodiments, the total number of stages included in VCO cell 600 or 700 ranges from 2 to 12. In some embodiments, the total number of stages included in VCO cell 600 or 700 is equal to 4, 6, or 8.

[0097] In the first to third non-limiting examples, embodiments of the IC 100 include a single VCO cell 130 (N=1), which corresponds to a VCO cell 600 including a total of four stages, a VCO cell 700 including a total of four stages, and a VCO cell 700 including a total of eight stages, respectively. Compared to an approach in which the VCO circuit includes 20 single-stage VCO cells, the circuit area is reduced from 100% to 38%, 39%, and 35%, respectively, and thermal linearity sensitivity is maintained or increased.

[0098] In fourth to eighth non-limiting examples, embodiments of the IC 100 respectively include each of the VCO cells 130-1 to 130-7 corresponding to the four-stage VCO cell 600, each of the VCO cells 130-1 to 130-5 corresponding to the four-stage VCO cell 700, the VCO cells 130-1 to 130-3 corresponding to one four-stage VCO cell 600 and two six-stage VCO cells 700, and each of the VCO cells 130-1 to 130-2 corresponding to the eight-stage VCO cell 700. Compared to an approach in which the VCO circuit includes 32 single-stage VCO cells, circuit area is reduced from 100% to 32%, 29%, 25%, and 26%, respectively, and thermal linear sensitivity is maintained.

[0099] Figure 8 is a schematic diagram of a multi-bit VCO cell 800 according to some embodiments. In embodiments where the VCO cells 130-1 to 130-N and the feedback path DFBK including the switching circuit 120 are configured to include multiple signal paths, the VCO cell 800 (also referred to as a multi-stage VCO cell 800 or a multi-bit VCO cell 800 in some embodiments) may be used as the reference signal path for the above embodiment. Figures 1 to 3EOne or more of the VCO cells 130 - 1 to 130 -N in question.

[0100] exist Figure 8 In the embodiment shown, the VCO unit 800 includes stages S1 to S4, each of which includes the Figure 6 and Figure 7 The VCO cell 800 includes a PMOS transistor P2 and an NMOS transistor N7 coupled in series between a power supply voltage node VDD and a reference voltage node VSS. The PMOS transistor P2 is configured to receive a voltage T0, and the NMOS transistor N7 is configured to receive a voltage VCTL. The VCO cell 800 also includes an inverter (not labeled) configured to receive a select signal SE and output a complementary select signal SEB.

[0101] Each stage S1 to S4 of the VCO cell 800 further includes two PMOS transistors (not labeled) of a first branch and two PMOS transistors (not labeled) of a second branch coupled between the power supply voltage node VDD and the transistor P2, and two NMOS transistors (not labeled) of a first branch and two NMOS transistors (not labeled) of a second branch coupled between the transistor N7 and the reference voltage node VSS.

[0102] The PMOS transistors of the first branches of stages S1 to S4 are configured to receive the selection signal SE and respective signals IN1 to IN4, while the NMOS transistors of the first branches of stages S1 to S4 are configured to receive the compensation selection signal SEB and respective signals IN1 to IN4. The PMOS transistors of the second branches of stages S1 to S4 are configured to receive the compensation selection signal SEB and respective signals SIN1 (from a source external to the VCO cell 800) and signals ZN1 to ZN3, while the NMOS transistors of the second branches of stages S1 to S4 are configured to receive the selection signal SE and respective signals SIN1 and ZN1 to ZN3.

[0103] Each stage S1 to S4 of the VCO cell 800 is thus configured to, in operation, alternately switch corresponding instances of the transistors P2 and N7 between the first branch and the second branch by outputting corresponding signals ZN1 to ZN4 in response to the corresponding signals IN1 to IN4 when the select signal SE has a low logic level, and outputting corresponding signals ZN1 to ZN4 in response to the corresponding signal SIN1 and signals ZN1 to ZN3 when the select signal SE has a high logic level.

[0104] The VCO cell 800 is therefore configured to respond to the high and low logic levels of the select signal SE in operation by alternately inverting and propagating the signal SIN1 and the signals ZN1 to ZN3 or the signals IN1 to IN4, and to perform signal propagation delays in response to the voltage level of the voltage VCTL received on the voltage node VCTLN, so that a circuit (e.g., IC 100 or IC 900) that includes the VCO stage 800 can achieve the benefits described above.

[0105] Figure 8 The number of stages and signals shown are non-limiting examples provided for illustration purposes. VCO cells 800 that include other numbers of stages and signals are within the scope of the present disclosure.

[0106] Figure 9 900 according to some embodiments. IC 900 corresponds to the embodiment of IC 100 described above, wherein the multi-stage VCO units 130-1 to 130-N correspond to the following reference Figure 8 The discussed example of multi-bit VCO cell 800. Compared to IC 100, IC 900 does not include voltage source 110, and VCO cell 130-1 includes circuit components (not shown) configured to output voltage VCTL in response to enable signal EN.

[0107] Figure 9 A non-limiting example of IC 900 is depicted in which VCO cell 130-1 comprises a 16-bit VCO cell 800, while VCO cells 130-2 through 130-N comprise 8-bit VCO cells 800. Other numbers of VCO cells 130, including other numbers of bits, are within the scope of the present disclosure.

[0108] In a non-limiting example, an embodiment of IC 100 or IC 900 includes VCO cell 130-1 corresponding to a 16-bit VCO cell 800 and each of VCO cells 130-2 and 130-3 corresponding to an 8-bit VCO cell 800. Compared to an approach in which the VCO circuit includes 32 single-stage VCO cells, circuit area is reduced from 100% to 46%, thermal linear sensitivity is maintained, and routing resources associated with voltage T0 and voltage VCTL are saved.

[0109] Figure 10 is a flow chart of a method 1000 of operating an IC according to some embodiments. The method 1000 can be used in an IC (e.g., Figures 1 to 9 is executed on the IC 100 or IC 900 in question).

[0110] In some embodiments, performing some or all of the operations of method 1000 is part of obtaining a temperature profile and / or performing a sign-off operation on a manufacturing process.

[0111] Figure 10 The order in which the operations of method 1000 are shown is for illustration only; the operations of method 1000 can be performed simultaneously or in different orders. Figure 10 In some embodiments, except Figure 10 Operations other than those shown are Figure 10 are performed before, between, during, and / or after the operations shown.

[0112] At operation 1002, in some embodiments, a voltage having a temperature-dependent voltage level is generated. In some embodiments, generating the voltage includes: using a voltage source. In some embodiments, generating the voltage includes: using the above reference Figures 1 to 9 The voltage source 110 in question.

[0113] In some embodiments, generating a voltage includes using a VCO unit (e.g., as described above with reference to Figures 1 to 9 Components of the VCO unit 130-1) in question.

[0114] In some embodiments, generating a voltage includes: responding to an enable signal (eg, Figures 1 to 9 The enable signal EN) in question generates a voltage.

[0115] At operation 1004, a voltage is received at the first multi-stage VCO unit. In some embodiments, receiving the voltage includes receiving a voltage from a source external to the IC. In some embodiments, receiving the voltage includes receiving a voltage from a source internal to the IC (e.g., as described above with reference to FIG. 1 ). Figures 1 to 9 The voltage of the voltage source 110 or VCO cell 130-1 in question.

[0116] In some embodiments, receiving a voltage at the first multi-stage VCO unit includes: Figures 1 to 9 The VCO cell 130 - 1 , 200A to 200C, 300A to 300C, or 600 to 800 in question receives a voltage.

[0117] Receiving a voltage at the first multi-stage VCO cell includes: at each stage of the VCO cell (eg, Figures 1 to 9 Each of the stages S1 to S4 / S8 / S16 in question receives a voltage.

[0118] In some embodiments, receiving a voltage at a first multi-stage VCO cell includes: Figures 1 to 9 The VCO cell 130 in question receives a voltage.

[0119] At operation 1006, an oscillation signal is generated by propagating a signal along the stages of the VCO unit based on the voltage level of the voltage. In some embodiments, generating the oscillation signal includes: generating the above reference Figures 1 to 9 The signal in question is OSC or FOUT.

[0120] In some embodiments, propagating the signal along the stages of the VCO unit includes: Figures 1 to 9 Stages S1 to S4 / S8 / S16 of the VCO cell 130 - 1 , 200A to 200C, 300A to 300C, or 600 to 800 in question propagate signals.

[0121] In some embodiments, propagating a signal along a stage of a VCO cell based on a voltage level of a voltage includes: Figures 1 to 9 The voltage level of the voltage VCTL in question propagates the signal.

[0122] At operation 1008, in some embodiments, the frequency of the oscillating signal is measured. In some embodiments, measuring the frequency of the oscillating signal includes using a circuit or device external to the IC. In some embodiments, measuring the frequency of the oscillating signal includes using a circuit internal to the IC, such as the one described above with reference to FIG. Figures 1 to 9 The frequency measurement circuit 160 in question.

[0123] By performing some or all of the operations of method 1000 , an oscillating signal having a temperature-dependent frequency is generated using a multi-stage VCO cell, thereby enabling the benefits discussed above with reference to IC 100 and IC 900 .

[0124] Figure 11 is a flow chart of a method 1100 for manufacturing an IC according to some embodiments. The method 1100 is operable to form the above reference Figures 1 to 9 Some or all of the IC 100 or IC 900 in question.

[0125] In some embodiments, performing some or all of the operations of method 1100 is a portion of constructing multiple IC devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing multiple manufacturing operations (e.g., one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing multiple IC devices in a semiconductor wafer).

[0126] In some embodiments, Figure 11 The operations of method 1100 are performed in the order shown. In some embodiments, Figure 11The operations of method 1100 may be performed in an order different from the order shown. In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 1100. In some embodiments, performing some or all of the operations of method 1100 includes performing the following reference IC manufacturing system 1400 and Figure 14 The operation or operations in question.

[0127] At operation 1102, in some embodiments, a plurality of transistor features are formed in a semiconductor substrate. In some embodiments, forming the plurality of transistor features includes: forming the above reference Figures 1 to 9 The transistor features discussed correspond to one or more instances of IC 100 or IC 900 .

[0128] In some embodiments, forming the plurality of transistor features includes performing one or more deposition and / or implantation processes in regions of the semiconductor substrate corresponding to one or more instances of IC 100 or IC 900. In some embodiments, forming the first epitaxial region and the second epitaxial region includes forming an active region and an S / D structure.

[0129] At operation 1104, a plurality of gate structures are constructed on the plurality of transistor features to form a multi-stage VCO unit between the first dummy gate structure and the second dummy gate structure. Forming the multi-stage VCO unit between the first dummy gate structure and the second dummy gate structure includes: forming the above reference 4 between the dummy gate structures DG. Figures 1 to 9 The stages S1 to S4 / S8 / S16 of the VCO cells 130 , 200A to 200C, 300A to 300C or 600 to 800 in question.

[0130] In some embodiments, constructing the plurality of gate structures includes forming one or more circuits in addition to the VCO unit, for example, one or more additional VCO units 130-1 to 130-N and / or the above referenced circuits. Figures 1 to 9 One or more of the voltage source 110 , the switching circuit 120 , the buffers 140 and 150 , or the frequency measurement circuit 160 in question.

[0131] In some embodiments, constructing the plurality of gate structures includes performing a plurality of fabrication operations, such as photolithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing the above referenced Figures 1 to 9 One or more of the other operations discussed for the plurality of gate structures.

[0132] At operation 1106, electrical connections are formed including a feedback path and a connection to a temperature-dependent voltage source, thereby forming a VCO. In some embodiments, forming the electrical connections includes: forming the above reference Figures 1 to 9The feedback path FDBK in question and the connection to the voltage source 110 .

[0133] In some embodiments, forming the VCO includes forming a voltage source 110 or voltage source component, a switching circuit 120, a VCO cell 130, and in some embodiments, buffers 140 and 150, each of which is referred to above. Figures 1 to 9 Being discussed.

[0134] In some embodiments, forming the electrical connection includes forming one or more via structures and / or metal segments by performing multiple manufacturing operations, the multiple manufacturing operations including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, so that the one or more conductive materials are configured to form a continuous low resistance structure.

[0135] At operation 1108, in some embodiments, an electrical connection is formed from the VCO to the frequency measurement circuit. In some embodiments, forming an electrical connection from the VCO to the frequency measurement circuit includes forming an electrical connection to a frequency measurement circuit external to the IC. In some embodiments, forming an electrical connection from the VCO to the frequency measurement circuit includes forming the above referenced Figures 1 to 9 The electrical connections to the frequency measurement circuit 160 are discussed.

[0136] By performing some or all of the operations of method 1100 , an IC is manufactured in which a VCO includes one or more multi-stage VCO cells configured to generate an oscillation signal having a temperature-dependent frequency, thereby enabling the benefits discussed above with reference to IC 100 and IC 900 .

[0137] Figure 12 is a flow chart of a method 1200 for generating an IC layout diagram according to some embodiments, for example, as described above with reference to Figures 2A to 2C The IC layouts 200A to 200C discussed above refer to FIG. Figure 3E The IC layouts in question are shown in Figures 300A to 300C.

[0138] In some embodiments, generating an IC layout diagram includes generating a layout diagram corresponding to the IC (eg, Figures 1 to 9 An IC layout diagram of the IC device 100 or the IC device 900 in question, wherein the IC is manufactured based on the generated IC layout diagram.

[0139] In some embodiments, some or all of method 1200 is executed by a processor of a computer (e.g., as described below). Figure 13 The processor 1302 of the IC layout generation system 1300 in question executes.

[0140] Some or all of the operations of method 1200 can be performed as described in a design studio (e.g., referenced below). Figure 14 This is performed as part of the design process performed in the design studio 1420 discussed.

[0141] In some embodiments, Figure 12 The operations of method 1200 are performed in the order shown. In some embodiments, the operations of method 1200 are performed simultaneously and / or in a sequential order. Figure 12 In some embodiments, one or more operations of method 1200 are performed before, between, during, and / or after one or more operations of method 1200 are performed.

[0142] At operation 1202, one or more multi-stage VCO cells are arranged in an IC layout. Arranging one or more multi-stage VCO cells includes: arranging the above reference Figures 1 to 9 One or more of the VCO cells 130, 200A to 200C, 300A to 300C or 600 to 800 in question.

[0143] In some embodiments, arranging one or more VCO cells includes arranging a stage array, such as described above with reference to Figures 2A to 3E The stages S1 to S8 / S16 of the VCO cells 200A to 200C or 300A to 300C in question.

[0144] In some embodiments, arranging one or more VCO cells includes: selecting from a cell library (e.g., Figure 13 The cell library 1307 of the IC layout generation system 1300 in question obtains one or more VCO cells.

[0145] In some embodiments, arranging the one or more VCO cells includes storing one or more modified IC layouts of the one or more VCO cells in a cell library, such as the cell library 1307 of the IC layout generation system 1300 .

[0146] At operation 1204, electrical connections from the temperature-dependent voltage source to each stage of the VCO cell are configured in the IC layout. In some embodiments, configuring electrical connections from the temperature-dependent voltage source to each stage of the VCO cell includes configuring connections from the voltage source 110 to the reference voltages above. Figures 1 to 9 The voltage node VCTLN of each stage of the VCO cell 130, 200A to 200C, 300A to 300C, or 600 to 800 in question.

[0147] In some embodiments, configuring the electrical connections includes configuring additional electrical connections, for example, configuring some or all of feedback path DFBK, connections to additional VCO cells 130 and / or between additional VCO cells 130, connections to buffers 140 and 150, and / or connections to a frequency measurement circuit (e.g., frequency measurement circuit 160).

[0148] At operation 1206, in some embodiments, an IC layout diagram including a multi-level VCO unit is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes: storing the above referenced Figures 1 to 9 The IC layouts 200A-200C, 300A-300C, and / or 600-800 are discussed.

[0149] In various embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in a non-volatile computer readable memory or a cell library (e.g., a database), and / or includes: storing the IC layout diagram on a network. In some embodiments, storing the IC layout diagram in a storage device includes: Figure 13 The IC layout diagram is stored in the layout diagram 1309 of the IC layout diagram generating system 1300 or on the network 1314 .

[0150] At operation 1208, in some embodiments, one or more manufacturing operations are performed based on the IC layout. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout. Figure 11 and the following references Figure 14 One or more manufacturing operations, such as one or more photolithographic exposures, are performed based on the IC layout.

[0151] By performing some or all of the operations of method 1200, an IC layout corresponding to an IC device is generated, wherein the VCO includes one or more multi-stage VCO cells, and the one or more multi-stage VCO cells are configured to generate an oscillation signal having a temperature-dependent frequency, thereby enabling the benefits discussed above with reference to IC 100 and IC 900.

[0152] Figure 13 13 is a block diagram of an IC layout generation system 1300 according to some embodiments. According to some embodiments, for example, the IC layout generation system 1300 can be used to implement the method of designing an IC layout according to one or more embodiments described herein.

[0153] In some embodiments, IC layout generation system 1300 is a general-purpose computing device that includes a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions), among other things. Instructions 1306 are executed (at least in part) by hardware processor 1302 to represent an electronic design automation (EDA) tool that implements a method (e.g., as described above with reference to FIG. Figure 5 The method 500 for generating an IC layout diagram described above and / or reference Figure 7 A portion or all of the described method 700 for generating an IC layout diagram) (hereinafter referred to as the described process and / or method).

[0154] The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an I / O interface 1310 via the bus 1308. A network interface 1312 is also electrically connected to the processor 1302 via the bus 1308. The network interface 1312 is connected to a network 1314, enabling the processor 1302 and the computer-readable storage medium 1304 to connect to external components via the network 1314. The processor 1302 is configured to execute computer program code 1306 encoded in the computer-readable storage medium 1304 to enable the IC layout generation system 1300 to perform some or all of the described processes and / or methods. In one or more embodiments, the processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0155] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1304 includes a compact disk read-only memory (CD-ROM), a compact disk rewritable / rewritable (CD-R / W), and / or a digital video disk (DVD).

[0156] In one or more embodiments, computer-readable storage medium 1304 stores computer program code 1306 configured to cause IC floor plan generation system 1300 (where such execution represents (at least in part) an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, computer-readable storage medium 1304 also stores information that facilitates the performance of some or all of the described processes and / or methods.

[0157] In one or more embodiments, computer readable storage medium 1304 stores a computer program including such units disclosed herein (e.g., the above referenced Figures 1 to 8 A cell library 1307 of cells of the VCO cells in question (130, 200A to 200C, 300A to 300C, and 600 to 800).

[0158] In one or more embodiments, computer-readable storage medium 1304 stores a layout diagram 1309 including such an IC layout diagram as disclosed herein.

[0159] IC layout generation system 1300 includes an I / O interface 1310. I / O interface 1310 is coupled to external circuitry. In one or more embodiments, I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for transmitting information and commands to processor 1302.

[0160] IC layout generation system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows system 1300 to communicate with a network 1314 to which one or more other computer systems are connected. Network interface 1312 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more IC layout generation systems 1300.

[0161] IC layout generation system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. The information is transmitted to processor 1302 via bus 1308. IC layout generation system 1300 is configured to receive information related to a user interface (UI) via I / O interface 1310. This information is stored in computer-readable medium 1304 as UI 1342.

[0162] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the described processes and / or methods are implemented as a software application used by the IC layout drawing generation system 1300. In some embodiments, the IC layout drawing generation system 1300 is used using a software application such as the one available from CADENCE DESIGN SYSTEMS, Inc. A tool such as or another suitable layout generation tool is used to generate a layout diagram including standard cells.

[0163] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: an optical disk (e.g., DVD), a magnetic disk (e.g., hard disk), a semiconductor memory (e.g., ROM), RAM, a memory card, etc.

[0164] Figure 14 1 is a block diagram of an IC manufacturing system 1400 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on an IC layout drawing, manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0165] exist Figure 14In the embodiment of the present invention, IC manufacturing system 1400 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1460, such as design room 1420, mask room 1430, and IC manufacturer / fabricator ("Fab") 1450. The entities in system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 are owned by a single larger company. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 coexist in a common facility and use common resources.

[0166] The design office (or design team) 1420 generates an IC design layout 1422. The IC design layout 1422 includes various geometric patterns, such as the above reference Figures 1 to 8 The VCO cells 130, 200A to 200C, 300A to 300C, and / or 600 to 800 in question correspond to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the integrated circuit device 1460 to be manufactured. The various layers are combined to form various IC features. For example, a portion of an IC design layout 1422 includes various IC features, such as active areas, gate electrodes, source and drain electrodes, metal lines or vias for interconnecting layers, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 1420 implements appropriate design programs to generate IC design layout 1422. The design program includes one or more of a logical design, a physical design, or a placement and routing. IC design layout 1422 is presented in one or more data files having information about the geometric patterns. For example, IC design layout 1422 can be represented in a GDSII file format or a DFII file format.

[0167] The mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. The mask chamber 1430 uses the IC design layout drawing 1422 to fabricate one or more masks 1445 for fabricating various layers of the IC device 1460 according to the IC design layout drawing 1422. The mask chamber 1430 performs mask data preparation 1432, wherein the IC design layout drawing 1422 is converted into a representative data file (RDF). The mask data preparation 1432 provides the RDF to the mask fabrication 1444. The mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1445 or a semiconductor wafer 1453). The design layout drawing 1422 is manipulated by the mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1450. In Figure 14 , mask data preparation 1432 and mask fabrication 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask fabrication 1444 may be collectively referred to as mask data preparation.

[0168] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1422. In some embodiments, mask data preparation 1432 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, or a combination thereof. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0169] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks an IC design layout 1422 that has been processed in OPC against a set of mask creation standard rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for the constraints during mask fabrication 1444, which may undo some of the modifications performed by the OPC to satisfy the mask creation standard rules.

[0170] In some embodiments, mask data preparation 1432 includes a lithography process check (LPC) that simulates a process to be implemented by IC fab 1450 to manufacture IC device 1460. LPC simulates this process based on IC design layout drawing 1422 to create a simulated manufactured device, such as IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination of the foregoing. In some embodiments, after the simulated manufactured device is created by LPC, if the shape of the simulated device is insufficient to meet the design rules, OPC and / or MRC are repeated to further improve the IC design layout drawing 1422.

[0171] It should be understood that the above description of mask data preparation 1432 has been simplified for the sake of clarity. In some embodiments, mask data preparation 1432 includes additional features such as logic operations (LOPs) to modify IC design layout 1422 according to manufacturing rules. In addition, the processes applied to IC design layout 1422 during mask data preparation 1432 can be performed in a variety of different orders.

[0172] After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 are fabricated based on the modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout 1422. In some embodiments, an electron beam (e-beam) or a plurality of electron beams are used to form a pattern on a mask (photomask or reticle) 1445 based on the modified IC design layout 1422. The mask 1445 can be formed using various techniques. In some embodiments, the mask 1445 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) or EUV beam) used to expose an image-sensitive material layer (e.g., a photoresist) that has been applied to the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1445 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1444 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in semiconductor wafer 1453, in an etching process to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0173] IC fab 1450 is an IC manufacturing enterprise that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, one fabrication facility may provide front-end fabrication (front-end of line (FEOL) fabrication) for multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end of line (BEOL) fabrication) for interconnection and packaging of the IC products. A third fabrication facility may provide other services for the foundry.

[0174] IC fab 1450 includes wafer fabrication tools 1452 configured to perform various fabrication operations on semiconductor wafer 1453 to fabricate IC devices 1460 based on mask(s) (e.g., mask 1445). In various embodiments, fabrication tools 1452 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0175] IC fab 1450 uses (one or more) masks 1445 manufactured by mask chamber 1430 to manufacture IC devices 1460. Therefore, IC fab 1450 at least indirectly uses IC design layout 1422 to manufacture IC devices 1460. In some embodiments, semiconductor wafer 1453 is manufactured by IC fab 1450 using (one or more) masks 1445 to form IC devices 1460. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0176] In some embodiments, an IC includes: a voltage source configured to generate a first voltage having a temperature-dependent voltage level; and a VCO including a feedback path and a first VCO cell configured to receive the first voltage, wherein the first VCO cell includes a series of stages, a first stage in the series of stages being configured to output a first signal within the first VCO cell based on a voltage level of the first voltage and an oscillating signal propagating on the feedback path, and a last stage in the series of stages being configured to output a second signal external to the first VCO cell based on the first signal and the voltage level of the first voltage. In some embodiments, the first VCO cell includes a first dummy gate structure and a second dummy gate structure, each stage in the series of stages including an inverter configured to receive the first voltage, the corresponding inverters being arranged in an array between the first dummy gate structure and the second dummy gate structure, and the array including a total of 1, 2, or 4 rows. In some embodiments, the first VCO cell further includes a third dummy gate structure and a fourth dummy gate structure located between the first dummy gate structure and the second dummy gate structure, a first subset of the array of inverters is located between the first dummy gate structure and the third dummy gate structure, a second subset of the array of inverters is located between the second dummy gate structure and the fourth dummy gate structure, and a voltage source is located between the third dummy gate structure and the fourth dummy gate structure. In some embodiments, the IC includes a fifth dummy gate structure and a sixth dummy gate structure, the fifth dummy gate structure being located between the voltage source and the third dummy gate structure and offset from the third dummy gate structure by a first multiple of the gate pitch, and the sixth dummy gate structure being located between the voltage source and the fourth dummy gate structure and offset from the fourth dummy gate structure by a second multiple of the gate pitch. In some embodiments, each stage in the series of stages includes first and second PMOS transistors and first and second NMOS transistors coupled in series between a power supply node and a reference voltage node, the power supply node being configured to have a power supply voltage, the reference voltage node being configured to have a reference voltage, the first PMOS transistor being coupled to the power supply node and including a gate configured to receive the reference voltage, the first NMOS transistor being coupled to the reference voltage node and including a gate configured to receive the first voltage, the second PMOS transistor and the second NMOS transistor of the first stage being coupled between the first PMOS transistor and the first NMOS transistor and including a gate configured to receive an oscillation signal, and the second PMOS transistor and the NMOS transistor of the last stage being coupled between the first PMOS transistor and the NMOS transistor and including a gate configured to receive the first signal or the third signal inside the VCO unit.In some embodiments, the series of stages includes a first internal stage and a second internal stage, wherein the second PMOS transistor and the second NMOS transistor of the first internal stage include gates configured to receive a first signal and are configured to output a fourth signal within the first VCO unit based on the first signal and a voltage level of the first voltage, while the second PMOS transistor and the second NMOS transistor of the second internal stage include gates configured to receive a fourth signal and are configured to output a third signal based on the fourth signal and a voltage level of the first voltage. In some embodiments, each of the first and second internal stages includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor being coupled between the first and second PMOS transistors, and the third NMOS transistor being coupled between the first and second NMOS transistors, wherein the third PMOS transistor and the third NMOS transistor include gates coupled to gates of the second PMOS transistor and the second NMOS transistor, and source terminals of the second PMOS transistor and the second NMOS transistor being coupled to each other and to drain terminals of the third PMOS transistor and the third NMOS transistor. In some embodiments, the series of stages includes a plurality of additional internal stages coupled between the first and second internal stages. In some embodiments, each stage in the series of stages includes: a first PMOS transistor and a first NMOS transistor coupled in series between a power supply node and a reference voltage node, the power supply node being configured to have a power supply voltage, and the reference voltage node being configured to have a reference voltage, wherein the first PMOS transistor includes a gate configured to receive the reference voltage, and the first NMOS transistor includes a gate configured to receive the first voltage; a first branch of PMOS transistors and a second branch of PMOS transistors coupled between the power supply node and the first PMOS transistor; and a first branch of NMOS transistors and a second branch of NMOS transistors coupled between the first NMOS transistor and the reference voltage node, wherein the first branch of PMOS transistors and the first branch of NMOS transistors are configured to receive a first input signal in response to a first logic level of a select signal, and the second branch of PMOS transistors and the second branch of NMOS transistors are configured to receive a second input signal in response to a second logic level of the select signal. In some embodiments, the first VCO cell includes a voltage source. In some embodiments, the VCO includes a second VCO cell coupled between the first VCO cell and the feedback path. In some embodiments, the IC includes a frequency measurement circuit coupled to the VCO and configured to generate an output signal based on a frequency of the oscillation signal.

[0177] In some embodiments, a method of manufacturing an IC includes: constructing a plurality of gate structures on a plurality of transistor features located in a semiconductor substrate, thereby forming a multi-stage VCO cell between a first dummy gate structure and a second dummy gate structure of the plurality of gate structures; and forming electrical connections including a feedback path and a connection from each of the plurality of stages to a temperature-dependent voltage source, thereby forming a VCO including the VCO cell; wherein forming the multi-stage VCO cell includes: forming an array of inverters between the first dummy gate structure and the second dummy gate structure, and the array includes a total number of rows equal to 1, 2, or 4. In some embodiments, forming the multi-stage VCO cell includes: forming a third dummy gate structure and a fourth dummy gate structure between the first dummy gate structure and the second dummy gate structure; forming a first subset of the array of inverters between the first dummy gate structure and the third dummy gate structure; and forming a second subset of the array of inverters between the second dummy gate structure and the fourth dummy gate structure, and constructing the plurality of gate structures includes: forming a voltage source between the third dummy gate structure and the fourth dummy gate structure. In some embodiments, forming the multi-stage VCO cell includes: constructing a fifth dummy gate structure between the voltage source and the third dummy gate structure; and constructing a sixth dummy gate structure between the voltage source and the fourth dummy gate structure. In some embodiments, the method includes forming an electrical connection from the VCO to a frequency measurement circuit.

[0178] In some embodiments, a method for generating an IC layout includes: arranging a multi-stage VCO cell in the IC layout, wherein the multi-stage VCO cell includes an array of inverters located between a first dummy gate region and a second dummy gate region, and the array includes a total of one, two, or four rows; configuring electrical connections from a temperature-dependent voltage source to each stage of the VCO cell; and storing the IC layout in a memory device. In some embodiments, the VCO cell further includes a third dummy gate region and a fourth dummy gate region located between the first dummy gate region and the second dummy gate region, a first subset of the array of inverters is located between the first dummy gate region and the third dummy gate region, a second subset of the array of inverters is located between the second dummy gate region and the fourth dummy gate region, and configuring electrical connections from the temperature-dependent voltage source to each stage of the VCO cell includes configuring electrical connections from the voltage source located between the third dummy gate region and the fourth dummy gate region. In some embodiments, the VCO cell includes a fifth dummy gate region located between the voltage source and the third dummy gate region, and a sixth dummy gate region located between the voltage source and the fourth dummy gate region. In some embodiments, the third and fifth dummy gate regions are offset from each other by a first multiple of the gate pitch, and the fourth and sixth dummy gate regions are offset from each other by a second multiple of the gate pitch.

[0179] It will be readily apparent to those skilled in the art that one or more of the embodiments of the present disclosure achieve one or more of the advantages described above. After reading the above description, those skilled in the art will be able to realize various variations, equivalent substitutions, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit (IC), comprising: a voltage source configured to generate a first voltage having a temperature-dependent voltage level; as well as a voltage controlled oscillator (VCO) comprising a feedback path and a first VCO unit configured to receive the first voltage, in, The first VCO unit comprises a series of stages, A first stage in the series of stages is configured to output a first signal inside the first VCO unit based on a voltage level of the first voltage and an oscillation signal propagating on the feedback path, and A last stage in the series of stages is configured to output a second signal external to the first VCO cell based on the first signal and a voltage level of the first voltage.

2. The IC according to claim 1, wherein The first VCO unit includes a first dummy gate structure and a second dummy gate structure, each stage in the series of stages includes an inverter configured to receive the first voltage, Corresponding inverters are arranged in an array between the first dummy gate structure and the second dummy gate structure, and The array comprises a total number of rows equal to 1, 2 or 4.

3. The IC according to claim 2, wherein: The first VCO unit further includes a third dummy gate structure and a fourth dummy gate structure located between the first dummy gate structure and the second dummy gate structure. a first subset of the array of inverters is located between the first dummy gate structure and the third dummy gate structure, A second subset of the array of inverters is located between the second dummy gate structure and the fourth dummy gate structure, and The voltage source is located between the third dummy gate structure and the fourth dummy gate structure.

4. The IC of claim 3 , further comprising: a fifth dummy gate structure, located between the voltage source and the third dummy gate structure and offset from the third dummy gate structure by a first multiple of the gate pitch; as well as A sixth dummy gate structure is located between the voltage source and the fourth dummy gate structure and is offset from the fourth dummy gate structure by a second multiple of the gate pitch.

5. The IC according to claim 1, wherein Each stage in the series of stages includes first and second PMOS transistors and first and second NMOS transistors coupled in series between a power supply node configured to have a power supply voltage and a reference voltage node configured to have a reference voltage, The first PMOS transistor is coupled to the power supply node and includes a gate configured to receive the reference voltage, the first NMOS transistor being coupled to the reference voltage node and including a gate configured to receive the first voltage, The second PMOS transistor and the second NMOS transistor of the first stage are coupled between the first PMOS transistor and the first NMOS transistor and include gates configured to receive the oscillation signal, and The second PMOS transistor and the NMOS transistor of the final stage are coupled between the first PMOS transistor and the NMOS transistor, and include gates configured to receive the first signal or the third signal inside the VCO cell.

6. The IC according to claim 5, wherein the series of stages comprising a first inner stage and a second inner stage, The second PMOS transistor and the second NMOS transistor of the first internal stage include gates configured to receive the first signal, and are configured to output a fourth signal inside the first VCO unit based on the first signal and a voltage level of the first voltage, and The second PMOS transistor and the second NMOS transistor of the second internal stage include gates configured to receive the fourth signal, and are configured to output the third signal based on the fourth signal and a voltage level of the first voltage.

7. The IC according to claim 6, wherein: Each of the first inner stage and the second inner stage further comprises: a third PMOS transistor and a third NMOS transistor, the third PMOS transistor being coupled between the first PMOS transistor and the second PMOS transistor, the third NMOS transistor being coupled between the first NMOS transistor and the second NMOS transistor, in, The third PMOS transistor and the third NMOS transistor include gates coupled to gates of the second PMOS transistor and the second NMOS transistor, and Source terminals of the second PMOS transistor and the second NMOS transistor are coupled to each other and to drain terminals of the third PMOS transistor and the third NMOS transistor.

8. The IC according to claim 6, wherein The series of stages includes a plurality of additional inner stages coupled between the first inner stage and the second inner stage.

9. A method of manufacturing an integrated circuit (IC), the method comprising: constructing a plurality of gate structures on a plurality of transistor features located in a semiconductor substrate, thereby forming a multi-stage voltage controlled oscillator (VCO) cell between a first dummy gate structure and a second dummy gate structure of the plurality of gate structures; as well as forming electrical connections including a feedback path and a connection from each of the plurality of stages to a temperature dependent voltage source, thereby forming a VCO including the VCO cell; in, Forming the multi-stage VCO unit includes forming an array of inverters between the first dummy gate structure and the second dummy gate structure, and The array comprises a total number of rows equal to 1, 2 or 4.

10. A method for generating an integrated circuit (IC) layout diagram, the method comprising: In the IC layout diagram, a multi-stage VCO unit is arranged, wherein The multi-stage VCO cell includes an array of inverters located between a first dummy gate region and a second dummy gate region, and The array comprises a total of 1, 2 or 4 rows; configuring electrical connections from a temperature-dependent voltage source to each stage of the VCO cell; as well as The IC layout diagram is stored in a storage device.

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