Display device

Abstract

A display device includes a display panel including a main area including a display area and a non-display area, and a sub-area including a circuit layer, an element layer, an encapsulation layer, and a touch sensor layer, the non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged, a bonding area surrounding the dam area, and a dam area disposed between one side of the main area and the bonding area, and the display panel further includes: a sensing transmission line electrically connected to the touch sensor layer and extending to the sub-area; a ground line adjacent to one of the sensing transmission lines; a bank disposed in the bank area and adjacent to the ground line; and a first electrostatic shielding portion overlapping the bank and electrically connected to the ground line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0032785 filed on March 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, the demand for display devices that can present images in various ways has increased significantly. For example, display devices have now become an integral part of various electronic products such as smartphones, digital cameras, portable computers, navigation systems and smart TVs.

[0005] The display device may be a flat panel type such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including micro light-emitting elements.

[0006] Organic light-emitting display devices generate images using light-emitting elements, each of which includes a light-emitting layer made of an organic light-emitting material. This self-emission technology enables organic light-emitting display devices to outperform other display technologies in aspects such as power consumption, response speed, luminous efficiency, brightness, and viewing angle.

[0007] The display device may have a display area and a non-display area surrounding the display area on one surface where an image is displayed. Within the display area, emission areas that emit light with various brightness and colors may be arranged. Summary of the Invention

[0008] A substrate of the display device may include a main region including a display region and a non-display region, and a sub-region protruding from one side of the main region.

[0009] The signal pads to which the circuit board is coupled may be provided in the secondary region of the substrate. Alternatively, a display driver circuit for supplying data signals may be installed in the secondary region. Accordingly, the display device may include wiring provided in the non-display area of ​​the primary region and extending to the secondary region.

[0010] The display device may further include: a shielding layer covering the bank disposed adjacent to one edge of the main area.

[0011] Because the shielding layer is adjacent to one edge of the main area and is designed as an island-shaped conductive layer, any static electricity introduced from the edge of the main area can be concentrated at the shielding layer.

[0012] However, the wiring extending to the secondary area is arranged along the boundary between the primary and secondary areas, making them susceptible to damage from static electricity introduced from the edge of the primary area or concentrated at the shielding layer. This can have a negative impact on the display quality and lifespan of the display device.

[0013] Embodiments of the present disclosure provide a display device that can reduce wiring damage caused by static electricity introduced from an edge of a main area.

[0014] According to an embodiment of the present disclosure, a display device is provided, which includes: a display panel including a main area and a sub-area protruding from one side of the main area, wherein the display panel includes a circuit layer arranged on a substrate, an element layer arranged on the circuit layer, an encapsulation layer arranged on the element layer, and a touch sensor layer arranged on the encapsulation layer, the main area includes a display area in which an emission area is arranged and a non-display area arranged adjacent to the display area, the non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged, a bonding area surrounding the dam area, and a levee area arranged between the side of the main area and the bonding area, and the display panel further includes: a sensing transmission line electrically connected to the touch sensor layer and extending to the sub-area; a ground line adjacent to one of the sensing transmission lines; a levee arranged in the levee area and adjacent to the ground line; and a first electrostatic shielding portion overlapping the levee and electrically connected to the ground line.

[0015] The touch sensor layer includes: a touch buffer layer overlapping the encapsulation layer; a first touch conductive layer arranged on the touch buffer layer; a touch interlayer insulating layer overlapping the first touch conductive layer; a second touch conductive layer arranged on the touch interlayer insulating layer; and a touch planarization layer overlapping the second touch conductive layer. The ground line includes: a first ground layer arranged in the first touch conductive layer; and a second ground layer arranged in the second touch conductive layer and electrically connected to the first ground layer through a hole penetrating the touch interlayer insulating layer. The first electrostatic shielding part is arranged in the first touch conductive layer and includes a main shielding part and a ground connection part. The main shielding part overlaps the embankment. The ground connection part extends from the main shielding part to the first ground layer and contacts the first ground layer.

[0016] The element layer includes a light-emitting element arranged in the emission area, and the circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting element; a data line configured to transmit a data signal to the light-emitting pixel driver; and data supply lines electrically connected to the data lines, respectively, arranged in the non-display area and extending to the sub-area, the data supply lines overlapping with a portion of the embankment, and the sensing transmission line is arranged in a portion of the embankment area adjacent to a side of the sub-area along the first direction, crosses the data supply lines, and is spaced apart from the embankment.

[0017] The circuit layer includes: a semiconductor layer, arranged on a substrate; a first gate insulating layer, overlapping with the semiconductor layer; a first gate conductive layer, arranged on the first gate insulating layer; a second gate insulating layer, overlapping with the first gate conductive layer; a second gate conductive layer, arranged on the second gate insulating layer; an interlayer insulating layer, overlapping with the second gate conductive layer; a first planarization layer, arranged on the interlayer insulating layer; and a second planarization layer, arranged on the first planarization layer, wherein the data supply line is arranged in the first gate conductive layer or the second gate conductive layer.

[0018] The element layer includes: anode electrodes, which are respectively arranged in the emission area; a pixel defining layer, which is arranged in the non-emission area, and the non-emission area is arranged between the emission areas and overlaps with the edge of each of the anode electrodes; a spacer layer, which is arranged on a part of the pixel defining layer; a light-emitting layer, which is respectively arranged on the anode electrode; and a cathode electrode, which is arranged on the pixel defining layer, the spacer layer and the light-emitting layer, wherein the embankment includes: a first embankment layer, which is arranged in the same layer as the first planarization layer; a second embankment layer, which is arranged in the same layer as the second planarization layer; a third embankment layer, which is arranged in the same layer as the pixel defining layer; and a fourth embankment layer, which is arranged in the same layer as the spacer layer, and the first embankment layer and the second embankment layer extend to the sub-area.

[0019] Each of the sensing transmission lines includes: a first sensing transmission layer disposed in the first touch conductive layer; and a second sensing transmission layer disposed in the second touch conductive layer and electrically connected to the first sensing transmission layer through a hole penetrating the touch interlayer insulating layer.

[0020] The display panel further includes a second electrostatic shielding portion disposed in the bank region and overlapping the data supply line, and the second electrostatic shielding portion is disposed in the second touch conductive layer.

[0021] The second electrostatic shielding portion is electrically connected to the first electrostatic shielding portion through a hole penetrating the touch interlayer insulating layer.

[0022] The display panel further includes a third electrostatic shielding portion arranged in the embankment area and overlapping the sensing transmission line, a portion of each of the sensing transmission lines crossing the embankment area is composed only of the first sensing transmission layer, and the third electrostatic shielding portion is arranged in the second touch conductive layer.

[0023] The third electrostatic shield portion is in contact with the second ground layer and is electrically connected to the ground line and the first electrostatic shield portion.

[0024] At least one dam portion includes two or more dam layers, each of the two or more dam layers is arranged in the same layer as one of the first planarization layer, the second planarization layer, the pixel definition layer and the spacer layer, the thickness of the dam is greater than or equal to the thickness of the at least one dam portion, the encapsulation layer includes: a first encapsulation layer, overlapping with the cathode electrode and including an inorganic insulating material; a second encapsulation layer, arranged on the first encapsulation layer and including an organic insulating material; and a third encapsulation layer, overlapping with the second encapsulation layer and including an inorganic insulating material, the second encapsulation layer is arranged in an area surrounded by the at least one dam portion, the first encapsulation layer contacts the interlayer insulating layer in the bonding area, the third encapsulation layer contacts the first encapsulation layer or the interlayer insulating layer in the bonding area, the dam is spaced apart from the encapsulation layer, and the touch buffer layer includes an inorganic insulating material and contacts the interlayer insulating layer in the bonding area and in a separation area between the dam and the encapsulation layer.

[0025] The sub-region includes a bending area transformed into a bending shape, a first sub-region arranged between the side of the main region and the first side of the bending area, and a second sub-region extending from the second side of the bending area, and the display panel further includes: a bending hole, which is arranged in the bending area and penetrates the buffer layer, the first gate insulation layer, the second gate insulation layer and the interlayer insulation layer; data bending lines, which are arranged in the bending area and are electrically connected to the data supply lines respectively; and sensing bending lines, which are arranged in the bending area and are electrically connected to the sensing transmission lines respectively, and each of the data bending lines and the sensing bending lines is arranged on the first embankment layer.

[0026] The display device further includes: a cover window facing the main area of ​​the display panel; an adhesive layer configured to fix the cover window on the display panel; and a bending cover layer spaced apart from the adhesive layer and overlapping with the bending area, wherein the main area includes: at least one folding area that is bent or unfolded about a folding axis extending in one direction; and a plurality of non-folding areas arranged on both sides of the at least one folding area, and a separation area between the adhesive layer and the bending cover layer overlaps with the embankment area.

[0027] According to an embodiment of the present disclosure, a display device is provided, which includes: a display panel including a main area and a sub-area protruding from one side of the main area, wherein the display panel includes a circuit layer arranged on a substrate, an element layer arranged on the circuit layer, an encapsulation layer arranged on the element layer, and a touch sensor layer arranged on the encapsulation layer, the main area includes a display area in which an emission area is arranged and a non-display area adjacent to the display area, the non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged, a bonding area surrounding the dam area, and a levee area arranged between the side of the main area and the bonding area, and the display panel further includes: a sensing transmission line electrically connected to the touch sensor layer and extending to the sub-area; a ground line adjacent to one of the sensing transmission lines; a levee arranged in the levee area, having a thickness greater than a thickness of at least one dam portion, and adjacent to the ground line; and a first electrostatic shielding portion overlapping with the levee and electrically connected to the ground line, and the first electrostatic shielding portion includes a main shielding portion overlapping with the levee and a ground connection portion arranged between the main shielding portion and the ground line.

[0028] The touch sensor layer includes: a touch buffer layer overlapping the encapsulation layer; a first touch conductive layer arranged on the touch buffer layer; a touch interlayer insulating layer overlapping the first touch conductive layer; a second touch conductive layer arranged on the touch interlayer insulating layer; and a touch planarization layer overlapping the second touch conductive layer. Each of the sensing transmission lines includes: a first sensing transmission layer arranged in the first touch conductive layer; and a second sensing transmission layer arranged in the second touch conductive layer and electrically connected to the first sensing transmission layer through a hole penetrating the touch interlayer insulating layer. The ground line includes: a first ground layer arranged in the first touch conductive layer; and a second ground layer arranged in the second touch conductive layer and electrically connected to the first ground layer through a hole penetrating the touch interlayer insulating layer. The first electrostatic shielding portion is arranged in the first touch conductive layer, and the grounding connection portion of the first electrostatic shielding portion is in contact with the first ground layer.

[0029] The element layer includes a light-emitting element arranged in the emission area, and the circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting element; a data line configured to transmit a data signal to the light-emitting pixel driver; and data supply lines electrically connected to the data lines, respectively, arranged in the non-display area and extending to the sub-area, the data supply lines overlapping a portion of the embankment, and the sensing transmission line is arranged in a portion of the embankment area adjacent to one side of the sub-area, crossing the data supply lines, and spaced apart from the embankment.

[0030] The display panel further includes a second electrostatic shielding portion arranged in the embankment area and overlapping the data supply line, the second electrostatic shielding portion is arranged in the second touch conductive layer, and the second electrostatic shielding portion is electrically connected to the ground line and the first electrostatic shielding portion through a hole penetrating the touch interlayer insulating layer.

[0031] The display panel further includes a third electrostatic shielding portion arranged in the embankment area and overlapping the sensing transmission line, a portion of each of the sensing transmission lines crossing the embankment area is composed only of the first sensing transmission layer, and the third electrostatic shielding portion is arranged in the second touch conductive layer and is electrically connected to the ground line and the first electrostatic shielding portion.

[0032] The circuit layer includes: a semiconductor layer, which is arranged on a substrate; a first gate insulating layer, overlapping with the semiconductor layer; a first gate conductive layer, which is arranged on the first gate insulating layer; a second gate insulating layer, which overlaps with the first gate conductive layer; a second gate conductive layer, which is arranged on the second gate insulating layer; an interlayer insulating layer, which overlaps with the second gate conductive layer; a first planarization layer, which is arranged on the interlayer insulating layer; and a second planarization layer, which is arranged on the first planarization layer. The element layer includes: anode electrodes, which are respectively arranged in the emission areas; a pixel defining layer, which is arranged in the non-emission areas, the non-emission areas are arranged between the emission areas and overlap with the edge of each of the anode electrodes; a spacer layer, which is arranged on a part of the pixel defining layer; a light-emitting layer, which is respectively arranged on the anode electrodes; and a cathode electrode, which is arranged on the pixel defining layer, the spacer layer and the light-emitting layer. The encapsulation layer includes: a first encapsulation layer, which overlaps with the cathode electrode and contains an inorganic insulating material; a second encapsulation layer, which overlaps with the cathode electrode and contains an inorganic insulating material; a second encapsulation layer, which overlaps with the cathode electrode and contains an inorganic insulating material. A second encapsulation layer is provided on the first encapsulation layer and includes an organic insulating material; and a third encapsulation layer overlaps with the second encapsulation layer and includes an inorganic insulating material. The embankment includes: a first embankment layer provided in the same layer as the first planarization layer; a second embankment layer provided in the same layer as the second planarization layer; a third embankment layer provided in the same layer as the pixel defining layer; and a fourth embankment layer provided in the same layer as the spacer layer, and the first embankment layer and the second embankment layer extend to the sub-area. The data supply line is provided in the first gate conductive layer or the second gate conductive layer. The second encapsulation layer is provided in an area surrounded by at least one dam portion. The first encapsulation layer contacts the interlayer insulating layer in the bonding area. The third encapsulation layer contacts the first encapsulation layer or the interlayer insulating layer in the bonding area. The embankment is spaced apart from the encapsulation layer. The touch buffer layer includes an inorganic insulating material and contacts the interlayer insulating layer in the bonding area and in a separation area between the embankment and the encapsulation layer.

[0033] The sub-region includes a bending area transformed into a bending shape, a first sub-region arranged between the side of the main region and the first side of the bending area, and a second sub-region extending from the second side of the bending area, the main region includes: at least one folding region, which is bent or unfolded about a folding axis extending in one direction; and a plurality of non-folding regions, which are arranged on both sides of at least one folding region, the display device further includes: a cover window, facing the main region of the display panel; an adhesive layer, configured to fix the cover window on the display panel; and a bending covering layer, spaced apart from the adhesive layer and overlapping with the bending area, wherein the separation area between the adhesive layer and the bending covering layer overlaps with the embankment area.

[0034] According to an embodiment of the present disclosure, the first electrostatic shielding portion is electrically connected to the ground line. This allows static electricity concentrated at the first electrostatic shielding portion to be quickly and effectively discharged through the ground line, thereby reducing the possibility of wiring damage in the bank area due to static electricity.

[0035] Therefore, the display quality and lifespan of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0037] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0038] Figure 2 It is an icon Figure 1 A plan view of a display device;

[0039] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA';

[0040] Figure 4 It shows Figure 3 A plan view of the substrate;

[0041] Figure 5 is a diagram illustrating a method according to an embodiment Figure 4 a layout diagram of part B;

[0042] Figure 6 It shows Figure 5 Equivalent circuit diagram of the light-emitting pixel driver;

[0043] Figure 7 is a diagram illustrating a method according to an embodiment Figure 3 A plan view of a touch sensor layer;

[0044] Figure 8 It shows Figure 7 an enlarged view of portion D;

[0045] Figure 9 It is along Figure 8 A cross-sectional view taken along line EE';

[0046] Figure 10 is a diagram showing a method according to an embodiment of the present invention. Figure 4 a layout diagram of part C;

[0047] Figure 11 It is along Figure 10 A cross-sectional view taken along line F-F';

[0048] Figure 12 It is along Figure 10 A cross-sectional view taken along line G-G';

[0049] Figure 13 is a diagram showing a method according to an embodiment of the present invention. Figure 4 a layout diagram of part C;

[0050] Figure 14 and Figure 15 According to the embodiment of the invention Figure 13 A cross-sectional view taken along line G-G';

[0051] Figure 16 is a diagram showing a method according to an embodiment of the present invention. Figure 4 a layout diagram of part C;

[0052] Figure 17 It is along Figure 16 A cross-sectional view taken along line H-H';

[0053] Figure 18 It is along Figure 16 A cross-sectional view taken along line G-G';

[0054] Figure 19 is a diagram showing a method according to an embodiment of the present invention. Figure 4 a layout diagram of part C;

[0055] Figure 20 It is along Figure 19 A cross-sectional view taken along line G-G';

[0056] Figure 21 and Figure 22 is a perspective view showing an unfolded state and a folded state of a display device according to an embodiment; and

[0057] Figure 23 It is along Figure 22 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0058] Embodiments will now be described in more detail with reference to the accompanying drawings. However, these embodiments may take various forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals are used to represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0059] In order to better focus on the embodiments of the present disclosure, some components not related to the description may be omitted.

[0060] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0061] In addition, the phrase "in a plan view" refers to viewing an object portion from above, while "in a schematic cross-sectional view" refers to viewing a schematic cross-section of an object portion that has been cut vertically from the side. The term "overlapping" or "overlapping" means that the first object can be above, below or to the side of the second object, and vice versa. In addition, the term "overlapping" can include various meanings such as layered, stacked, facing, extending over, covering or partially covering, or any other suitable term understood by a person of ordinary skill in the art. The expression "non-overlapping" can imply meanings such as "separated from," "set to the side of," "deviating from," or other suitable equivalents as recognized by a person of ordinary skill in the art. The term "facing" indicates that the first object can be directly or indirectly opposite to the second object. If a third object is between the first object and the second object, the first object and the second object can still be considered to be indirectly opposite or facing each other.

[0062] Spatially relative terms such as "below," "beneath," "under," "above," or "upper" are used herein to facilitate describing the relationship between one element or component and another element or component as illustrated in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the devices illustrated in the accompanying drawings are flipped over, a device that is "below" or "beneath" another device may be "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. Devices may also be oriented in other directions, and therefore spatially relative terms may be interpreted differently depending on the orientation.

[0063] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “comprising,” and / or “having” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0064] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, when discussing a "first element" in the description, it can be referred to as a "second element" or a "third element," and the "second element" and "third element" can be named in a similar manner.

[0065] As used herein, the term "about" or "approximately" is inclusive of the stated value and refers to an acceptable range of deviation determined by one of ordinary skill in the art. This range takes into account problematic measurements and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0066] Throughout the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or." Throughout the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0067] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (e.g., terms defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and, unless explicitly defined in the specification, should not be interpreted in an idealized or overly formal sense.

[0068] Figure 1 is a perspective view illustrating a display device according to an embodiment. Figure 2 It is an icon Figure 1 A plan view of a display device. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'.

[0069] refer to Figure 1 and Figure 2 The display device 10, which is a device for displaying moving images or still images, can be used as a display screen for various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs).

[0070] The display device 10 may be an organic light-emitting display device such as an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro-light-emitting display device using a micro- or nano-light-emitting diode (LED). In the following description, it is assumed that the display device 10 is an organic light-emitting display device. However, the present disclosure is not limited thereto and may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0071] The display device 10 may be flat, but is not limited thereto. For example, the display device 10 may include curved portions at the left and right ends that may have a constant or varying curvature. In addition, the display device 10 may be designed to be flexible, allowing it to be bent, folded, or rolled.

[0072] like Figure 1 、 Figure 2 and Figure 3 As shown in FIG, a display device 10 according to an embodiment includes a display panel 100 that emits light from at least one surface.

[0073] The display panel 100 includes a main area MA and a sub-area SBA protruding from one side of the main area MA.

[0074] like Figure 2 As shown in FIG, the main area MA may include a display area DA mainly disposed at the center and a non-display area NDA disposed around the display area DA.

[0075] In a plan view, the display area DA may have a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined curvature or may be right angles. The planar shape of the display area DA is not limited to a rectangle and may also be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0076] The non-display area NDA may be disposed at an edge of the main area MA to surround the display area DA.

[0077] The sub-area SBA may extend in the second direction DR2 from a portion of one side of the main area MA extending in the first direction DR1.

[0078] The sub-area SBA may include a bending area BA (see FIG. Figure 3 ).

[0079] Figure 2 and Figure 3 The figure shows the bending area BA in the sub-area SBA (see Figure 3 ) is a display device 10 that is transformed into a bent shape.

[0080] like Figure 3 and Figure 4 As shown in (see also Figure 23 ), the sub-area SBA may include a bending area BA transformed into a bending shape, a first sub-area SB1 set between one side of the main area MA and one side of the bending area BA, and a second sub-area SB2 extending from the other side of the bending area BA.

[0081] When the bending area BA is transformed into a bent shape, the second sub-area SB2 may be disposed on the rear surface of the display panel 100 and may overlap with the main area MA.

[0082] The display driving circuit 200 provided as an integrated circuit (IC) chip may be mounted in the second sub-area SB2 .

[0083] The circuit board 300 may be coupled to one side of the second sub-area SB2 .

[0084] The touch driving circuit 400 , provided as an integrated circuit (IC) chip, may be mounted on the circuit board 300 .

[0085] refer to Figure 3 According to the embodiment, the display panel 100 of the display device 10 may include a substrate 110, a circuit layer 120 provided on the substrate 110, an element layer 130 provided on the circuit layer 120, an encapsulation layer 140 provided on the element layer 130, and a touch sensor layer 150 provided on the encapsulation layer 140.

[0086] The display panel 100 of the display device 10 according to the embodiment may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0087] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled.

[0088] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0089] The substrate 110 may include a main area MA and a sub-area SBA.

[0090] Figure 4 It shows Figure 3 A plan view of the substrate.

[0091] refer to Figure 4, the display panel 100 of the display device 10 according to the embodiment may include a substrate 110, and the substrate 110 may include a main area MA corresponding to a display surface and a sub-area SBA extending from one side of the main area MA.

[0092] The main area MA may include a display area DA located mainly at the center and a non-display area NDA located at the periphery, surrounding the display area DA.

[0093] The non-display area NDA may include at least one dam portion DM (see FIG. Figure 10 ) of the dam area DMA, the bonding area JNA surrounding the dam area DMA, and the bank area BNA located between one side of the main area MA and the bonding area JNA.

[0094] The dam area DMA may be spaced apart from the display area DA.

[0095] The sub-area SBA may include a bending area BA transformed into a bending shape, a first sub-area SB1 disposed between a first side of the bending area BA and the main area MA, and a second sub-area SB2 connected to a second side of the bending area BA.

[0096] When the bending area BA is transformed into the bending shape, the second sub-region SB2 may be disposed under the substrate 110 and overlapped with the main region MA.

[0097] The display driving circuit 200 may be installed in the second sub-area SB2. For example, the display driving circuit 200 may be installed at a central portion of the second sub-area SB2.

[0098] In the second sub-area SB2 , signal pads SPD to which the circuit board 300 is coupled may be provided.

[0099] Figure 5 is a diagram illustrating a method according to an embodiment Figure 4 Layout diagram of part B.

[0100] refer to Figure 5 The emission area EA may be arranged in the main area MA of the display panel 100 of the display device 10 according to the embodiment (see Figure 4 ) display area DA (see Figure 4 )middle.

[0101] In addition, the display area DA may include a non-emission area disposed in a gap between the emission areas EA.

[0102] Component layer 130 (see Figure 3 ) may include light emitting elements LE respectively arranged in the emission area EA (see Figure 6 and Figure 9 ).

[0103] Circuit layer 120 (see Figure 3 ) may include electrically connected to the element layer 130 (see Figure 3 )'s light-emitting pixel driver EPD.

[0104] The light emitting pixel drivers EPD may be arranged side by side in the first direction DR1 and the second direction DR2 in the display area DA.

[0105] In a plan view, the emission area EA may have a rhombus shape or a rectangular shape. However, this is only an example, and the planar shape of the emission area EA according to the embodiment is not limited to Figure 5 In other words, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular or elliptical shape including edges of curved lines.

[0106] The emission area EA may include a first emission area EA1 that emits light of a first color in a predetermined wavelength band, a second emission area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0107] For example, the first color may be red having a wavelength band of approximately 600 nm to 750 nm, the second color may be green having a wavelength band of approximately 480 nm to 560 nm, and the third color may be blue having a wavelength band of approximately 370 nm to 460 nm.

[0108] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0109] The second emission regions EA2 may be arranged side by side with each other in at least one of the first direction DR1 and the second direction DR2.

[0110] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in diagonal directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2 .

[0111] Pixels PX displaying their own brightness and color may be provided by the first, second, and third emission areas EA1, EA2, and EA3 that are adjacent to each other among the emission areas EA.

[0112] In other words, the pixel PX may serve as a basic unit for displaying various colors including white at a predetermined brightness.

[0113] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Accordingly, each of the pixels PX may display various colors by combining light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other.

[0114] Figure 6 It shows Figure 5 Equivalent circuit diagram of the light-emitting pixel driver.

[0115] refer to Figure 6 , component layer 130 (see Figure 3 ) can be electrically connected to the circuit layer 120 (see Figure 3 ) between one of the light-emitting pixel drivers EPD and the second power source ELVSS.

[0116] In other words, the anode electrode of the light emitting element LE is electrically connected to the light emitting pixel driver EPD, and the second power ELVSS lower than the first power ELVDD may be applied to the cathode electrode of the light emitting element LE.

[0117] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode and the cathode electrode of the light emitting element LE.

[0118] Circuit layer 120 (see Figure 3 ) may include a first power line VDL for transmitting a first power source ELVDD, a gate initialization voltage line VGIL for transmitting a gate initialization voltage VGINT, and an anode initialization voltage line VAIL for transmitting an anode initialization voltage VAINT.

[0119] Circuit layer 120 (see Figure 3 ) may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, and a gate control line GCL for transmitting a gate control signal GC.

[0120] Circuit layer 120 (see Figure 3 ) may include one of the light emitting pixel drivers EPD configured to generate a driving current for driving the light emitting element LE, a first transistor T1, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one pixel capacitor PC1.

[0121] The first transistor T1 may be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (eg, source electrode) of the first transistor T1. The second node N2 is electrically connected to a second electrode (eg, drain electrode) of the first transistor T1.

[0122] The first node N1 may be electrically connected to the first power line VDL through the fifth transistor T5 .

[0123] The second node N2 may be electrically connected to the anode electrode of the light emitting element LE through the sixth transistor T6 .

[0124] The pixel capacitor PC1 may be electrically connected between the first power line VDL and a third node N3. The third node N3 is electrically connected to the gate electrode of the first transistor T1.

[0125] In other words, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the pixel capacitor PC1 .

[0126] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained at the voltage stored in the pixel capacitor PC1 .

[0127] The second transistor T2 may be electrically connected between the data line DL and the first node N1 .

[0128] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0129] In other words, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0130] The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL.

[0131] The fifth transistor T5 may be electrically connected between the first node N1 and the first power line VDL.

[0132] The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light emitting element LE.

[0133] In other words, the fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0134] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LE.

[0135] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0136] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may correspond to a difference between the first power source ELVDD and the data signal Vdata.

[0137] In this case, when the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (eg, gate-source voltage difference) reaches or exceeds the threshold voltage, the first transistor T1 may be turned on to generate a drain-source current corresponding to the data signal Vdata.

[0138] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first power source ELVDD, the first transistor T1, the light emitting element LE, and the second power source ELVSS can be connected in series. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the driving current of the light emitting element LE.

[0139] Therefore, the light emitting element LE may emit light with brightness corresponding to the data signal Vdata.

[0140] The third transistor T3 may be electrically connected between the second node N2 and the third node N3. In other words, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0141] The third transistor T3 may include a plurality of sub-transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32.

[0142] A first electrode of the first sub-transistor T31 may be connected to the gate electrode of the first transistor T1, a second electrode of the first sub-transistor T31 may be connected to the first electrode of the second sub-transistor T32, and a second electrode of the second sub-transistor T32 may be connected to the second electrode of the first transistor T1.

[0143] In this manner, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to leakage current from the third transistor T3 when the third transistor T3 is not turned on.

[0144] The first sub-transistor T31 and the second sub-transistor T32 may be turned on by a scan write signal GW of a scan write line GWL.

[0145] When the first sub-transistor T31 and the second sub-transistor T32 are turned on, a voltage difference between the second node N2 and the third node N3 may be initialized.

[0146] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. In other words, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0147] The fourth transistor T4 may include a plurality of sub-transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42.

[0148] A first electrode of the third sub-transistor T41 may be connected to the gate electrode of the first transistor T1 , a second electrode of the third sub-transistor T41 may be connected to a first electrode of the fourth sub-transistor T42 , and a second electrode of the fourth sub-transistor T42 may be connected to the gate initialization voltage line VGIL.

[0149] In this way, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to the leakage current of the fourth transistor T4 when the fourth transistor is not turned on.

[0150] The third sub-transistor T41 and the fourth sub-transistor T42 may be turned on by a scan initialization signal GI of a scan initialization line GIL.

[0151] When the third sub-transistor T41 and the fourth sub-transistor T42 are turned on, the potential of the third node N3 may be initialized to the gate initialization voltage VGINT.

[0152] The seventh transistor T7 may be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. In other words, the seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the anode initialization voltage line VAIL.

[0153] The seventh transistor T7 may be turned on by the gate control signal GC of the gate control line GCL.

[0154] When the seventh transistor T7 is turned on, the potential of the fourth node N4 may be initialized to the anode initialization voltage VAINT.

[0155] like Figure 6 As shown in , according to an embodiment, the first to seventh transistors T1 to T7 may be provided as P-type MOSFETs. However, this is merely an example, and some of the first to seventh transistors T1 to T7 may be provided as N-type MOSFETs. For example, the third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0156] Figure 7 is a diagram illustrating a method according to an embodiment Figure 3 A plan view of the touch sensor layer. Figure 8 It shows Figure 7An enlarged view of portion D of FIG. Figure 9 It is along Figure 8 A cross-sectional view taken along line EE'.

[0157] Figure 7 The touch sensor layer 150 using a capacitance method is shown. In this case, the touch drive circuit 400 (see Figure 3 ) can detect touch based on fluctuations in capacitance. However, for ease of description, Figure 7 The illustration in FIG is taken as an example, and the touch sensor layer 150 according to the embodiment is not limited to Figure 7 The structure shown in .

[0158] To keep it simple, Figure 7 Only a portion of the components of touch sensor layer 150 are illustrated.

[0159] refer to Figure 7 , the touch sensor layer 150 may be provided in the main area MA. The touch sensor layer 150 may include a touch sensing area TSA for sensing a user's touch and a touch peripheral area TPA around the touch sensing area TSA.

[0160] The touch sensing area TSA is wider than the display area DA and may overlap the display area DA. Accordingly, the touch peripheral area TPA, which is the periphery of the touch sensing area TSA, may be similar to the non-display area NDA, which is the periphery of the display area DA.

[0161] For example, the touch sensing area TSA may overlap the display area DA and an edge of the non-display area NDA in contact with the display area DA. In this case, the touch peripheral area TPA may overlap the remaining portion of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0162] The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE arranged in a matrix within the touch sensing area TSA to generate mutual capacitance, and sensing transmission lines SENL provided in the touch peripheral area TPA.

[0163] The sensor electrodes SE may include driving electrodes TE (touch driving electrodes) to which driving signals are applied and sensing electrodes RE (receiving electrodes) that detect a voltage charged in a mutual capacitance with the driving electrodes TE.

[0164] The sensing transmission line SENL may include a first driving line TL1 , a second driving line TL2 , and a sensing line RL.

[0165] Each of the first and second driving lines TL1 and TL2 may be electrically connected to two or more driving electrodes TE extending in the second direction DR2 among the driving electrodes TE.

[0166] The first driving line TL1 may extend from a first edge of the touch sensing area TSA, which is positioned adjacent to the sub-area SBA, to the sub-area SBA.

[0167] The second driving line TL2 may extend from a second edge of the touch sensing area TSA opposite to the first edge along a third edge of the touch sensing area TSA between the first and second edges to the sub-area SBA.

[0168] The sensing line RL may be electrically connected to two or more sensing electrodes RE extending in the first direction DR1 among the sensing electrodes RE.

[0169] The sensing electrodes RE may be arranged side by side in the first direction DR1 , and the sensing electrodes RE adjacent to each other in the first direction DR1 may be electrically connected to each other through the protrusions in the first direction DR1 .

[0170] The driving electrodes TE may be arranged side by side in the second direction DR2. Adjacent driving electrodes TE in the second direction DR2 may be connected to each other by bridge electrodes BE extending in the second direction DR2 (see FIG. Figure 8 ) are electrically connected to each other.

[0171] Each of the driving electrode TE and the sensing electrode RE may be shaped to surround the dummy electrode DE located at the center thereof.

[0172] Each of the dummy electrodes DE may be spaced apart from the driving electrode TE or the sensing electrode RE surrounding it. The dummy electrodes DE may be in a floating state.

[0173] Figure 7 The case where each of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE has a rhombus planar shape is shown, but this is only an example. In other words, the planar shape of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE may be a quadrilateral shape other than a rhombus, a polygonal shape other than a quadrilateral, a circular shape, or an elliptical shape.

[0174] The display panel 100 of the display device 10 according to the embodiment may include a second sub-area SB2 provided in the substrate 110 and connected to the circuit board 300 (see FIG. Figure 3 )’s signal pad SPD.

[0175] The signal pad SPD may include a signal pad electrically connected to the display driving circuit 200 or the circuit layer 120 (see FIG. Figure 3 ) and the touch pads TPD1 and TPD2 electrically connected to the sensing transmission line SENL of the touch sensor layer 150.

[0176] For example, the second sub-area SB2 may include a display pad area DPDA adjacent to the display driving circuit 200 and first and second touch pad areas TPDA1 and TPDA2 disposed at both sides of the display pad area DPDA.

[0177] The display pad DPD may be provided in the display pad area DPDA.

[0178] First touch pads TPD1 electrically connected to the first driving line TL1 and the second driving line TL2 , respectively, may be disposed in the first touch pad area TPDA1 .

[0179] Second touch pads TPD2 electrically connected to the sensing lines RL, respectively, may be disposed in the second touch pad area TPDA2.

[0180] refer to Figure 8 , the touch sensor layer 150 may further include a bridge electrode BE electrically connecting the driving electrodes TE adjacent to each other in the second direction DR2 .

[0181] The bridge electrode BE may be electrically connected to the driving electrode TE through the touch electrode connection hole TCNT1 .

[0182] The driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected to each other through two or more bridge electrodes BE. In this way, the reliability of the electrical connection between the driving electrodes TE may be improved.

[0183] although Figure 8 It is illustrated that two bridging electrodes BE side by side with each other are provided between the driving electrodes TE adjacent to each other in the second direction DR2 , but this is only an example.

[0184] although Figure 8 The bridge electrode having a shape including one bend is illustrated, but this is merely an example.

[0185] The driving electrodes TE and the sensing electrodes RE may be spaced apart from each other.

[0186] The bridging electrode BE may be disposed in a different conductive layer from the driving electrode TE and the sensing electrode RE.

[0187] The drive electrodes TE, the sensing electrodes RE, and the bridging electrodes BE may have a grid structure or a mesh structure in a plan view. The dummy electrodes DE may also have a grid structure or a mesh structure in a plan view. In this way, by reducing the overlapping width of the drive electrodes TE, the sensing electrodes RE, the dummy electrodes DE, and the bridging electrodes BE in the emission area EA, the reduction in the luminous efficiency of the emission area EA caused by these electrodes can be reduced.

[0188] refer to Figure 9The display panel 100 of the display device 10 according to the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110, an element layer 130 on the circuit layer 120, an encapsulation layer 140 on the element layer 130, and a touch sensor layer 150 on the encapsulation layer 140.

[0189] In addition, the display panel 100 of the display device 10 according to the embodiment may further include a polarization layer 160 disposed on the touch sensor layer 150 .

[0190] The circuit layer 120 may include a semiconductor layer SEL (CH1, E11, E21, CH6, E16 and E26) disposed on the substrate 110, a first gate insulating layer 122 covering the semiconductor layer SEL, a first gate conductive layer GCDL1 (G1 and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer GCDL1, a second gate conductive layer GCDL2 (CAE) disposed on the second gate insulating layer 123, an interlayer insulating layer 124 covering the second gate conductive layer GCDL2, a first source-drain conductive layer SDCDL1 (ANCE1) disposed on the interlayer insulating layer 124, a first planarizing layer 125 covering the first source-drain conductive layer SDCDL1, a second source-drain conductive layer SDCDL2 (ANCE2) disposed on the first planarizing layer 125, and a second planarizing layer 126 covering the second source-drain conductive layer SDCDL2.

[0191] The circuit layer 120 may further include a buffer layer 121 covering the substrate 110 .

[0192] In this case, the semiconductor layer SEL may be disposed on the buffer layer 121 .

[0193] The circuit layer 120 may include light emitting pixel drivers EPD corresponding to the emission areas EA, respectively.

[0194] Each of the light emitting pixel drivers EPD may include a first transistor T1, a second transistor T2 to a seventh transistor T7 electrically connected to the first transistor T1 (see FIG. Figure 6 ) and at least one capacitor PC1 (see Figure 6 ).

[0195] Figure 9 Shown Figure 6 The first transistor T1, the sixth transistor T6 and the light emitting element LE of the light emitting pixel driver EPD.

[0196] The semiconductor layer SEL on the buffer layer 121 may include channel portions CH1 and CH6 of each of the first to seventh transistors T1 to T7 provided as P-type MOSFETs, first electrode portions E11 and E16 , and second electrode portions E21 and E26 .

[0197] In each of the first and sixth transistors T1 and T6 , first electrode portions E11 and E16 may be connected to first ends of the channel portions CH1 and CH6 , and second electrode portions E21 and E26 may be connected to second ends of the channel portions CH1 and CH6 .

[0198] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6 .

[0199] The first gate conductive layer GCDL1 on the first gate insulating layer 122 may include gate electrodes G1 and G6 of each of the first to seventh transistors T1 to T7 provided as P-type MOSFETs.

[0200] In the first transistor T1 and the sixth transistor T6 , the gate electrodes G1 and G6 may overlap with the channel portions CH1 and CH6 , respectively.

[0201] exist Figure 6 In the light-emitting pixel driver EPD, like the first transistor T1 and the sixth transistor T6, the second transistor T2, the first sub-transistor T31, the second sub-transistor T32, the third sub-transistor T41, the fourth sub-transistor T42, the fifth transistor T5, and the seventh transistor T7 are all P-type MOSFETs. Therefore, redundant descriptions will be omitted.

[0202] The second gate conductive layer GCDL2 on the second gate insulating layer 123 may include a capacitor electrode CAE.

[0203] The capacitor electrode CAE may overlap with the gate electrode G1 of the first transistor T1 .

[0204] Accordingly, the pixel capacitor PC1 (see Figure 6 ) may be provided by an overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0205] Each of the buffer layer 121 , the first gate insulating layer 122 , the second gate insulating layer 123 , and the interlayer insulating layer 124 may include an inorganic insulating material.

[0206] The first source-drain conductive layer SDCDL1 on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1 .

[0207] The first anode connection electrode ANCE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1 .

[0208] The second source-drain conductive layer SDCDL2 on the first planarization layer 125 may include a second anode connection electrode ANCE2 .

[0209] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 .

[0210] The anode electrode 131 of the element layer 130 may be disposed on the second planarization layer 126 and may be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 .

[0211] Accordingly, the anode electrode 131 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first and second anode connection electrodes ANCE1 and ANCE2 .

[0212] The element layer 130 on the circuit layer 120 may include light emitting elements LE respectively disposed in the emission areas EA1 , EA2 , and EA3 .

[0213] Each of the light emitting elements LE may include a structure in which a light emitting layer 133 is provided between an anode electrode 131 and a cathode electrode 134 facing each other.

[0214] According to an embodiment, the element layer 130 may include an anode electrode 131 respectively arranged in the emission area EA, a pixel defining layer 132 arranged in the non-emission area NEA and covering the edge of the anode electrode 131, a spacer layer 132' arranged on a portion of the pixel defining layer 132, a light emitting layer 133 respectively arranged on the anode electrode 131, and a cathode electrode 134 arranged on the light emitting layer 133, the pixel defining layer 132 and the spacer layer 132'.

[0215] Alternatively, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134 .

[0216] The encapsulation layer 140 may cover the element layer 130 .

[0217] The encapsulation layer 140 is used to prevent oxygen or moisture from penetrating into the element layer 130 and reduce electrical or physical impact on the circuit layer 120 and the element layer 130 .

[0218] The encapsulation layer 140 may include a first encapsulation layer 141 covering the element layer 130 and including an inorganic insulating material, a second encapsulation layer 142 disposed on the first encapsulation layer 141, overlapping the element layer 130 and including an organic insulating material, and a third encapsulation layer 143 disposed on the first encapsulation layer 141, covering the second encapsulation layer 142 and including an inorganic insulating material.

[0219] The touch sensor layer 150 may be disposed on the encapsulation layer 140 .

[0220] The touch sensor layer 150 may include a touch buffer layer 151 disposed on the encapsulation layer 140, a first touch conductive layer TCDL1 (BE) disposed on the touch buffer layer 151, a touch interlayer insulating layer 152 covering the first touch conductive layer TCDL1, a second touch conductive layer TCDL2 (TE and RE) disposed on the touch interlayer insulating layer 152, and a touch planarization layer 153 covering the second touch conductive layer TCDL2.

[0221] The first touch conductive layer TCDL1 on the touch buffer layer 151 may include a bridge electrode BE.

[0222] The second touch conductive layer TCDL2 on the touch interlayer insulating layer 152 may include driving electrodes TE and sensing electrodes RE.

[0223] Similar to the driving electrode TE and the sensing electrode RE, the dummy electrode DE located inside each of the driving electrode TE and the sensing electrode RE, the first driving line TL1 and the second driving line TL2 connected to the driving electrode TE, and the sensing line RL connected to the sensing electrode RE may all be located in the second touch conductive layer TCDL2 on the touch interlayer insulating layer 152.

[0224] The driving electrode TE may be electrically connected to the bridge electrode BE through the touch electrode connection hole TCNT1 penetrating the touch interlayer insulating layer 152 .

[0225] The touch buffer layer 151 may include an inorganic insulating material.

[0226] The touch interlayer insulating layer 152 may include an inorganic insulating material or an organic insulating material.

[0227] The touch planarization layer 153 may include an organic insulating material.

[0228] The polarizing layer 160 may be disposed on the touch sensor layer 150 .

[0229] Figure 10 is a diagram showing a method according to an embodiment of the present invention. Figure 4 Layout diagram of part C. Figure 11 It is along Figure 10 A cross-sectional view taken along line FF'. Figure 12 It is along Figure 10 A cross-sectional view taken along line G-G'.

[0230] refer to Figure 10 The display panel 100 of the display device 10 according to the embodiment includes a main area MA (see Figure 4 ) and a sub-area SBA, the main area MA includes a display area DA and a non-display area NDA, and the sub-area SBA protrudes from a first side of the main area MA.

[0231] According to an embodiment, the non-display area NDA may include a dam area DMA in which at least one dam portion DM is arranged around the display area DA, a bonding area JNA surrounding the dam area DMA, and a bank area BNA disposed between the bonding area JNA and a first side of the main area MA adjacent to the sub-area SBA.

[0232] The display panel 100 of the display device 10 according to the embodiment may include a touch sensor layer 150 (see FIG. Figure 7 ) and extends to the sensing transmission lines SENL of the sub-area SBA. Adjacent to one of the sensing transmission lines SENL, a ground line GNDL is disposed on one side. For example, for each pair of sensing transmission lines SENL, the ground line GNDL is adjacent to one of the sensing transmission lines SENL. Furthermore, a bank BNK is disposed in the bank area BNA adjacent to the ground line GNDL, and a first electrostatic shield portion ESHL1 covers the bank BNK and is electrically connected to the ground line GNDL.

[0233] According to the embodiment, the element layer 130 (see Figure 9 ) may include locations in the emission areas EA1, EA2, and EA3 (see Figure 9 ) in the light emitting element LE (see Figure 9 ).

[0234] According to an embodiment, the circuit layer 120 (see FIG. Figure 9 ) may include electrical connections to the light emitting element LE (see Figure 9 ) of the light-emitting pixel driver EPD, the data signal Vdata (see Figure 6 ) are transmitted to the data lines DL of the light-emitting pixel driver EPD and the data supply lines DSPL electrically connected to the data lines DL, respectively, disposed in the non-display area NDA and extending to the sub-area SBA.

[0235] The light emitting pixel drivers EPD may be arranged in a matrix in the first direction DR1 and the second direction DR2 in the display area DA.

[0236] The data lines DL may extend in the second direction DR2.

[0237] The data supply line DSPL can be electrically connected between the data line DL and the display driving circuit 200 (see Figure 4 )between.

[0238] The data supply line DSPL may overlap a portion of the bank BNK.

[0239] In other words, the data supply line DSPL may be arranged in the center portion of the sub-area SBA in the first direction DR1. Therefore, a portion of the bank BNK facing the center portion of the sub-area SBA may overlap with the data supply line DSPL. Furthermore, a portion of the first electrostatic shielding portion ESHL1 covering the bank BNK and facing the center portion of the sub-area SBA may also overlap with the data supply line DSPL.

[0240] The sensing transmission line SENL may be disposed in a portion of the bank area BNA adjacent to one side of the sub area SBA in the first direction DR1 , cross the data supply line DSPL, and may be spaced apart from the bank BNK.

[0241] In other words, the sensing transmission line SENL may be disposed at one side of the sub area SBA in the first direction DR1 , and the data supply line DSPL may be disposed at a central portion of the sub area SBA.

[0242] Among the sensing transmission lines SENL, the sensing transmission lines SENL arranged at one side along the first direction DR1 may be adjacent to the ground line GNDL.

[0243] For example, Figure 10 As shown in , the sensing transmission lines SENL may be divided into a first wiring group arranged at a first side of the data supply line DSPL along the first direction DR1 and a second wiring group arranged at a second side of the data supply line DSPL along the first direction DR1.

[0244] The two sensing transmission lines SENL arranged at both sides of the first wiring group along the first direction DR1 may be adjacent to the two ground lines GNDL, respectively.

[0245] Similarly, two sensing transmission lines SENL arranged at both sides of the second wiring group along the first direction DR1 may be adjacent to the two ground lines GNDL, respectively.

[0246] The ground line GNDL may transmit ground power.

[0247] The ground line GNDL may be adjacent to the bank BNK in the first direction DR1 .

[0248] In other words, the ground line GNDL may be disposed between the bank BNK and one of the sensing transmission lines SENL disposed on one side.

[0249] According to an embodiment, the first electrostatic shielding portion ESHL1 covering the bank BNK may extend along the first direction DR1 to the ground line GNDL adjacent to the bank BNK and may be electrically connected to the ground line GNDL.

[0250] In this configuration, even if external static electricity is concentrated on the first electrostatic shielding portion ESHL1, it can be discharged to the ground line GNDL, thereby preventing damage to the wiring caused by static electricity accumulation on the first electrostatic shielding portion ESHL1. Therefore, the display quality and life of the display device 10 can be improved.

[0251] According to an embodiment, the sub-area SBA may include a bending area BA transformed into a bent shape, a Figure 4 ) between one side of the first sub-area SB1 and one side of the bending area BA and a second sub-area SB2 extending from the other side of the bending area BA (see Figure 4 ).

[0252] According to an embodiment, the display panel 100 may further include data bending lines DTBDL disposed in the bending area BA and electrically connected to the data supply lines DSPL, and sensing bending lines SEBDL disposed in the bending area BA and electrically connected to the sensing transmission lines SENL. Each of the data bending lines DTBDL and the sensing bending lines SEBDL may be bent as their names suggest.

[0253] refer to Figure 11 The circuit layer 120 may include a semiconductor layer SEL (see FIG. Figure 9 ), covering semiconductor layer SEL (see Figure 9 ) of the first gate insulating layer 122, and a first gate conductive layer GCDL1 (see FIG. Figure 9 ), covering the first gate conductive layer GCDL1 (see Figure 9 ) of the second gate insulating layer 123, and a second gate conductive layer GCDL2 (see FIG. Figure 9 ), covering the second gate conductive layer GCDL2 (see Figure 9 ), a first planarization layer 125 disposed on the interlayer insulating layer 124, and a second planarization layer 126 disposed on the first planarization layer 125. The circuit layer 120 may further include a buffer layer 121 covering the substrate 110.

[0254] The element layer 130 may include a pixel defining layer 132 disposed in the non-emission region of the display area DA, a spacer layer 132′ disposed on a portion of the pixel defining layer 132 (see FIG. Figure 9) and a cathode electrode 134 disposed in the display area DA.

[0255] The pixel defining layer 132 and the cathode electrode 134 may extend to the non-display area NDA.

[0256] Each of the at least one dam portion DM arranged in the dam area DMA may include two or more dam layers DML11 , DML21 , DML31 , DML12 , DML22 , DML32 , and DML42 .

[0257] Each of the two or more dam layers DML11, DML21, DML31, DML12, DML22, DML32, and DML42 may be disposed on the same layer as one of the first planarization layer 125, the second planarization layer 126, the pixel defining layer 132, and the spacer layer 132' (see FIG. Figure 9 ).

[0258] For example, the at least one dam portion DM may include a first dam portion DM1 surrounding the display area DA and a second dam portion DM2 surrounding the first dam portion DM1 .

[0259] The first dam portion DM1 may include a first dam layer DML11 disposed at the same layer as the second planarization layer 126, a second dam layer DML21 disposed at the same layer as the pixel defining layer 132, and a spacer layer 132' (see FIG. Figure 9 ) is set at the third dam layer DML31 on the same layer.

[0260] The second dam portion DM2 may include a first dam layer DML12 disposed at the same layer as the first planarization layer 125, a second dam layer DML22 disposed at the same layer as the second planarization layer 126, a third dam layer DML32 disposed at the same layer as the pixel defining layer 132, and a spacer layer 132′ (see FIG. 1 ). Figure 9 ) is provided on the same layer as the fourth dam layer DML42.

[0261] The encapsulation layer 140 may include a first encapsulation layer 141 covering the cathode electrode 134 of the element layer 130 and including an inorganic insulating material, a second encapsulation layer 142 disposed on the first encapsulation layer 141 and including an organic insulating material, and a third encapsulation layer 143 covering the second encapsulation layer 142 and including an inorganic insulating material.

[0262] The second encapsulation layer 142 may be formed of an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0263] The second encapsulation layer 142 may be prepared by a process in which an organic material in a liquid state is applied to the first encapsulation layer 141, diffused to cover the display area DA, and then cured. The diffusion range of the liquid organic material may be limited by at least one dam portion DM.

[0264] In other words, the second encapsulation layer 142 may be disposed in a region surrounded by at least one dam portion DM.

[0265] The first encapsulation layer 141 may make contact with the interlayer insulating layer 124 in the bonding area JNA.

[0266] The third encapsulation layer 143 may make contact with the first encapsulation layer 141 or the interlayer insulating layer 124 in the bonding area JNA.

[0267] The touch sensor layer 150 disposed on the encapsulation layer 140 includes a touch buffer layer 151 covering the encapsulation layer 140 .

[0268] The touch buffer layer 151 may make contact with the third encapsulation layer 143 or the interlayer insulating layer 124 in the bonding area JNA.

[0269] Accordingly, a bonding structure between the inorganic materials may be provided in the bonding area JNA.

[0270] like Figure 10 As shown in FIG, the data supply line DSPL crosses the bonding area JNA.

[0271] Accordingly, if Figure 11 and Figure 12 As shown in FIG, each of the data supply lines DSPL may be provided in a first gate conductive layer GCDL1 (see FIG. Figure 9 ) and the second gate conductive layer GCDL2 (see Figure 9 ). For example, in Figure 11 In the embodiment, the data supply line DSPL may be in direct contact with the upper surface of the first gate insulating layer 122 .

[0272] like Figure 11 As shown in FIG, the data line DL may be disposed on the second source-drain conductive layer SDCDL2 on the first planarization layer 125 (see FIG. Figure 9 ). For example, Figure 11 The data line DL in the embodiment may contact the data supply line DSPL through a hole penetrating the first planarization layer 125 , the interlayer insulating layer 124 , and the second gate insulating layer 123 .

[0273] In addition, the data bending line DTBDL may be disposed on the first bank layer BNL1 , and the second bank layer BNL2 may cover the data bending line DTBDL.

[0274] For example, the data bending line DTBDL may be connected to the second source-drain conductive layer SDCDL2 (see Figure 9 ) are set in the same layer.

[0275] like Figure 11 As shown in FIG, in order to position the bonding structure between the inorganic materials in the bonding area JNA, the bank BNK may be spaced apart from the encapsulation layer 140 within the bonding area JNA.

[0276] The bank BNK may be configured as a structure in which two or more bank layers BNL1 , BNL2 , BNL3 , and BNL4 are stacked, resulting in a thickness greater than that of at least one dam portion DM.

[0277] For example, the bank BNK may include a first bank layer BNL1 disposed in the same layer as the first planarization layer 125, a second bank layer BNL2 disposed in the same layer as the second planarization layer 126, a third bank layer BNL3 disposed in the same layer as the pixel defining layer 132, and a spacer layer 132′ (see FIG. Figure 9 ) A fourth bank layer BNL4 is provided in the same layer.

[0278] According to an embodiment, to position the data bending line DTBDL and the sensing bending line SEBDL in the bending area BA, the first and second bank layers BNL1 and BNL2 disposed in the same layer as the first and second planarization layers 125 and 126 may extend to the sub area SBA.

[0279] like Figure 11 and Figure 12 As shown in the figure, the touch sensor layer 150 may include a touch buffer layer 151 covering the encapsulation layer 140, a first touch conductive layer TCDL1 arranged on the touch buffer layer 151, a touch interlayer insulating layer 152 covering the first touch conductive layer TCDL1, a second touch conductive layer TCDL2 arranged on the touch interlayer insulating layer 152, and a touch planarization layer 153 covering the second touch conductive layer TCDL2.

[0280] According to an embodiment, each of the sensing transmission lines SENL may include a first sensing transmission layer STR1 disposed in the first touch conductive layer TCDL1 and a second sensing transmission layer STR2 disposed in the second touch conductive layer TCDL2. The first sensing transmission layer STR1 may overlap the second sensing transmission layer STR2.

[0281] In each of the sensing transmission lines SENL, the second sensing transmission layer STR2 may be electrically connected to the first sensing transmission layer STR1 through a hole penetrating the touch interlayer insulating layer 152 .

[0282] The ground line GNDL may include a first ground layer GNL1 disposed in the first touch conductive layer TCDL1 and a second ground layer GNL2 disposed in the second touch conductive layer TCDL2. The first ground layer GNL1 may overlap the second ground layer GNL2.

[0283] The second ground layer GNL2 may be electrically connected to the first ground layer GNL1 through a hole penetrating the touch interlayer insulating layer 152 .

[0284] According to an embodiment, a first electrostatic shielding portion ESHL1 covering the bank BNK may be provided in the first touch conductive layer TCDL1 .

[0285] The first electrostatic shielding portion ESHL1 may include a main shielding portion MSH covering the bank BNK and a ground connection portion GCN disposed between the main shielding portion MSH and the ground line GNDL.

[0286] The ground connection portion GCN may extend from the main shielding portion MSH to the first ground layer GNL1 of the ground line GNDL to make contact with the first ground layer GNL1 .

[0287] Accordingly, the first electrostatic shield portion ESHL1 may be electrically connected to the ground line GNDL.

[0288] As described above, according to embodiments, the first electrostatic shielding portion ESHL1 may include not only the main shielding portion MSH that covers the bank BNK, but also the ground connection portion GCN that contacts the ground line GNDL located between the sensing transmission line SENL and the bank BNK and extends from the main shielding portion MSH in the first direction DR1. Therefore, even if static electricity from the outside is concentrated on the first electrostatic shielding portion ESHL1, which is a conductive pattern having a relatively large width, it can be discharged through the ground line GNDL electrically connected to the first electrostatic shielding portion ESHL1. This helps prevent damage to the wiring caused by external static electricity, thereby improving the display quality and lifespan of the display device 10.

[0289] Figure 13 is a diagram showing a method according to an embodiment of the present invention. Figure 4 Layout diagram of part C. Figure 14 and Figure 15 According to the embodiment of the invention Figure 13 A cross-sectional view taken along line G-G'.

[0290] In addition to the display panel 100 further including the second electrostatic shielding portion ESHL2, according to Figure 13 、 Figure 14 and Figure 15 The display device 10 of the embodiment shown in FIG. Figures 1 to 12The display device 10 of the embodiment shown in FIG. 1 is substantially the same. Therefore, redundant description will be omitted.

[0291] like Figure 13 As shown in FIG, the second electrostatic shielding portion ESHL2 may be disposed in the bank area BNA and may overlap the data supply line DSPL.

[0292] Specifically, the second electrostatic shielding portion ESHL2 may be disposed in a portion of the bank area BNA facing the central portion of the sub area SBA and may overlap the data supply line DSPL.

[0293] In addition, a portion of the first electrostatic shielding portion ESHL1 and a portion of the bank BNK facing the central portion of the sub-area SBA may overlap with the second electrostatic shielding portion ESHL2 .

[0294] Since each of the data supply lines DSPL extends from the sub area SBA to each of the data lines DL, it may not be straight in one direction but may be bent at least once.

[0295] Since static electricity tends to concentrate at a bent portion of a conductor, the bent portion of each of the data supply lines DSPL may be more susceptible to static electricity.

[0296] Therefore, according to Figure 13 In the embodiment shown in FIG, the second electrostatic shielding portion ESHL2 may extend into a portion of the junction region JNA adjacent to the bank region BNA. As a result, the bent portion of the data supply line DSPL located in the junction region JNA and the bank region BNK may be covered by the second electrostatic shielding portion ESHL2.

[0297] In this way, damage to the data supply line DSPL due to static electricity can be further reduced.

[0298] like Figure 14 As shown in FIG, the second electrostatic shielding portion ESHL2 may be provided in the second touch conductive layer TCDL2. In this case, the second electrostatic shielding portion ESHL2 may overlap with the first electrostatic shielding portion ESHL1.

[0299] The second electrostatic shield portion ESHL2 may be electrically connected to the first electrostatic shield portion ESHL1 through a hole penetrating the touch interlayer insulating layer 152 .

[0300] The first electrostatic shield portion ESHL1 may include a ground connection portion GCN contacting the first ground layer GNL1 and thus may be electrically connected to the ground line GNDL. Accordingly, the second electrostatic shield portion ESHL2 may be electrically connected to the first electrostatic shield portion ESHL1 and the ground line GNDL.

[0301] Alternatively, as Figure 15 As shown in FIG, the second electrostatic shielding portion ESHL2 may extend to the ground line GNDL and may contact the second ground layer GNL2. For example, the second electrostatic shielding portion ESHL2 may be electrically connected to the first ground layer GNL1 through a hole penetrating the touch interlayer insulating layer 152.

[0302] As described above, according to embodiments, the data supply line DSPL in the bank area BNA can be doubly covered by the first electrostatic shielding portion ESHL1 and the second electrostatic shielding portion ESHL2. Because the first and second electrostatic shielding portions ESHL1 and ESHL2 are electrically connected to the ground line GNDL, any static electricity accumulated in the first and second electrostatic shielding portions ESHL1 and ESHL2 can be easily and quickly discharged through the ground line GNDL. Consequently, the risk of damage to the data supply line DSPL due to external static electricity is further reduced.

[0303] Figure 16 is a diagram showing a method according to an embodiment of the present invention. Figure 4 Layout diagram of part C. Figure 17 It is along Figure 16 A cross-sectional view taken along line H-H'. Figure 18 It is along Figure 16 A cross-sectional view taken along line G-G'.

[0304] In addition to the display panel 100 further including the third electrostatic shielding portion ESHL3, according to Figure 16 、 Figure 17 and Figure 18 The display device 10 of the embodiment shown in FIG. Figures 1 to 12 The display device 10 of the embodiment shown in FIG. 1 is substantially the same. Therefore, redundant description will be omitted.

[0305] like Figure 16 As shown in FIG, the third electrostatic shielding portion ESHL3 may be disposed in the bank area BNA and may overlap the sensing transmission line SENL.

[0306] The third electrostatic shielding portion ESHL3 may further overlap at least one of the data supply lines DSPL disposed at the edge of the bank BNK.

[0307] For example, when the sensing transmission line SENL is divided into a first wiring group arranged on a first side of the data supply line DSPL along the first direction DR1 and a second wiring group arranged on a second side of the data supply line DSPL along the first direction DR1, two third electrostatic shielding portions ESHL3 can be provided that overlap with the first wiring group and the second wiring group, respectively.

[0308] like Figure 17 and Figure 18 As shown in , each of the sensing transmission lines SENL may include a first sensing transmission layer STR1 disposed in the first touch conductive layer TCDL1 and a second sensing transmission layer STR2 disposed in the second touch conductive layer TCDL2.

[0309] According to one embodiment, the second sensing transmission layer STR2 of each of the sensing transmission lines SENL may be removed from the bank area BNA.

[0310] Specifically, a portion of each of the sensing transmission lines SENL crossing the bank area BNA may consist of only the first sensing transmission layer STR1 .

[0311] In addition, a third electrostatic shielding portion ESHL3 may be provided in the second touch conductive layer TCDL2 .

[0312] A portion of each of the sensing transmission lines SENL crossing the bank area BNA may overlap with the third electrostatic shielding portion ESHL3 disposed in the bank area BNA.

[0313] like Figure 17 As shown in FIG, the sensing bending line SEBDL may be disposed on the first bank layer BNL1. The second bank layer BNL2 may cover the sensing bending line SEBDL.

[0314] The sensing bending line SEBDL may be electrically connected to the first sensing transmission layer STR1 or the second sensing transmission layer STR2 of the sensing transmission line SENL.

[0315] like Figure 18 As shown in FIG, the third electrostatic shielding portion ESHL3 may be electrically connected to the first electrostatic shielding portion ESHL1 through a hole penetrating the touch interlayer insulating layer 152 .

[0316] Alternatively, the third electrostatic shield portion ESHL3 may be in contact with the second ground layer GNL2.

[0317] Accordingly, the third electrostatic shield portion ESHL3 may be electrically connected to the first electrostatic shield portion ESHL1 and the ground line GNDL.

[0318] As described above, according to embodiments, the sensing transmission line SENL can be covered by the third electrostatic shielding portion ESHL3 in the bank area BNA. Since the third electrostatic shielding portion ESHL3 is electrically connected to the ground line GNDL, static electricity accumulated in the third electrostatic shielding portion ESHL3 can be easily and quickly discharged through the ground line GNDL. Consequently, damage to the sensing transmission line SENL caused by externally introduced static electricity can be reduced.

[0319] Figure 19 is a diagram showing a method according to an embodiment of the present invention. Figure 4 Layout diagram of part C. Figure 20 It is along Figure 19 A cross-sectional view taken along line G-G'.

[0320] In addition to the display panel 100 including the second electrostatic shielding portion ESHL2 and the third electrostatic shielding portion ESHL3, according to Figure 19 and Figure 20 The display device 10 of the embodiment shown in FIG. Figures 10 to 18 The embodiments shown in FIG. 1 are substantially the same. Therefore, redundant descriptions will be omitted.

[0321] As described above, the display panel 100 of the display device 10 according to one embodiment includes the first electrostatic shielding portion ESHL1, the second electrostatic shielding portion ESHL2, and the third electrostatic shielding portion ESHL3. Therefore, damage to the data supply line DSPL and damage to the sensing transmission line SENL due to static electricity introduced from the outside can be reduced.

[0322] Figure 21 and Figure 22 2 is a perspective view of an unfolded state and a folded state of a display device according to an embodiment. Figure 23 It is along Figure 22 A cross-sectional view taken along line II'.

[0323] Figure 21 The expanded state of the display device 10 according to the embodiment is illustrated, and Figure 22 The folded state of the display device 10 according to the embodiment is illustrated.

[0324] refer to Figure 21 and Figure 22 , one surface of the display device 10 according to the embodiment may include a main area MA including a display area DA and a non-display area NDA.

[0325] The display area DA may be an area where the image IM is provided.

[0326] The non-display area NDA may be a boundary area surrounding the display area DA.

[0327] According to an embodiment, the main area MA may include a folding axis FX extending in one direction (see Figure 22 ) at least one folding area FA that is bent or unfolded and a plurality of non-folding areas NFA1 and NFA2 arranged on both sides of the at least one folding area FA.

[0328] For example, when the main area MA includes a folding area FA, the multiple non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2, the first non-folding area NFA1 contacts the first side of the folding area FA extending side by side with the folding axis FX, and the second non-folding area NFA2 contacts the second side of the folding area FA extending side by side with the folding axis FX.

[0329] The folding axis FX may extend in one of the first direction DR1 and the second direction DR2 .

[0330] refer to Figure 23 The display device 10 according to the embodiment may further include a cover window 500 facing the main area MA of the display panel 100, an adhesive layer 600 fixing the cover window 500 on the display panel 100, and a bending cover layer 700 spaced apart from the adhesive layer 600 and covering the bending area BA.

[0331] Since the display device 10 according to the embodiment can transition between an unfolded state and a folded state, the adhesive layer 600 on the display panel 100 can also transition between a stretched state and a bent state, along with the at least one folding area FA. Furthermore, in the folded state, the adhesive layer 600 bends and moves away from the folding axis FX, potentially becoming wider than in its unfolded state. Therefore, to accommodate the expansion of the adhesive layer 600, the bending cover layer 700 can be spaced apart from the adhesive layer 600.

[0332] According to one embodiment, the separation region GAP between the adhesive layer 600 and the bending cover layer 700 may overlap with the bank area BNA. In other words, at least a portion of the bank area BNA becomes the separation region GAP between the adhesive layer 600 and the bending cover layer 700, so that it can be exposed to the outside without being covered by the adhesive layer 600 or the bending cover layer 700.

[0333] However, as described above, the display panel 100 of the display device 10 according to the embodiment includes the first electrostatic shielding portion ESHL1 electrically connected to the ground line GNDL and disposed in the bank area BNA, or includes at least one of the second and third electrostatic shielding portions ESHL2 and ESHL3 .

[0334] Therefore, even if the separation area GAP between the adhesive layer 600 and the bending cover layer 700 overlaps with the bank area BNA, static electricity is blocked by at least one of the first electrostatic shielding part ESHL1, the second electrostatic shielding part ESHL2 and the third electrostatic shielding part ESHL3 provided in the bank area BNA.

[0335] Therefore, even when the display device 10 transitions between the unfolded state and the folded state, the display quality and lifespan can be improved.

[0336] However, the effects of the present disclosure are not limited to the effects mentioned here. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device comprising: The display panel includes a main area and a sub-area protruding from one side of the main area, The display panel includes a circuit layer provided on a substrate, a component layer provided on the circuit layer, a packaging layer provided on the component layer, and a touch sensor layer provided on the packaging layer. The main area includes a display area in which the emission area is arranged and a non-display area provided adjacent to the display area, The non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged, a bonding area surrounding the dam area, and a bank area provided between the side of the main area and the bonding area, and The display panel further comprises: a sensing transmission line electrically connected to the touch sensor layer and extending to the secondary region; a ground line adjacent to one of the sensing transmission lines; a bank disposed in the bank region and adjacent to the ground line; and A first electrostatic shield portion overlaps the bank and is electrically connected to the ground line.

2. The display device according to claim 1, wherein The touch sensor layer includes: a touch buffer layer, overlapping the encapsulation layer; a first touch conductive layer, disposed on the touch buffer layer; a touch interlayer insulating layer, overlapping the first touch conductive layer; a second touch conductive layer, disposed on the touch interlayer insulating layer; and A touch planarization layer overlapping the second touch conductive layer, The grounding wire includes: a first ground layer, disposed in the first touch conductive layer; and a second ground layer provided in the second touch conductive layer and electrically connected to the first ground layer through a hole penetrating the touch interlayer insulating layer, and The first electrostatic shielding portion is provided in the first touch conductive layer and includes a main shielding portion overlapping the dam and a ground connecting portion extending from the main shielding portion to the first ground layer and contacting the first ground layer.

3. The display device according to claim 2, wherein: The element layer includes a light emitting element provided in the emission region, The circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting element; a data line configured to transmit a data signal to the light-emitting pixel driver; and Data supply lines, electrically connected to the data lines, are disposed in the non-display area and extend to the auxiliary area, The data supply line overlaps a portion of the bank, and The sensing transmission line is arranged in a portion of the bank area adjacent to one side of the sub-region along the first direction, crosses the data supply line, and is spaced apart from the bank.

4. The display device according to claim 3, wherein The circuit layer includes: a semiconductor layer, disposed on the substrate; a first gate insulating layer overlapping the semiconductor layer; a first gate conductive layer, disposed on the first gate insulating layer; a second gate insulating layer overlapping the first gate conductive layer; a second gate conductive layer, disposed on the second gate insulating layer; an interlayer insulating layer overlapping the second gate conductive layer; a first planarization layer disposed on the interlayer insulating layer; and a second planarization layer, disposed on the first planarization layer; Wherein, the component layer includes: Anode electrodes are respectively arranged in the emission regions; a pixel defining layer disposed in a non-emitting region, the non-emitting region being disposed between the emitting regions and overlapping an edge of each of the anode electrodes; a spacer layer disposed on a portion of the pixel defining layer; light-emitting layers, respectively disposed on the anode electrodes; and a cathode electrode, disposed on the pixel defining layer, the spacer layer and the light emitting layer, The data supply line is provided in the first gate conductive layer or the second gate conductive layer. Wherein, the embankment comprises: a first bank layer, disposed in the same layer as the first planarization layer; a second bank layer, disposed in the same layer as the second planarization layer; a third bank layer, disposed in the same layer as the pixel defining layer; and a fourth bank layer provided in the same layer as the spacer layer, and The first bank layer and the second bank layer extend to the sub-region.

5. The display device according to claim 4, wherein Each of the sensing transmission lines comprises: a first sensing transmission layer, disposed in the first touch conductive layer; and The second sensing transmission layer is provided in the second touch conductive layer and is electrically connected to the first sensing transmission layer through a hole penetrating the touch interlayer insulating layer. The display device according to claim 5 , wherein: The display panel further includes a second electrostatic shielding portion disposed in the bank region and overlapping the data supply line, and The second electrostatic shielding portion is provided in the second touch conductive layer.

7. The display device according to claim 6, wherein: The second electrostatic shielding portion is electrically connected to the first electrostatic shielding portion through a hole penetrating the touch interlayer insulating layer.

8. The display device according to claim 5, wherein The display panel further includes a third electrostatic shielding portion disposed in the bank region and overlapping the sensing transmission line, A portion of each of the sensing transmission lines crossing the bank region is composed only of the first sensing transmission layer, and The third electrostatic shielding portion is provided in the second touch conductive layer.

9. The display device according to claim 8, wherein The third electrostatic shield portion is in contact with the second ground layer and is electrically connected to the ground line and the first electrostatic shield portion.

10. The display device according to claim 5, wherein said at least one dam portion comprises two or more dam layers, Each of the two or more dam layers is disposed in the same layer as one of the first planarization layer, the second planarization layer, the pixel defining layer, and the spacer layer, the thickness of the bank being greater than or equal to the thickness of the at least one dam portion, The encapsulation layer includes: a first encapsulation layer, overlapping the cathode electrode and comprising an inorganic insulating material; a second encapsulation layer disposed on the first encapsulation layer and comprising an organic insulating material; and a third encapsulation layer, overlapping the second encapsulation layer and comprising the inorganic insulating material, the second encapsulation layer is provided in a region partially surrounded by the at least one dam, The first encapsulation layer is in contact with the interlayer insulating layer in the bonding area, The third encapsulation layer is in contact with the first encapsulation layer or the interlayer insulating layer in the bonding region, the dam is spaced apart from the encapsulation layer, and The touch buffer layer includes the inorganic insulating material and contacts the interlayer insulating layer in the bonding area and in a separation region between the bank and the encapsulation layer.

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