Display device

Abstract

A display device is provided. The display device includes a first sub-pixel and a second sub-pixel. Each of the first sub-pixel and the second sub-pixel includes: a first electrode; a pixel defining layer on the first electrode and having an opening; a light emitting structure on the first electrode and the pixel defining layer; a second electrode on the light emitting structure and having a disconnected portion; and a third electrode on the second electrode and overlapping the disconnected portion. A width of the broken portion in the first direction is 2.7% or less of a width of the opening in the first direction.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are continuously being conducted. Summary of the Invention

[0003] Embodiments of the present disclosure may relate to a display device having improved reliability.

[0004] However, the aspects and features of the present disclosure are not limited to the above contents, and the above and other aspects and features may be more clearly understood by those having ordinary skill in the art through the following description.

[0005] According to one or more embodiments of the present disclosure, a display device includes a first subpixel and a second subpixel. Each of the first subpixel and the second subpixel includes: a first electrode; a pixel-defining layer on the first electrode and having an opening; a light-emitting structure on the first electrode and the pixel-defining layer; a second electrode on the light-emitting structure and having a disconnected portion; and a third electrode on the second electrode and overlapping the disconnected portion. The width of the disconnected portion in the first direction is 2.7% or less of the width of the opening in the first direction.

[0006] In an embodiment, the disconnected portion may be located between the first sub-pixel and the second sub-pixel.

[0007] In an embodiment, the light emitting structure may be at least partially separated between the first sub-pixel and the second sub-pixel.

[0008] In an embodiment, the third electrode may be located within the disconnected portion.

[0009] In an embodiment, the third electrode may overlap the opening.

[0010] In an embodiment, the third electrode may include a transparent conductive material.

[0011] In an embodiment, the third electrode may not overlap with the opening.

[0012] In an embodiment, the third electrode may include at least one of a transparent conductive material, a semi-transparent conductive material, and an opaque conductive material.

[0013] In an embodiment, the third electrode may be located between the first sub-pixel and the second sub-pixel.

[0014] In an embodiment, the thickness of the second electrode may be 3 nm or more and 14 nm or less.

[0015] In an embodiment, the thickness of the third electrode may be 5 nm or more and 200 nm or less.

[0016] According to one or more embodiments of the present disclosure, a display device includes a first subpixel and a second subpixel. Each of the first subpixel and the second subpixel includes: a first electrode; a pixel-defining layer on the first electrode and having an opening; a light-emitting structure on the first electrode and the pixel-defining layer and having a first disconnected portion; a second electrode on the light-emitting structure and having at least one second disconnected portion; and a third electrode on the second electrode and overlapping the at least one second disconnected portion. The width of the at least one second disconnected portion in the first direction is 2.7% or less of the width of the opening in the first direction.

[0017] In an embodiment, the at least one second disconnected portion may overlap the first disconnected portion.

[0018] In an embodiment, the second electrode may be located within the first disconnected portion.

[0019] In an embodiment, the third electrode may be located within the second disconnected portion.

[0020] In an embodiment, the third electrode may be located within the first disconnected portion and the second disconnected portion.

[0021] In an embodiment, the first disconnected portion and the second disconnected portion may be located between the first sub-pixel and the second sub-pixel.

[0022] In an embodiment, the third electrode may include a transparent conductive material.

[0023] In an embodiment, the thickness of the second electrode may be 3 nm or more and 14 nm or less.

[0024] In an embodiment, the thickness of the third electrode may be 5 nm or more and 200 nm or less.

[0025] According to some embodiments of the present disclosure, the light emitting structure may be at least partially separated by a separator formed in a boundary region between adjacent sub-pixels, thereby minimizing or reducing the current flowing out to adjacent sub-pixels.

[0026] According to some embodiments of the present disclosure, even if the cathode electrode is partially disconnected in a boundary region between adjacent sub-pixels, a connection electrode may be formed, and thus, reliability degradation of the display device may be prevented or substantially prevented.

[0027] However, the present disclosure is not limited to the above aspects and features, and the above and additional aspects and features will be set forth in part in the detailed description with reference to the accompanying drawings and in part will be obvious from the same, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0030] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Block diagram of a sub-pixel.

[0031] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Circuit diagram of a sub-pixel.

[0032] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of the display panel.

[0033] Figure 5 It shows Figure 4 An exploded perspective view of a portion of a display panel.

[0034] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0035] Figures 7 to 12 It is along Figure 6 A cross-sectional view taken along line II'.

[0036] Figure 13 is a diagram showing the embodiment of the present invention. Figures 7 to 12 A cross-sectional view of a light emitting structure in any one of the first to third light emitting elements.

[0037] Figure 14 is a diagram showing the embodiment of the present invention. Figures 7 to 12 A cross-sectional view of a light emitting structure in any one of the first to third light emitting elements.

[0038] Figure 15 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0039] Figure 16 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0040] Figure 17 is a block diagram illustrating a display system according to an embodiment.

[0041] Figure 18 is a diagram showing a method according to an embodiment of the present invention. Figure 17 A perspective view showing the application of the display system.

[0042] Figure 19 is shown as worn by the user Figure 18 Figure 1 shows a head-mounted display device. DETAILED DESCRIPTION

[0043] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numerals represent the same elements throughout the drawings and written description, and therefore, their redundant descriptions may not be repeated.

[0044] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0045] In addition, as will be understood by those skilled in the art, in view of the entire disclosure, each suitable feature of the various embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be technically connected and operated in various suitable manners, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0046] In the accompanying drawings, the relative sizes, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatially relative terms such as "under," "beneath," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as "under," "beneath," or "below" another element or feature will subsequently be oriented "above" the other element or feature. Thus, the example terms "under" and "below" can encompass both above and below orientations. The device can be positioned differently (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0047] Furthermore, it should be appreciated that the shapes shown in the drawings may vary in practice due to, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of the present disclosure should not be construed as limited to the specific shapes shown in the drawings, and should be construed to take into account variations in shape that may result, for example, from manufacturing. Thus, the shapes shown in the drawings may not depict the actual shape of regions of the device, and the present disclosure is not limited thereto.

[0048] In the drawings, the DR1, DR2, and DR3 axes are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0049] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, a first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part without departing from the spirit and scope of the present disclosure.

[0050] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Similarly, when a layer, region, or element is referred to as being “electrically connected to” another layer, region, or element, the layer, region, or element can be directly electrically connected to the other layer, region, or element, or can be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements therebetween. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0051] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when the terms "comprise", "include", "have" and variations thereof are used in this specification, the description indicates the presence of the stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" means A, B or A and B. When an expression such as "at least one (kind / person) of..." follows a column of elements, the entire column of elements is modified, rather than the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" refer to only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0052] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not terms of degree, and are intended to account for the inherent variation in measured or calculated values ​​that one of ordinary skill in the art would recognize. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0054] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0055] Reference Figure 1 , the display device 100 includes a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 and a controller 150 .

[0056] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm, where m is an integer greater than 1. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn, where n is an integer greater than 1.

[0057] Each of the sub-pixels SP may include at least one light emitting element to generate light. Therefore, each of the sub-pixels SP may generate light of a desired color (e.g., a specific or predetermined color) such as red, green, blue, cyan, magenta, yellow, etc. Two or more sub-pixels SP among the sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG, three sub-pixels SP may constitute one pixel PXL.

[0058] The gate driver 120 may be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing of applying a data signal, and the like.

[0059] In some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver to control the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0060] The gate driver 120 may be provided on one side of the display panel 110. However, the present disclosure is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and the drivers may be provided on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. Thus, according to various embodiments, the gate driver 120 may be provided around the display panel 110 in various suitable shapes and arrangements.

[0061] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0062] The data driver 130 can apply data signals having grayscale voltages corresponding to the image data DATA to the first to nth data lines DL1 to DLn using voltages from the voltage generator 140. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, the data signal corresponding to the image data DATA can be applied to the first to nth data lines DL1 to DLn. Consequently, the corresponding subpixels SP can generate light corresponding to the data signal. In this manner, an image can be displayed on the display panel 110.

[0063] In some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0064] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may generate a plurality of voltages and may provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 may generate the plurality of voltages by receiving a voltage (e.g., an input voltage) input from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0065] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS may be applied to the subpixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0066] In addition, the voltage generator 140 can generate various types of voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of a plurality of sub-pixels SP, a reference voltage (e.g., a predetermined reference voltage) can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate the reference voltage.

[0067] The controller 150 may control various operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display device 100 from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0068] The controller 150 may convert the input image data IMG to fit the display device 100 or the display panel 110 and output the image data DATA. In some embodiments, the controller 150 may arrange the input image data IMG to fit sub-pixels SP in row units and output the image data DATA.

[0069] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted together on one integrated circuit. Figure 1 As shown in FIG, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC (e.g., as a separate IC).

[0070] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may sense the temperature of its surroundings and generate temperature data TEP representing the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0071] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signal and the first and second power voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0072] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Block diagram of a sub-pixel. Figure 2 In the above reference Figure 1 The subpixel SPij arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) among the described subpixels SP may be shown as an example.

[0073] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD may be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN may be a transmission node. Figure 1 The first power voltage VDD node described above and the second power voltage node VSSN may be transmitted with reference to Figure 1 A node of the second power voltage VSS is described.

[0075] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0076] The sub-pixel circuit SPC can be connected to the above reference Figure 1 The i-th gate line GLi among the first to m-th gate lines GL1 to GLm, the i-th emission control line ELi among the first to m-th emission control lines EL1 to ELm, and the j-th data line DLj among the first to n-th data lines DL1 to DLn are described. The sub-pixel circuit SPC can control the light emitting element LD according to the signals received through these signal lines.

[0077] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In some embodiments, as shown in FIG. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In other words, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0078] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0079] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light-emitting element LD according to the stored voltage in response to the emission control signal received via the i-th emission control line ELi. Consequently, the light-emitting element LD can generate light having a brightness corresponding to the data signal.

[0080] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Circuit diagram of a sub-pixel.

[0081] Reference Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0082] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi' and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi described above, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared to the ith emission control line ELi described above, the ith emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2 .

[0083] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0084] The first transistor T1 may be connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2, and thus, the first transistor T1 may be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0085] The second transistor T2 may be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1, and thus, the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0086] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2, and thus, the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub-emission control line SEL2, and thus, the fourth transistor T4 may be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0088] The fifth transistor T5 can be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN can transmit the initialization voltage. In some embodiments, the initialization voltage can be determined by referring to the above reference. Figure 1 In other embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, and thus, the fifth transistor T5 may be turned on in response to a gate signal of the third sub-gate line SGL3.

[0089] The sixth transistor T6 may be connected between the first power voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub-emission control line SEL1, and thus, the sixth transistor T6 may be turned on in response to the emission control signal of the first sub-emission control line SEL1.

[0090] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power voltage node VDDN and the second node N2.

[0091] As described above, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. However, the present disclosure is not limited thereto. The sub-pixel circuit SPC may be implemented as any of various suitable types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to some embodiments, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may also be modified in various ways as needed or desired.

[0092] The first to sixth transistors T1 to T6 may be P-type transistors. Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). However, the present disclosure is not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 may be an N-type transistor.

[0093] In some embodiments, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0094] The light-emitting element LD may include an anode electrode AE, a cathode electrode CE, and an emission layer. The emission layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled at a low level. The first transistor T1 may be turned on according to the voltage of the second node N2, and thus, current may flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element LD may emit light according to the amount of the flowing current.

[0095] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of the display panel.

[0096] Reference Figure 4 , the display panel DP may be as shown above Figure 1The embodiment of the display panel 110 described above may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA may be disposed around the display area DA. For example, the non-display area NDA may surround the display area DA (e.g., around the display area DA).

[0097] The display panel DP may include a substrate SUB, sub-pixels SP, and pads (or referred to as “pads” or “pads”) PD.

[0098] When the display panel DP is used as a display screen for a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be provided very close to the user's eyes. In this case, it is desirable to have sub-pixels SP with a relatively high degree of integration. In order to increase the degree of integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB which is a silicon substrate. The display device 100 (e.g., see FIG. 1 ) including the display panel DP formed on the substrate SUB which is a silicon substrate Figure 1 ) can be called an OLED-on-silicon (OLEDoS) display device.

[0099] The sub-pixels SP may be arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 that crosses or intersects the first direction DR1. However, the present disclosure is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in an RGBG or diamond shape (e.g., PENTILE ® Shape, Pentile ® is an officially registered trademark of Samsung Display Co., Ltd.) The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0100] Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL.

[0101] Components for controlling the sub-pixels SP may be provided in the non-display area NDA on the substrate SUB. For example, the lines connected to the sub-pixels SP (such as those shown above) may be provided in the non-display area NDA on the substrate SUB. Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn described above may be disposed in the non-display area NDA.

[0102] Refer to above Figure 1At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 described above may be integrated into the non-display area NDA of the display panel DP. In some embodiments, the gate driver 120 may be mounted on the display panel DP and disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In some embodiments, the temperature sensor 160 may be disposed in the non-display area NDA to detect the temperature of the display panel DP.

[0103] The pad PD may be disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0104] The pad PD may connect the display panel DP to the display device 100 (eg, see Figure 1 ) other components. In some embodiments, voltages and signals for operating components included in the display panel DP can be provided from the driver integrated circuit DIC via the pad PD. For example, the first to nth data lines DL1 to DLn can be connected to the driver integrated circuit DIC via the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pad PD.

[0105] In some embodiments, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) may be mounted on the circuit board and electrically connected to the pad PD.

[0106] In some embodiments, the display area DA may have various suitable shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have various suitable shapes, such as a polygon, a circle, a semicircle, or an ellipse.

[0107] In some embodiments, the display panel DP may have a flat or substantially flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded (or rounded) or curved. In some embodiments, the display panel DP may be bendable, foldable, or rollable. In this case, the display panel DP and / or the substrate SUB may comprise various suitable materials having flexible properties.

[0108] Figure 5 It shows Figure 4 An exploded perspective view of a portion of a display panel.

[0109] exist Figure 5 For the convenience of explanation, the display panel DP can be schematically shown as shown in FIG. Figure 4 A portion corresponding to two pixels PXL1 and PXL2 among the described pixels PXL and a portion corresponding to the other remaining pixels PXL of the display panel DP may have the same or substantially the same configuration as that of the two pixels PXL1 and PXL2.

[0110] Reference Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0111] exist Figure 5 In the embodiment, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., in a plan view), the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be illustrated as having a quadrilateral shape having the same size as one another. However, the present disclosure is not limited thereto. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be modified in various ways as needed or desired to have various suitable shapes.

[0112] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0113] In some embodiments, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0114] The pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element, line, or the like. The conductive pattern may include copper, but the present disclosure is not limited thereto.

[0115] The circuit element may include a sub-pixel circuit SPC (eg, see FIG. 1 ) for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Figure 2 ). The sub-pixel circuit (SPC) may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In some embodiments, when the substrate SUB may be set to a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In some embodiments, when the substrate SUB is set to a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2 (for example, in a plan view). For example, each capacitor may include electrodes spaced apart from each other in the third direction DR3 with an insulating layer interposed therebetween.

[0116] The lines of the pixel circuit layer PCL may include signal lines (such as gate lines, emission control lines, data lines, etc.) connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The lines may also include lines connected to the above referenced Figure 2 The line of the first power voltage node VDDN described above may also include a line connected to the above reference Figure 2 A line describing the second power voltage node VSSN.

[0117] The light emitting element layer LDL may include an anode electrode AE ​​(eg, a first electrode), a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE (eg, a second electrode).

[0118] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the present disclosure is not limited thereto.

[0119] The pixel defining layer (PDL) may be disposed on the anode electrode (AE). The pixel defining layer (PDL) may include an opening (OP) exposing a portion of each of the anode electrodes (AE). The opening (OP) of the pixel defining layer (PDL) may correspond to the emission regions of the first, second, and third sub-pixels (SP1, SP2, and SP3), respectively.

[0120] In some embodiments, the pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include a plurality of stacked inorganic layers. In this case, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0121] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include an emission layer for generating light, an electron transport layer for transporting electrons, and a hole transport layer for transporting holes.

[0122] In some embodiments, the light-emitting structure EMS may fill the opening OP of the pixel-defining layer PDL and may be disposed entirely on the pixel-defining layer PDL. In other words, the light-emitting structure EMS may extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this case, at least some of the layers in the light-emitting structure EMS may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be spaced apart (e.g., separated) from each other, and each of them may be disposed within a corresponding opening OP of the pixel-defining layer PDL.

[0123] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third subpixels SP1 to SP3. In other words, the cathode electrode CE may serve as a common electrode for the first to third subpixels SP1 to SP3.

[0124] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE may be formed of a relatively thin metal material or a transparent conductive material. In some embodiments, the cathode electrode CE may include at least one of various suitable transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and suitable mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0125] The anode electrode AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith may be understood to constitute a light emitting element LD (eg, see Figure 2). In other words, each of the light-emitting elements LD of the first to third subpixels SP1 to SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS overlapping the anode electrode AE, and a portion of the cathode electrode CE overlapping the anode electrode AE. In each of the first to third subpixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the emission layer of the light-emitting structure EMS to generate excitons, and when the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined by the amount of current flowing through the emission layer. The wavelength range of the generated light may be determined by the configuration of the emission layer.

[0126] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may prevent or substantially prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In some embodiments, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). For example, the organic layer may include one or more organic insulating materials such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0127] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include or contain aluminum oxide (AlO x The thin layer including aluminum oxide may be provided on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0128] The thin layer including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the present disclosure is not limited thereto. The encapsulation layer TFE may also include a thin layer formed of at least one of various suitable materials suitable for improving encapsulation efficiency.

[0129] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0130] The color filter layer CFL may be provided between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may filter the light emitted from the light emitting structure EMS and selectively output light within a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, and each of the color filters CF may allow light of a desired wavelength range corresponding to the wavelength range of the corresponding sub-pixel to pass through. For example, the color filter CF corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter CF corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter CF corresponding to the third sub-pixel SP3 may allow blue light to pass through. Depending on the light emitted from the light emitting structure EMS of each sub-pixel, at least some of the color filters CF may be omitted.

[0131] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each lens LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS via a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In some embodiments, the lenses LS may include an organic material. In some embodiments, the lenses LS may include an acrylic material. However, the material of the lenses LS is not limited thereto.

[0132] In some embodiments, at least a portion of the color filters CF of the color filter layer CFL and at least a portion of the lenses LS of the lens array LA may be offset in a direction parallel to or substantially parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the openings OP of the pixel defining layer PDL. More specifically, in a central region of the display area DA, when viewed in a third direction DR3 (e.g., in a plan view), the centers of the color filters CF and the lenses LS may be aligned with or overlap with the centers of the corresponding openings OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the openings OP of the pixel defining layer PDL may completely overlap with the corresponding color filters CF of the color filter layer CFL and the corresponding lenses LS of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3 (e.g., in a plan view), the centers of the color filters CF and the lenses LS may be offset in a planar direction from the centers of the corresponding openings OP of the pixel defining layer PDL. For example, in an area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, in the center of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction normal to the display surface. In areas outside the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction inclined at an angle (e.g., a predetermined angle) relative to the normal to the display surface.

[0133] An overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various suitable materials suitable for protecting underlying layers from foreign matter (such as dust, moisture, etc.). For example, the overcoat layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer OC may include epoxy resin, but the present disclosure is not limited thereto. The overcoat layer OC may have a refractive index lower than that of the lens array LA.

[0134] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may protect the underlying layers. The cover window CW may have a refractive index higher than that of the overcoat layer OC. The cover window CW may comprise glass, but the present disclosure is not limited thereto. For example, the cover window CW may be encapsulating glass configured to protect the components disposed thereunder. In other embodiments, the cover window CW may be omitted as needed or desired.

[0135] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0136] exist Figure 6 For the sake of convenience, the above reference Figure 5 The first pixel PXL1 among the first and second pixels PXL1 and PXL2 is described. The remaining pixels PXL may have the same or substantially the same configuration as that of the first pixel PXL1.

[0137] Reference Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged along the first direction DR1.

[0138] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA surrounding the first emission area EMA1 (e.g., around an outer periphery of the first emission area EMA1). The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA surrounding the second emission area EMA2 (e.g., around an outer periphery of the second emission area EMA2). The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA surrounding the third emission area EMA3 (e.g., around an outer periphery of the third emission area EMA3).

[0139] The first emission area EMA1 may be where light is emitted from the light emitting structure EMS (eg, see Figure 5 ) of the portion corresponding to the first sub-pixel SP1. The second emission area EMA2 may be a region where light is emitted from the portion corresponding to the second sub-pixel SP2 of the light emitting structure EMS. The third emission area EMA3 may be a region where light is emitted from the portion corresponding to the third sub-pixel SP3 of the light emitting structure EMS. Figure 5 As described above, each emission region may be understood as a corresponding opening OP of the pixel defining layer PDL for each of the first to third sub-pixels SP1 to SP3 .

[0140] Figures 7 to 12 It is along Figure 6 A cross-sectional view taken along line II'.

[0141] Reference Figure 7 , a substrate SUB may be provided, and the pixel circuit layer PCL may be provided on the substrate SUB.

[0142] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0143] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC included in the first sub-pixel SP1 (e.g., see Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for ease of illustration, one of the transistors for each of the sub-pixels is shown, and the remaining circuit elements are not shown.

[0144] The transistor T_SP1 of the first subpixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0145] The source region SRA and the drain region DRA may be provided in the substrate SUB. A well WL formed by an ion implantation process may be provided in the substrate SUB, and the source region SRA and the drain region DRA may be provided to be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0146] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed at (e.g., in or above) the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material (such as a gate insulating layer GI). The gate electrode GE may include a conductive material.

[0147] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via one or more drain connection portions DRC penetrating through the insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via one or more source connection portions SRC penetrating through the insulating layers.

[0148] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1.

[0149] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured in the same or substantially the same manner as the transistor T_SP1 of the first subpixel SP1 .

[0150] As such, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0151] The via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have an overall flat or substantially flat surface. The via layer VIAL may flatten or substantially flatten the steps on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbide nitride (SiCN), but the present disclosure is not limited thereto.

[0152] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0153] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 may be disposed in the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 may contact a corresponding circuit element disposed at (e.g., in or above) the pixel circuit layer PCL through a via hole penetrating the via layer VIAL.

[0154] The first to third reflective electrodes RE1 to RE3 can function as total reflection mirrors that reflect light emitted from the light emitting structure EMS toward a display surface (e.g., toward the cover window CW). The first to third reflective electrodes RE1 to RE3 may include one or more metal materials suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and suitable alloys of two or more thereof, but the present disclosure is not limited thereto.

[0155] In some embodiments, a contact electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The contact electrode may improve the electrical connection between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The contact electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), and / or tantalum nitride (TaN), among others, but the present disclosure is not limited thereto. In some embodiments, the corresponding reflective electrode may be disposed between multiple layers of the contact electrode.

[0156] A buffer pattern BFP may be disposed below at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material (such as silicon carbide nitride), but the present disclosure is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0157] The first to third reflective electrodes RE1 to RE3 can function as fully reflective mirrors, and the cathode electrode CE can function as a semi-reflective mirror. Light emitted from the emission layer of the light-emitting structure EMS can be at least partially amplified by reciprocating between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonant distance for light emitted from the corresponding emission layer of the light-emitting structure EMS.

[0158] Due to the buffer pattern BFP, the first subpixel SP1 can have a shorter resonance distance than the other subpixels. This adjusted resonance distance effectively and efficiently amplifies light within a desired or specific wavelength range (e.g., red). Consequently, the first subpixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0159] exist Figure 7 In the figure, the buffer pattern BFP is shown as being provided to the first subpixel SP1 but not to the second and third subpixels SP2 and SP3, but the present disclosure is not limited thereto. The buffer pattern BFP may also be provided to at least one of the second and third subpixels SP2 and SP3 to adjust the resonance distance of at least one of the second and third subpixels SP2 and SP3. For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively. In this case, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0160] To flatten or substantially flatten the steps between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may substantially cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and may have a flat or substantially flat surface. In some embodiments, the planarization layer PLNL may be omitted as needed or desired.

[0161] Anode electrodes AE1, AE2, and AE3 (e.g., first electrodes) may be disposed on the planarization layer PLNL. The first to third anode electrodes AE1 to AE3 may overlap the first to third reflective electrodes RE1 to RE3, respectively. When viewed in the third direction DR3 (e.g., in a plan view), the first to third anode electrodes AE1 to AE3 may have the same shape as that of the above reference electrode. Figure 6 The shapes of the first to third emission areas EMA1 to EMA3 are similar to those described above. The first to third anode electrodes AE1 to AE3 can be connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode electrode AE1 can be connected to the first reflective electrode RE1 via a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 via a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 via a third via VIA3 penetrating the planarization layer PLNL.

[0162] In some embodiments, the first to third anode electrodes AE1 to AE3 may include various suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0163] In some embodiments, the insulating layer may be further configured to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be provided between one or more of the first to third anode electrodes AE1 to AE3 and their corresponding reflective electrodes. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively. In this case, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. The pixel defining layer PDL may be provided on portions of the first to third anode electrodes AE1 to AE3 and the planarization layer PLNL. The pixel defining layer PDL may include openings OP that respectively expose a portion of each of the first to third anode electrodes AE1 to AE3. Each of the openings OP of the pixel defining layer PDL may define the emission area of ​​a corresponding one of the first to third subpixels SP1 to SP3. In this way, the pixel defining layer PDL may be provided above with reference to Figure 6 The non-emitting area NEA is described and may be defined above with reference to Figure 6 Described are the first emission area EMA1 to the third emission area EMA3.

[0164] In some embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer (PDL) may include first to third inorganic insulating layers stacked sequentially. The first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the present disclosure is not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the opening OP.

[0165] The separator SPR may be provided at the boundary area BDA between adjacent sub-pixels. In other words, the separator SPR may be provided at the boundary area BDA. Figure 4 At each of the boundary regions between the sub-pixels SP in .

[0166] The separator SPR may cause discontinuity to be formed in the light emitting structure EMS at the boundary area BDA. For example, the light emitting structure EMS may be broken or bent at the boundary area BDA due to the separator SPR.

[0167] The separator SPR may be provided at (eg, in or on) the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH as separators SPR at the boundary area BDA. In some embodiments, as Figure 7 As shown in , the trench TRCH may penetrate the pixel defining layer PDL and may also partially penetrate the planarization layer PLNL. In other embodiments, the trench TRCH may penetrate the pixel defining layer PDL and the planarization layer PLNL and may also partially penetrate the via layer VIAL. In other embodiments, the trench TRCH may at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed within the trench TRCH.

[0168] exist Figure 7 , one trench TRCH is shown as being provided at the boundary area BDA, but the present disclosure is not limited thereto. For example, the pixel defining layer PDL may include two or more trenches at the boundary area BDA.

[0169] Due to the trench TRCH, discontinuous portions (such as voids VD) may be formed in the light emitting structure EMS at the boundary area BDA. Some of the multiple layers stacked in the light emitting structure EMS may be cut or bent due to the voids VD. For example, at least one charge generation layer included in the light emitting structure EMS may be cut due to the voids VD. In this way, the light emitting structures EMS included in the first to third subpixels SP1 to SP3 may be at least partially separated due to the trench TRCH.

[0170] In some embodiments, the light emitting structure EMS may be formed by various suitable processes such as vacuum deposition and / or inkjet printing, etc. In this case, the same material as that of the light emitting structure EMS may be provided on the bottom surface of the trench TRCH adjacent to the via layer VIAL.

[0171] The separator SPR can be provided in various suitable forms so that the light emitting structure EMS can have a discontinuous portion at the boundary area BDA. In some embodiments, in the absence of the trench TRCH, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL can be provided at the boundary area BDA. In this case, the width of the topmost inorganic insulating pattern among the additionally stacked inorganic insulating patterns can be greater than the width of the inorganic insulating pattern directly below it. For example, at the boundary area BDA, the first to third inorganic insulating patterns can be stacked sequentially from the pixel defining layer PDL, and the topmost third inorganic insulating pattern can have a width greater than the width of the second inorganic insulating pattern. For example, the pixel defining layer PDL can have a "T"-shaped or "I"-shaped cross-section at the boundary area BDA. Depending on the shape of the pixel defining layer PDL, the multiple layers included in the light emitting structure EMS can be at least partially broken or bent at the boundary area BDA.

[0172] The light-emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light-emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be disposed integrally across the first to third sub-pixels SP1 to SP3. As described above, the light-emitting structure EMS may be at least partially broken or bent at the boundary area BDA due to the separator SPR. Therefore, when the display panel DP is operated, the current flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through the layers included in the light-emitting structure EMS may be reduced. Therefore, the first to third light-emitting elements LD1 to LD3 may operate with relatively high reliability.

[0173] A cathode electrode CE (e.g., a second electrode) may be provided on the light emitting structure EMS. The cathode electrode CE may be provided commonly to the first to third subpixels SP1 to SP3. The cathode electrode CE may function as a semi-reflective mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS. For example, the thickness of the cathode electrode CE in the third direction DR3 may be 3 nm or greater and 14 nm or less.

[0174] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0175] The cathode electrode CE may be partially disconnected between the first to third subpixels SP1 to SP3 (e.g., at the boundary area BDA). For example, the cathode electrode CE may include a disconnected portion TC disposed between the first to third subpixels SP1 to SP3 (e.g., at the boundary area BDA).

[0176] The width WT of the disconnected portion TC of the cathode electrode CE in the first direction DR1 may be smaller than the width WO of the opening OP of the pixel defining layer PDL in the first direction DR1. For example, the width WT of the disconnected portion TC of the cathode electrode CE in the first direction DR1 may be less than or equal to 2.7% of the width WO of the opening OP of the pixel defining layer PDL in the first direction DR1. When the width WT of the disconnected portion TC of the cathode electrode CE in the first direction DR1 exceeds 2.7% of the width WO of the opening OP of the pixel defining layer PDL in the first direction DR1, electrical characteristics of the display device may be degraded.

[0177] A connecting electrode TEL (e.g., a third electrode or a transparent electrode) may be provided on the cathode electrode CE. The connecting electrode TEL can be used to electrically connect a disconnected cathode electrode CE. Therefore, even if the cathode electrode CE is partially disconnected, a reduction in the reliability of the display device 100 can be prevented or substantially prevented. Thus, the thickness of the connecting electrode TEL in the third direction DR3 can be 5 nm or greater and 200 nm or less.

[0178] The connection electrode TEL may be disposed on the disconnected portion TC of the cathode electrode CE. The connection electrode TEL may overlap the disconnected portion TC of the cathode electrode CE in the third direction DR3. The connection electrode TEL may be disposed within the disconnected portion TC of the cathode electrode CE.

[0179] The connection electrode TEL may be provided throughout the first to third sub-pixels SP1 to SP3. For example, the connection electrode TEL may overlap the first to third sub-pixels SP1 to SP3 in the third direction DR3. The connection electrode TEL may overlap the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent conductive material. For example, the connection electrode TEL may include various suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

[0180] According to the embodiment, Figure 8As shown in , the connection electrode TEL may be provided between the first sub-pixel SP1 to the third sub-pixel SP3 (for example, at the boundary area BDA). For example, the connection electrode TEL may overlap with the pixel defining layer PDL in the third direction DR3. The connection electrode TEL may not overlap with the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent, translucent and / or opaque conductive material. For example, the connection electrode TEL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). As another example, the connection electrode TEL may include at least one of silver (Ag), magnesium (Mg), and a suitable mixture thereof.

[0181] According to the embodiment, Figure 9 As shown in , the light emitting structure EMS and the cathode electrode CE may include disconnected portions EC and TC, respectively. The light emitting structure EMS may be partially disconnected between the first to third sub-pixels SP1 to SP3 (e.g., at the boundary area BDA). The light emitting structure EMS may include a disconnected portion EC disposed between the first to third sub-pixels SP1 to SP3 (e.g., at the boundary area BDA).

[0182] The cathode electrode CE may be partially disconnected between the first to third subpixels SP1 to SP3 (e.g., at the boundary area BDA). For example, the cathode electrode CE may include a disconnected portion TC disposed between the first to third subpixels SP1 to SP3 (e.g., at the boundary area BDA).

[0183] The width WT of the disconnected portion TC of the cathode electrode CE in the first direction DR1 may be smaller than the width WO of the opening OP of the pixel defining layer PDL in the first direction DR1. For example, the width WT of the disconnected portion TC of the cathode electrode CE in the first direction DR1 may be smaller than or equal to 2.7% of the width WO of the opening OP of the pixel defining layer PDL in the first direction DR1.

[0184] The disconnect portion TC of the cathode electrode CE may overlap the disconnect portion EC of the light emitting structure EMS in the third direction DR3. The cathode electrode CE may be disposed within the disconnect portion EC of the light emitting structure EMS. The disconnect portion EC of the light emitting structure EMS and the disconnect portion TC of the cathode electrode CE may be formed sequentially. For example, the disconnect portion EC may be formed by drilling a hole in the light emitting structure EMS using a laser, and then the cathode electrode CE may be formed on the light emitting structure EMS. Subsequently, the disconnect portion TC may be formed by drilling a hole in the cathode electrode CE using a laser, and then the connecting electrode TEL may be formed on the cathode electrode CE. However, the present disclosure is not necessarily limited to this.

[0185] The connection electrode TEL may be provided on the cathode electrode CE. The connection electrode TEL may be used to electrically connect the disconnected cathode electrode CE. Therefore, as described above, even if the cathode electrode CE is partially disconnected, a reduction in the reliability of the display device 100 may be prevented or substantially prevented. Thus, the thickness of the connection electrode TEL in the third direction DR3 may be 5 nm or greater and 200 nm or less.

[0186] The connection electrode TEL may be disposed on the disconnected portion TC of the cathode electrode CE. The connection electrode TEL may be disposed within the disconnected portion TC of the cathode electrode CE. The connection electrode TEL may overlap the disconnected portion TC of the cathode electrode CE in the third direction DR3.

[0187] The connection electrode TEL may be provided throughout the first to third sub-pixels SP1 to SP3. For example, the connection electrode TEL may overlap the first to third sub-pixels SP1 to SP3 in the third direction DR3. The connection electrode TEL may overlap the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent conductive material. For example, the connection electrode TEL may include various suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

[0188] According to the embodiment, Figure 10 As shown in , the connection electrode TEL may be provided between the first sub-pixel SP1 to the third sub-pixel SP3 (for example, at the boundary area BDA). For example, the connection electrode TEL may overlap with the pixel defining layer PDL in the third direction DR3. The connection electrode TEL may not overlap with the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent, translucent and / or opaque conductive material. For example, the connection electrode TEL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). As another example, the connection electrode TEL may include at least one of silver (Ag), magnesium (Mg), and a suitable mixture thereof.

[0189] According to the embodiment, Figure 11 As shown in FIG, the disconnection portion TC of the cathode electrode CE may overlap the disconnection portion EC of the light emitting structure EMS in the third direction DR3. The disconnection portion TC of the cathode electrode CE may be formed concurrently (e.g., simultaneously or substantially simultaneously) with the disconnection portion EC of the light emitting structure EMS in the same process, but the present disclosure is not necessarily limited thereto. For example, the disconnection portion TC of the cathode electrode CE and the disconnection portion EC of the light emitting structure EMS may be formed concurrently (e.g., simultaneously or substantially simultaneously) with each other by laser drilling, but the present disclosure is not limited thereto.

[0190] The connection electrode TEL may be disposed on the disconnection portion EC of the light emitting structure EMS and the disconnection portion TC of the cathode electrode CE. The connection electrode TEL may overlap the disconnection portion EC of the light emitting structure EMS and the disconnection portion TC of the cathode electrode CE in the third direction DR3. The connection electrode TEL may be disposed within the disconnection portion EC of the light emitting structure EMS and the disconnection portion TC of the cathode electrode CE.

[0191] The connection electrode TEL may be provided throughout the first to third sub-pixels SP1 to SP3. For example, the connection electrode TEL may overlap the first to third sub-pixels SP1 to SP3 in the third direction DR3. The connection electrode TEL may overlap the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent conductive material. For example, the connection electrode TEL may include various suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

[0192] According to the embodiment, Figure 12 As shown in , the connection electrode TEL may be provided between the first sub-pixel SP1 to the third sub-pixel SP3 (for example, at the boundary area BDA). For example, the connection electrode TEL may overlap with the pixel defining layer PDL in the third direction DR3. The connection electrode TEL may not overlap with the opening OP of the pixel defining layer PDL in the third direction DR3. In this case, the connection electrode TEL may include a transparent, translucent and / or opaque conductive material. For example, the connection electrode TEL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). As another example, the connection electrode TEL may include at least one of silver (Ag), magnesium (Mg), and a suitable mixture thereof.

[0193] The encapsulation layer TFE may be provided on the connection electrode TEL. The encapsulation layer TFE may prevent or substantially prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0194] The optically functional layer OFL may be disposed on the encapsulation layer TFE. In some embodiments, the optically functional layer OFL may be attached to the encapsulation layer TFE using an adhesive layer APL. For example, the optically functional layer OFL may be manufactured separately and then attached to the encapsulation layer TFE using the adhesive layer APL. The adhesive layer APL may also function to protect underlying layers including the encapsulation layer TFE.

[0195] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 (e.g., first, second, and third color filters CF1, CF2, and CF3) corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may pass light of different wavelength ranges. For example, the first to third color filters CF1 to CF3 may pass red, green, and blue light, respectively.

[0196] In some embodiments, the first to third color filters CF1 to CF3 may partially overlap each other at the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0197] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may improve light output efficiency by outputting light emitted from the first to third light-emitting elements LD1 to LD3 along desired paths, respectively.

[0198] Figure 13 is a diagram showing the embodiment of the present invention. Figures 7 to 12 A cross-sectional view of a light emitting structure in any one of the first to third light emitting elements.

[0199] Reference Figure 13, the light emitting structure EMS may have a series structure including a first light emitting unit (eg, a first light emitting layer) EU1 and a second light emitting unit (eg, a second light emitting layer) EU2 stacked. Figures 7 to 12 The light emitting structure EMS in each of the first to third light emitting elements LD1 to LD3 may be configured to be identical or substantially identical to each other.

[0200] Each of the first and second light-emitting units EU1 and EU2 may include at least one emission layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first emission layer EML1, a first electron transport unit (e.g., first electron transport layer) ETU1, and a first hole transport unit (e.g., first hole transport layer) HTU1. The first emission layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second emission layer EML2, a second electron transport unit (e.g., second electron transport layer) ETU2, and a second hole transport unit (e.g., second hole transport layer) HTU2. The second emission layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0201] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer if necessary or desired. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0202] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and / or a hole blocking layer if necessary or desired. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0203] A connection layer, which may be provided in the form of a charge generation layer (CGL), may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect them to each other. In some embodiments, the charge generation layer (CGL) may have a stacked structure of a p-type dopant layer and an n-type dopant layer. For example, the p-type dopant layer may include a p-type dopant (such as HAT-CN, TCNQ, and / or NDP-9). The n-type dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a suitable combination thereof. However, the present disclosure is not limited thereto.

[0204] In some embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors from each other. The light emitted from each of the first emission layer EML1 and the second emission layer EML2 may be mixed with each other and be perceived as white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may generate yellow light. In some embodiments, the second emission layer EML2 may include a structure in which a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light are stacked. The red light and the green light may be mixed with each other to provide yellow light. In this case, an intermediate layer that performs the function of transporting holes and / or preventing or substantially preventing the transport of electrons may be further provided between the first sub-emission layer and the second sub-emission layer.

[0205] In other embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of the same color as each other.

[0206] The light emitting structure EMS may be formed by various suitable methods such as vacuum deposition and inkjet printing, but the present disclosure is not limited thereto.

[0207] Figure 14 is a diagram showing the embodiment of the present invention. Figures 7 to 12 A cross-sectional view of a light emitting structure in any one of the first to third light emitting elements.

[0208] Reference Figure 14 , the light emitting structure EMS′ may have a series structure including first to third light emitting units (eg, first light emitting layers) EU1 ′ to EU3 ′ stacked. Figures 7 to 12 The light emitting structure EMS′ in each of the first to third light emitting elements LD1 to LD3 may be configured to be identical or substantially identical to each other.

[0209] Each of the first to third light-emitting units EU1' to EU3' may include an emission layer that generates light in response to an applied current. The first light-emitting unit EU1' may include a first emission layer EML1', a first electron transport unit (e.g., first electron transport layer) ETU1', and a first hole transport unit (e.g., first hole transport layer) HTU1'. The first emission layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second emission layer EML2', a second electron transport unit (e.g., second electron transport layer) ETU2', and a second hole transport unit (e.g., second hole transport layer) HTU2'. The second emission layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third emission layer EML3', a third electron transport unit (e.g., third electron transport layer) ETU3', and a third hole transport unit (e.g., third hole transport layer) HTU3'. The third emission layer EML3 ′ may be disposed between the third electron transport unit ETU3 ′ and the third hole transport unit HTU3 ′.

[0210] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and if necessary or desired, may further include a hole buffer layer and / or an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0211] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and if necessary or desired, may further include an electron buffer layer and / or a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0212] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0213] In some embodiments, the first emission layer EML1' to the third emission layer EML3' can generate light of different colors from each other. The light emitted from each of the first emission layer EML1' to the third emission layer EML3' can be mixed with each other and be perceived as white light. For example, the first emission layer EML1' can generate blue light, the second emission layer EML2' can generate green light, and the third emission layer EML3' can generate red light.

[0214] In other embodiments, two or more of the first to third emission layers EML1 ′ to EML3 ′ may generate light of the same color as each other.

[0215] and Figure 13 and Figure 14 The content shown in Figures 7 to 12 The light emitting structure EMS may include one light emitting unit (for example, one light emitting layer) in each of the first to third light emitting elements LD1 to LD3. In this case, the light emitting units included in each of the first to third light emitting elements LD1 to LD3 may emit light of different colors from each other. For example, the light emitting unit of the first light emitting element LD1 may emit red light, the light emitting unit of the second light emitting element LD2 may emit green light, and the light emitting unit of the third light emitting element LD3 may emit blue light. In this case, Figures 7 to 12 Unlike what is shown in , the light emitting units of the first to third sub-pixels SP1 to SP3 may be spaced apart from each other (e.g., may be separated), and each of them may be disposed within a corresponding opening OP of the pixel defining layer PDL. In this case, at least some of the color filters CF1 to CF3 may be omitted as needed or desired.

[0216] Figure 15 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0217] Reference Figure 15 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0218] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' surrounding the first emission area EMA1' (e.g., around an outer periphery of the first emission area EMA1'). The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' surrounding the second emission area EMA2' (e.g., around an outer periphery of the second emission area EMA2'). The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' surrounding the third emission area EMA3' (e.g., around an outer periphery of the third emission area EMA3').

[0219] The first subpixel SP1' and the second subpixel SP2' may be arranged along the second direction DR2. The third subpixel SP3' may be arranged along the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0220] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have an area larger than that of the first emission area EMA1', and the third emission area EMA3' may have an area larger than that of the second emission area EMA2'. However, the present disclosure is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have the same or substantially the same area as each other, and the third sub-pixel SP3' may have an area larger than the area of ​​each of the first sub-pixel SP1' and the second sub-pixel SP2'. In this way, the areas of the first to third sub-pixels SP1' to SP3' may be variously modified as needed or desired.

[0221] Figure 16 is a diagram showing a method according to an embodiment of the present invention. Figure 5 A plan view of pixels.

[0222] Reference Figure 16 The first sub-pixel SP1″ may include a first emission area EMA1″ and a non-emission area NEA″ around the first emission area EMA1″ (e.g., around the outer periphery of the first emission area EMA1″). The second sub-pixel SP2″ may include a second emission area EMA2″ and a non-emission area NEA″ around the second emission area EMA2″ (e.g., around the outer periphery of the second emission area EMA2″). The third sub-pixel SP3″ may include a third emission area EMA3″ and a non-emission area NEA″ around the third emission area EMA3″ (e.g., around the outer periphery of the third emission area EMA3″).

[0223] When viewed in the third direction DR3 (eg, in a plan view), the first to third sub-pixels SP1 to SP3 ″ may have polygonal shapes. For example, the first to third sub-pixels SP1 ″ to SP3 ″ may have polygonal shapes. Figure 16 The hexagonal shape shown in .

[0224] When viewed in the third direction DR3 (e.g., in a plan view), the first to third emission areas EMA1 to EMA3" may have a circular shape. However, the present disclosure is not limited thereto. For example, each of the first to third emission areas EMA1 to EMA3" may have a polygonal shape.

[0225] The first and third subpixels SP1 ″ and SP3 ″ may be arranged along the first direction DR1 . The second subpixel SP2 ″ may be arranged along a direction inclined at an acute angle (eg, obliquely) with respect to the second direction DR2 and with respect to the first subpixel SP1 ″.

[0226] However, the present disclosure is not limited to Figure 6 、 Figure 15 and Figure 16 Each pixel may include two or more sub-pixels, the sub-pixels may be arranged in various suitable manners, each of the sub-pixels may have various suitable shapes, and each of their emission regions may have various suitable shapes.

[0227] Figure 17 is a block diagram illustrating a display system according to an embodiment.

[0228] Reference Figure 17 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0229] The processor 1100 can perform various suitable tasks and calculations. In some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, and / or a central processing unit (CPU). The processor 1100 can be connected to other components of the display system 1000 via a bus system and control the other components of the display system 1000.

[0230] exist Figure 17 , the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0231] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1The display device 100 described above is similarly constructed. In this case, the first image data IMG1 and the first control signal CTRL1 can be respectively set to Figure 1 Describe the input image data IMG and control signal CTRL.

[0232] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is similarly constructed. In this case, the second image data IMG2 and the second control signal CTRL2 can be respectively set to the above reference Figure 1 Describe the input image data IMG and control signal CTRL.

[0233] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a portable multimedia player (PMP), a navigation and / or ultra mobile personal computer (UMPC), etc. The display system 1000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc.

[0234] Figure 18 is a diagram showing a method according to an embodiment of the present invention. Figure 17 A perspective view showing the application of the display system.

[0235] Reference Figure 18 , refer to above Figure 17 The display system 1000 described may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0236] The head-mounted display device 2000 may include a headband 2100 and a display device storage case 2200. The headband 2100 may be connected to the display device storage case 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may wrap around the sides of the user's head, and the vertical strap may wrap around the top of the user's head. However, the present disclosure is not limited thereto. For example, the headband 2100 may be implemented in the form of an eyeglass frame and / or a helmet.

[0237] The display device storage case 2200 can accommodate the above reference Figure 17The first display device 1210 and the second display device 1220 described above. The display device storage housing 2200 can also accommodate the above-mentioned Figure 17 Processor 1100 is described.

[0238] Figure 19 is shown as worn by the user Figure 18 Figure 1 shows a head-mounted display device.

[0239] Reference Figure 19 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 may be provided in the head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0240] In the display device storage case 2200 , a right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user. In the display device storage case 2200 , a left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user.

[0241] The image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 so that the light is directed toward the user's right eye. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0242] The image output from the second display panel DP2 can be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 so that the light is directed toward the user's left eye. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0243] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the corresponding sub-region for viewing by the user.

[0244] The foregoing is an illustration of some embodiments of the present disclosure and is not to be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications are possible in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with the specific embodiments may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and is not to be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a first sub-pixel; as well as The second sub-pixel, Each of the first sub-pixel and the second sub-pixel includes: a first electrode; a pixel defining layer on the first electrode and having an opening; a light emitting structure on the first electrode and the pixel defining layer; a second electrode on the light emitting structure and having a disconnected portion; and a third electrode on the second electrode and overlapping the disconnected portion, and The width of the disconnected portion in the first direction is 2.7% or less of the width of the opening in the first direction.

2. The display device according to claim 1, wherein The disconnected portion is located between the first sub-pixel and the second sub-pixel.

3. The display device according to claim 1, wherein The light emitting structure is at least partially separated between the first sub-pixel and the second sub-pixel.

4. The display device according to claim 1, wherein The third electrode is located in the disconnected portion.

5. The display device according to claim 1, wherein The third electrode overlaps the opening. The display device according to claim 1 , wherein: The third electrode does not overlap the opening.

7. The display device according to claim 1, wherein The third electrode is located between the first sub-pixel and the second sub-pixel.

8. The display device according to claim 1, wherein The thickness of the second electrode is 3 nm or more and 14 nm or less.

9. The display device according to claim 1, wherein The thickness of the third electrode is 5 nm or more and 200 nm or less.

10. A display device, comprising: a first sub-pixel; as well as The second sub-pixel, Each of the first sub-pixel and the second sub-pixel includes: a first electrode; a pixel defining layer on the first electrode and having an opening; a light emitting structure on the first electrode and the pixel defining layer and having a first disconnected portion; a second electrode on the light emitting structure and having at least one second disconnected portion; and a third electrode on the second electrode and overlapping the at least one second disconnected portion, and Wherein, a width of the at least one second disconnected portion in the first direction is 2.7% or less of a width of the opening in the first direction.

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