Display device and electronic device

Abstract

A display device and an electronic device are provided, the display device including: a light emitting element disposed on a substrate; a driving voltage line supplying a driving voltage; a first transistor controlling a driving current supplied to the light emitting element; a second transistor supplying a data voltage to a gate electrode of the first transistor; a third transistor supplying a driving voltage to a drain electrode of the first transistor; a first capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the first electrode of the light emitting element; and a second capacitor including a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the light emitting element. The first and second electrodes of the second capacitor are over the first and second electrodes of the first capacitor.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0033230 filed in the Korean Intellectual Property Office on March 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device. Background Art

[0003] As our information-driven society develops, the demands for display devices are increasing. For example, display devices are being adopted by various electronic devices, such as smartphones, digital cameras, laptops, navigation devices, and smart televisions. Display devices can be flat-panel display devices, such as liquid crystal displays, field emission displays, and organic light-emitting displays. Among these flat-panel display devices, emissive displays can include self-emitting light-emitting elements, allowing each pixel in the display panel to emit its own light. Consequently, emissive displays can display images without a backlight unit to supply light to the display panel.

[0004] It will be understood that this background section is intended, in part, to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or insights that were not part of what was known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0005] The disclosed aspects provide a display device that allows easy design of high-resolution pixels by reducing the area of ​​pixel circuits.

[0006] It should be noted that the objects of the disclosure are not limited to the above objects; and other objects of the disclosure will be apparent to those skilled in the art from the following description.

[0007] According to an embodiment, a display device may include: a light-emitting element disposed on a substrate; a driving voltage line for supplying a driving voltage; a first transistor for controlling a driving current supplied to the light-emitting element; a second transistor for supplying a data voltage to a gate electrode of the first transistor; a third transistor for supplying a driving voltage to a drain electrode of the first transistor; a first capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the first electrode of the light-emitting element; and a second capacitor including a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the light-emitting element. The first and second electrodes of the second capacitor are disposed above the first and second electrodes of the first capacitor.

[0008] The display device may further include: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer, the first gate layer including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer disposed on the first gate layer; a first source metal layer disposed on the second gate layer; and a second source metal layer disposed on the first source metal layer. The first gate layer and the second gate layer may include a first material, and the first source metal layer and the second source metal layer may include a second material different from the first material.

[0009] The active layer may include an oxide-based semiconductor region.

[0010] The first electrode of the first capacitor may be formed as a first gate layer, and the second electrode of the first capacitor may be formed as a second gate layer. The first electrode of the second capacitor may be formed as a first source metal layer, and the second electrode of the second capacitor may be formed as a second source metal layer.

[0011] The driving voltage line may include a first portion formed as a first source metal layer and extending in a first direction; and a second portion formed as a second source metal layer and extending in the first direction.

[0012] The first portion of the driving voltage line may include a first electrode of the second capacitor.The second portion of the driving voltage line may supply the driving voltage to a drain electrode of the third transistor.

[0013] The display device may further include an anode connection electrode formed as a second source metal layer, including a second electrode of the second capacitor, and electrically connecting the source electrode of the first transistor to the first electrode of the light emitting element.

[0014] The display area may further include: a display region including a light-emitting element, a first transistor, a second transistor, and a third transistor, and a first capacitor and a second capacitor; and a non-display region surrounding the display area. The first portion and the second portion of the driving voltage line may be spaced apart from each other in the display region and connected to each other in the non-display region.

[0015] The first portion and the second portion of the driving voltage line may overlap each other and may be connected to each other in the display area.

[0016] The display device may further include a third source metal layer disposed on the second source metal layer. The first electrode of the second capacitor may be formed as the second source metal layer, and the second electrode of the second capacitor may be formed as the third source metal layer.

[0017] The display device may further include: a third source metal layer disposed on the second source metal layer; and a fourth source metal layer disposed on the third source metal layer. The first electrode of the second capacitor may be formed as the third source metal layer, and the second electrode of the second capacitor may be formed as the fourth source metal layer.

[0018] The display device may further include: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer, the first gate layer including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer disposed on the first gate layer; a third gate layer disposed on the second gate layer; and a source metal layer disposed on the third gate layer. The first gate layer, the second gate layer, and the third gate layer may include a first material, and the source metal layer may include a second material different from the first material.

[0019] The first electrode of the first capacitor may be formed as a first gate layer, and the second electrode of the first capacitor may be formed as a second gate layer. The first electrode of the second capacitor may be formed as a third gate layer, and the second electrode of the second capacitor may be formed as a source metal layer.

[0020] According to an embodiment, a display device may include: a light-emitting element disposed on a substrate; a driving voltage line including a first portion extending in a first direction and a second portion disposed on the first portion and extending in the first direction; a first transistor controlling a driving current supplied to the light-emitting element; a capacitor electrode disposed on a gate electrode of the first transistor and electrically connected to the first electrode of the light-emitting element; a second transistor supplying a data voltage to the gate electrode of the first transistor; a third transistor receiving a driving voltage from the second portion of the driving voltage line to supply the driving voltage to a drain electrode of the first transistor; an anode connection electrode formed as the same layer as the second portion of the driving voltage line and electrically connecting the first transistor to the light-emitting element; a first capacitor including a first electrode including the gate electrode of the first transistor and a second electrode corresponding to a portion of the capacitor electrode; and a second capacitor including a first electrode corresponding to a portion of the first portion of the driving voltage line and a second electrode corresponding to a portion of the anode connection electrode.

[0021] The display device may further include: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer, the first gate layer including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer disposed on the first gate layer; a first source metal layer disposed on the second gate layer; and a second source metal layer disposed on the first source metal layer. The first gate layer and the second gate layer may include a first material, and the first source metal layer and the second source metal layer may include a second material different from the first material.

[0022] The gate electrode of the first transistor may be formed as a first gate layer, and the capacitor electrode may be formed as a second gate layer. The first portion of the driving voltage line may be formed as a first source metal layer, and the anode connection electrode may be formed as a second source metal layer.

[0023] The display device may further include a third source metal layer disposed on the second source metal layer. The first portion of the driving voltage line may be formed as the second source metal layer, and the anode connection electrode may be formed as the third source metal layer.

[0024] The display device may further include: a third source metal layer disposed on the second source metal layer; and a fourth source metal layer disposed on the third source metal layer. The first portion of the driving voltage line may be formed as the third source metal layer, and the anode connection electrode may be formed as the fourth source metal layer.

[0025] The display device may further include: a display area including a light-emitting element, first, second, and third transistors, and first and second capacitors; and a non-display area surrounding the display area. The first and second portions of the driving voltage line may be spaced apart from each other in the display area and connected to each other in the non-display area.

[0026] The first portion and the second portion of the driving voltage line may overlap each other and may be connected to each other in the display area.

[0027] According to an embodiment, an electronic device includes: a display module configured to provide an image; and a processor configured to transmit an image data signal to the display module. The display module includes: a light-emitting element disposed on a substrate; a driving voltage line for supplying a driving voltage; a first transistor for controlling a driving current supplied to the light-emitting element; a second transistor for supplying a data voltage to a gate electrode of the first transistor; a third transistor for supplying a driving voltage to a drain electrode of the first transistor; a first capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the first electrode of the light-emitting element; and a second capacitor including a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the light-emitting element. The first and second electrodes of the second capacitor are disposed above the first and second electrodes of the first capacitor.

[0028] According to an embodiment, a display device may include a first capacitor formed between a first gate layer and a second gate layer, and a second capacitor formed between a first source metal layer and a second source metal layer, so that the area of ​​a pixel circuit can be reduced by reducing line width and pixel design space, and voltage drop can be reduced. Therefore, the display device can be easily used in a small device.

[0029] It should be noted that the effects of the disclosure are not limited to the above-mentioned effects, and other effects of the disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings, in which: Figure 1 is a schematic perspective view showing a display device according to an embodiment; Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment; Figure 3 is a schematic plan view showing a display unit of a display device according to an embodiment; Figure 4 is a block diagram showing a display panel and a display driver according to an embodiment; Figure 5 is a schematic diagram of an equivalent of a pixel of a display device according to an embodiment; Figure 6 is a schematic diagram showing a layout of pixels of a display device according to an embodiment; Figure 7 It shows Figure 6 A schematic diagram of the layers in the view; Figure 8 It shows Figure 6 Schematic diagram of other layers in the view; Figure 9 It is along Figures 6 to 8 A schematic cross-sectional view taken along line II'; Figure 10 is a schematic diagram showing a layout of layers of pixels in a display device according to an embodiment; Figure 11 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment; Figure 12 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment; Figure 13 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment; Figure 14 is a block diagram of an electronic device according to one embodiment of the present disclosure; Figure 15 is a schematic diagram of an electronic device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] In the following description, for the purpose of explanation, in order to provide a thorough understanding of the various embodiments or implementations disclosed, many specific details are set forth. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method using one or more disclosures disclosed herein. However, it is obvious that various embodiments can be put into practice without these specific details or with one or more equivalent arrangements. In other examples, in order to avoid unnecessarily blurring the various embodiments, structures and devices are shown in block diagram form. In addition, various embodiments can be different, but do not have to be exclusive, nor do they have to limit disclosure. For example, without departing from the disclosure, the specific shape, configuration and characteristics of the embodiment can be used or implemented in other embodiments.

[0032] Unless otherwise specified, the illustrated embodiments will be understood to provide features that provide varying details of some of the disclosed methods that can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be further combined, separated, interchanged, and / or rearranged without departing from the disclosure.

[0033] The use of cross-hatching and / or shading is often provided in the drawings to clarify boundaries between adjacent elements. As such, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. for elements.

[0034] In addition, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0035] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there may be no intervening elements or layers. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0036] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore, the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0037] For the purpose of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, XZ, etc.).

[0038] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in either a conjunction or a disjunction sense and may be understood to be equivalent to "and / or".

[0039] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be named a second element without departing from the teachings of the disclosure.

[0040] For descriptive purposes, spatially relative terms such as "below," "beneath," "beneath," "down," "above," "upper," "on," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (additional) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" another element or feature would then be positioned "above" the other element or feature. Thus, the term "below" can encompass both an above and a below orientation. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0041] The term "overlying" or "overlying" means that a first object can be above, below, or to one side of a second object, and vice versa. Additionally, the term "overlying" may include layering, stacking, facing, or variations thereof, extending over, covering, or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0042] The term "facing" and its variations mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is placed between the first and second elements, although the first and second elements still face each other, the first and second elements can be understood to be indirectly opposite to each other.

[0043] When an element is described as “not overlying” another element or variations thereof, this may include the elements being spaced apart, separated, or offset from each other, or any other appropriate terminology as will be appreciated and understood by those having ordinary skill in the art.

[0044] The terms used herein are for the purpose of describing the embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well.

[0045] When the terms "comprises," "including," "having," and / or variations thereof are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation and not as terms of degree, and are used as such to account for the inherent variations in measured, calculated, and / or provided values ​​that one of ordinary skill in the art would recognize.

[0046] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic representations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments disclosed herein should not necessarily be construed as limited to the illustrated shapes of regions, but rather include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of the device and, as such, are not necessarily intended to be limiting.

[0047] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, parts (components), and / or modules. Those skilled in the art will appreciate that these blocks, units, parts (components), and / or modules are physically implemented using electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based or other manufacturing technologies. Where a block, unit, part (component), and / or module is implemented by a microprocessor or other similar hardware, the block, unit, part (component), and / or module can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and the block, unit, part (component), and / or module can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, part (component), and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, without departing from the scope of the disclosure, each block, unit, part (component) and / or module of some embodiments may be physically divided into two or more interacting and discrete blocks, units, parts (components) and / or modules. In addition, without departing from the scope of the disclosure, the blocks, units, parts (components) and / or modules of some embodiments may be physically combined into more complex blocks, units, parts (components) and / or modules.

[0048] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context and disclosure of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0050] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a schematic perspective view showing a display device according to an embodiment.

[0052] Reference Figure 1 The display device 10 can be used in portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for televisions, laptop computers, monitors, electronic billboards, or Internet of Things (IoT) devices. As another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0053] When viewed from the top, the display device 10 may have a shape similar to a quadrilateral. For example, when viewed from the top, the display device 10 may have a shape similar to a rectangle having a shorter side in the X-axis direction and a longer side in the Y-axis direction. The corner where the shorter side in the X-axis direction and the longer side in the Y-axis direction meet may be rounded to have a selectable curvature or may be formed at a right angle. The shape of the display device 10 when viewed from the top is not limited to a quadrilateral, but may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0054] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0055] The display panel 100 may include a main area MA and an auxiliary area SBA.

[0056] The main area MA may include a display area DA having pixels for displaying an image and a non-display area NDA located around or disposed around the display area DA. The display area DA may output light from multiple emission areas or multiple opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining the emission area or the opening area, and a self-luminous element.

[0057] For example, the self-luminous element may include but is not limited to at least one of the following: an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum dot LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0058] The non-display area NDA may be located or disposed outside the display area DA. The non-display area NDA may be defined as an edge of the main area MA of the display panel 100. The non-display area NDA may include a scan driver that provides scan signals to scan lines and a fan-out line that connects the display driver 200 to the display area DA.

[0059] The auxiliary area SBA may extend from one side or lateral portion of the main area MA. The auxiliary area SBA may include a flexible material that can be bent, folded, or curled. For example, if the auxiliary area SBA is bent, the auxiliary area SBA may overlap the main area MA in the thickness direction (Z-axis direction). The auxiliary area SBA may include a pad (also known as a "soldering pad") that connects to the display driver 200 and the circuit board 300. Alternatively, the auxiliary area SBA may be eliminated, and the display driver 200 and the pad may be disposed in the non-display area NDA.

[0060] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to the data lines. The display driver 200 can apply power voltages to the power lines and supply scan control signals to the scan driver. The display driver 200 can be implemented as an integrated circuit (IC) and can be attached to the display panel 100 using chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 can be disposed in the auxiliary area SBA and can overlap with the main area MA in the thickness direction (Z-axis direction) as the auxiliary area SBA bends. For another example, the display driver 200 can be mounted on the circuit board 300.

[0061] The circuit board 300 may be attached to the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0062] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the multiple touch electrodes of the touch sensing unit and sense changes in capacitance between the multiple touch electrodes. For example, the touch drive signal may be a pulse signal with a selectable frequency. The touch driver 400 may determine whether an input has occurred and locate the coordinates of the input based on the change in capacitance between the touch electrodes. The touch driver 400 may be implemented as an integrated circuit (IC).

[0063] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment.

[0064] Reference Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a transistor layer TFTL, an emission material layer EDL, and an encapsulation layer TFEL.

[0065] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (PI). For another example, the substrate SUB may include a glass material or a metal material.

[0066] The transistor layer TFTL may be disposed on the substrate SUB. The transistor layer TFTL may include a plurality of transistors forming pixel circuits of the pixels. The transistor layer TFTL may also include scan lines, data lines, voltage lines, scan control lines, fan-out lines for connecting the display driver 200 to the data lines, leads for connecting the display driver 200 to pads, and the like. Each transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if a scan driver is formed in the non-display area (NDA) of the display panel 100, the scan driver may include transistors.

[0067] The transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the auxiliary area SBA. Transistors, scan lines, data lines, and power lines for pixels in the transistor layer TFTL may be disposed in the display area DA. Scan control lines and fan-out lines in the transistor layer TFTL may be disposed in the non-display area NDA. Lead lines of the transistor layer TFTL may be disposed in the auxiliary area SBA.

[0068] An emission material layer (EDL) may be disposed on the transistor layer TFTL. The emission material layer (EDL) may include a plurality of light-emitting elements and a pixel-defining layer for defining pixels. In each of the plurality of light-emitting elements, a first electrode, an emission layer, and a second electrode are sequentially stacked to emit light. The plurality of light-emitting elements in the emission material layer (EDL) may be disposed in the display area (DA).

[0069] For example, the emission layer may be an organic light-emitting layer comprising an organic material. The emission layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives an anode voltage through a transistor in the transistor layer TFTL and the second electrode receives a cathode voltage through a transistor in the transistor layer TFTL, holes may move to the organic light-emitting layer through the hole transport layer, and electrons may move to the organic light-emitting layer through the electron transport layer, so that the holes and electrons recombine in the organic light-emitting layer to emit light. For example, the first electrode may be an anode electrode or a pixel electrode, and the second electrode may be a cathode electrode or a common electrode. However, it will be understood that the disclosure is not limited thereto.

[0070] As another example, the light emitting elements may include quantum dot light emitting diodes each including a quantum dot emission layer, inorganic light emitting diodes each including an inorganic semiconductor, or micro light emitting diodes.

[0071] The encapsulation layer TFEL may cover the upper surface and side surfaces of the emission material layer EDL and may protect the emission material layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EDL.

[0072] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing a user's touch through capacitive sensing, and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing unit TSU may sense a user's touch through mutual capacitance sensing or self-capacitance sensing. The plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0073] For another example, the touch sensing unit TSU may be provided on a separate substrate provided on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0074] A color filter layer (CFL) may be provided on the touch sensing unit (TSU). The color filter layer (CFL) may include a plurality of color filters, each associated with a plurality of emission regions. Each color filter selectively transmits light of a selectable wavelength and blocks or absorbs light of other wavelengths. The color filter layer (CFL) may absorb some light introduced from outside the display device 10 to reduce reflection of external light. Thus, the color filter layer (CFL) may prevent color distortion caused by reflection of external light.

[0075] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0076] The auxiliary area SBA of the display panel 100 may extend from one side or lateral portion of the main area MA. The auxiliary area SBA may include a flexible material that can be bent, folded, or rolled. For example, if the auxiliary area SBA is bent, the auxiliary area SBA may overlap the main area MA in the thickness direction (Z-axis direction). The auxiliary area SBA may include pads electrically connected to the display driver 200 and the circuit board 300.

[0077] Figure 3 is a schematic plan view showing a display unit of a display device according to an embodiment.

[0078] Reference Figure 3 , the display unit DU may include a display area DA and a non-display area NDA.

[0079] The display area DA displays an image therein and may be defined as the central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of scan lines SL, a plurality of data lines DL, and a plurality of voltage lines VL. Each of the plurality of pixels SP may be defined as a minimum unit for outputting light.

[0080] The plurality of scan lines SL may provide scan signals received from the scan driver 500 to the plurality of pixels SP. The plurality of scan lines SL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction.

[0081] The plurality of data lines DL may supply data voltages received from the display driver 200 to the plurality of pixels SP. The plurality of data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0082] The plurality of voltage lines VL may supply a power supply voltage received from the display pad DP to the plurality of pixels SP. The power supply voltage may be at least one of a driving voltage, a high-level voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-level voltage. The plurality of voltage lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0083] The non-display area NDA may surround the display area DA or may be adjacent to the display area DA. The non-display area NDA may include a scan driver 500, fan-out lines FOL, and scan control lines SCL. The scan driver 500 may generate a plurality of scan signals based on the scan control signal and may sequentially supply the scan signals to the scan lines SL in a selectable order.

[0084] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0085] The scan control line SCL may extend from the display pad DP to the scan driver 500. The scan control line SCL may provide a scan control signal received from the display pad DP to the scan driver 500.

[0086] The auxiliary area SBA may include the display driver 200 , a display pad area DPA, and first and second touch pad areas TPA1 and TPA2 .

[0087] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be applied to the plurality of pixels SP so that the brightness of the plurality of pixels SP may be determined.

[0088] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed on an edge of the auxiliary area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using a low-resistance, highly reliable material such as an anisotropic conductive film and a self-assembly anisotropic conductive paste (SAP).

[0089] The display pad area DPA may include a plurality of display pads DP. The plurality of display pads DP may be electrically connected to a graphics system via a circuit board 300. The plurality of display pads DP may be connected to the circuit board 300 to receive digital video data and may supply the digital video data to the display driver 200. The display pads DP may supply scan control signals to the scan driver 500 via scan control lines SCL.

[0090] The first touch pad area TPA1 may be provided on one side or side of the display pad area DPA and may include a plurality of first touch pads TP1. The plurality of first touch pads TP1 may be electrically connected to a touch driver 400 provided on the circuit board 300. The plurality of first touch pads TP1 may supply touch drive signals to the plurality of drive electrodes through a plurality of drive lines.

[0091] The second touch pad area TPA2 may be provided on an opposite side of the display pad area DPA and may include a plurality of second touch pads TP2. The plurality of second touch pads TP2 may be electrically connected to a touch driver 400 provided on the circuit board 300. The touch driver 400 may receive touch sensing signals through a plurality of sensing lines connected to the plurality of second touch pads TP2 and may sense changes in capacitance between the driving electrodes and the sensing electrodes.

[0092] Figure 4 is a block diagram illustrating a display panel and a display driver according to an embodiment.

[0093] Reference Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0094] The display area DA may include a plurality of pixels SP, a plurality of voltage lines VL connected to the pixels SP, a plurality of scan lines SL, and a plurality of data lines DL.

[0095] Each of the pixels SP may be connected to a scan line SL, a data line DL, and a voltage line VL. Each of the pixels SP may include a transistor, a light emitting element, and a capacitor.

[0096] The scan lines SL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction. The scan lines SL may sequentially supply scan signals to the plurality of pixels SP.

[0097] The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The data lines DL may supply a data voltage to the pixels SP. The data voltage may determine the brightness of each of the plurality of pixels SP.

[0098] The voltage lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The voltage lines VL may supply a power supply voltage to the plurality of pixels SP. The power supply voltage may be at least one of a driving voltage, a high-level voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-level voltage.

[0099] The timing controller 210 may receive digital video data DATA and a timing signal from the circuit board 300. The timing controller 210 may generate a data control signal DCS based on the timing signal. The timing controller 210 may supply the digital video data DATA and the data control signal DCS to the display driver 200 to control the operation timing of the display driver 200. The display driver 200 may convert the digital video data DATA into analog data voltages and supply them to the data lines DL. The timing controller 210 may generate a scan control signal SCS based on the timing signal. The timing controller 210 may control the operation timing of the scan driver 500 by supplying the scan control signal SCS to the scan driver 500. The scan driver 500 may be provided on at least one of the left and right sides of the non-display area NDA.

[0100] The scan driver 500 may include a plurality of transistors and may generate a scan signal based on a scan control signal SCS. The scan signal of the scan driver 500 may be used to select a pixel SP to which a data voltage is applied, and the selected pixel SP may receive the data voltage via the data line DL. For example, the transistors of the scan driver 500 may be formed in the same layer as the transistors of the pixel SP. The scan driver 500 may supply the scan signal to the scan line SL.

[0101] The power supply unit 600 may apply a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 600 may generate a driving voltage to supply it to a driving voltage line, may generate an initialization voltage to supply it to an initialization voltage line, may generate a bias voltage to supply it to a bias voltage line, and may generate a low-level voltage to supply it to a low-level voltage line.

[0102] Figure 5 is a schematic diagram of an equivalent of a pixel of a display device according to an embodiment.

[0103] Reference Figure 5 , the pixel SP may be connected to the first scan line GWL, the second scan line GCL, the data line DL, the driving voltage line VDL, and the low-level voltage line VSL.

[0104] The pixel SP may include a light emitting element ED and a pixel circuit driving the light emitting element ED. The pixel circuit may include first to third transistors T1, T2, and T3 and first and second capacitors C1 and C2.

[0105] The first transistor T1 may control a driving current supplied to the light emitting element ED. The first transistor T1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor T1 may be connected to the first node N1, the drain electrode thereof may be connected to the third transistor T3, and the source electrode thereof may be connected to the second node N2. The first transistor T1 may control a drain-source current Ids (hereinafter, referred to as "driving current") according to a data voltage applied to the gate electrode. The driving current Ids flowing through the channel of the first transistor T1 may be proportional to the square of the difference between the threshold voltage (Vth) and the voltage (Vgs) between the gate electrode and the source electrode of the first transistor T1 (Ids=k×(Vgs–Vth) 2 ), where k represents a proportionality coefficient determined by the structure and physical properties of the first transistor T1, Vgs represents the drain-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1.

[0106] The light-emitting element ED can receive a driving current Ids to emit light. The amount or brightness of light emitted from the light-emitting element ED can be proportional to the magnitude of the driving current Ids. The light-emitting element ED may include a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element ED may be connected to a second node N2. The first electrode of the light-emitting element ED may be electrically connected to the source electrode of the first transistor T1, the second electrode of the first capacitor C1, and the second electrode of the second capacitor C2 via the second node N2. The second electrode of the light-emitting element ED may be connected to a low-level voltage line VSL to receive a low-level voltage therefrom. For example, the first electrode of the light-emitting element ED may be an anode electrode or a pixel electrode, and the second electrode thereof may be a cathode electrode or a common electrode. However, it will be understood that the disclosure is not limited thereto.

[0107] The second transistor T2 can be turned on by the first scan signal of the first scan line GWL to electrically connect the data line DL to the first node N1, which is the gate electrode of the first transistor T1. The second transistor T2 can be turned on in response to the first scan signal to apply the data voltage to the first node N1. The gate electrode of the second transistor T2 can be connected to the first scan line GWL, the drain electrode thereof can be connected to the data line DL, and the source electrode thereof can be connected to the first node N1.

[0108] The third transistor T3 can be turned on by the second scan signal of the second scan line GCL to electrically connect the drain electrode of the first transistor T1 to the driving voltage line VDL. The gate electrode of the third transistor T3 can be connected to the second scan line GCL, the drain electrode thereof can be connected to the driving voltage line VDL, and the source electrode thereof can be connected to the drain electrode of the first transistor T1.

[0109] In a case where both the third transistor T3 and the first transistor T1 are turned on, the driving current Ids may be supplied to the light emitting element ED.

[0110] The first to third transistors T1, T2, and T3 may include an oxide-based semiconductor region. For example, each of the first to third transistors T1, T2, and T3 may have a coplanar structure in which a gate electrode is disposed above the oxide-based semiconductor region. Transistors having such a coplanar structure have excellent leakage current characteristics and allow low-frequency driving, thereby reducing power consumption. Therefore, the display device 10 may include first to third transistors T1, T2, and T3 having good leakage current characteristics, so that leakage current can be prevented from flowing inside the pixel and the voltage inside the pixel can be stably maintained.

[0111] The first to third transistors T1, T2, and T3 may be n-type transistors. Each of the first to third transistors T1, T2, and T3 may include a drain electrode and a source electrode doped to an n-type. For example, each of the first to third transistors T1, T2, and T3 may output a current flowing into the drain electrode to the source electrode in response to a gate high voltage applied to the gate electrode.

[0112] The first capacitor C1 may be connected between a first node N1, which is the gate electrode of the first transistor T1, and a second node N2, which is the first electrode of the light-emitting element ED. For example, the first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2, so that a potential difference between the gate electrode of the first transistor T1 and the first electrode of the light-emitting element ED can be maintained.

[0113] The second capacitor C2 may be connected between the second node N2, which is the first electrode of the light-emitting element ED, and the driving voltage line VDL. For example, the second electrode of the second capacitor C2 may be connected to the second node N2, and the first electrode of the second capacitor C2 may be connected to the driving voltage line VDL, so that the potential difference between the first electrode of the light-emitting element ED and the driving voltage line VDL can be maintained.

[0114] Figure 6 is a view showing a layout of pixels of a display device according to an embodiment. Figure 7 It shows Figure 6 , showing a stacked structure of a metal layer BML, an active layer ACTL, a first gate layer GTL1 and a second gate layer GTL2. Figure 8 It shows Figure 6 The views of other layers in the view of FIG. 1 show the stacked structure of the first source metal layer SDL1 and the second source metal layer SDL2. Figure 9 It is along Figures 6 to 8Schematic cross-sectional view taken along line II'.

[0115] Reference Figures 6 to 9 , the pixel SP may be connected to the first scan line GWL, the second scan line GCL, the data line DL, the driving voltage line VDL, and the low-level voltage line VSL.

[0116] The first transistor T1 may include a semiconductor region ACT1, a drain electrode DE1, a source electrode SE1, and a gate electrode GE1. The semiconductor region ACT1, drain electrode DE1, and source electrode SE1 of the first transistor T1 may be disposed in (or formed as) the active layer ACTL, and the gate electrode GE1 of the first transistor T1 may be disposed in (or formed as) the first gate layer GTL1. The gate electrode GE1 of the first transistor T1 may be part of the first electrode C1a of the first capacitor C1 and may overlap with the semiconductor region ACT1 of the first transistor T1. For example, the semiconductor region ACT1 of the first transistor T1 may include an oxide, and the drain electrode DE1 and source electrode SE1 of the first transistor T1 may be doped to an n-type.

[0117] The gate electrode GE1 of the first transistor T1 can be electrically connected to the source electrode SE2 of the second transistor T2 via the connection electrode CNE of the second gate layer GTL2. The drain electrode DE1 of the first transistor T1 can be integrated with the source electrode SE3 of the third transistor T3. The source electrode SE1 of the first transistor T1 can be electrically connected to the first electrode AE ​​of the light emitting element ED via the capacitor electrode CPE of the second gate layer GTL2 and the anode connection electrode ANE of the second source metal layer SDL2.

[0118] The second transistor T2 may include a semiconductor region ACT2, a drain electrode DE2, a source electrode SE2, and a gate electrode GE2. The semiconductor region ACT2, drain electrode DE2, and source electrode SE2 of the second transistor T2 may be disposed in (or formed as) the active layer ACTL, and the gate electrode GE2 of the second transistor T2 may be disposed in (or formed as) the first gate layer GTL1. The gate electrode GE2 of the second transistor T2 may overlap with the semiconductor region ACT2 of the second transistor T2. For example, the semiconductor region ACT2 of the second transistor T2 may include an oxide, and the drain electrode DE2 and source electrode SE2 of the second transistor T2 may be doped to an n-type.

[0119] The gate electrode GE2 of the second transistor T2 can be connected to the first scan line GWL of the second gate layer GTL2 to receive a first scan signal. The first scan line GWL can extend in the X-axis direction between the first transistor T1 and the third transistor T3. The drain electrode DE2 of the second transistor T2 can be connected to the data line DL of the first source metal layer SDL1 to receive a data voltage. The source electrode SE2 of the second transistor T2 can be electrically connected to the gate electrode GE1 of the first transistor T1 via the connection electrode CNE.

[0120] The third transistor T3 may include a semiconductor region ACT3, a drain electrode DE3, a source electrode SE3, and a gate electrode GE3. The semiconductor region ACT3, the drain electrode DE3, and the source electrode SE3 of the third transistor T3 may be disposed in (or formed as) the active layer ACTL, and the gate electrode GE3 of the third transistor T3 may be disposed in (or formed as) the first gate layer GTL1. The gate electrode GE3 of the third transistor T3 may overlap with the semiconductor region ACT3 of the third transistor T3. For example, the semiconductor region ACT3 of the third transistor T3 may include an oxide, and the drain electrode DE3 and the source electrode SE3 of the third transistor T3 may be doped to an n-type.

[0121] The gate electrode GE3 of the third transistor T3 can be connected to the first portion GCLa of the second scan line GCL to receive the second scan signal. The first portion GCLa of the second scan line GCL can be disposed in (or formed as) the second gate layer GTL2 and can extend in the X-axis direction. The second portion GCLb of the second scan line GCL can be disposed in (or formed as) the second source metal layer SDL2 and can extend in the Y-axis direction. The drain electrode DE3 of the third transistor T3 can be connected to the second portion VDLb of the drive voltage line VDL to receive a drive voltage or a high-level voltage. The second portion VDLb of the drive voltage line VDL can be disposed in (or formed as) the second source metal layer SDL2 and can extend in the Y-axis direction. The source electrode SE3 of the third transistor T3 can be integral with the drain electrode DE1 of the first transistor T1.

[0122] The first capacitor C1 may include a first electrode C1a and a second electrode C1b. The first electrode C1a and the second electrode C1b of the first capacitor C1 may overlap each other. The first electrode C1a of the first capacitor C1 may be disposed in (or formed as) the first gate layer GTL1, and the second electrode C1b may be disposed in (or formed as) the second gate layer GTL2. The first electrode C1a of the first capacitor C1 may include the gate electrode GE1 of the first transistor T1, and the second electrode C1b may be part of the capacitor electrode CPE. The capacitor electrode CPE may be connected to the source electrode SE1 and the anode connection electrode ANE of the first transistor T1. Thus, the first capacitor C1 may be formed between the first gate layer GTL1 and the second gate layer GTL2.

[0123] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be disposed in (or formed as) the first source metal layer SDL1, and the second electrode C2b may be disposed in (or formed as) the second source metal layer SDL2. The first electrode C2a of the second capacitor C2 may be part of the first portion VDLa of the drive voltage line VDL of the first source metal layer SDL1. The first portion VDLa and the second portion VDLb of the drive voltage line VDL may be spaced apart from each other in the display area DA and may extend parallel in the Y-axis direction when viewed from the top. The first portion VDLa and the second portion VDLb of the drive voltage line VDL may be connected to each other in the non-display area NDA, but the connection location is not limited thereto. The second electrode C2b of the second capacitor C2 may be part of the anode connection electrode ANE. Therefore, the second capacitor C2 may be formed between the first source metal layer SDL1 and the second source metal layer SDL2.

[0124] The low-level voltage line VSL may not be provided in the display area DA, and the voltage of the first electrode AE ​​of the light-emitting element ED may be stabilized by a second capacitor C2 electrically connected to the drive voltage line VDL. Since the display device 10 includes a first capacitor C1 formed between the first gate layer GTL1 and the second gate layer GTL2, and a second capacitor C2 formed between the first source metal layer SDL1 and the second source metal layer SDL2, the area of ​​the pixel circuit can be reduced by reducing the line width and pixel design space, and voltage drop (IR drop) can be reduced. Therefore, the display device 10 can be easily used in small devices with high resolution.

[0125] exist Figure 2In the embodiment, the display panel 100 may include a substrate SUB, a transistor layer TFTL, an emission material layer EDL, and an encapsulation layer TFEL.

[0126] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (PI). For another example, the substrate SUB may include a glass material or a metal material.

[0127] The transistor layer TFTL may include a metal layer BML, a buffer layer BF, an active layer ACTL, a first gate insulator GI1, a first gate layer GTL1, a second gate insulator GI2, a second gate layer GTL2, an interlayer dielectric layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, and a second via layer VIA2. The first gate layer GTL1 and the second gate layer GTL2 may include a first material, and the first source metal layer SDL1 and the second source metal layer SDL2 may include a second material different from the first material. For example, the line width of the first source metal layer SDL1 and the second source metal layer SDL2 may be greater than the line width of the first gate layer GTL1 and the second gate layer GTL2, and the resistance of the first source metal layer SDL1 and the second source metal layer SDL2 may be less than the resistance of the first gate layer GTL1 and the second gate layer GTL2.

[0128] The metal layer BML may be disposed on the substrate SUB. The metal layer BML may include first to third metal layers BML1, BML2, and BML3. The first metal layer BML1 may be disposed below or under the first transistor T1 and may overlap the semiconductor region ACT1 of the first transistor T1. The first metal layer BML1 may block light incident from below the first transistor T1.

[0129] The second metal layer BML2 may be disposed under or below the second transistor T2 and may overlap the semiconductor region ACT2 of the second transistor T2. The second metal layer BML2 may block light incident from below the second transistor T2.

[0130] The third metal layer BML3 may be disposed under or below the third transistor T3 and may overlap the semiconductor region ACT3 of the third transistor T3. The third metal layer BML3 may block light incident from below the third transistor T3.

[0131] The buffer layer BF may be provided on the metal layer BML. For example, the buffer layer BF may include an inorganic film that may prevent air or moisture from penetrating. For example, the buffer layer BF may include a plurality of inorganic films alternately stacked on each other.

[0132] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include an oxide-based material. The active layer ACTL may include semiconductor regions ACT1, ACT2, and ACT3 of the respective first to third transistors T1, T2, and T3, drain electrodes DE1, DE2, and DE3, and source electrodes SE1, SE2, and SE3.

[0133] A first gate insulator GI1 may be disposed on the active layer ACTL. The first gate insulator GI1 may insulate the active layer ACTL from the first gate layer GTL1.

[0134] The first gate layer GTL1 may be disposed on the first gate insulator GI1 . The first gate layer GTL1 may include gate electrodes GE1 , GE2 , and GE3 of respective first to third transistors T1 , T2 , and T3 .

[0135] The second gate insulator GI2 may be disposed on the first gate layer GTL1. The second gate insulator GI2 may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0136] The second gate layer GTL2 may be disposed on the second gate insulator GI2. The second gate layer GTL2 may include the first scan line GWL, the first portion GCLa of the second scan line GCL, the connection electrode CNE, and the capacitor electrode CPE.

[0137] An interlayer dielectric layer ILD may be disposed on the second gate layer GTL2 , and may insulate the second gate layer GTL2 from the first source metal layer SDL1 .

[0138] The first source metal layer SDL1 may be disposed on the interlayer dielectric layer ILD. The first source metal layer SDL1 may include the data line DL and the first portion VDLa of the driving voltage line VDL.

[0139] The first via layer VIA1 may be disposed on the first source metal layer SDL1 and may insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0140] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include an anode connection electrode ANE.

[0141] The second via layer VIA2 may be disposed on the second source metal layer SDL2 and may insulate the second source metal layer SDL2 from the first electrode AE ​​of the light emitting element ED.

[0142] The emission material layer EDL may include a pixel defining layer PDL and a light emitting element ED. The light emitting element ED may include a first electrode AE, an emission layer EL, and a second electrode CE.

[0143] The pixel defining layer PDL may be disposed on the second via layer VIA2 . The pixel defining layer PDL may define a plurality of emission areas EA . The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0144] The first electrode AE ​​may be disposed on the second via layer VIA2. The first electrode AE ​​may overlap one of the plurality of emission areas EA defined by the pixel defining layer PDL. The first electrode AE ​​may receive a driving current from a pixel circuit of the pixel SP.

[0145] The emission layer EL may be disposed on the first electrode AE. For example, the emission layer EL may be, but is not limited to, an organic emission layer made of an organic material. If the emission layer EL is an organic light-emitting layer, when the pixel circuit of the pixel SP applies a selectable voltage to the first electrode AE ​​and the second electrode CE receives a common voltage or a cathode voltage, holes may move to the emission layer EL through the hole transport layer, and electrons may move to the emission layer EL through the electron transport layer, where they recombine to emit light.

[0146] The second electrode CE may be provided on the emission layer EL. For example, the second electrode CE may be implemented in the form of a common electrode extending across all pixels SP, rather than being provided individually in each pixel SP. The second electrode CE may be provided on the emission layer EL in the emission area EA, and may be provided on the pixel defining layer PDL in other areas except the emission area EA.

[0147] The encapsulation layer TFEL may be provided on the second electrode CE to cover the light emitting element ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element ED. The encapsulation layer TFEL may include at least one organic film to protect the light emitting element ED from particles such as dust.

[0148] Figure 10 1 is a diagram showing a layout of layers of pixels in a display device according to an embodiment. In addition to the configuration of the first source metal layer SDL1 and the second source metal layer SDL2, Figure 10 Display device and Figure 6 The display devices are substantially the same; therefore, redundant descriptions will be omitted.

[0149] Reference Figure 10The first source metal layer SDL1 may include a data line DL and a first portion VDLa of a driving voltage line VDL. The data line DL may extend in the Y-axis direction and may supply a data voltage to the drain electrode DE2 of the second transistor T2.

[0150] The first portion VDLa of the driving voltage line VDL may extend in the Y-axis direction. When viewed from the top, the first portion VDLa and the second portion VDLb of the driving voltage line VDL may overlap and may be connected to each other in the display area DA. The first portion VDLa of the driving voltage line VDL may include the first electrode C2a of the second capacitor C2. The first electrode C2a of the second capacitor C2 may not overlap with the second portion VDLb of the driving voltage line VDL.

[0151] The second source metal layer SDL2 may include a second portion GCLb of the second scan line GCL, an anode connection electrode ANE, and a second portion VDLb of the driving voltage line VDL. The second portion GCLb of the second scan line GCL may extend in the Y-axis direction and may be connected to the first portion GCLa of the second scan line GCL of the second gate layer GTL2.

[0152] The anode connection electrode ANE may be connected to the capacitor electrode CPE of the second gate layer GTL2 and the first electrode of the light emitting element ED. The anode connection electrode ANE may include a second electrode C2b of the second capacitor C2.

[0153] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be part of the first portion VDLa of the drive voltage line VDL, and the second electrode C2b may be part of the anode connection electrode ANE. Therefore, the second capacitor C2 may be formed between the first source metal layer SDL1 and the second source metal layer SDL2.

[0154] The low-level voltage line VSL may not be provided in the display area DA, and the voltage of the first electrode AE ​​of the light-emitting element ED may be stabilized by a second capacitor C2 electrically connected to the drive voltage line VDL. Since the display device 10 includes a first capacitor C1 formed between the first gate layer GTL1 and the second gate layer GTL2, and a second capacitor C2 formed between the first source metal layer SDL1 and the second source metal layer SDL2, the area of ​​the pixel circuit can be reduced by reducing the line width and pixel design space, and voltage drop (IR drop) can be reduced. Therefore, the display device 10 can be easily used in small devices with high resolution.

[0155] Figure 111 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment. Figure 11 The display device may further include a third source metal layer SDL3 and the first source metal layer SDL1 and the second source metal layer SDL2 have different configurations. Figure 11 Display device and Figure 6 The display devices are substantially the same; therefore, redundant descriptions will be omitted.

[0156] Reference Figure 11 The first source metal layer SDL1 may include a data line DL. The data line DL may extend in the Y-axis direction and may supply a data voltage to the drain electrode DE2 of the second transistor T2.

[0157] The second source metal layer SDL2 may include a first portion VDLa of the driving voltage line VDL. The first portion VDLa of the driving voltage line VDL may extend in the Y-axis direction. The first portion VDLa of the driving voltage line VDL may include a first electrode C2a of the second capacitor C2.

[0158] A third source metal layer SDL3 may be disposed on the second via layer VIA2. The third via layer VIA3 may be disposed on the third source metal layer SDL3 to insulate the third source metal layer SDL3 from the first electrode AE ​​of the light-emitting element ED. The third source metal layer SDL3 may include an anode connection electrode ANE. The anode connection electrode ANE may be connected to the capacitor electrode CPE of the second gate layer GTL2 and the first electrode AE ​​of the light-emitting element ED. The anode connection electrode ANE may include the second electrode C2b of the second capacitor C2.

[0159] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be part of the first portion VDLa of the drive voltage line VDL, and the second electrode C2b may be part of the anode connection electrode ANE. Therefore, the second capacitor C2 may be formed between the second source metal layer SDL2 and the third source metal layer SDL3.

[0160] The low-level voltage line VSL may not be provided in the display area DA, and the voltage of the first electrode AE ​​of the light-emitting element ED may be stabilized by a second capacitor C2 electrically connected to the drive voltage line VDL. Since the display device 10 includes a first capacitor C1 formed between the first gate layer GTL1 and the second gate layer GTL2, and a second capacitor C2 formed between the second source metal layer SDL2 and the third source metal layer SDL3, the area of ​​the pixel circuit can be reduced by reducing the line width and pixel design space, and voltage drop (IR drop) can be reduced. Therefore, the display device 10 can be easily used in small devices with high resolution.

[0161] Figure 12 1 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment. Figure 12 The display device may further include a third source metal layer SDL3 and a fourth source metal layer SDL4, and in addition to the first source metal layer SDL1 and the second source metal layer SDL2 having different configurations, Figure 12 Display device and Figure 6 The display devices are substantially the same; therefore, redundant descriptions will be omitted.

[0162] Reference Figure 12 The first source metal layer SDL1 may include a data line DL. The data line DL may extend in the Y-axis direction and may supply a data voltage to the drain electrode DE2 of the second transistor T2.

[0163] The second source metal layer SDL2 may be disposed on the first source metal layer SDL1. Figure 12 In the embodiment, the second source metal layer SDL2 may include at least one of the second portion GCLb of the second scan line GCL and the second portion VDLb of the driving voltage line VDL.

[0164] The third source metal layer SDL3 may include a first portion VDLa of the driving voltage line VDL. The first portion VDLa of the driving voltage line VDL may extend in the Y-axis direction. The first portion VDLa of the driving voltage line VDL may include a first electrode C2a of the second capacitor C2.

[0165] A fourth source metal layer SDL4 may be disposed on the third via layer VIA3. The fourth via layer VIA4 may be disposed on the fourth source metal layer SDL4 to insulate the fourth source metal layer SDL4 from the first electrode AE ​​of the light-emitting element ED. The fourth source metal layer SDL4 may include an anode connection electrode ANE. The anode connection electrode ANE may be connected to the capacitor electrode CPE of the second gate layer GTL2 and the first electrode AE ​​of the light-emitting element ED. The anode connection electrode ANE may include the second electrode C2b of the second capacitor C2.

[0166] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be part of the first portion VDLa of the drive voltage line VDL, and the second electrode C2b may be part of the anode connection electrode ANE. Therefore, the second capacitor C2 may be formed between the third source metal layer SDL3 and the fourth source metal layer SDL4.

[0167] The low-level voltage line VSL may not be provided in the display area DA, and the voltage of the first electrode AE ​​of the light-emitting element ED may be stabilized by the second capacitor C2 electrically connected to the drive voltage line VDL. Since the display device 10 includes the first capacitor C1 formed between the first gate layer GTL1 and the second gate layer GTL2, and the second capacitor C2 formed between the third source metal layer SDL3 and the fourth source metal layer SDL4, the area of ​​the pixel circuit can be reduced by reducing the line width and pixel design space, and the voltage drop (IR drop) can be reduced. Therefore, the display device 10 can be easily used in small devices with high resolution.

[0168] Figure 13 is a schematic cross-sectional view showing a pixel in a display device according to an embodiment. Except that the first source metal layer SDL1 and the second source metal layer SDL2 are eliminated, and Figure 13 The display device may further include a third gate insulator GI3, a third gate layer GTL3 and a source metal layer SDL. Figure 13 Display device and Figure 6 The display devices are substantially the same; therefore, redundant descriptions will be omitted.

[0169] Reference Figure 13 A third gate insulator GI3 may be disposed on the second gate layer GTL2 to insulate the second gate layer GTL2 from the third gate layer GTL3. The third gate layer GTL3 may be disposed on the third gate insulator GI3 and include a first portion VDLa of the drive voltage line VDL. The first portion VDLa of the drive voltage line VDL may include the first electrode C2a of the second capacitor C2. For example, the third gate layer GTL3 may also include a gate electrode of a transistor or a scan line.

[0170] The third gate layer GTL3 may include the same first material as the first gate layer GTL1 and the second gate layer GTL2, and the source metal layer SDL may include a second material different from the first material. For example, the line width of the source metal layer SDL may be greater than the line widths of the first to third gate layers GTL1, GTL2, and GTL3, and the resistance of the source metal layer SDL may be less than the resistance of the first to third gate layers GTL1, GTL2, and GTL3.

[0171] The source metal layer SDL may include a data line DL and an anode connection electrode ANE. The data line DL may extend in the Y-axis direction and may supply a data voltage to the drain electrode DE2 of the second transistor T2. A via layer VIA may be provided on the source metal layer SDL.

[0172] The anode connection electrode ANE may be connected to the capacitor electrode CPE of the second gate layer GTL2 and the first electrode of the light emitting element ED. The anode connection electrode ANE may include a second electrode C2b of the second capacitor C2.

[0173] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be part of the first portion VDLa of the drive voltage line VDL, and the second electrode C2b may be part of the anode connection electrode ANE. Therefore, the second capacitor C2 may be formed between the third gate layer GTL3 and the source metal layer SDL.

[0174] The low-level voltage line VSL may not be provided in the display area DA, and the voltage of the first electrode AE ​​of the light-emitting element ED may be stabilized by a second capacitor C2 electrically connected to the drive voltage line VDL. Since the display device 10 includes a first capacitor C1 formed between the first gate layer GTL1 and the second gate layer GTL2, and a second capacitor C2 formed between the third gate layer GTL3 and the source metal layer SDL, the area of ​​the pixel circuit can be reduced by reducing the line width and pixel design space, and voltage drop (IR drop) can be reduced. Therefore, the display device 10 can be easily used in small devices with high resolution.

[0175] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. The electronic device according to one embodiment of the present disclosure includes the above-mentioned display device and may further include a module or device having additional functions in addition to the display device.

[0176] Figure 14 is a block diagram of an electronic device according to one embodiment of the present disclosure.

[0177] Reference Figure 14 According to one embodiment of the present disclosure, the electronic device 1 may include a display module 11 , a processor 12 , a memory 13 , and a power module 14 .

[0178] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0179] The memory 13 may store data information necessary for the operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, which may process the received signals and output image information through a display screen.

[0180] The power module 14 may include a power supply module (such as a power adapter or a battery, for example) and a power conversion module that converts power supplied by the power supply module to generate power necessary for the operation of the electronic device 1 .

[0181] At least one of the components of the electronic device 1 according to one embodiment of the present disclosure may be included in the display device 10 according to an embodiment of the present disclosure. In addition, some of the modules functionally included in one module may be included in the display device 10, and other modules may be provided separately from the display device 10. For example, the display device 10 may include the display module 11, and the processor 12, the memory 13, and the power module 14 may be provided in the form of other devices in the electronic device 1 in addition to the display device 10.

[0182] Figure 15 is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0183] Reference Figure 15 The various electronic devices to which the display device 10 according to an embodiment of the present disclosure is applied may include not only image display electronic devices (such as a smart phone 10_1a, a tablet PC (personal computer) 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e), but also wearable electronic devices including a display module (such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, for example) and vehicle electronic devices 10_3 including a display module (such as a CID (Central Information Display) and a room mirror display arranged on an instrument panel, a center instrument panel, and an instrument panel of a car).

Claims

1. A display device, comprising: A light-emitting element is disposed on the substrate; A driving voltage line, supplying driving voltage; a first transistor for controlling a driving current supplied to the light emitting element; a second transistor, providing a data voltage to a gate electrode of the first transistor; a third transistor, providing the driving voltage to the drain electrode of the first transistor; a first capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the first electrode of the light emitting element; as well as a second capacitor including a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the light emitting element; The first electrode and the second electrode of the second capacitor are arranged above the first electrode and the second electrode of the first capacitor.

2. The display device according to claim 1, further comprising: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer and including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer, disposed on the first gate layer; a first source metal layer, disposed on the second gate layer; as well as A second source metal layer is provided on the first source metal layer, wherein: The first gate layer and the second gate layer include a first material, and The first source metal layer and the second source metal layer include a second material different from the first material.

3. The display device according to claim 2, wherein: The active layer includes an oxide-based semiconductor region.

4. The display device according to claim 2, wherein The first electrode of the first capacitor is formed as the first gate layer, and the second electrode of the first capacitor is formed as the second gate layer, and The first electrode of the second capacitor is formed as the first source metal layer, and the second electrode of the second capacitor is formed as the second source metal layer.

5. The display device according to claim 2, wherein The driving voltage line includes: a first portion formed as the first source metal layer and extending in a first direction; and The second portion is formed as the second source metal layer and extends in the first direction. The display device according to claim 5 , wherein: The first portion of the driving voltage line includes the first electrode of the second capacitor, and The second portion of the driving voltage line supplies the driving voltage to a drain electrode of the third transistor.

7. The display device according to claim 6, further comprising: An anode connection electrode is formed as the second source metal layer, includes the second electrode of the second capacitor, and electrically connects the source electrode of the first transistor to the first electrode of the light emitting element.

8. The display device according to claim 5, further comprising: A display area including the light emitting element, the first transistor, the second transistor, the third transistor, the first capacitor, and the second capacitor; as well as a non-display area surrounding the display area, The first portion and the second portion of the driving voltage line are spaced apart from each other in the display area and connected to each other in the non-display area.

9. The display device according to claim 5, wherein: The first portion and the second portion of the driving voltage line overlap each other and are connected to each other in a display area.

10. The display device according to claim 2, further comprising a third source metal layer, wherein the third source metal layer is disposed on the second source metal layer. in, The first electrode of the second capacitor is formed as the second source metal layer, and the second electrode of the second capacitor is formed as the third source metal layer.

11. The display device according to claim 2, further comprising: a third source metal layer, disposed on the second source metal layer; as well as a fourth source metal layer, disposed on the third source metal layer, The first electrode of the second capacitor is formed as the third source metal layer, and the second electrode of the second capacitor is formed as the fourth source metal layer.

12. The display device according to claim 1, further comprising: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer and including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer, disposed on the first gate layer; a third gate layer, disposed on the second gate layer; as well as a source metal layer, disposed on the third gate layer, The first gate layer, the second gate layer, and the third gate layer include a first material, and the source metal layer includes a second material different from the first material.

13. The display device according to claim 12, wherein: The first electrode of the first capacitor is formed as the first gate layer, and the second electrode of the first capacitor is formed as the second gate layer, and The first electrode of the second capacitor is formed as the third gate layer, and the second electrode of the second capacitor is formed as the source metal layer.

14. A display device, comprising: A light-emitting element is disposed on the substrate; a driving voltage line comprising a first portion extending in a first direction and a second portion disposed on the first portion and extending in the first direction; a first transistor for controlling a driving current supplied to the light emitting element; a capacitor electrode provided on the gate electrode of the first transistor and electrically connected to the first electrode of the light emitting element; a second transistor for supplying a data voltage to the gate electrode of the first transistor; a third transistor receiving a driving voltage from the second portion of the driving voltage line to supply the driving voltage to a drain electrode of the first transistor; an anode connection electrode formed in the same layer as the second portion of the driving voltage line and electrically connecting the first transistor to the light emitting element; a first capacitor including a first electrode including the gate electrode of the first transistor and a second electrode corresponding to a portion of the capacitor electrode; as well as The second capacitor includes a first electrode corresponding to a portion of the first portion of the driving voltage line and a second electrode corresponding to a portion of the anode connection electrode.

15. The display device according to claim 14, further comprising: a metal layer disposed on the substrate; an active layer disposed on the metal layer, the active layer including a semiconductor region of each of the first transistor, the second transistor, and the third transistor; a first gate layer disposed on the active layer, the first gate layer including a gate electrode of each of the first transistor, the second transistor, and the third transistor; a second gate layer, disposed on the first gate layer; a first source metal layer, disposed on the second gate layer; as well as a second source metal layer, disposed on the first source metal layer; The first gate layer and the second gate layer include a first material, and the first source metal layer and the second source metal layer include a second material different from the first material.

16. The display device according to claim 15, wherein The gate electrode of the first transistor is formed as the first gate layer, and the capacitor electrode is formed as the second gate layer, and The first portion of the driving voltage line is formed as the first source metal layer, and the anode connection electrode is formed as the second source metal layer.

17. The display device according to claim 15, further comprising: a third source metal layer, disposed on the second source metal layer; The first portion of the driving voltage line is formed as the second source metal layer, and the anode connection electrode is formed as the third source metal layer.

18. The display device according to claim 15, further comprising: a third source metal layer, disposed on the second source metal layer; and a fourth source metal layer, disposed on the third source metal layer, The first portion of the driving voltage line is formed as the third source metal layer, and the anode connection electrode is formed as the fourth source metal layer.

19. The display device according to claim 14, further comprising: A display area including the light emitting element, the first transistor, the second transistor, the third transistor, the first capacitor, and the second capacitor; as well as a non-display area surrounding the display area, The first portion and the second portion of the driving voltage line are spaced apart from each other in the display area and connected to each other in the non-display area.

20. The display device according to claim 14, wherein The first portion and the second portion of the driving voltage line overlap each other and are connected to each other in a display area.

21. An electronic device, comprising: a display module configured to provide an image; as well as a processor configured to transmit an image data signal to the display module, and The display module includes: a light-emitting element disposed on a substrate; a driving voltage line for supplying a driving voltage; a first transistor for controlling a driving current supplied to the light-emitting element; a second transistor for supplying a data voltage to a gate electrode of the first transistor; a third transistor for supplying the driving voltage to a drain electrode of the first transistor; a first capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the first electrode of the light-emitting element; and a second capacitor including a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the light-emitting element. The first electrode and the second electrode of the second capacitor are arranged above the first electrode and the second electrode of the first capacitor.

Images