Display device and mobile electronic device including the same

Abstract

A display device and a mobile electronic device including the same are provided. The display device includes a display panel having a display area and a non-display area outside the display area. The display panel includes a light emitting element in the display area and a dam structure in the non-display area. The dam structure includes a dam spacer penetrating an insulating film on a substrate of the display panel, a dam insulating film on the insulating film around the dam spacer, and an encapsulation layer covering the dam insulating film and the dam spacer, and the dam insulating film has a tapered shape, the tapered shape has a width that decreases from a surface of the insulating film toward a top of the dam insulating film.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0032011 filed on March 6, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Aspects of embodiments of the present disclosure relate to a display device and a mobile electronic device including the display device. Background Art

[0003] Wearable devices, such as glasses or helmets, have been developed that focus at a distance close to the user's eyes. For example, these wearable devices may be head-mounted displays (HMDs) or AR glasses. These wearable devices can provide users with augmented reality (hereinafter referred to as "AR") or virtual reality (hereinafter referred to as "VR") images.

[0004] Wearable devices, such as head-mounted displays (HMDs) or augmented reality (AR) glasses, ideally require a display resolution of at least 2000 pixels per inch (PPI) to allow users to use them for extended periods without feeling dizzy. To this end, organic light-emitting diode on silicon (OLEDoS) technology, featuring high-resolution, compact organic light-emitting displays, is gaining popularity. In an OLEDoS display panel, a display element layer, including light-emitting elements, is disposed on a semiconductor wafer substrate with a complementary metal oxide semiconductor (CMOS) layer disposed thereon. The display element layer is then covered by an encapsulation layer.

[0005] The encapsulation layer is disposed to extend to the dam area in the non-display area of ​​the display panel to prevent oxygen or moisture from penetrating into the display element layer. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device capable of preventing oxygen or moisture from penetrating into a display element layer by preventing cracks in an encapsulation layer in a dam region of a display panel, and also provide a mobile electronic device including the display device.

[0007] However, the aspects and features of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to an embodiment of the present disclosure, a display device includes a display panel having a display area and a non-display area outside the display area, the display panel including a light-emitting element in the display area and a dam structure in the non-display area. The dam structure includes a dam spacer penetrating an insulating film on a substrate of the display panel, a dam insulating film located on the insulating film around the dam spacer, and an encapsulation layer covering the dam insulating film and the dam spacer, wherein the dam insulating film has a tapered shape having a width that decreases from a surface of the insulating film toward a top of the dam insulating film.

[0009] The dam insulating film may include: a first dam insulating film on the insulating film; a second dam insulating film on the first dam insulating film; and a third dam insulating film on the second dam insulating film.

[0010] The first dam insulating film may have a first width, the second dam insulating film may have a second width smaller than the first width, and the third dam insulating film may have a third width smaller than the second width.

[0011] The light emitting element may include a first electrode, a light emitting stack, and a second electrode sequentially stacked on an insulating film. The edge of the first electrode may be covered by a pixel defining film, and the pixel defining film may be on the same layer as the dam insulating film.

[0012] The pixel-defining film may include: a first pixel-defining film on the insulating film; a second pixel-defining film on the first pixel-defining film; and a third pixel-defining film on the second pixel-defining film.

[0013] At the periphery of the light emitting element, the width of the first pixel defining layer may be greater than the width of the second pixel defining layer and the width of the third pixel defining layer, and the width of the second pixel defining layer may be greater than the width of the third pixel defining layer.

[0014] The first dam insulating film may be at the same layer as the first pixel defining film, the second dam insulating film may be at the same layer as the second pixel defining film, and the third dam insulating film may be at the same layer as the third pixel defining film.

[0015] Each of the first to third dam insulating films may include silicon oxide (SiO x ) of inorganic membrane.

[0016] The thickness of each of the first to third dam insulating films may be 500 Å.

[0017] The encapsulation layer may include: a first encapsulation inorganic film; and a second encapsulation inorganic film on the first encapsulation inorganic film.

[0018] According to another embodiment of the present disclosure, a mobile electronic device includes a display panel having a display area and a non-display area outside the display area, the display panel including a light-emitting element in the display area and a dam structure in the non-display area. The dam structure includes a dam spacer penetrating an insulating film on a substrate of the display panel, a dam insulating film positioned on the insulating film around the dam spacer, and an encapsulation layer covering the dam insulating film and the dam spacer, wherein the dam insulating film has a tapered shape having a width that decreases from a surface of the insulating film toward a top of the dam insulating film.

[0019] The dam insulating film may include: a first dam insulating film on the insulating film; a second dam insulating film on the first dam insulating film; and a third dam insulating film on the second dam insulating film.

[0020] The first dam insulating film may have a first width, the second dam insulating film may have a second width smaller than the first width, and the third dam insulating film may have a third width smaller than the second width.

[0021] The light emitting element may include a first electrode, a light emitting stack, and a second electrode sequentially stacked on an insulating film. The edge of the first electrode may be covered by a pixel defining film, and the pixel defining film may be on the same layer as the dam insulating film.

[0022] The pixel-defining film may include: a first pixel-defining film on the insulating film; a second pixel-defining film on the first pixel-defining film; and a third pixel-defining film on the second pixel-defining film.

[0023] At the periphery of the light emitting element, the width of the first pixel defining layer may be greater than the width of the second pixel defining layer and the width of the third pixel defining layer, and the width of the second pixel defining layer may be greater than the width of the third pixel defining layer.

[0024] The first dam insulating film may be on the same layer as the first pixel defining film, the second dam insulating film may be on the same layer as the second pixel defining film, and the third dam insulating film may be on the same layer as the third pixel defining film.

[0025] Each of the first to third dam insulating films may include silicon oxide (SiO x ) of inorganic membrane.

[0026] The thickness of each of the first to third dam insulating films may be 500 Å.

[0027] The encapsulation layer may include: a first encapsulation inorganic film; and a second encapsulation inorganic film on the first encapsulation inorganic film.

[0028] According to an embodiment of the present disclosure, a display device and a mobile electronic device including the same can prevent oxygen or moisture from penetrating into a display element layer by preventing cracks in an encapsulation layer in a dam region of a display panel.

[0029] However, the aspects and features of the embodiments of the present disclosure are not limited to the above-explained aspects and features, and various other aspects and features are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view of a display device according to one embodiment; Figure 2 is a block diagram illustrating a display device according to one embodiment; Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one embodiment; Figure 4 is a diagram showing a layout of a display panel according to one embodiment; Figure 5 and Figure 6 According to various embodiments Figure 4 The layout diagram of the display area shown in ; Figure 7 It is along Figure 5 A cross-sectional view of the display panel taken along line I1-I1'; Figure 8 is a perspective view of a head mounted display according to one embodiment; Figure 9 yes Figure 8 An exploded perspective view of the head mounted display shown in FIG; Figure 10 is a perspective view of a head-mounted display according to another embodiment; Figure 11 is a diagram showing a mother substrate for manufacturing a display panel according to one embodiment; Figure 12 It is along Figure 11 A cross-sectional view of a display panel according to a comparative example taken along line AA′ in FIG. Figure 13 yes Figure 12 a cross-sectional view of a portion of the dam area shown in ; Figure 14 It is along Figure 11 A cross-sectional view of a display panel according to an embodiment taken along line AA′ in FIG. Figure 15 and Figure 16 According to various embodiments Figure 14 A cross-sectional view of a portion of the dam area is shown in FIG. DETAILED DESCRIPTION

[0031] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0032] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. When an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, no intervening elements or layers are present. For example, when a first element is described as being “coupled to” or “connected to” a second element, the first element may be directly coupled to or directly coupled to the second element, or the first element may be indirectly coupled to or indirectly coupled to the second element via one or more intervening elements.

[0033] In the accompanying drawings, the dimensions of various elements, layers, etc. may be exaggerated for clarity. Identical reference numerals represent identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." Expressions such as "at least one of..." and "any of...", when following a list of elements, modify the entire list of elements, rather than the individual elements in that list. For example, the expression "at least one of a, b, and c" refers to only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c, or variations thereof. As used herein, the term "using" and its variations may be considered synonymous with the term "utilizing" and its variations, respectively. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent variability of measured or calculated values ​​that one of ordinary skill in the art would recognize.

[0034] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the exemplary embodiments, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0035] For ease of description, spatially relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0036] The terms used herein are for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms. It will also be understood that when the terms "comprises," "comprising," and / or variations thereof are used in this specification, the description indicates the presence of the stated features, wholes, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0037] It will be understood by those skilled in the art that, in view of the overall content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be technically interlocked and operated in various suitable manners, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0038] In addition, any numerical range disclosed and / or described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the described minimum value of 1.0 and the described maximum value of 10.0, for example, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to explicitly describe any subranges contained within the ranges explicitly described herein. All such ranges are intended to be inherently described in this specification so that modifications to explicitly describe any such subranges will meet the requirements.

[0039] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0040] Figure 1 is an exploded perspective view of a display device according to one embodiment. Figure 2 is a block diagram illustrating a display device according to one embodiment.

[0041] Reference Figure 1 and Figure 2 According to one embodiment, the display device 10 is a device for displaying moving images and / or still images. The display device 10 according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). For example, the display device 10 according to one embodiment can be applied to (or used as) a display unit for a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. In other embodiments, the display device 10 can be applied to smart watches, watch phones, head-mounted displays (HMDs) for implementing virtual reality and augmented reality, and the like.

[0042] According to one embodiment, a display device 10 includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0043] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 that intersects (e.g., intersects) the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of the present disclosure are not limited thereto.

[0044] like Figure 2 As shown in FIG, the display panel 100 has a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0045] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0046] The plurality of pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 and be arranged in the second direction DR2 (e.g., adjacent to each other in the second direction DR2). The plurality of data lines DL may extend in the second direction DR2 and be arranged in the first direction DR1 (e.g., adjacent to each other in the first direction DR1).

[0047] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0048] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may each include, for example, Figure 3 The plurality of pixel transistors shown in FIG. 3 and FIG. 4 can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see, for example, FIG. 4 ). Figure 7 For example, a plurality of pixel transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0049] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines GBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the received data voltage.

[0050] The non-display area NDA includes a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0051] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see, for example, FIG. 1 ) by a semiconductor process. Figure 7 ) on. For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed as CMOS. Although Figure 2 The embodiment shown in FIG shows that the scan driver 610 is arranged on the left side of the display area DAA and the emission driver 620 is arranged on the right side of the display area DAA, but the embodiments of the present disclosure are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be arranged on both the left and right sides of the display area DAA.

[0052] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400 and may sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS and may sequentially output the bias scan signal to the bias scan line GBL.

[0053] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate a first emission control signal based on the emission timing control signal ECS and can sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 can generate a second emission control signal based on the emission timing control signal ECS and can sequentially output the second emission control signal to the second emission control line EL2.

[0054] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see, for example, FIG. 1 ) by a semiconductor process. Figure 7 For example, the plurality of data transistors may be formed as CMOS.

[0055] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In such an embodiment, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0056] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 dissipates heat generated in (or by) the display panel 100. The heat dissipation layer 200 may include a layer (for example, a metal layer) containing a material having relatively high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0057] The circuit board 300 can be electrically connected to a plurality of first pads PD1 (see, for example, FIG. 1 ) of a first pad portion PDA1 of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ). The circuit board 300 may be a flexible printed circuit board formed of a flexible material or may be a flexible film. Figure 1100, but the circuit board 300 may be bent. In the bent state, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be a plurality of first pads PD1 of the circuit board 300 connected to the first pad portion PDA1 of the display panel 100 using a conductive adhesive member (see, for example, Figure 4 ) at the opposite end of the other end.

[0058] The timing control circuit 400 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0059] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and can supply them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0060] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In such an embodiment, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 via the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 via the circuit board 300.

[0061] In another embodiment, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100. In such an embodiment, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on the semiconductor substrate SSUB (see, for example, FIG. 1 ) by a semiconductor process. Figure 7 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed as CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be provided between the data driver 700 and the first pad portion PDA1 (see, for example Figure 4 )between.

[0062] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0063] Reference Figure 3 , the first subpixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first subpixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. For example, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In such an embodiment, the first drive voltage VSS can be lower than the third drive voltage VINT, and the second drive voltage VDD can be higher than the third drive voltage VINT.

[0064] According to the illustrated embodiment, the first subpixel SP1 includes a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0065] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE (e.g., the amount of light emitted by the light-emitting element LE) may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but embodiments of the present disclosure are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0066] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as a "driving current") flowing between its source and drain electrodes according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0067] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0068] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. To this end, because the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0069] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0070] The fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0071] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0072] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0073] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0074] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0075] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present disclosure are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. In some embodiments, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0076] although Figure 3 The embodiment shown in FIG shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3The number of transistors and the number of capacitors shown in .

[0077] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same as that of the first sub-pixel SP1 , and therefore, descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are omitted in the present disclosure.

[0078] Figure 4 is a layout diagram of a display panel according to an embodiment.

[0079] Reference Figure 4 According to one embodiment, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix form. According to one embodiment, the non-display area NDA of the display panel 100 includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0080] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, embodiments of the present disclosure are not limited thereto, and in other embodiments, the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0081] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0082] The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0083] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or probe pins during the inspection process or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0084] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P data lines DL (where P is a positive integer of 2 or greater), thereby reducing the number of first pads PD1. The first distribution circuit 710 can be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0085] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0086] Figure 5 and Figure 6 According to various embodiments Figure 4 Layout diagram of the display area shown in .

[0087] Reference Figure 5 and Figure 6 , each of the pixels PX includes a first emission area EA1 as an emission area of ​​the first sub-pixel SP1, a second emission area EA2 as an emission area of ​​the second sub-pixel SP2, and a third emission area EA3 as an emission area of ​​the third sub-pixel SP3.

[0088] Each of the first, second, and third emission regions EA1, EA2, and EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape in a plan view.

[0089] The maximum length of the first emission area EA1 in the first direction DR1 may be less than the maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the third emission area EA3 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0090] The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2 and the maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 may be less than the maximum length of the third emission area EA3 in the second direction DR2. In another embodiment, the maximum length of the third emission area EA3 in the second direction DR2 may be less than the maximum length of the second emission area EA2 in the second direction DR2.

[0091] like Figure 6 As shown in FIG, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape having six straight lines (or formed by six straight lines) in a plan view, but the embodiments of the present disclosure are not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a hexagon, a circular shape, an elliptical shape, or an atypical shape in a plan view.

[0092] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different from each other.

[0093] In another embodiment, if Figure 6 As shown in , the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1 and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0094] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. In one embodiment, the light of the first color may be light in a blue band, the light of the second color may be light in a green band, and the light of the third color may be light in a red band. For example, the blue band may be a band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green band may be a band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red band may be a band of light having a main peak wavelength in the range of about 600 nm to about 750 nm.

[0095] exist Figure 5 and Figure 6 In the embodiment shown in , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the embodiments of the present disclosure are not limited thereto. For example, in other embodiments, each of the plurality of pixels PX may include four emission areas.

[0096] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 5 and Figure 6 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged in the first direction DR1, a PenTile structure in which the emission regions are arranged in a diamond shape, or a PenTile structure in which the emission regions are arranged in a diamond shape. ® (Registered trademark of Samsung Display Co., Ltd.) structure, or Figure 6 The hexagonal structure shown in FIG. 1 has emitting areas having a hexagonal shape in a plan view arranged side by side.

[0097] Figure 7 It is along Figure 5 sectional view of the display panel taken along line I1-I1'.

[0098] Reference Figure 7 The display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate POL.

[0099] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 4 The first to sixth transistors T1 to T6 are described.

[0100] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be disposed in (or on) the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0101] Each of the plurality of well regions WA has a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0102] The lower insulating film BINS may be provided between the gate electrode GE and the well area WA. The side insulating film SINS may be provided on the side surface of the gate electrode GE. The side insulating film SINS may be provided on the lower insulating film BINS.

[0103] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0104] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby preventing a breakdown phenomenon and a hot carrier phenomenon that may be caused by a short channel.

[0105] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0106] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0107] A plurality of contact terminals CTE may be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of each of the pixel transistors PTR via a hole (e.g., an opening) penetrating (or extending through) the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these.

[0108] The third semiconductor insulating film SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0109] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate (such as polyimide). In such an embodiment, the pixel transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0110] The light emitting element back plate EBP includes a plurality of conductive layers ML1 to ML8 , a plurality of vias VA1 to VA9 , and a plurality of insulating films INS1 to INS9 .

[0111] The first conductive layer ML1 to the eighth conductive layer ML8 are connected to a plurality of contact terminals CTE exposed from the semiconductor back plate SBP, thereby realizing, for example, Figure 4 , the circuit of the first subpixel SP1 is shown in FIG. For example, the first to sixth transistors T1 to T6 are formed on the semiconductor backplane SBP, and connections between the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2 are established through the first to eighth conductive layers ML1 to ML8. Furthermore, connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also established through the first to eighth conductive layers ML1 to ML8.

[0112] The first insulating film INS1 may be provided on the semiconductor backplane SBP. Each of the first via holes VA1 may penetrate the first insulating film INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be provided on the first insulating film INS1 and may be connected to the first via hole VA1.

[0113] The second insulating film INS2 may be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second via holes VA2 may penetrate the second insulating film INS2 and may be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating film INS2 and may be connected to the second via holes VA2.

[0114] The third insulating film INS3 may be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third via holes VA3 may penetrate the third insulating film INS3 and may be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating film INS3 and may be connected to the third via holes VA3.

[0115] The fourth insulating film INS4 may be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth via holes VA4 may penetrate the fourth insulating film INS4 and may be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating film INS4 and may be connected to the fourth via holes VA4.

[0116] The fifth insulating film INS5 may be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth via holes VA5 may penetrate the fifth insulating film INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating film INS5 and may be connected to the fifth via holes VA5.

[0117] The sixth insulating film INS6 may be provided on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth via holes VA6 may penetrate the sixth insulating film INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be provided on the sixth insulating film INS6 and may be connected to the sixth via hole VA6.

[0118] The seventh insulating film INS7 may be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh via holes VA7 may penetrate the seventh insulating film INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating film INS7 and may be connected to the seventh via hole VA7.

[0119] The eighth insulating film INS8 may be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth via holes VA8 may penetrate the eighth insulating film INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating film INS8 and may be connected to the eighth via hole VA8.

[0120] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any one of them. The first to eighth insulating films INS1 to INS8 may be made of substantially the same material. The first to eighth insulating films INS1 to INS8 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0121] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å, the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be approximately 1440Å, and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may be approximately 1150Å.

[0122] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0123] The ninth insulating film INS9 may be provided on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0124] Each of the ninth via holes VA9 may penetrate the ninth insulating film INS9 and may be connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. The thickness of the ninth via hole VA9 may be approximately 16,500 Å.

[0125] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include a light emitting element LE, a reflective electrode layer RL, tenth and eleventh insulating films INS10 and INS11, tenth via holes VA10, a pixel defining layer PDL, and a plurality of trenches TRC. Each light emitting element LE includes a first electrode AND, a light emitting stack IL, and a second electrode CAT.

[0126] The reflective electrode layer RL may be provided on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include: Figure 7 1 to the fourth reflective electrodes RL1 , RL2 , RL3 and RL4 shown in FIG.

[0127] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0128] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0129] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0130] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0131] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å.

[0132] The tenth insulating film INS10 may be provided on the ninth insulating film INS9. The tenth insulating film INS10 may be provided between the reflective electrode layers RL adjacent to each other in the horizontal direction. Figure 7Although not specifically shown, the tenth insulating film INS10 may be provided on the reflective electrode layer RL in the third sub-pixel SP3. The tenth insulating film INS10 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0133] The eleventh insulating film INS11 may be provided on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 may be made of silicon oxide (SiO x The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL among light emitted from the light emitting element LE passes.

[0134] Although Figure 7 Although not specifically shown, in order to match the resonance distance of the light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be disposed under the first electrode AND of the first sub-pixel SP1. The first electrode AND of the first sub-pixel SP1 may be directly disposed on the reflective electrode layer RL. The eleventh insulating film INS11 may be disposed under the first electrode AND of the second sub-pixel SP2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed under the first electrode AND of the third sub-pixel SP3. In other embodiments, such as Figure 7 As shown in , the eleventh insulating film INS11 can be disposed under the first electrode AND of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and the thickness of the eleventh insulating film INS11 under the first electrode AND of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different from each other.

[0135] Therefore, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main (or primary) peak wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7In the embodiment shown in , the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, but the embodiments of the present disclosure are not limited thereto.

[0136] In addition, despite Figure 7 In the embodiment shown in , the tenth insulating film INS10 and the eleventh insulating film INS11 are shown, but a twelfth insulating film provided under the first electrode AND of the first sub-pixel SP1 may be added. In such an embodiment, the eleventh insulating film INS11 and the twelfth insulating film may be provided under the first electrode AND of the second sub-pixel SP2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be provided under the first electrode AND of the third sub-pixel SP3.

[0137] Each of the tenth via holes VA10 may penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second sub-pixel SP2 and the third sub-pixel SP3 and may be connected to the fourth reflective electrode RL4 in the reflective electrode layer RL. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. The thickness of the tenth via hole VA10 in the second sub-pixel SP2 may be thinner than the thickness of the tenth via hole VA10 in the third sub-pixel SP3.

[0138] The first electrode AND of each light-emitting element LE may be disposed on the eleventh insulating film INS11 and the tenth insulating film INS10 and connected to the tenth via VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0139] The pixel definition film PDL may be disposed on a portion of the first electrode AND of each light emitting element LE. The pixel definition film PDL may cover an edge of the first electrode AND of each light emitting element LE. The pixel definition film PDL may partition the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0140] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0141] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto. The first pixel defining film PDL1, the second pixel defining film PDL2 and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0142] When the first, second, and third pixel-defining films PDL1, PDL2, and PDL3 are formed into a single pixel-defining film, the height of the single pixel-defining film increases, potentially causing the first encapsulating inorganic film TFE1 to be severed (or separated) due to step coverage. Step coverage refers to the ratio of the amount of film applied on inclined portions to the amount applied on flat portions. The lower the step coverage, the more likely the film will be severed at the inclined portion.

[0143] Therefore, to prevent the first encapsulating inorganic film TFE1 from being cut due to step coverage, the first, second, and third pixel defining films PDL1, PDL2, and PDL3 may have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second and third pixel defining films PDL2, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first and second directions DR1 and DR2.

[0144] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In addition, each of the plurality of trenches TRC may penetrate the eleventh insulating film INS11. The tenth insulating film INS10 may be partially recessed at each of the plurality of trenches TRC.

[0145] At least one trench TRC may be provided between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 An embodiment is shown in which two trenches TRC are provided between adjacent sub-pixels SP1 , SP2 , and SP3 , but embodiments of the present disclosure are not limited thereto.

[0146] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 The light emitting stack IL has a three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a two-series structure including two intermediate layers.

[0147] In a triple-series structure, the light-emitting stack IL may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights (e.g., lights of different colors). For example, the light-emitting stack IL may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a second color, and a third stack layer IL3 that emits light of a third color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be stacked sequentially.

[0148] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0149] A first charge generation layer for supplying holes to the second stack layer IL2 and electrons to the first stack layer IL1 may be provided between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0150] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be provided between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0151] The first stacked layer IL1 can be disposed on the first electrode AND and the pixel-defining film PDL and can be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be cut off between adjacent sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut off between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS (or empty space) can be formed between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and can be arranged to cover the second stacked layer IL2 in each trench TRC. For example, in a three-tandem structure, each of the multiple trenches TRC can be a structure for cutting off the first and second stacked layers IL1 and IL2 of the display element layer EML and the first and second charge generation layers between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in the two-series structure, each of the trenches TRC may be a structure for cutting off the charge generation layer provided between the lower intermediate layer and the upper intermediate layer, and the lower intermediate layer.

[0152] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel-defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL in the third direction DR3. In order to cut off the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure may be used instead of the grooves TRC. For example, instead of the grooves TRC, an inverted tapered partition wall may be provided on the pixel-defining film PDL.

[0153] The number of stacked layers IL1, IL2 and IL3 emitting different light is not limited to Figure 7 . For example, the light-emitting stack IL may include two intermediate layers. In such an embodiment, one of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In such an embodiment, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be provided between the two intermediate layers.

[0154] in addition, Figure 7 An embodiment is shown in which the first to third stacked layers IL1, IL2, and IL3 are all disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. For example, the first stacked layer IL1 may be disposed in the first emission area EA1 and may not be disposed in the second emission area EA2 and the third emission area EA3. In addition, the second stacked layer IL2 may be disposed in the second emission area EA2 and may not be disposed in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be disposed in the third emission area EA3 and may not be disposed in the first emission area EA1 and the second emission area EA2. In such an embodiment, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0155] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO) such as ITO or IZO, or a semi-transmitting conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmitting conductive material, light emission efficiency may be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0156] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0157] The first encapsulation inorganic film TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic film TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic film TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0158] The second encapsulation inorganic film TFE2 may be provided on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 may be made of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but the embodiments of the present disclosure are not limited thereto. The second encapsulating inorganic film TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulating inorganic film TFE2 may be less than that of the first encapsulating inorganic film TFE1.

[0159] The organic film APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0160] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0161] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light in a blue wavelength band). The blue wavelength band may be in the range of approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0162] The second color filter CF2 may overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color (e.g., light in a green wavelength band). The green wavelength band may be in the range of approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0163] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light in a red wavelength band). The red wavelength band may be in the range of approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0164] A plurality of lenses LNS may be provided on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front side of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0165] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0166] The cover layer CVL may be disposed on the filler layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it may be attached to the filler layer FIL. In such an embodiment, the filler layer FIL may bond the cover layer CVL to the underlying layer. When the cover layer CVL is a glass substrate, it may serve as an encapsulation substrate. When the cover layer CVL is a polymer resin, it may be applied directly to the filler layer FIL.

[0167] A polarizing plate (POL) may be provided on one surface of the cover layer (CVL). The polarizing plate (POL) may be configured to prevent visibility degradation caused by external light reflection. The polarizing plate (POL) may include a linear polarizing plate and a phase retarder film. For example, the phase retarder film may be a λ / 4 plate (quarter-wave plate), but the embodiments of the present disclosure are not limited thereto. However, if visibility degradation caused by external light reflection is sufficiently mitigated by using the first to third color filters (CF1, CF2, and CF3), the polarizing plate (POL) may be omitted.

[0168] Figure 8 is a perspective view of a head-mounted display according to one embodiment. Figure 9 yes Figure 8 An exploded perspective view of the head-mounted display shown in .

[0169] Reference Figure 8 and Figure 9 According to one embodiment, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520 and a control circuit board 1600.

[0170] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0171] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0172] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 supports and secures the first and second display devices 10_1 and 10_2 and the control circuit board 1600.

[0173] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0174] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In another embodiment, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0175] The display device housing 1100 accommodates the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is provided and a second eyepiece 1220 at which the user's right eye is provided. Figure 8 and Figure 9 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately provided, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0176] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0177] The head-mounted strap 1300 fixes the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned on the user's left eye and right eye, respectively (for example, in front of the user's left eye and right eye). When the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 may be provided with a plurality of eyepieces such as the eyepiece 1210 and the eyepiece 1220. Figure 10 The eyeglass frame shown in FIG. 1 is not a headband 1300 .

[0178] The head-mounted display 1000 may also include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0179] Figure 10 is a perspective view showing a head-mounted display according to another embodiment.

[0180] Reference Figure 10 According to one embodiment, the head-mounted display 1000_1 may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to one embodiment, the head-mounted display 1000_1 may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0181] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may view an augmented reality image through the right eye that is a combination of a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020.

[0182] Figure 10 While an embodiment in which the display device housing 1200_1 is disposed at the right end of the support frame 1030 is shown, embodiments of the present disclosure are not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in such an embodiment, the image of the display device 10_3 may be provided to the user's left eye. In another embodiment, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in such an embodiment, the user may view the image displayed on the display device 10_3 with both the left and right eyes.

[0183] Figure 11 is a diagram illustrating a mother substrate for manufacturing the display panel 100 according to one embodiment.

[0184] Reference Figure 11The mother substrate 1700 may be a semiconductor wafer used to manufacture the OLEDoS display panel 100. In the present disclosure, the semiconductor wafer may be referred to as a "semiconductor substrate," a "substrate," or a "semiconductor wafer substrate."

[0185] The mother substrate 1700 may include a plurality of mesh dies 1701, and one mesh die 1701 may correspond to one display panel 100. For example, the mother substrate 1700 as a semiconductor wafer may include about 76 mesh dies 1701, which means that about 76 display panels 100 can be manufactured from one mother substrate 1700.

[0186] The plurality of display panels 100 manufactured based on the mother substrate 1700 may be individually separated through a scribing (or cutting) process and a grinding process in which a corner of each display panel 100 is polished into a round shape.

[0187] The display panel 100 may have a display area DAA at which the light emitting element LE is disposed and a non-display area NDA disposed outside the display area DAA.

[0188] A driving circuit such as the data driver 700 may be provided in the non-display area NDA of the display panel 100. Figure 4 As described, the data driver 700 may be disposed adjacent to one end of the display panel 100. In the illustrated embodiment, although the data driver 700 is disposed adjacent to the lower end of the display panel 100, embodiments of the present disclosure are not limited thereto.

[0189] Weir area 1803 for preventing moisture and oxygen penetration (see e.g. Figure 12 ), moisture penetration / crack prevention area 1805 (see e.g. Figure 12 ) and at least one dummy region 1801, 1804, and 1806 (see e.g. Figure 12 ) is provided in the non-display area NDA of the display panel 100. Figure 12 and Figure 14 The non-display area NDA of the display panel 100 is described in detail.

[0190] Figure 12 Based on the comparison example Figure 11 A cross-sectional view of the display panel taken along line AA' in FIG. Figure 12 , the pixel definition film PDL is shown as the uppermost layer, and the stacked structure (eg, Figure 7 The encapsulation layer TFE shown in FIG.

[0191] Reference Figure 12, the display panel according to the comparative example has a display area DAA at which the light emitting element LE is provided and a non-display area NDA provided outside the display area DAA.

[0192] According to a comparative example, the non-display area NDA may include a first dummy area 1801, a cathode contact area 1802, a dam area 1803, a second dummy area 1804, a moisture permeation / crack prevention area 1805, and a third dummy area 1806. The non-display area NDA may not include at least one of the first dummy area 1801, the second dummy area 1804, and the third dummy area 1806.

[0193] According to a comparative example, the first dummy region 1801 may be positioned closest to the display region DAA, and the third dummy region 1806 may be positioned furthest from the display region DAA. The second dummy region 1804 may be positioned between the first dummy region 1801 and the third dummy region 1806. The dam region 1803 may be positioned between the first dummy region 1801 and the second dummy region 1804. The moisture penetration / crack prevention region 1805 may be positioned between the second dummy region 1804 and the third dummy region 1806.

[0194] The cathode contact region 1802 includes a cathode pad, and the second electrode extending from the display area DAA is connected to the cathode pad. For example, the second electrode can be connected to the first driving voltage line VSL (see, for example, FIG. 2 ) through the cathode contact region 1802. Figure 3 ).

[0195] The dam area 1803 includes at least one dam structure DAM having a dam spacer DTRC penetrating the insulating film INS. The dam area 1803 may be a boundary area to which the encapsulation layer TFE covering the display area DAA extends.

[0196] The moisture penetration / crack prevention region 1805 blocks oxygen or moisture from flowing into the display panel 100 during a scribing process and a grinding process for the display panel 100 .

[0197] The third dummy region 1806 may be substantially a region for cutting one display panel 100 during a scribing process.

[0198] According to the comparative example, the stack structure of each of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, the moisture penetration / crack prevention region 1805, and the third dummy region 1806 is similar to the stack structure of the semiconductor back panel SBP and the light emitting element back panel EBP provided in the display area DAA. For example, the stack structure of each of the first conductive layer ML1 to the eighth conductive layer ML8 (see, for example, FIG. 1 ) of the semiconductor back panel SBP and the light emitting element back panel EBP provided in the display area DAA is similar to the stack structure of the semiconductor back panel SBP and the light emitting element back panel EBP provided in the display area DAA. Figure 7 ) A dummy conductive layer provided in the same layer is provided in each of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, the moisture penetration / crack prevention region 1805, and the third dummy region 1806. Figure 12 Reference numerals ML1 to ML8 shown in FIG. Figure 7 The first conductive layer ML1 to the eighth conductive layer ML8 shown in FIG. 5 are provided on the same layer as the dummy conductive layers ML1 to ML8 .

[0199] According to a comparative example, at least some of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, the moisture penetration / crack prevention region 1805, and the third dummy region 1806 may further include a dummy reflective electrode provided at the same layer as the reflective electrode layer RL provided in the display area DAA. Figure 12 As shown in FIG, each of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, and the third dummy region 1806 may further include a reflective electrode layer RL disposed in the display area DAA (see, for example, FIG. Figure 7 ) is provided on the same layer as the dummy reflective electrode. Figure 12 The reference symbol RL shown in FIG. Figure 7 The reflective electrode layer RL shown in FIG is provided on the same layer as the dummy reflective electrode RL.

[0200] According to a comparative example, at least some of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, the moisture permeation / crack prevention region 1805, and the third dummy region 1806 may include a first electrode AND disposed in the display area DAA (see, e.g., Figure 7 ) is provided on the same layer as the dummy conductive layer. Figure 12 The reference symbol AND shown in Figure 7 The first electrode AND shown in FIG is provided on the same layer as the dummy conductive layer AND.

[0201] According to the comparative example, a pixel defining film PDL extending from the display area DAA is provided on the dummy conductive layer AND in each of the first dummy region 1801, the cathode contact region 1802, the dam region 1803, the second dummy region 1804, the moisture permeation / crack prevention region 1805, and the third dummy region 1806. The pixel defining film PDL may function as a dam insulating film DINS forming the dam structure DAM in the dam region 1803.

[0202] In the following, reference will be made to Figure 13A stack structure of the dam region 1803 of the display panel 100 according to a comparative example and its disadvantages are described.

[0203] Figure 13 It shows that according to Figure 12 18 is a cross-sectional view of a portion of a dam region 1803 of a comparative example shown in FIG.

[0204] Reference Figure 12 and Figure 13 The dam region 1803 of the display panel according to the comparative example includes at least one dam structure DAM. The dam structure DAM includes a substrate (eg, Figure 7 The insulating film INS (for example, Figure 7 The dam spacer DTRC includes a tenth insulating film INS10 and / or an eleventh insulating film INS11, a dam insulating film DINS disposed on the insulating film INS around the dam spacer DTRC, and an encapsulation layer TFE (for example, Figure 7 encapsulation layer TFE).

[0205] According to the comparative example, the insulating film INS penetrated by the dam spacer DTRC may be a reference Figure 7 The tenth insulating film INS10 and the eleventh insulating film INS11 are described.

[0206] According to the comparative example, the dam insulating film DINS disposed on the insulating film INS around the dam spacer DTRC may be the same as the reference Figure 7 The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are described as being arranged on the same insulating film layer. For example, the dam insulating film DINS may include a first dam insulating film DINS1, a second dam insulating film DINS2 arranged on the first dam insulating film DINS1, and a third dam insulating film DINS3 arranged on the second dam insulating film DINS2. The first dam insulating film DINS1 includes the same material as the first pixel defining film PDL1 and is arranged on the same layer as the first pixel defining film PDL1. The second dam insulating film DINS2 includes the same material as the second pixel defining film PDL2 and is arranged on the same layer as the second pixel defining film PDL2. The third dam insulating film DINS3 includes the same material as the third pixel defining film PDL3 and is arranged on the same layer as the third pixel defining film PDL3.

[0207] According to the comparative example, the encapsulation layer TFE is provided to extend from the display area DAA to the dam area 1803 of the non-display area NDA. For example, the encapsulation layer TFE is provided to extend from the display area DAA to the first dummy area 1801, the cathode contact area 1802, and the dam area 1803. For example, the encapsulation layer TFE includes a first encapsulation inorganic film (e.g., Figure 7 in TFE1) and a second encapsulating inorganic film (e.g., Figure 7 TFE2 in ).

[0208] According to the comparative example, in the dam region 1803 of the display panel, the first dam insulating film DINS1, the second dam insulating film DINS2, and the third dam insulating film DINS3 have the same width 1902. In this case, the height from the bottom surface of the dam spacer DTRC to the dam insulating film DINS increases, so that some layers of the encapsulation layer TFE (such as Figure 7 The first encapsulating inorganic film TFE1) may be cut off due to the step coverage.

[0209] exist Figure 13 In the figure, reference numeral 1901 denotes a boundary portion of the bottom surface of the dam spacer DTRC, and a crack may occur at the boundary portion 1901 where the encapsulation layer TFE is cut due to the step coverage. The crack in the encapsulation layer TFE may cause oxygen or moisture to penetrate into the display element layer EML.

[0210] In one embodiment of the present disclosure, the dam insulating film DINS may have a cross-sectional structure with a stepped portion (eg, a forward tapered structure) to prevent cracks in the encapsulation layer TFE that may be caused in the dam region 1803 of the display panel 100 according to the comparative example. Figures 14 to 16 A cross-sectional structure of the dam insulating film DINS according to one embodiment is described in detail.

[0211] Figure 14 According to one embodiment, Figure 11 1 is a cross-sectional view of the display panel 100 taken along line AA′ in FIG. Figure 15 yes Figure 14 A cross-sectional view of a portion of the dam area 1803 is shown in FIG.

[0212] According to one embodiment, Figure 14 and Figure 15 The display panel 100 shown in FIG. 1 may be at least partially similar to the display panel 100 according to FIG. Figure 12 and Figure 13 The following description will focus on the display panel of the comparative example. Figure 14 and Figure 15 The embodiment shown in Figure 12 and Figure 13 The display panel of the comparative example described is characterized by its distinctive features. Figure 14 and Figure 15 Features not described in the above reference Figure 12 and Figure 13 The description of the comparative example described in detail is replaced.

[0213] Reference Figure 14 and Figure 15 According to one embodiment, the display panel 100 and Figure 12 and Figure 13 The comparative example shown in is different in that the dam insulating film DINS has a cross-sectional structure with a stepped portion (for example, a forward tapered structure).

[0214] According to one embodiment, the width 2001 of the first dam insulating film DINS1 is greater than the width 2002 of the second dam insulating film DINS2 and the width 2003 of the third dam insulating film DINS3. In addition, the width 2002 of the second dam insulating film DINS2 is greater than the width 2003 of the third dam insulating film DINS3. For example, the first dam insulating film DINS1 may have a first width 2001, the second dam insulating film DINS2 may have a second width 2002 smaller than the first width 2001, and the third dam insulating film DINS3 may have a third width 2003 smaller than the second width 2002.

[0215] In the display panel 100, according to one embodiment, since the first to third dam insulating films DINS1 to DINS3 form a cross-sectional structure having a stepped portion in the dam region 1803, the step coverage characteristics of the dam spacer DTRC (or in the dam spacer DTRC) are improved. In this embodiment, cracks in the encapsulation layer TFE can be prevented during the manufacturing process of forming the display panel 100. For example, Figure 15 , reference numeral 1901 denotes a boundary portion of the bottom surface of the dam spacer DTRC, and the encapsulation layer TFE is not cut at the boundary portion 1901 due to the stepped structure of the first to third dam insulating films DINS1 to DINS3.

[0216] According to one embodiment, the dam insulating film DINS may be an insulating film extending from the pixel defining film PDL disposed in the display area DAA. For example, the first dam insulating film DINS1 includes the same material as the first pixel defining film PDL1 and is disposed on the same layer as the first pixel defining film PDL1. The second dam insulating film DINS2 includes the same material as the second pixel defining film PDL2 and is disposed on the same layer as the second pixel defining film PDL2. The third dam insulating film DINS3 includes the same material as the third pixel defining film PDL3 and is disposed on the same layer as the third pixel defining film PDL3.

[0217] According to one embodiment, each of the first dam insulating film DINS1, the second dam insulating film DINS2, and the third dam insulating film DINS3 may include silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0218] According to one embodiment, each of the first dam insulating film DINS1, the second dam insulating film DINS2, and the third dam insulating film DINS3 may have a thickness of about 500 Å.

[0219] In the present disclosure, since the dam spacer DTRC is a portion of the dam structure DAM that penetrates a portion of the insulating film INS, the dam spacer DTRC may be referred to as a 'dam trench'.

[0220] In this disclosure, the dam structure DAM may be referred to as an "uneven structure". Figure 13 、 Figure 15 and Figure 16 Although three dam structures (e.g., three dam spacers DTRC) including a first dam structure DM1, a second dam structure DM2, and a third dam structure DM3 are shown as being provided in the dam region 1803, the present disclosure is not limited thereto. For example, the number of dam structures (e.g., dam spacers DTRC) provided in the dam region 1803 of the display panel 100 may be one or more.

[0221] Figure 16 yes Figure 14 A cross-sectional view of a portion of the dam area 1803 is shown in FIG. For example, Figure 16 It is modified according to Figure 15 FIG. 1 is a cross-sectional view of a dam region 1803 of a display panel 100 according to an embodiment of the structure of a pixel definition layer (PDL).

[0222] Figure 16 The embodiment shown in Figure 15The embodiment shown in FIG is different in that the third dam insulating film DINS3 is provided to cover the entire dam region 1803. For example, the third dam insulating film DINS3 may cover not only the second dam insulating film DINS2 but also the side and bottom surfaces of the dam spacer DTRC.

[0223] According to one embodiment, the first dam insulating film DINS1 and the second dam insulating film DINS2 included in the dam insulating film DINS may have a cross-sectional structure with a stepped portion (e.g., a forward tapered structure), and the third dam insulating film DINS3 may extend to cover the side and bottom surfaces of the dam spacer DTRC and the second dam insulating film DINS2. For example, the first dam insulating film DINS1 may have a first width 2001, the second dam insulating film DINS2 may have a second width 2002 smaller than the first width 2001, and the third dam insulating film DINS3 may extend to cover the entire dam region 1803.

[0224] In the display panel 100 according to one embodiment, since the first dam insulating film DINS1 and the second dam insulating film DINS2 form a cross-sectional structure having a stepped portion in the dam region 1803, the step coverage characteristic in the dam spacer DTRC is improved. In the illustrated embodiment, during the manufacturing process of forming the encapsulation layer TFE of the display panel 100, cracks in the encapsulation layer TFE can be prevented. For example, Figure 16 , reference numeral 1901 denotes a boundary portion of the bottom surface of the dam spacer DTRC, and the encapsulation layer TFE is not cut at the boundary portion 1901 due to the stepped structure of the first and second dam insulating films DINS1 and DINS2.

[0225] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments described herein without departing substantially from the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a generic and descriptive sense rather than for the purpose of limitation.

Claims

1. A display device, comprising: A display panel having a display area and a non-display area outside the display area, the display panel including a light emitting element in the display area and a dam structure in the non-display area, The dam structure includes a dam spacer penetrating an insulating film on a substrate of the display panel, a dam insulating film located on the insulating film around the dam spacer, and an encapsulation layer covering the dam insulating film and the dam spacer. The dam insulating film has a tapered shape having a width that decreases from a surface of the insulating film toward a top of the dam insulating film.

2. The display device according to claim 1, wherein The dam insulating film includes: a first dam insulating film on the insulating film; a second dam insulating film on the first dam insulating film; and The third dam insulating film is on the second dam insulating film.

3. The display device according to claim 2, wherein: The first dam insulating film has a first width, wherein the second dam insulating film has a second width smaller than the first width, and The third dam insulating film has a third width smaller than the second width.

4. The display device according to claim 3, wherein The light emitting element includes a first electrode, a light emitting stack, and a second electrode sequentially stacked on the insulating film, an edge of the first electrode being covered by a pixel defining film, and The pixel definition film and the dam insulating film are in the same layer.

5. The display device according to claim 4, wherein The pixel defining film includes: a first pixel defining film on the insulating film; a second pixel defining film on the first pixel defining film; and The third pixel defining film is on the second pixel defining film. The display device according to claim 5 , wherein: At the periphery of the light emitting element, the width of the first pixel defining film is greater than the width of the second pixel defining film and the width of the third pixel defining film, and Wherein, the width of the second pixel defining layer is greater than the width of the third pixel defining layer.

7. The display device according to claim 6, wherein: The first dam insulating film and the first pixel defining film are on the same layer, The second dam insulating film and the second pixel defining film are on the same layer, and The third dam insulating film and the third pixel defining film are in the same layer.

8. The display device according to claim 7, wherein: Each of the first to third dam insulating films is an inorganic film including silicon oxide.

9. The display device according to claim 7, wherein: The thickness of each of the first to third dam insulating films is 500 Å.

10. The display device according to claim 1, wherein The encapsulation layer includes: a first encapsulating inorganic film; and The second encapsulation inorganic film is on the first encapsulation inorganic film.

11. A mobile electronic device, comprising: A display panel having a display area and a non-display area outside the display area, the display panel including a light emitting element in the display area and a dam structure in the non-display area, The dam structure includes a dam spacer penetrating an insulating film on a substrate of the display panel, a dam insulating film located on the insulating film around the dam spacer, and an encapsulation layer covering the dam insulating film and the dam spacer. The dam insulating film has a tapered shape having a width that decreases from a surface of the insulating film toward a top of the dam insulating film.

12. The mobile electronic device according to claim 11, wherein: The dam insulating film includes: a first dam insulating film on the insulating film; a second dam insulating film on the first dam insulating film; and The third dam insulating film is on the second dam insulating film.

13. The mobile electronic device according to claim 12, wherein: The first dam insulating film has a first width, wherein the second dam insulating film has a second width smaller than the first width, and The third dam insulating film has a third width smaller than the second width.

14. The mobile electronic device according to claim 13, wherein: The light emitting element includes a first electrode, a light emitting stack, and a second electrode sequentially stacked on the insulating film, an edge of the first electrode being covered by a pixel defining film, and The pixel definition film and the dam insulating film are in the same layer.

15. The mobile electronic device according to claim 14, wherein: The pixel defining film includes: a first pixel defining film on the insulating film; a second pixel defining film on the first pixel defining film; and The third pixel defining film is on the second pixel defining film. The mobile electronic device according to claim 15 , wherein: At the periphery of the light emitting element, the width of the first pixel defining film is greater than the width of the second pixel defining film and the width of the third pixel defining film, and Wherein, the width of the second pixel defining layer is greater than the width of the third pixel defining layer.

17. The mobile electronic device according to claim 16, wherein: The first dam insulating film and the first pixel defining film are on the same layer, The second dam insulating film and the second pixel defining film are on the same layer, and The third dam insulating film and the third pixel defining film are in the same layer.

18. The mobile electronic device according to claim 17, wherein: Each of the first to third dam insulating films is an inorganic film including silicon oxide.

19. The mobile electronic device according to claim 17, wherein: The thickness of each of the first to third dam insulating films is 500 Å.

20. The mobile electronic device according to claim 11, wherein The encapsulation layer includes: a first encapsulating inorganic film; and The second encapsulation inorganic film is on the first encapsulation inorganic film.

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