Semiconductor device

Abstract

A semiconductor device (1) is provided with: a semiconductor layer (40) divided into three regions, i.e., a first region (A1), a second region (A2), and a third region (A3), which do not overlap each other in a planar view; a first vertical MOS transistor (10) formed in the first region (A1); a second vertical MOS transistor (20) formed in the second region (A2); a third vertical MOS transistor (30) formed in the third region (A3); a first gate wiring (118) of the first vertical MOS transistor (10) and a third gate wiring (138) of the third vertical MOS transistor (30) are electrically connected in series via a first diode (113) in the forward direction in this order, and a second gate wiring (128) of the second vertical MOS transistor (20) and the third gate wiring (138) are electrically connected in series via a second diode (123) in the forward direction in this order.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip-scale package type semiconductor device. Background Art

[0002] Vertical MOS transistors are sometimes used in circuits that combine two systems with different rated current values ​​into one system.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 7253674. Summary of the Invention

[0006] Problems to be solved by the invention

[0007] There is a demand for miniaturization of circuits using vertical MOS transistors.

[0008] Means for solving problems

[0009] In order to solve the above-mentioned problems, a semiconductor device of one embodiment of the present invention is a chip-size package type semiconductor device that can be mounted face down, comprising: a semiconductor layer having a semiconductor substrate on the back side, which is divided into three regions, namely a first region, a second region, and a third region, which do not overlap with each other and are not dispersed when the semiconductor device is viewed from the plane; a first vertical MOS transistor, which is formed as a whole in the first region of the semiconductor layer; a second vertical MOS transistor, which is formed as a whole in the second region of the semiconductor layer; a third vertical MOS transistor, which is formed as a whole in the third region of the semiconductor layer; and a metal layer, which is formed in contact with the back side of the semiconductor layer; the semiconductor substrate is a common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor; when viewed from the plane, A first source pad and a first gate pad of the first vertical MOS transistor and a first gate wiring connected to the first gate pad are formed at a position within the region when viewed in the plane; a second source pad and a second gate pad of the second vertical MOS transistor and a second gate wiring connected to the second gate pad are formed at a position included in the second region when viewed in the plane; a third source pad and a third gate wiring of the third vertical MOS transistor are formed at a position included in the third region when viewed in the plane; the first gate wiring and the third gate wiring are electrically connected in series via a first diode with a direction from the first gate wiring toward the third gate wiring as a forward direction; the second gate wiring and the third gate wiring are electrically connected in series via a second diode with a direction from the second gate wiring toward the third gate wiring as a forward direction.

[0010] Effects of the Invention

[0011] By using the triple-structured vertical MOS transistor described above for a circuit that combines two conduction paths having different rated current values ​​into one, for example, it is possible to reduce the area required for the circuit compared to conventional circuits.

[0012] Therefore, according to the semiconductor device having the above structure, it is possible to achieve miniaturization of a circuit using vertical MOS transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment.

[0014] Figure 2A It is a schematic plan view showing an example of the structure of a semiconductor device according to an embodiment.

[0015] Figure 2BIt is a schematic plan view showing an example of the structure of a semiconductor device according to an embodiment.

[0016] Figure 3A It is a schematic plan view showing an example of a part of the structure of the semiconductor device according to the embodiment.

[0017] Figure 3B This is a schematic cross-sectional view showing an example of a portion of the structure of a semiconductor device according to an embodiment.

[0018] Figure 3C This is a schematic cross-sectional view showing an example of a portion of the structure of a semiconductor device according to an embodiment.

[0019] Figure 4A It is a schematic plan view showing an example of a part of the structure of the semiconductor device according to the embodiment.

[0020] Figure 4B This is a schematic cross-sectional view showing an example of a portion of the structure of a semiconductor device according to an embodiment.

[0021] Figure 4C This is a schematic cross-sectional view showing an example of a portion of the structure of a semiconductor device according to an embodiment.

[0022] Figure 5A FIG. 1 is a schematic plan view of a rough unit structure of a first transistor according to an embodiment.

[0023] Figure 5B It is a schematic perspective view of a rough unit structure of a first transistor according to an embodiment.

[0024] Figure 6 This is a circuit diagram showing an example of use of the semiconductor device according to the embodiment.

[0025] Figure 7 This is a circuit diagram showing a usage example of a semiconductor device according to a comparative example.

[0026] Figure 8A 1 is a schematic plan view showing an example of the structure of a transistor of a comparative example.

[0027] Figure 8B 1 is a schematic plan view showing an example of the structure of a transistor of a comparative example.

[0028] Figure 9A 1 is a schematic plan view showing an example of the structure of a transistor of a comparative example.

[0029] Figure 9B 1 is a schematic plan view showing an example of the structure of a transistor of a comparative example.

[0030] Figure 10AIt is a schematic plan view showing a modified example of the structure of the semiconductor device according to the embodiment.

[0031] Figure 10B It is a schematic plan view showing a modified example of the structure of the semiconductor device according to the embodiment.

[0032] Figure 11 This graph plots the relationship between the area of ​​a transistor when viewed in plan and its ESD resistance. DETAILED DESCRIPTION

[0033] The embodiments described below are specific examples of the present disclosure. The numerical values, shapes, materials, components, configuration positions of components, and connection methods shown in the following embodiments are examples and are not intended to limit the present disclosure.

[0034] In the present disclosure, “A and B are electrically connected” includes the case where A and B are directly connected via wiring, the case where A and B are directly connected without wiring, and the case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0035] (Implementation Method)

[0036] [1. Structure of Semiconductor Device]

[0037] The following describes the structure of a semiconductor device according to an embodiment. The semiconductor device according to an embodiment is a face-down mountable chip-size package (CSP) semiconductor device with a dual structure consisting of two vertical MOS (metal oxide semiconductor) transistors formed in a semiconductor substrate. These two vertical MOS transistors are power transistors, so-called trench MOS FETs (field effect transistors).

[0038] Figure 1 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1 according to the embodiment. Figure 2A 、 Figure 2B 1 is a schematic plan view showing an example of the structure of the semiconductor device 1 according to the embodiment. Figure 2A 、 Figure 2B In the figure, the size and shape of the semiconductor device 1 are examples. The size, shape, and arrangement of the pads and electrodes are also examples.

[0039] also, Figure 2BThe diagram shows the state immediately after forming portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring 118, portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring 128, portion 33 of the third source electrode 31, and the third gate wiring 138 on the surface side of the semiconductor layer 40. Pads that should not be visible at this point are indicated by dotted lines. Each component will be described later.

[0040] Figure 1 It is along Figure 2A II is a cut surface when the semiconductor device 1 is cut.

[0041] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor substrate 42, a metal layer 41, and a low-concentration impurity layer 43 formed on the semiconductor substrate 42. In the present disclosure, the semiconductor substrate 42 and the low-concentration impurity layer 43 are collectively referred to as a semiconductor layer 40.

[0042] Semiconductor substrate 42 is disposed on the back side of semiconductor layer 40 and is composed of silicon of the first conductivity type containing impurities at a first concentration. Semiconductor layer 40 includes a low-concentration impurity layer 43 of the first conductivity type formed in contact with semiconductor substrate 42 and containing impurities at a second concentration lower than the first concentration. Low-concentration impurity layer 43 is formed on semiconductor substrate 42 by, for example, epitaxial growth.

[0043] like Figure 1 and Figure 2A As shown, the semiconductor device 1 has: a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10"), which is formed as a whole in the first area A1 of the semiconductor layer 40; a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20"), which is formed as a whole in the second area A2 of the semiconductor layer 40; and a third vertical MOS transistor 30 (hereinafter also referred to as "transistor 30"), which is formed as a whole in the third area A3 of the semiconductor layer 40.

[0044] The transistor 10 formed entirely within the first area A1 means that, when viewed in plan, all elements constituting the transistor 10 are contained within the first area A1 and are not contained in any area other than the first area A1. Similarly, the transistor 20 formed entirely within the second area A2 means that, when viewed in plan, all elements constituting the transistor 20 are contained within the second area A2 and are not contained in any area other than the second area A2. Similarly, the transistor 30 formed entirely within the third area A3 means that, when viewed in plan, all elements constituting the transistor 30 are contained within the third area A3 and are not contained in any area other than the third area A3.

[0045] like Figure 2AAs shown, when viewed in plan, the surface side of the semiconductor layer 40 is divided into a first region A1, a second region A2, and a third region A3 that do not overlap with each other and are not dispersed. Here, the first region A1, the second region A2, and the third region A3 are not dispersed, which means that the first region A1, the second region A2, and the third region A3 are not accompanied by enclaves. Figure 2A In FIG. 4 , the imaginary boundary lines 90 that divide the first area A1, the second area A2, and the third area A3 are shown as dashed lines. For ease of understanding, the dashed lines representing the boundary lines 90 are shown extending to the outside of the semiconductor layer 40. However, the actual boundary lines 90 terminate at the periphery of the semiconductor layer 40 when viewed from above (at the end of FIG. 4 ). Figure 2A 、 Figure 2B For convenience, the end points of the boundary line 90 are respectively indicated as P1, P2, P3, and P4. The boundary line 90 will be described later.

[0046] In addition, Figure 2A In the figure, for ease of understanding, the dotted lines representing the first area A1, the second area A2, and the third area A3 do not strictly coincide with the periphery of the semiconductor layer 40 and the boundary line 90, but are shown inside with some spaces between them. However, in practice, the periphery of the first area A1, the periphery of the second area A2, and the periphery of the third area A3 coincide with the periphery of the semiconductor layer 40 and the boundary line 90. In the semiconductor device 1 of the embodiment, when viewed in plan, there is no area that is neither the first area A1, the second area A2, nor the third area A3.

[0047] The metal layer 41 is formed in contact with the back side of the semiconductor layer 40 and can be made of silver (Ag) or copper (Cu) as a non-limiting example. In addition, the metal layer 41 may contain a trace amount of elements other than metals mixed as impurities during the manufacturing process of the metal material.

[0048] like Figure 1 As shown, a first body region 18 of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low-concentration impurity layer 43. A first source region 14 of the first conductivity type is formed in the first body region 18.

[0049] Furthermore, a plurality of first gate trenches 17 are formed in the first region A1. The plurality of first gate trenches 17 are formed at a depth that penetrates the first source region 14 and the first body region 18 from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 43. Furthermore, a first gate conductor 15 is formed on the first gate insulating film 16 within the first gate trenches 17. The first gate conductor 15 is a buried gate electrode buried within the semiconductor layer 40. The first gate conductor 15 is electrically connected to the first gate electrode 19 via the first gate wiring 118 (see FIG. 1 ). Figure 2B ).

[0050] The first source electrode 11 includes a portion 12 and a portion 13 . The portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0051] Portion 12 of the first source electrode 11 is a layer that is bonded to the solder during reflow in face-down mounting, and can be made of, as a non-limiting example, a metal material containing one or more of nickel, titanium, tungsten, and palladium. Portion 12 can be plated with gold or the like.

[0052] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including any one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0053] The first gate electrode 19 may be formed simultaneously with the first source electrode 11 , and may be formed of the same structure and / or the same material as the first source electrode 11 .

[0054] like Figure 2B As shown, the first gate wiring 118 is provided so as to surround the portion 13 of the first source electrode 11 and the first gate electrode 19 in a planar view. The first gate wiring 118 is connected in series to the first gate electrode 19 via the first gate resistor 117 . Figure 3B A schematic cross-sectional view showing the first gate resistor element 117 is shown. Figure 3B It is along Figure 3A The cut surface when the semiconductor device 1 is cut is II-II, Figure 3A It will be Figure 2B Schematic plan view showing an enlarged view of the area A11 surrounded by a dotted line.

[0055] like Figure 2B As shown, a first Zener diode 115 is provided between the portion 13 of the first source electrode 11 and the first gate electrode 19 when viewed in plan. Figure 3C FIG. 4 is a cross-sectional view showing a first Zener diode 115 . Figure 3C It is along Figure 3A The first gate electrode 19 and the portion 13 of the first source electrode 11 are electrically connected via the first Zener diode 115 .

[0056] Both the gate resistor and the Zener diode are designed to provide a protective function, preventing transistor destruction when excessive voltage is applied to the gate electrode. Specifically, they are designed to improve ESD (electrostatic discharge) resistance. Both the first gate resistor 117 and the first Zener diode 115 can be formed, for example, by implanting impurities into polysilicon. By controlling the type, amount, and location of the impurities, the resistivity of the first gate resistor 117 and the location, number, and electrical direction of the PN junctions in the first Zener diode 115 can be controlled.

[0057] For example, Figure 3C As shown, the first Zener diode 115 may be formed alternately with a portion that is implanted with the first conductive type impurities to become the first conductive type and a portion that is implanted with the second conductive type impurities to become the second conductive type. Figure 3C In the example shown, two PN junctions are bidirectionally formed between the first gate electrode 19 and the portion 13 of the first source electrode 11 via the first Zener diode 115 .

[0058] When viewed in plan, a first EQR (equipotential ring) 116 electrically connected to the semiconductor substrate 42 may be provided on the periphery of the first region A1. The first EQR 116 is provided to prevent leakage current from flowing between the outside and the first body region 18 in the transistor 10. As a non-limiting example, the first EQR 116 may be formed of one or more metal materials including aluminum, copper, gold, and silver.

[0059] Furthermore, in the semiconductor device 1 according to the embodiment, it is not necessary to provide a gate resistance element, a Zener diode, and an EQR.

[0060] A second body region 28 of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 43. A second source region 24 of the first conductivity type is formed in the second body region 28.

[0061] In addition, a plurality of second gate trenches 27 are formed in the second region A2. The plurality of second gate trenches 27 are formed at a depth that penetrates the second source region 24 and the second body region 28 from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 43. Furthermore, a second gate conductor 25 is formed on the second gate insulating film 26 within the second gate trenches 27. The second gate conductor 25 is a buried gate electrode buried in the semiconductor layer 40. The second gate conductor 25 is electrically connected to the second gate electrode 29 via the second gate wiring 128 (see Figure 2B ).

[0062] The second source electrode 21 includes a portion 22 and a portion 23 . The portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 .

[0063] Portion 22 of the second source electrode 21 is a layer that is bonded to the solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 can be plated with gold or the like.

[0064] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0065] The second gate electrode 29 may be formed simultaneously with the second source electrode 21 , and may be formed of the same structure and / or the same material as the second source electrode 21 .

[0066] like Figure 2B As shown, the second gate wiring 128 is provided so as to surround the portion 23 of the second source electrode 21 and the second gate electrode 29 in a planar view. The second gate wiring 128 is connected in series to the second gate electrode 29 via the second gate resistor 127 .

[0067] like Figure 2B As shown, in plan view, a second Zener diode 125 is provided between the portion 23 of the second source electrode 21 and the second gate electrode 29 . The second gate electrode 29 and the portion 23 of the second source electrode 21 are electrically connected via the second Zener diode 125 .

[0068] Both the second gate resistor 127 and the second Zener diode 125 can be formed by, for example, implanting impurities into polysilicon. By controlling the type, amount, and location of the impurities, the resistivity of the second gate resistor 127 and the location, number, and electrical direction of the PN junctions in the second Zener diode 125 can be controlled.

[0069] The second Zener diode 125 may be, for example, Figure 3C The first Zener diode 115 shown is constructed identically.

[0070] When viewed in plan, a second EQR 126 electrically connected to the semiconductor substrate 42 may be provided on the periphery of the second region A2. The second EQR 126 is provided to prevent leakage current from flowing between the outside and the second body region 28 in the transistor 20. As a non-limiting example, the second EQR 126 may be formed of one or more metal materials including aluminum, copper, gold, and silver.

[0071] A third body region 38 of the second conductivity type is formed in the third region A3 of the low-concentration impurity layer 43. A third source region 34 of the first conductivity type is formed in the third body region 38. In addition, a plurality of third gate trenches 37 are formed in the third region A3. The plurality of third gate trenches 37 are formed at a depth that penetrates the third source region 34 and the third body region 38 from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 43. Furthermore, a third gate conductor 35 is formed on the third gate insulating film 36 inside the third gate trench 37. The third gate conductor 35 is a buried gate electrode buried in the interior of the semiconductor layer 40. The third gate conductor 35 is electrically connected to the third gate wiring 138 (see Figure 2B ).

[0072] The third source electrode 31 includes a portion 32 and a portion 33 . The portion 32 is connected to the third source region 34 and the third body region 38 via the portion 33 .

[0073] Portion 32 of the third source electrode 31 is a layer that is bonded to the solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 32 can be plated with gold or other materials.

[0074] The portion 33 of the third source electrode 31 is a layer connecting the portion 32 and the semiconductor layer 40 , and may be made of a metal material including any one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0075] When viewed in plan, a third EQR 136 electrically connected to the semiconductor substrate 42 may be provided on the periphery of the third region A3. The third EQR 136 is provided to prevent leakage current from flowing between the outside and the third body region 38 in the transistor 30. As a non-limiting example, the third EQR 136 may be formed of a metal material including one or more of aluminum, copper, gold, and silver.

[0076] like Figure 2B As shown, the third gate wiring 138 is provided so as to surround the portion 33 of the third source electrode 31 when viewed in plan. However, in the present disclosure, in the position included in the third area A3, there is no gate electrode or gate pad connected to the third gate wiring 138. In addition, the gate resistor element and Zener diode that can be provided in the first area A1 or the second area A2 are not formed.

[0077] The third gate wiring 138 is connected in series with the first gate wiring 118 via the first diode 113. The first diode 113 is formed so that the direction from the first gate wiring 118 toward the third gate wiring 138 is electrically a forward direction. Figure 4BFIG. 4 is a cross-sectional view showing a first diode 113 . Figure 4B It is along Figure 4A The cut surface when the semiconductor device 1 is cut is IV-IV. Figure 4A It will be Figure 2B Schematic plan view showing an enlarged view of the area A12 surrounded by a dotted line.

[0078] The third gate wiring 138 is connected in series with the first gate wiring 118 via the first resistor 114. Therefore, the first diode 113 and the first resistor 114 are connected in parallel between the first gate wiring 118 and the third gate wiring 138. Figure 4C A schematic cross-sectional view showing the first resistor element 114 is shown. Figure 4C It is along Figure 4A VV is a cut surface when the semiconductor device 1 is cut.

[0079] Both first resistor 114 and first diode 113 can be formed, for example, by implanting impurities into polysilicon. By controlling the type, amount, and location of the impurities, the resistivity of first resistor 114 and the location, number, and electrical direction of the PN junctions in first diode 113 can be controlled.

[0080] For example, Figure 4B As shown, the first diode 113 may be formed with a portion that is implanted with the first conductivity type impurities to become the first conductivity type and a portion that is implanted with the second conductivity type impurities to become the second conductivity type. Figure 4B In the example shown, only one PN junction is formed which is electrically in the forward direction from the first gate wiring 118 toward the third gate wiring 138 .

[0081] The third gate wiring 138 is connected in series with the second gate wiring 128 via the second diode 123. The second diode 123 is formed so that the direction from the second gate wiring 128 toward the third gate wiring 138 is electrically the forward direction. In addition, the third gate wiring 138 is connected in series with the second gate wiring 128 via the second resistor 124. Therefore, the second diode 123 and the second resistor 124 are connected in parallel between the second gate wiring 128 and the third gate wiring 138.

[0082] Second resistor 124 and second diode 123 can both be formed by, for example, implanting impurities into polysilicon. By controlling the type, amount, and location of the impurities, the resistivity of second resistor 124 and the location, number, and electrical direction of the PN junctions in second diode 123 can be controlled.

[0083] The second diode 123 is, for example, Figure 4BThe first diode 113 shown has a similar structure, and only one PN junction is formed, which is electrically in the forward direction from the second gate wiring 128 toward the third gate wiring 138 .

[0084] like Figure 1 As shown, the first body region 18 and the first source region 14 are covered by an interlayer insulating layer 44 having an opening, and a portion 13 of the first source electrode 11 is provided through the opening of the interlayer insulating layer 44 and connected to the first source region 14. The interlayer insulating layer 44 and the portion 13 of the first source electrode 11 are covered by a passivation layer 45 having an opening, and a portion 12 is provided through the opening of the passivation layer 45 and connected to the portion 13 of the first source electrode 11.

[0085] Similarly, the second body region 28 and the second source region 24 are covered by an interlayer insulating layer 44 having an opening, and a portion 23 of the second source electrode 21 is provided through the opening of the interlayer insulating layer 44 and connected to the second source region 24. The interlayer insulating layer 44 and the portion 23 of the second source electrode 21 are covered by a passivation layer 45 having an opening, and a portion 22 is provided through the opening of the passivation layer 45 and connected to the portion 23 of the second source electrode 21.

[0086] Similarly, the third body region 38 and the third source region 34 are covered by an interlayer insulating layer 44 having an opening, and a portion 33 of the third source electrode 31 is provided through the opening of the interlayer insulating layer 44 and connected to the third source region 34. The interlayer insulating layer 44 and the portion 33 of the third source electrode 31 are covered by a passivation layer 45 having an opening, and a portion 32 is provided through the opening of the passivation layer 45 and connected to the portion 33 of the third source electrode 31.

[0087] Therefore, according to Figure 2B As can be seen, the first source pad 111, the second source pad 121, and the third source pad 131 refer to regions where the first source electrode 11, the second source electrode 21, and the third source electrode 31 are partially exposed on the surface of the semiconductor device 1, that is, the terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 refer to regions where the first gate electrode 19 and the second gate electrode 29 are partially exposed on the surface of the semiconductor device 1, that is, the terminal portions.

[0088] The number of first source pads 111 , second source pads 121 , and third source pads 131 is not necessarily limited to Figure 2A In addition, the shapes of the first source pad 111, the second source pad 121, and the third source pad 131 do not need to be limited to Figure 2AThe elliptical shape shown as an example may also be a rectangular shape or a circular shape. In addition, the arrangement of the first source pad 111, the second source pad 121, and the third source pad 131 is not limited to Figure 2A The illustrated configuration.

[0089] The number of the first gate pads 119 and the second gate pads 129 is not necessarily limited to Figure 2A The number of examples may be more than two. In addition, the shapes of the first gate pad 119 and the second gate pad 129 do not need to be limited to Figure 2A The circular shape exemplified may be, for example, a rectangular shape or an elliptical shape.

[0090] Through the above-mentioned structures of transistor 10, transistor 20, and transistor 30, the semiconductor substrate 42 and the range near directly above the semiconductor substrate 42 in the low-concentration impurity layer 43 are common drain regions that make the first drain region of transistor 10, the second drain region of transistor 20, and the third drain region of transistor 30 common.

[0091] The metal layer 41 is a common drain electrode that makes the first drain electrode of the transistor 10 , the second drain electrode of the transistor 20 , and the third drain electrode of the transistor 30 common.

[0092] In addition, in this disclosure, the center of a shape when viewed from a plane is defined as follows. Figure 2A For a circular shape like first gate pad 119 in FIG, it refers to its center. For a rectangular shape like first region A1, it refers to the intersection of its diagonals. For an oblong region like first source pad 111, it refers to the intersection of the axis of symmetry extending in its length direction and the axis of symmetry extending in its width direction.

[0093] In addition, if Figure 2A As shown, the first region A1 and the second region A2 are arranged with the third region A3 sandwiched between them. In this disclosure, the phrase "first region A1 and second region A2 sandwich the third region A3" means that the first region A1 and the third region A3 are adjacent to each other without any other region sandwiched between them, and that the second region A2 and the third region A3 are adjacent to each other without any other region sandwiched between them. Therefore, when the semiconductor layer 40 is viewed from a planar perspective, the third region A3 is adjacent to both the first region A1 and the second region A2.

[0094] The phrase "an area and an area are adjacent to each other in plan view" is the same as "opposing" and means that their outer peripheries coincide with each other at a boundary line 90. Hereinafter, the length of the boundary line 90 may be referred to as an opposing length.

[0095] like Figure 2BAs shown, the boundary line 90 between the first area A1 and the third area A3 can be understood as an imaginary line along the center position of the gap between the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31. In addition, the boundary line 90 has a limited width, but it can also be understood as the gap itself. Even this gap can be recognized as a line in the appearance under the naked eye or low magnification. The boundary line 90 between the first area A1 and the third area A3 is Figure 2A 、 Figure 2B In the example shown, this is a dashed line from P1 to P2.

[0096] Furthermore, when viewed in plan, if the first EQR 116 is provided on the periphery of the first area A1 and the third EQR 136 is provided on the periphery of the third area A3, the first EQR 116 and the third EQR 136 may be unified into one at the point where the peripheries of the first area A1 and the third area A3 coincide. In this case, the point where the unified EQR is provided can be understood as the boundary 90 between the first area A1 and the third area A3 when viewed in plan.

[0097] In short, if Figure 2B As shown, in the semiconductor device 1 of the embodiment, the first diode 113 is provided astride the boundary line 90 between the first area A1 and the third area A3 when viewed in plan. That is, when viewed in plan, one end of the first diode 113 is located in the first area A1 and the other end is located in the third area A3.

[0098] like Figure 2B As shown, in the semiconductor device 1 of the embodiment, the first resistor 114 is provided so as to straddle the boundary line 90 between the first area A1 and the third area A3 when viewed in plan. That is, when viewed in plan, one end of the first resistor 114 is located in the first area A1 and the other end is located in the third area A3.

[0099] The boundary line 90 between the second area A2 and the third area A3 can be understood as an imaginary line along the center position of the gap between the portion 23 of the second source electrode 21 and the portion 33 of the third source electrode 31. In addition, although it has a finite width, it can also be understood as the gap itself. Figure 2A 、 Figure 2B In the example shown, the boundary line 90 between the second area A2 and the third area A3 is a dotted line extending from P3 to P5 and then to P4.

[0100] Furthermore, when viewed in plan, if the second EQR 126 is provided on the periphery of the second area A2 and the third EQR 136 is provided on the periphery of the third area A3, the second EQR 126 and the third EQR 136 may be combined into one at the point where the peripheries of the second area A2 and the third area A3 coincide. In this case, the point where the combined EQRs are provided can be understood as the boundary 90 between the second area A2 and the third area A3 when viewed in plan.

[0101] In short, if Figure 2B As shown, in the semiconductor device 1 of the embodiment, the second diode 123 is provided across the boundary line 90 between the second area A2 and the third area A3 when viewed in plan. That is, when viewed in plan, one end of the second diode 123 is located in the second area A2 and the other end is located in the third area A3.

[0102] like Figure 2B As shown, in the semiconductor device 1 of the embodiment, the second resistor 124 is provided astride the boundary line 90 between the second area A2 and the third area A3 when viewed in plan. That is, when viewed in plan, one end of the second resistor 124 is located in the first area A1 and the other end is located in the third area A3.

[0103] In addition, although Figure 2A 、 Figure 2B It is not shown in FIG, but the case where the first area A1 and the second area A2 are adjacent can also be considered (refer to Figure 10A 、 Figure 10B The boundary between the first region A1 and the second region A2 can be understood as an imaginary line extending along the center of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Furthermore, although it has a finite width, it can also be understood as the gap itself.

[0104] Furthermore, when viewed in plan, if the first EQR 116 is provided on the periphery of the first area A1 and the second EQR 126 is provided on the periphery of the second area A2, the first EQR 116 and the second EQR 126 may be unified into one at the point where the peripheries of the first area A1 and the second area A2 coincide. In this case, the point where the unified EQR is provided can be understood as the boundary between the first area A1 and the second area A2 when viewed in plan.

[0105] In the semiconductor device 1 of the embodiment, as Figure 2A 、 Figure 2BAs shown, the area a1 of the first region A1 when viewed in plan is larger than the area a3 of the third region A3 when viewed in plan (a1>a3). Furthermore, the area a3 of the third region A3 when viewed in plan is larger than the area a2 of the second region A2 when viewed in plan (a3>a2). Therefore, the areas of the first region A1, the second region A2, and the third region A3 when viewed in plan have the relationship of a1>a3>a2.

[0106] On the other hand, Figure 2B In the example shown, the area of ​​the portion 13 of the first source electrode 11 formed in the first region A1 is substantially equal to the area of ​​the portion 33 of the third source electrode 31 formed in the third region A3 when viewed in plan. This is because, as described above, the area a1 of the first region A1 when viewed in plan is larger than the area a3 of the third region A3 when viewed in plan (a1>a3). However, since the first gate electrode 19 is formed in the first region A1, the area of ​​the portion 13 of the first source electrode 11 when viewed in plan is reduced accordingly.

[0107] Figure 5A and Figure 5B The schematic diagrams are respectively a plan view and a perspective view of a rough unit structure of the transistor 10, the transistor 20, and the transistor 30 repeatedly formed in the X direction and the Y direction of the semiconductor device 1 according to the embodiment. Figure 5A and Figure 5B In the figure, the semiconductor substrate 42 and the metal layer 41 , as well as the passivation layer 45 and the first source electrode 11 , the second source electrode 21 , the third source electrode 31 , and the interlayer insulating layer 44 are not shown for ease of understanding.

[0108] The Y direction is parallel to the surface of the semiconductor layer 40 and is a direction in which the first gate trench 17 extends. The X direction is parallel to the surface of the semiconductor layer 40 and is perpendicular to the Y direction. The Z direction is perpendicular to both the X and Y directions and indicates the height direction of the semiconductor device.

[0109] like Figure 5A and Figure 5B As shown, transistor 10 includes a first connecting portion 18a electrically connecting first body region 18 to first source electrode 11. First connecting portion 18a is a region of first body region 18 where first source region 14 is not formed, and has the same second conductivity type as first body region 18. First source regions 14 and first connecting portion 18a are alternately and periodically arranged along the Y direction. The same applies to transistors 20 and 30.

[0110] In the semiconductor device 1 disclosed herein, the first conductivity type is set to N-type, the second conductivity type is set to P-type, the first source region 14, the second source region 24, the third source region 34, the semiconductor substrate 42 and the low-concentration impurity layer 43 are N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, the second connection portion 28a, the third body region 38, and the third connection portion 38a are P-type semiconductors.

[0111] [2. Operation of Semiconductor Device]

[0112] In semiconductor device 1 of the embodiment, it is assumed that current flows from either first source pad 111 in first area A1 or second source pad 121 in second area A2 as an inlet, passes through the common drain region and back-surface drain electrode 41, and exits at third source pad 131 in third area A3. In other words, the embodiment does not assume current conduction along a path from first source pad 111 to second source pad 121 or a path in the opposite direction.

[0113] In semiconductor device 1, a conduction path in which current flows from first source pad 111 in first area A1 as an inlet and from third source pad 131 in third area A3 as an outlet is referred to as a first conduction path. A conduction path in which current flows from second source pad 121 in second area A2 as an inlet and from third source pad 131 in third area A3 as an outlet is referred to as a second conduction path.

[0114] Current flows in the first conduction path as follows. First, in the semiconductor device 1, a high voltage is applied to the first source electrode 11, a low voltage is applied to the third source electrode 31, and a sufficiently high voltage, above the threshold value, is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11 (ON control). This forms a conduction channel near the first gate insulating film 16 in the first body region 18.

[0115] Furthermore, the voltage applied to the first gate electrode 19 is transmitted to the third gate conductor 35 via the first gate wiring 118, the first diode 113, and the third gate wiring 138. When this voltage is equal to or higher than a threshold value (conduction control), a conductive channel is formed near the third gate insulating film 36 in the third body region 38. At this time, current flows along the following path: first source electrode 11 - first source region 14 - conductive channel formed in the first body region 18 - low-concentration impurity layer 43 - semiconductor substrate 42 - metal layer 41 - semiconductor substrate 42 - low-concentration impurity layer 43 - conductive channel formed in the third body region 38 - third source region 34 - third source electrode 31, and the semiconductor device 1 enters the on state.

[0116] The above-mentioned path is a first conduction path. The semiconductor device 1 of the embodiment has a structure in which the transistor 30 is naturally controlled to be turned on when the transistor 10 is controlled to be turned on.

[0117] It should be noted that when the first conduction path is turned on, the PN junction at the interface between the second body region 28 and the low-concentration impurity layer 43 in the transistor 20 functions as a body diode. Therefore, no conduction occurs from the first source pad 111 to the second source pad 121. When the first conduction path is used in the semiconductor device 1, it is preferable that a voltage above the threshold value is not applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20 (off control).

[0118] Furthermore, a certain voltage drop occurs in the first diode 113 . Therefore, the voltage applied to the first gate electrode 19 to conduct the first conduction path needs to be adjusted to be greater than the threshold value of the transistor 30 by the voltage drop of the first diode 113 .

[0119] The third gate wiring 138 is also connected to the second gate wiring 128 via the second diode 123. However, the second diode 123 is formed so that the direction from the third gate wiring 138 to the second gate wiring 128 is electrically reversed. Therefore, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (second gate conductor 25).

[0120] Furthermore, the third gate wiring 138 is also connected to the second gate wiring 128 via the second resistor 124. However, the resistance value of the second resistor 124 is adjusted to a value that sufficiently reduces the voltage from the third gate wiring 138. Therefore, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (second gate conductor 25) at least at a value exceeding a threshold.

[0121] Current flows in the second conduction path as follows. First, in the semiconductor device 1, a high voltage is applied to the second source electrode 21, a low voltage is applied to the third source electrode 31, and a sufficiently high voltage, above the threshold value, is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21 (conduction control). This forms a conduction channel near the second gate insulating film 26 in the second body region 28.

[0122] Furthermore, the voltage applied to the second gate electrode 29 is transmitted to the third gate conductor 35 via the second gate wiring 128, the second diode 123, and the third gate wiring 138. When this voltage reaches or exceeds a threshold value (conduction control), a conductive channel is formed near the third gate insulating film 36 in the third body region 38. At this time, current flows along the path: second source electrode 21 - second source region 24 - conductive channel formed in the second body region 28 - low-concentration impurity layer 43 - semiconductor substrate 42 - metal layer 41 - semiconductor substrate 42 - low-concentration impurity layer 43 - conductive channel formed in the third body region 38 - third source region 34 - third source electrode 31, and the semiconductor device 1 enters the on state.

[0123] The above-mentioned path is the second conduction path. The semiconductor device 1 of the embodiment has a structure in which the transistor 30 is naturally controlled to be turned on when the transistor 20 is controlled to be turned on.

[0124] It should be noted that when the second conduction path is turned on, the PN junction at the interface between first body region 18 and low-concentration impurity layer 43 in transistor 10 functions as a body diode. Therefore, no conduction occurs from second source pad 121 to first source pad 111. When the second conduction path is used in semiconductor device 1, it is preferable that a voltage above the threshold value is not applied to first gate electrode 19 (first gate conductor 15) of transistor 10 (off control).

[0125] Furthermore, a certain voltage drop occurs in the second diode 123 . Therefore, the voltage applied to the second gate electrode 29 to conduct the second conduction path needs to be adjusted to be greater than the threshold value of the transistor 30 by the voltage drop in the second diode 123 .

[0126] Furthermore, the third gate wiring 138 is also connected to the first gate wiring 118 via the first diode 113, but the first diode 113 is formed so that the direction from the third gate wiring 138 to the first gate wiring 118 is electrically reversed. Therefore, the voltage applied to the second gate electrode 29 is not transmitted to the first gate wiring 118 (first gate conductor 15).

[0127] Furthermore, the third gate wiring 138 is also connected to the first gate wiring 118 via the first resistor 114. However, the resistance value of the first resistor 114 is adjusted to a value that sufficiently reduces the voltage from the third gate wiring 138. Therefore, the voltage applied to the second gate electrode 29 is not transmitted to the first gate wiring 118 (first gate conductor 15) at least at a value exceeding a threshold.

[0128] As described above, first diode 113 preferably has a structure having only one PN junction so that the voltage applied to first gate pad 119 does not drop unnecessarily before being transmitted to third gate wiring 138. Furthermore, first resistor 114 is required to have a sufficiently large resistance value so that the voltage applied to first gate pad 119 drops to a voltage below a threshold before being transmitted to second gate wiring 128.

[0129] Similarly, it is preferable that second diode 123 has a structure having only one PN junction so that the voltage applied to second gate pad 129 does not drop unnecessarily before being transmitted to third gate wiring 138. Furthermore, second resistor 124 is required to have a sufficiently large resistance value so that the voltage applied to second gate pad 129 drops to a voltage below the threshold before being transmitted to first gate wiring 118.

[0130] Furthermore, regardless of whether it is the first conductive path or the second conductive path, current flowing in the semiconductor device 1 in the horizontal direction mostly passes through the metal layer 41 having a low resistivity, but a portion of the current may flow through the semiconductor substrate 42 .

[0131] [3. Example of use of semiconductor devices]

[0132] Figure 6 This circuit diagram shows a portion of a power supply circuit that flows current from a detachable first power supply 51 and a detachable second power supply 52 to a load 6 via a semiconductor device 1 according to an embodiment. Here, the potential of the first power supply 51 is higher than that of the second power supply 52, with respect to the potential of the load 6.

[0133] The semiconductor device 1 of the embodiment is configured to realize the function of merging two systems: power supply from a high-potential first power supply 51 and power supply from a lower-potential second power supply 52 , and integrating them into one system toward a downstream load 6 at a lower potential.

[0134] The maximum value of the current flowing due to the power supplied from the high-potential first power supply 51 is denoted as I1 [A], and the maximum value of the current flowing due to the power supplied from the low-potential second power supply 52 having a lower potential than the first power supply 51 is denoted as I2 [A]. I1 and I2 can be understood as the specified maximum current values ​​for the first conduction path and the second conduction path, respectively, as described in the product data sheet of the semiconductor device 1 according to the embodiment.

[0135] The relationship between the potentials of first power supply 51 and second power supply 52 is such that I1>I2. The side of first power supply 51 through which relatively large current I1 flows is connected to first source pad 111 of transistor 10 having a large area when viewed in plan, in semiconductor device 1. The side of second power supply 52 through which relatively small current I2 flows is connected to second source pad 121 of transistor 20 having a small area when viewed in plan, in semiconductor device 1.

[0136] Furthermore, a switching element 8 (e.g., a single-type vertical MOS transistor) is connected between the semiconductor device 1 and the second power supply 52. ​​A control IC 4 is connected to the switching element 8 and the semiconductor device 1, and the control IC 4 independently controls the on / off states of the switching element 8, the transistor 10, and the transistor 20.

[0137] First, a state where only the first power source 51 is connected and the second power source 52 is not connected is described ( Figure 6 (The second power supply 52 is not present in the semiconductor device 1). At this time, control IC 4 turns on transistor 10 and turns off transistor 20. Since transistor 10 is turned on, transistor 30 is also naturally turned on. Thus, power is supplied from first power supply 51 to load 6 via the first conductive path within semiconductor device 1.

[0138] The first conduction path is a conduction path within semiconductor device 1. As previously described, this conduction path allows current to flow through first source pad 111 of transistor 10 as an inlet and third source pad 131 of transistor 30 as an outlet. When the first conduction path is turned on, transistor 20 is turned off. Since transistor 20 is turned off, current supplied by first power supply 51 is prevented from flowing toward second power supply 52.

[0139] Next, a state where only the second power source 52 is connected and the first power source 51 is not connected is described ( Figure 6 (The first power supply 51 is not present in the semiconductor device 1). At this time, control IC 4 turns on transistor 20 and turns off transistor 10. Since transistor 20 is turned on, transistor 30 is also naturally turned on. Power is then supplied from second power supply 52 to load 6 via the second conductive path within semiconductor device 1.

[0140] The second conduction path is a conduction path within semiconductor device 1. As previously described, this conduction path allows current to flow through second source pad 121 of transistor 20 as an inlet and third source pad 131 of transistor 30 as an outlet. When the second conduction path is turned on, transistor 10 is turned off. Since transistor 10 is turned off, current supplied by second power supply 52 is prevented from flowing toward first power supply 51.

[0141] When the first power source 51 and the second power source 52 are connected at the same time ( Figure 6 (state), control IC4 first turns off switching element 8, resulting in a state where only power is supplied from first power supply 51. This is because first power supply 51 has a higher potential, providing an advantage in terms of power supply. Furthermore, by turning on transistor 10 and turning off transistor 20, transistor 30 is also turned on, allowing power to be supplied from first power supply 51 to load 6 via the first conduction path.

[0142] [4. Effects of Semiconductor Devices]

[0143] exist Figure 7 It is shown in Figure 6 The comparative example in which the semiconductor device 1 of the embodiment is not used in the power supply circuit shown. The following describes the effect of using the semiconductor device 1 of the embodiment by comparison with the comparative example.

[0144] exist Figure 7 In the comparative example shown, instead of the semiconductor device 1 of the embodiment, for example, Figure 8A and Figure 8B In the figure, a vertical MOS transistor 10B (hereinafter referred to as transistor 10B) having a single structure is shown as a schematic plan view as an example of a structure, and Figure 9A and Figure 9B FIG. 2 shows a plan view of a vertical MOS transistor 20B (hereinafter referred to as transistor 20B) of a single structure as an example of a structure. In addition, immediately before the load 6, a transistor 20B is connected to the load 6. Figure 8A 、 Figure 8B 1 is a schematic plan view showing a single-structure vertical MOS transistor 30B (hereinafter referred to as transistor 30B) as an example of its structure.

[0145] In the transistor 10B, the transistor 20B, and the transistor 30B, components identical to those of the semiconductor device 1 according to the embodiment are illustrated by adding B to the reference numerals of the corresponding components.

[0146] Transistor 10B has one drain pad 151B in addition to two source pads 111B and one gate pad 119B in plan view. Drain pad 151B of transistor 10B is connected to a surface drain electrode and serves as an outflow port for current flowing in from source pad 111B of transistor 10B.

[0147] Transistor 20B has one drain pad 152B in addition to two source pads 121B and one gate pad 129B in plan view. Drain pad 152B of transistor 20B is connected to a surface drain electrode and serves as an outflow port for current flowing in from source pad 121B of transistor 20B.

[0148] Transistor 30B has one drain pad 153B in addition to two source pads 131B and one gate pad 139B in plan view. Drain pad 153B of transistor 30B is connected to a surface drain electrode and serves as an inlet for current flowing to source pad 131B of transistor 30B.

[0149] exist Figure 8B 、 Figure 9B , and a schematic plan view of the semiconductor device 1 of this embodiment ( Figure 2B ) is the same as the situation shown in FIG, which shows the situation after the source electrode portion 13B (23B, 33B), the gate electrode 19B (29B, 39B), the gate wiring 118B (128B, 138B) and the surface drain electrode connected to the drain pad 151B (152B, 153B) are formed on the surface side of the semiconductor layer 40. Figure 8B 、 Figure 9B In the figure, for easier understanding, pads that should not be visible at that point in time are shown with dotted lines.

[0150] The area of ​​the portion 13B of the source electrode of the transistor 10B when viewed in plan view is the same as the area of ​​the portion 13 of the first source electrode 11 of the transistor 10 included in the semiconductor device 1 of the embodiment when viewed in plan view. In addition, the area of ​​the portion 33B of the source electrode of the transistor 30B when viewed in plan view is the same as the area of ​​the portion 33 of the third source electrode 31 of the transistor 30 included in the semiconductor device 1 of the embodiment when viewed in plan view. Figure 7 The on-resistance of the path from the first power source 51 to the load 6 via the transistor 10B and the transistor 30B can be understood as Figure 6 The on-resistance of the first conduction path of the semiconductor device 1 in the embodiment is equivalent.

[0151] The area of ​​the portion 23B of the source electrode of the transistor 20B when viewed in plan view is the same as the area of ​​the portion 23 of the second source electrode 21 of the transistor 20 included in the semiconductor device 1 of the embodiment when viewed in plan view. Figure 7 The on-resistance of the path from the second power supply 52 to the load 6 via the transistor 20B and the transistor 30B can be understood as Figure 6 The on-resistance of the second conduction path of the semiconductor device 1 in the embodiment is equivalent.

[0152] exist Figure 7 In the power supply circuit shown, when only the first power supply 51 ( Figure 7 When the second power supply 52 does not exist (in the case of a transistor 10B), the control IC 4 cuts off the transistor 20B to prevent the current supplied by the first power supply 51 from flowing to the second power supply 52. ​​Furthermore, a voltage above the threshold is applied to the gate pad 119B of the transistor 10B to control the transistor 10B to be on, and a voltage above the threshold is also applied to the gate pad 139B of the transistor 30B to control the transistor 30B to be on.

[0153] Therefore, the current flowing due to the power supply from the first power supply 51 flows in from the source pad 111B of the transistor 10B, flows out from the drain pad 151B, then flows in from the drain pad 153B of the transistor 30B, and flows out from the source pad 131B. Figure 8A 、 Figure 8B As shown, the area of ​​the transistor 10B in plan view (the area of ​​the source electrode portion 13B) is relatively large because the current flowing due to the power supply from the first power source 51 is relatively large.

[0154] exist Figure 7 In the power supply circuit shown, when only the second power supply 52 ( Figure 7 When first power supply 51 is absent (e.g., when first power supply 51 is not present), control IC 4 cuts off transistor 10B to prevent the current supplied by second power supply 52 from flowing to first power supply 51. Furthermore, a voltage above the threshold is applied to gate pad 129B of transistor 20B to control its on-state. Furthermore, a voltage above the threshold is also applied to gate pad 139B of transistor 30B to control its on-state.

[0155] Therefore, the current flowing due to the power supply from the second power supply 52 flows in from the source pad 121B of the transistor 20B, flows out from the drain pad 152B, then flows in from the drain pad 153B of the transistor 30B, and flows out from the source pad 131B. Figure 9A 、 Figure 9BAs shown, the area of ​​the transistor 20B in plan view (the area of ​​the source electrode portion 23B) is relatively small because the current flowing due to the power supply from the second power supply 52 is relatively small.

[0156] As mentioned above, in Figure 7 In the power supply circuit of the comparative example shown, the transistors 10B and 30B function as Figure 6 The transistor 10 and the transistor 30 of the semiconductor device 1 in the embodiment of the power supply circuit have the same function. Figure 7 In the power supply circuit of the comparative example shown, the transistors 20B and 30B function as Figure 6 The transistor 20 and the transistor 30 in the power supply circuit of the embodiment have the same function as those included in the semiconductor device 1 .

[0157] However, in Figure 7 In the circuit board equipped with the power supply circuit of the comparative example shown, it is necessary to ensure sufficient area for each of transistors 10B, 20B, and 30B, and to provide a certain margin between them. Furthermore, since transistors 10B, 20B, and 30B each have a drain pad (151B, 152B, 153B) when viewed in plan, they require a certain area.

[0158] On the other hand, Figure 6 In the circuit board of the power supply circuit shown, by utilizing the semiconductor device 1 of the embodiment, the transistors 10B, 20B, and 30B of the comparative example can be combined into a single device. This eliminates the need for the required margin between the transistors 10B, 20B, and 30B required in the circuit board mounting the power supply circuit of the comparative example.

[0159] In addition, in the semiconductor device 1 of the embodiment, the drain pads (151B, 152B, 153B) of the transistors 10B, 20B, and 30B in the comparative example can be deleted. Furthermore, in the semiconductor device 1 of the embodiment, since the third transistor 30 does not have a gate pad, it is also unnecessary to have a gate pad in the transistor 10B, 20B, and 30B. Figure 7 The transistor 30B ( Figure 8B ) formed in the gate pad 139B.

[0160] As described above, if the semiconductor device 1 of the embodiment is used, the area required for the circuit board can be greatly reduced. Figure 6 In the circuit board of the power supply circuit shown, the board itself can be made smaller than in the comparative example, and other components can be mounted on the remaining portion.

[0161] Therefore, the semiconductor layer 1 of the embodiment is a chip-size package type semiconductor device 1 that can be face-down mounted, comprising: a semiconductor layer 40, having a semiconductor substrate 42 on the back side, which is divided into three regions that do not overlap with each other and are not dispersed when the semiconductor device 1 is viewed in a planar manner, namely, a first region A1, a second region A2, and a third region A3; a first vertical MOS transistor 10, which is formed as a whole in the first region A1 of the semiconductor layer 40; a second vertical MOS transistor 20, which is formed as a whole in the second region A2 of the semiconductor layer 40; a third vertical MOS transistor 30, which is formed as a whole in the third region A3 of the semiconductor layer 40; and a metal layer 41, which is formed in contact with the back side of the semiconductor layer 40; the semiconductor substrate 42 is a common drain region of the first vertical MOS transistor 10, the second vertical MOS transistor 20, and the third vertical MOS transistor 30, and when viewed in a planar manner, a first vertical MO is formed at a position included in the first region A1. The first source pad 111 and the first gate pad 119 of the S transistor 10 and the first gate wiring 118 connected to the first gate pad 119 are formed; when viewed in a planar manner, the second source pad 121 and the second gate pad 129 of the second vertical MOS transistor 20 and the second gate wiring 128 connected to the second gate pad 129 are formed at a position included in the second area A2; when viewed in a planar manner, the third source pad 131 and the third gate wiring 138 of the third vertical MOS transistor 30 are formed at a position included in the third area A3; the first gate wiring 118 and the third gate wiring 138 are electrically connected in series via a first diode 113 with the direction from the first gate wiring 118 toward the third gate wiring 138 as the forward direction, and the second gate wiring 128 and the third gate wiring 138 are electrically connected in series via a second diode 123 with the direction from the second gate wiring 128 toward the third gate wiring 138 as the forward direction.

[0162] The semiconductor device 1 of the embodiment includes the first diode 113. When the transistor 10 is turned on, the transistor 30 is also automatically turned on, thereby conducting the first conduction path. In this case, the second diode 123 is electrically formed in the reverse direction as viewed from the third gate wiring 138, and the transistor 20 is not turned on.

[0163] Similarly, the second diode 123 is provided so that when transistor 20 is turned on, transistor 30 is also automatically turned on, thereby conducting the second conduction path. At this time, as viewed from the third gate wiring 138, the first diode 113 is electrically formed in the reverse direction, and transistor 10 is not turned on.

[0164] One end of the first diode 113 is connected to the first gate wiring 118, and the other end is connected to the third gate wiring 138. Similarly, one end of the second diode 123 is connected to the second gate wiring 128, and the other end is connected to the third gate wiring 138.

[0165] Therefore, in the semiconductor device 1 of the embodiment, it is characterized in that, when observed in a plane, the first diode 113 is formed so that the end of one side of the first diode 113 is located in the first area A1, and the end of the other side of the first diode 113 is located in the third area A3, and when observed in a plane, the second diode 123 is formed so that the end of one side of the second diode 123 is located in the second area A2, and the end of the other side of the second diode 123 is located in the third area A3.

[0166] By forming the first diode 113 and the second diode 123 as described above, it is possible to obtain an effect of preventing the conduction area of ​​the first conduction path or the second conduction path from being unnecessarily reduced.

[0167] like Figure 2B As shown, the first diode 113 is typically provided across the boundary line 90 (dashed line from P1 to P2) between the first area A1 and the third area A3 when viewed in plan. When the first EQR 116 is provided in the first area A1 and the third EQR 136 is provided in the third area A3, the first EQR 116 and the third EQR 136 share a common point at the boundary line 90 between the first area A1 and the third area A3 when viewed in plan. However, in order to provide the first diode 113, the shared EQRs may need to be partially cut off.

[0168] Therefore, in the semiconductor device 1 of the embodiment, the first EQR 116 may be formed in at least a portion of the outer periphery of the first area A1 when viewed in plan, and the third EQR 136 may be formed in at least a portion of the outer periphery of the third area A3 when viewed in plan. The first EQR 116 and the third EQR 136 may be shared in the portion where the first area A1 and the third area A3 face each other when viewed in plan, and the first diode 113 may be provided in the portion where the first and third EQRs are not shared when viewed in plan. In other words, the first diode 113 may be provided in a portion where the shared EQRs are interrupted, which serves as the boundary line 90 between the first area A1 and the third area A3 when viewed in plan.

[0169] In addition, Figure 6In the illustrated power supply circuit, there is a case where no voltage is applied to first gate pad 119 and second gate pad 129. In this case, depending on the state of use immediately before, semiconductor device 1 may have a residual potential in first gate wiring 118 and third gate wiring 138, or in second gate wiring 128 and third gate wiring 138.

[0170] Connecting first gate wiring 118 and third gate wiring 138 via first resistor 114 is preferable because a path is formed for releasing the residual potential of first gate wiring 118 and third gate wiring 138 to first gate pad 119, even if the resistance value of first resistor 114 is high. Similarly, connecting second gate wiring 128 and third gate wiring 138 via second resistor 124 is preferable because a path is formed for releasing the residual potential of second gate wiring 128 and third gate wiring 138 to second gate pad 129, even if the resistance value of second resistor 124 is high.

[0171] Therefore, in the semiconductor device 1 of the embodiment, the first gate wiring 118 and the third gate wiring 138 may be connected in series via the first resistor element 114, the first diode 113 and the first resistor element 114 may be connected in parallel between the first gate wiring 118 and the third gate wiring 138, the second gate wiring 128 and the third gate wiring 138 may be connected in series via the second resistor element 124, and the second diode 123 and the second resistor element 124 may be connected in parallel between the second gate wiring 128 and the third gate wiring 138.

[0172] One end of the first resistor 114 is connected to the first gate wiring 118, and the other end is connected to the third gate wiring 138. Similarly, one end of the second resistor 124 is connected to the second gate wiring 128, and the other end is connected to the third gate wiring 138.

[0173] Therefore, in the semiconductor device 1 of the embodiment, it is preferred that, when observed in a plane, the first resistor element 114 is formed so that the end of one side of the first resistor element 114 is located in the first area A1, and the end of the other side of the first resistor element 114 is located in the third area A3, and when observed in a plane, the second resistor element 124 is formed so that the end of one side of the second resistor element 124 is located in the second area A2, and the end of the other side of the second resistor element 124 is located in the third area A3.

[0174] By forming the first resistance element 114 and the second resistance element 124 as described above, it is possible to obtain an effect of preventing the conduction area of ​​the first conduction path or the second conduction path from being unnecessarily reduced.

[0175] In the semiconductor device 1 of the embodiment, the first conductive path has the first source pad 111 of the first area A1 as the inlet and the third source pad 131 of the third area A3 as the outlet. Therefore, if the first area A1 and the third area A3 are adjacent when viewed in plan, the first conductive path is shortened, which can reduce the on-resistance, thus making it preferable. Similarly, the second conductive path has the second source pad 121 of the second area A2 as the inlet and the third source pad 131 of the third area A3 as the outlet. Therefore, if the second area A2 and the third area A3 are adjacent when viewed in plan, the second conductive path is shortened, which can reduce the on-resistance, thus making it preferable.

[0176] Therefore, it is preferable that the first area A1 and the second area A2 are arranged with the third area A3 interposed therebetween when viewed in plan, and the third area A3 is adjacent to the first area A1 and the second area A2.

[0177] In the semiconductor device 1 of the embodiment, emphasis is placed on reducing the on-resistance of the first conduction path. Figure 2A or Figure 2B As shown, it is preferable that, when viewed in plan, the opposing length between the first region A1 and the third region A3 (the length of the dashed line from P1 to P2) is longer than the opposing length between the second region A2 and the third region A3 (the length of the dashed line from P3 through P5 to P4). When the semiconductor device 1 is arranged in this manner when viewed in plan, the portion of the first conduction path where the current density is highest can be expanded (the opposing length can be increased), thereby reducing on-resistance.

[0178] In the semiconductor device 1 of the embodiment, it is preferable that the inlet and outlet of the first conduction path for conducting a relatively large current have approximately the same area when viewed in plan. This is because if either the inlet or outlet is relatively small, it becomes a bottleneck, increasing the on-resistance.

[0179] Therefore, in the semiconductor device 1 of the embodiment, it is preferred that, when viewed in plan, the first source electrode of the first vertical MOS transistor 10 is formed at a position included in the first area A1, and the third source electrode of the third vertical MOS transistor 30 is formed at a position included in the third area A3, and when viewed in plan, the area of ​​the first source electrode and the area of ​​the third source electrode are substantially equal. The first source electrode and the third source electrode referred to herein refer to the portion 13 and the portion 33 of the first source electrode 11 and the third source electrode 31 that are in direct contact with the semiconductor layer 40.

[0180] In addition, in the semiconductor device 1 of the embodiment, there is no gate pad and gate electrode in the third area A3 when viewed in a planar manner. Therefore, even if the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31 have the same area when viewed in a planar manner, the area a3 of the third area A3 can be reduced compared to the area a1 of the first area A1.

[0181] Furthermore, since the rated current of the second conduction path is smaller, the conduction area can be reduced to take this into account. In this case, it is not a problem if the area of ​​the outflow port (portion 33 of the third source electrode 31) is larger than the area of ​​the inflow port (portion 23 of the second source electrode 21) when viewed in plan.

[0182] Therefore, in the semiconductor device 1 of the embodiment, it is preferable that, when viewed in plan, the area a1 of the first region A1 is larger than the area a3 of the third region A3, and the area a3 of the third region A3 is larger than the area a2 of the second region A2. Furthermore, the difference between the area a1 of the first region A1 and the area a3 of the third region A3 when viewed in plan is approximately equal to the area of ​​one first gate pad 119.

[0183] exist Figure 10A 、 Figure 10B 2 is a schematic plan view showing a modified example of the structure of the semiconductor device 1 according to the embodiment. Figure 10B and Figure 2B Similarly, the diagram shows a state immediately after forming portion 13 of first source electrode 11, first gate electrode 19, first gate wiring 118, portion 23 of second source electrode 21, second gate electrode 29, second gate wiring 128, portion 33 of third source electrode 31, and third gate wiring 138 on the surface side of semiconductor layer 40. Pads that should not be visible at this point in time are shown with dotted lines.

[0184] exist Figure 10A 、 Figure 10B In the modified example shown, Figure 2A 、 Figure 2B In contrast, the third region A3 is not sandwiched between the first region A1 and the second region A2, but is adjacent to the first region A1 and the second region A2. In addition, the first gate pad 119 is provided in the first region A1 close to the third region A3 in plan view.

[0185] The first gate pad 119 is arranged at a position close to the third area A3 in the first area A1, which means that in the first area A1, no part of the first source pad 111 is sandwiched between the first gate pad 119 and the third area A3 closest to the first gate pad 119.

[0186] This arrangement shortens the connection distance between first gate pad 119 and third gate wiring 138. Consequently, the voltage applied to first gate pad 119 can be quickly transmitted to third gate wiring 138, thereby improving the response speed of semiconductor device 1. This effect also applies to the arrangement of second gate pad 129 and third area A3 when viewed in plan.

[0187] Therefore, the first gate pad 119 may be provided at a position close to the third area A3 when viewed in a planar manner, and the second gate pad 129 may be provided at a position close to the third area A3 when viewed in a planar manner.

[0188] In addition, whether in Figure 2B and Figure 10B In any of the examples shown, when forming the first Zener diode 115 and / or the second Zener diode 125 in the semiconductor device 1, the first diode 113 and / or the second diode 123 are preferably formed simultaneously. By forming them simultaneously, the semiconductor device 1 can be manufactured more easily.

[0189] Originally, the first Zener diode 115 and / or the second Zener diode 125 and the first diode 113 and / or the second diode 123 are all diodes, and their respective functions can be realized by properly controlling the formation position, number, or electrical direction of the PN junction. Figure 2B As shown, when the semiconductor device 1 is viewed in plan, the first Zener diode 115 and / or the second Zener diode 125 differ from the first diode 113 and / or the second diode 123 only in their in-plane locations. Therefore, they can be formed simultaneously simply by changing the in-plane dopant implantation locations accordingly.

[0190] In this case, when the regions of the first diode 113 and the first Zener diode 115 exhibiting the same conductivity type are compared in plan view, the concentration of the impurity of that conductivity type is the same. The same impurity concentration means that the concentration distribution of the impurity is substantially the same when comparing one region with another region in the depth direction.

[0191] Therefore, when viewed in a planar manner, the first source electrode 11 (part 13) and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first area A1, and when viewed in a planar manner, the first Zener diode 115 is formed between the first source electrode 11 (part 13) and the first gate electrode 19, and the impurities of the same conductive type in the regions of the same conductive type contained in the first diode 113 and the first Zener diode 115 have the same concentration.

[0192] Likewise, when forming the first gate resistor 117 and / or the second gate resistor 127 in the semiconductor device 1, the first resistor 114 and / or the second resistor 124 are preferably formed simultaneously. Simultaneous formation facilitates manufacturing of the semiconductor device 1.

[0193] Therefore, when viewed in a planar manner, a first gate electrode 19 of the first vertical MOS transistor 10 is formed in the first region A1, and when viewed in a planar manner, a first gate resistor 117 is formed between the first gate electrode 19 and the first gate wiring 118, and the impurities of the same conductive type in the regions of the same conductive type contained in the first resistor 114 and the first gate resistor 117 have the same concentration.

[0194] [5. Additional Investigation]

[0195] Return to the semiconductor device 1 according to the embodiment Figure 6 In the example shown. In a transistor in the on state, generally, as the area of ​​the transistor when viewed in plan view increases, the total gate width increases, thereby reducing the on-resistance. In other words, the area of ​​the transistor when viewed in plan view and the on-resistance are roughly inversely proportional.

[0196] In semiconductor device 1, the planar area a1 of transistor 10 forming the first conduction path is larger than the planar area a2 of transistor 20 forming the second conduction path. Therefore, the first conduction path has a low on-resistance and is suitable for flowing a relatively large current.

[0197] The on-resistance R1 [Ω] of the first conduction path can be determined by taking into account the maximum value I1 [A] of the current flowing due to the power supplied from the first power supply 51. Similarly, the on-resistance R2 [Ω] of the second conduction path can be determined by taking into account the maximum value I2 [A] of the current flowing due to the power supplied from the second power supply 52. ​​Therefore, in the semiconductor device 1 of the embodiment, it is preferable to determine the areas of the transistors 10 and 20 so as to achieve on-resistances suitable for the first conduction path and the second conduction path, respectively.

[0198] However, if the planar area of ​​each transistor calculated as described above is too small, ESD resistance may be reduced. This is because if the planar area of ​​a transistor is small, the excess voltage and surge current applied to the gate electrode will not be sufficiently distributed within the cell (gate conductor) of the transistor.

[0199] Hereinafter, if the ESD guaranteed value (electrostatic tolerance guaranteed value) of the semiconductor device 1 is expressed as ESDt [V], then in the semiconductor device 1 of the embodiment, it is required to achieve a tolerance of ESDt or more in the transistor 20 having the smallest area. Figure 6 In the case of the power supply circuit shown, the ESDt required of the semiconductor device 1 is typically about 1000 [V] to 2000 [V].

[0200] For the purpose of achieving a desired ESDt, the second Zener diode 125 and / or the second gate resistor element 127 are provided for the transistor 20. However, as shown in FIG. Figure 6 As shown in the portion of the transistor 20 in FIG, setting the second Zener diode 125 results in setting a path connecting the second gate pad 129 (second gate electrode 29) and the second source pad 121 (portion 23 of the second source electrode 21), thereby having the side effect of generating leakage current between the gate and the source.

[0201] Figure 11 The area a [mm] of the transistor when viewed from a plane is experimentally confirmed by the present inventors. 2 ] and the maximum voltage value ESDt [V] at which the transistor is confirmed to be undamaged when applied to the gate pad. The horizontal axis is a, and the vertical axis is ESDt. Furthermore, regarding the area a of the transistor when viewed in plan, for the example of the semiconductor device 1 according to the embodiment, the area a1 of the first region A1 and the area a2 of the second region A2 when viewed in plan are respectively represented by the area a1 of the first region A1 and the area a2 of the second region A2 when viewed in plan. This includes areas that do not contribute to conduction.

[0202] The data plotted with circles are obtained using a transistor with neither a Zener diode nor a gate resistor. The data plotted with triangles are obtained using a transistor with only a Zener diode and no gate resistor. The data plotted with diamonds are obtained using a transistor with both a Zener diode and a gate resistor.

[0203] according to Figure 11 It can be seen that when no gate resistor is provided, the ESDt tends to increase as the transistor area a increases. Furthermore, even without increasing the transistor area a, the ESDt increases when a Zener diode is provided. When a gate resistor is provided in addition to a Zener diode, a nearly constant ESDt is achieved regardless of the transistor area.

[0204] When the ESD guaranteed value of the semiconductor device 1 of the embodiment is to be set to 2000 [V], for example, it is sufficient to ensure 2000 [V] for the transistor 20 having the smallest area when viewed in plan. Figure 11If the area a2 of the transistor 20 when viewed from the plane is less than about 2.0 [mm 2 ], it can be said that it is preferable to provide the second Zener diode 125 and the second gate resistor 127. On the other hand, according to the provision of the second Zener diode 125, when it is desired to avoid an increase in the leakage current between the gate and the source, it is preferable not to provide the second Zener diode 125. If the required ESD guarantee value is 2000 [V], the area a2 of the transistor 20 when viewed in plan is approximately 2.0 [mm 2 ]The above is enough.

[0205] Therefore, according to Figure 11 For the data of the circle mark, if the guaranteed electrostatic tolerance value described in the product data sheet of the semiconductor device 1 is set to ESDt [V], and the area of ​​the second region A2 when viewed from the plane is set to a2 [mm 2 ], then the relationship a2>(ESDt-93) / 990 is established.

[0206] Furthermore, at this time, it is also possible that a portion 23 of the second source electrode 21 and a second gate electrode 29 of the second vertical MOS transistor 20 are formed at a position included in the second area A2 when viewed in a planar manner, and a path electrically connecting the portion 23 of the second source electrode 21 and the second gate electrode 29 does not exist, and the second gate electrode 29 and the second gate wiring 128 are not connected via a resistor.

[0207] By adopting the above-described structure, an increase in the gate-source leakage current can be avoided in the transistor 20 , and a desired ESD guaranteed value (ESDt [V]) can be obtained in the semiconductor device 1 .

[0208] At this time, in the semiconductor device 1, sufficient ESDt should already be achieved in the transistor 10, which has a larger area when viewed in plan. Therefore, when viewed in plan, the portion 13 of the first source electrode 11 and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first area A1, and no path electrically connecting the portion 13 of the first source electrode 11 and the first gate electrode 19 exists, so that the first gate electrode 19 and the first gate wiring 118 are connected without a resistor.

[0209] With such a structure, in the transistor 10 , it is possible to avoid an unnecessary increase in leakage current between the gate and the source.

[0210] Even if the area a2 of the second region A2 in planar view satisfies the relationship a2<(ESDt-93) / 990, a desired ESD guaranteed value may be achieved by providing the second Zener diode 125 and the second gate resistor 127 .

[0211] Therefore, it is also possible that, when viewed in a planar manner, a position included in the first area A1 forms a portion 13 of the first source electrode 11 and the first gate electrode 19 of the first vertical MOS transistor 10, a path electrically connecting the portion 13 of the first source electrode 11 and the first gate electrode 19 does not exist, and the first gate electrode 19 is connected to the first gate wiring 118 without a resistor. When viewed in a planar manner, a position included in the second area A2 forms a portion 23 of the second source electrode 21 and the second gate electrode 29 of the second vertical MOS transistor 20, the portion 23 of the second source electrode 21 and the second gate electrode 29 are connected via a second Zener diode 125, and the second gate electrode 29 and the second gate wiring 128 are connected in series via a second gate resistor element 127.

[0212] By adopting the above-described structure, in the transistor 10 , it is possible to obtain a desired ESD guaranteed value (ESDt [V]) of the semiconductor device 1 while avoiding an unnecessary increase in the gate-source leakage current.

[0213] While the semiconductor device of one embodiment of the present disclosure has been described above based on the embodiments and variations thereof, the present disclosure is not limited to the embodiments. As long as they do not depart from the spirit of the present disclosure, embodiments resulting from various modifications conceived by those skilled in the art to these embodiments, and embodiments constructed by combining components from different embodiments and variations thereof, may also be included within the scope of one or more embodiments of the present disclosure.

[0214] Industrial Applicability

[0215] A semiconductor device including the vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0216] Description of Reference Numerals

[0217] 1Semiconductor devices

[0218] 4. Control IC

[0219] 6 load

[0220] 8 switching elements

[0221] 10 transistors (first vertical MOS transistors)

[0222] 10B, 20B, 30B transistors (single-structure vertical MOS transistors) 11 first source electrode

[0223] Parts 12, 13, 13B, 22, 23, 23B, 32, 33, and 33B

[0224] 14First source region

[0225] 15 first gate conductor

[0226] 16 first gate insulating film

[0227] 17 first gate trench

[0228] 18 First Body Region

[0229] 18a first connecting portion

[0230] 19 first gate electrode

[0231] 19B, 29B, 39B gate electrodes

[0232] 20 transistors (second vertical MOS transistors)

[0233] 21 second source electrode

[0234] 24 second source region

[0235] 25 second gate conductor

[0236] 26 second gate insulating film

[0237] 27 Second gate trench

[0238] 28 Second body region

[0239] 28a Second connecting portion

[0240] 29 second gate electrode

[0241] 30 transistor (third vertical MOS transistor)

[0242] 31 third source electrode

[0243] 34 third source region

[0244] 35 third gate conductor

[0245] 36 third gate insulating film

[0246] 37 third gate trench

[0247] 38 Third Body Region

[0248] 38a third connecting portion

[0249] 40 semiconductor layers

[0250] 41 metal layer (back drain electrode)

[0251] 42 semiconductor substrate

[0252] 43 low concentration impurity layer

[0253] 44 interlayer insulation layer

[0254] 45 passivation layer

[0255] 90 Boundary Line

[0256] 111 first source pad

[0257] 111B, 121B, 131B source pads

[0258] 113 first diode

[0259] 114 first resistance element

[0260] 115 First Zener diode

[0261] 116 First EQR

[0262] 117 first gate resistance element

[0263] 118 first gate wiring

[0264] 118B, 128B, 138B gate wiring

[0265] 119 first gate pad

[0266] 119B, 129B, 139B gate pads

[0267] 121 second source pad

[0268] 123 second diode

[0269] 124 second resistance element

[0270] 125 Second Zener diode

[0271] 126 Second EQR

[0272] 127 second gate resistance element

[0273] 128 second gate wiring

[0274] 129 second gate pad

[0275] 131 third source pad

[0276] 136 Third EQR

[0277] 138 third gate wiring

[0278] 151B, 152B, 153B drain pads

[0279] A1 first area

[0280] A2 Second Area

[0281] A3 Third Area

Claims

1. A semiconductor device, which is a chip-size package type semiconductor device capable of face-down mounting, characterized in that: have: The semiconductor layer has a semiconductor substrate on the back side and is divided into three regions, namely, a first region, a second region, and a third region, which do not overlap with each other and are not dispersed when the semiconductor device is viewed in a plan view; a first vertical MOS transistor, formed entirely in the first region of the semiconductor layer; a second vertical MOS transistor, formed entirely in the second region of the semiconductor layer; a third vertical MOS transistor, formed entirely in the third region of the semiconductor layer; as well as a metal layer formed in contact with the back side of the semiconductor layer, The semiconductor substrate is a common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor. When viewed in the planar view, a first source pad and a first gate pad of the first vertical MOS transistor and a first gate wiring connected to the first gate pad are formed at a position included in the first region. When viewed in the planar view, a second source pad and a second gate pad of the second vertical MOS transistor and a second gate wiring connected to the second gate pad are formed at a position included in the second region. When viewed in the planar view, a third source pad and a third gate wiring of the third vertical MOS transistor are formed at a position included in the third region. The first gate wiring and the third gate wiring are electrically connected in series via a first diode with a direction from the first gate wiring toward the third gate wiring as a forward direction. The second gate wiring and the third gate wiring are electrically connected in series via a second diode with a direction from the second gate wiring toward the third gate wiring as a forward direction.

2. The semiconductor device according to claim 1, wherein The first diode is formed so that one end of the first diode is located in the first region and the other end of the first diode is located in the third region. The second diode is formed so that one end portion of the second diode is located in the second region and the other end portion of the second diode is located in the third region.

3. The semiconductor device according to claim 1, wherein The first gate wiring and the third gate wiring are further connected in series via a first resistor element. The first diode and the first resistor are connected in parallel between the first gate wiring and the third gate wiring. The second gate wiring and the third gate wiring are further connected in series via a second resistor element. The second diode and the second resistor are connected in parallel between the second gate wiring and the third gate wiring.

4. The semiconductor device according to claim 3, wherein The first resistor element is formed so that one end of the first resistor element is located in the first region and the other end of the first resistor element is located in the third region. The second resistor element is formed so that one end portion of the second resistor element is located in the second region and the other end portion of the second resistor element is located in the third region.

5. The semiconductor device according to claim 1, wherein When viewed in the planar view, the first region is adjacent to the third region, and the second region is adjacent to the third region.

6. The semiconductor device according to claim 1, wherein When viewed in the plane, the area of ​​the first region is larger than that of the third region, and the area of ​​the third region is larger than that of the second region.

7. The semiconductor device according to claim 6, wherein: When viewed in the planar view, a first source electrode of the first vertical MOS transistor is formed at a position included in the first region. When viewed in the planar view, a third source electrode of the third vertical MOS transistor is formed at a position included in the third region. When viewed in the planar view, the area of ​​the first source electrode is substantially equal to the area of ​​the third source electrode.

8. The semiconductor device according to claim 1, wherein When viewed from the plane, a first EQR (EQuipotential Ring) is formed on at least a portion of the outer periphery of the first region. When viewed from the plane, a third EQR is formed on at least a portion of the periphery of the third region. In the planar view, the first EQR and the third EQR are common in a portion where the first region and the third region face each other. In the planar view, the first diode is provided at a portion that is not shared by the first EQR and the third EQR.

9. The semiconductor device according to claim 1, wherein When viewed from the plane, the first gate pad is disposed at a position close to the third region. The second gate pad is provided at a position close to the third region in the planar view.

10. The semiconductor device according to claim 1, wherein When viewed in the planar view, a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region. When viewed in the planar view, a first Zener diode is formed between the first source electrode and the first gate electrode. The concentration of impurities of the same conductivity type in regions of the same conductivity type included in the first diode and the first Zener diode is the same.

11. The semiconductor device according to claim 3, wherein When viewed in the planar view, a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region. When viewed in the planar view, a first gate resistance element is formed between the first gate electrode and the first gate wiring. The concentration of impurities of the same conductivity type in regions of the same conductivity type included in the first resistor and the first gate resistor is the same.

12. The semiconductor device according to claim 1, wherein In the planar view, a gate electrode and a gate pad connected to the third gate wiring are not formed at a position included in the third region.

13. The semiconductor device according to claim 6, wherein The guaranteed electrostatic tolerance value listed in the product data sheet of the semiconductor device is defined as ESDt [V]. The area of ​​the second region when viewed from the plane is set to a2 [mm 2 ], Then the relationship a2>(ESDt-93) / 990 holds true.

14. The semiconductor device according to claim 13, wherein When viewed in the planar view, a second source electrode and a second gate electrode of the second vertical MOS transistor are formed at positions included in the second region. There is no path electrically connecting the second source electrode and the second gate electrode. The second gate electrode and the second gate wiring are connected without a resistor.

15. The semiconductor device according to claim 14, wherein When viewed in the planar view, a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region. There is no path electrically connecting the first source electrode and the first gate electrode. The first gate electrode and the first gate wiring are connected without a resistor.

16. The semiconductor device according to claim 6, wherein In the plan view, a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region. There is no path electrically connecting the first source electrode and the first gate electrode. The first gate electrode and the first gate wiring are connected without a resistor. In the plan view, a second source electrode and a second gate electrode of the second vertical MOS transistor are formed at positions included in the second region. The second source electrode and the second gate electrode are connected via a second Zener diode, The second gate electrode and the second gate wiring are connected in series with a second gate resistance element therebetween.

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