Digital BPL long wave time service receiving device and method capable of automatically compensating and highly stably outputting pulse per second

Abstract

The invention discloses a digital BPL long-wave time service receiving device and method capable of automatically compensating high-stability output pulse per second, and the device comprises an FPGA unit, an A / D conversion unit, a program programming storage unit, a storage unit, and a constant-temperature crystal oscillator. Converting the 14-bit digital signal into a second pulse signal and standard time; the A / D conversion unit is used for converting the wireless digital long-wave analog signal into a digital signal with the width of 14 bits; hardware is designed on the basis of an FPGA, receiving and processing of BPL long-wave time service information are achieved in combination with a verilog HDL, the automatic compensation high-stability second pulse output method can dynamically compensate the second pulse output initial position according to the received long-wave time service message information, stable second pulses are provided for other systems, and the accuracy of second pulse output is improved. The long-wave time service system can be used as an effective supplementary means for satellite time service and wired time service, and can provide standard time information and second pulse signals for users in real time in a long-wave time service system coverage area.

Description

Technical Field

[0001] The present invention relates to a BPL long-wave timing receiving device and method, in particular to a digital BPL long-wave timing receiving device and method capable of automatically compensating for highly stable output second pulses. Background Art

[0002] The BPL long-wave timing system is the timing service provider for my country's time service center. Since its official operation, the system has provided reliable timing services to numerous industries and sectors of my country's national economy, playing a vital role in the national economy. my country's long-wave timing system is primarily based on Loran-C technology and is a ground-based radio positioning, navigation, and timing (PNT) system that utilizes a multi-pulse phase-coded transmission system on a 100 kHz carrier frequency. The transmission format involves a master station transmitting a group of nine pulses, with the first eight pulses separated by 1ms, and the ninth and eighth pulses separated by 2ms. These serve as identification pulses for the master station. After a certain delay, a slave station transmits a group of eight pulses, separated by 1ms. Only the first pulse of the master station's pulse group is aligned with UTC (USN) at the specified time. After several slave stations have transmitted, the master station resumes transmission after a period of time.

[0003] However, the equipment that uses long-wave time stations for standard time reception is mainly long-wave time receivers. As far as we know, the baseband processing in long-wave time receivers generally adopts the FPGA+DSP design method. Since this design method requires two main chips to work together, there is room for improvement in software design and development, cost control, and post-maintenance. On the other hand, existing long-wave receivers generally focus on studying the reception of long-wave time information and second pulses or using external reference second pulses to calibrate the second pulses received by BPL long waves. They do not consider how to ensure the fast, reliable and effective output of highly stable second pulses and time code information due to certain errors in the long-wave wireless time signal reception process. Summary of the Invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a digital BPL long-wave timing receiving device that can automatically compensate for the highly stable output of second pulses, so that the BPL long-wave timing receiving device can quickly and reliably output highly stable second pulses and time code information. On the other hand, a digital BPL long-wave timing receiving method that can automatically compensate for the highly stable output of second pulses is provided.

[0005] Technical solution: The BPL long-wave timing receiver of the present invention includes an FPGA unit, an A / D conversion unit, a program burning storage unit, a storage unit, and a constant temperature crystal oscillator. The storage unit is coupled to the FPGA unit, the A / D conversion unit and the program burning storage unit are coupled to the control signal terminal of the FPGA unit, and the output terminal of the constant temperature crystal oscillator is coupled to the clock input terminal of the FPGA unit.

[0006] FPGA unit, used to receive wireless digitized long-wave analog signals and convert 14-bit digital signals into pulse-per-second signals and standard time;

[0007] A / D conversion unit, used to convert wireless digitized long-wave analog signals into digital signals with a width of 14 bits;

[0008] Program burning storage unit, used for program burning storage of FPGA unit;

[0009] A storage unit, used to store data of the FPGA unit during the long-wave timing reception processing;

[0010] Oven-controlled crystal oscillator, used to provide standard clock frequency for FPGA modules.

[0011] Preferably, the FPGA unit includes an ADC control unit, an FIR filtering unit, a Roland C decoding unit, an RS decoding unit, a CRC check unit, a time and pulse per second compensation unit, a DDR storage control unit and a serial port transceiver unit.

[0012] Preferably, the ADC control unit is used to read a digital signal with a width of 14 bits in a time sequence, and read and write a dual-clock FIFO memory, wherein the width of the dual-clock FIFO memory is 14 bits and the depth is 8 bytes;

[0013] The FIR filtering unit is used to read the 14-bit digital signal from the dual-clock FIFO memory and filter it to extract the valid data in the long-wave timing signal;

[0014] The Roland C decoding unit is used to perform Roland C decoding on the filtered data;

[0015] The RS decoding unit is used to perform RS decoding on the data decoded by the Roland C decoding unit;

[0016] The CRC check unit is used to perform CRC check on the data input by the RS decoding unit to obtain 56-bit BPL valid data in the GRI pulse group and form a frame group according to the BPL timing message format;

[0017] The time and pulse-second compensation unit is used to analyze and perform algorithmic processing on the received frame group data, calculate the start time of the pulse-second and perform automatic compensation;

[0018] The serial port transceiver unit is used to delay a fixed time and send BPL time information TOD when the time and second pulse locking unit receives the second pulse as a trigger;

[0019] The DDR storage control unit is used to store the backup of each unit data and the received BPL timing information.

[0020] The BPL long-wave timing receiving method of the present invention comprises the following steps:

[0021] S1, A / D conversion unit receives wireless digitized long-wave analog signal and converts it into a digital signal with a width of 14 bits;

[0022] S2, the ADC control unit reads the 14-bit digital signal in time sequence, and the FIR filter unit filters the 14-bit digital signal;

[0023] S3, determine the BPL pulse start of the filtered data and confirm the decoded data, the Loran C decoding unit performs Loran C decoding and sends it to the RS decoding unit;

[0024] S4, the RS decoding unit performs RS decoding on the received data, and then sends the RS decoded data to the CRC check unit;

[0025] S5, the CRC check unit performs CRC check on the data input by the RS decoding unit to obtain the 56-bit BPL valid data in the GRI pulse group, forms a frame group according to the BPL timing message format, and outputs it to the time and second pulse locking unit through the enable signal control;

[0026] S6, the time and second pulse compensation unit parses and processes the received frame group data, obtains the current time information, and simultaneously obtains the millisecond, microsecond information and GRI compensation time according to the BPL timing message 2, calculates the start time of the second pulse, and automatically compensates the second pulse;

[0027] S7, the asynchronous serial port transceiver unit is triggered by the time and second pulse locking unit receiving the second pulse, delays for a fixed time, and completes the sending of the BPL time information TOD;

[0028] S8, DDR storage control unit stores the backup of each unit's data and the received BPL timing information, and finally the FPGA unit outputs the second pulse signal and standard time.

[0029] Preferably, said S3 includes: judging the start of the filtered BPL pulse and confirming the decoded data according to the GRI pulse group as a period;

[0030] S31, confirm the starting bpl_pulse of a single pulse in the GRI pulse group through the input filtered data, high level is valid;

[0031] S32, timing two adjacent pulses bpl_pulse by a state machine, and demodulating the modulation data information of the last six pulses of the eight pulses in each GRI pulse group period;

[0032] S33, combining the last 6 single pulse data information in the GRI pulse group to obtain decoded data, then performing 7-bit confirmation according to the modulation pattern, and effectively sending the obtained 7-bit data to the RS decoding unit for RS decoding through the enable signal control data.

[0033] Preferably, the S6 includes:

[0034] S61. The received frame group data is judged as a message type according to the BPL message format. Frame[55:52]=4'b0100 is a timing message.

[0035] S62, the frame group data BPL message format is used to determine the message subtype. Frame[51:50]=2'b01 is BPL timing message 1, and frame[51:50]=2'b10 is BPL timing message 2.

[0036] S63: If the received frame group data message subtype is timing message 1, perform year-month-day parsing based on the frame group data to obtain the current year-month-day information;

[0037] S64. If the received frame group data message subtype is timing message 2, the hour, minute, second, millisecond, and microsecond information is parsed based on the frame group data to obtain the current hour, minute, second, millisecond, and microsecond information.

[0038] S65, judging the transmitting station of the received BPL timing message 2-frame data, and confirming the gri time, gri_ms millisecond time, and gri_us microsecond time according to the transmitting station;

[0039] S66. Extract the received BPL timing second pulse based on the currently calculated gri time, gri_ms millisecond time, gri_us microsecond time, local delay time local_delay, system delay time sys_delay, and compensated clock deviation time_usec_add. The local delay is adjusted and assigned a value based on the geographical situation of the receiving device. The local_delay includes local_delay_ms and local_delay_us, the sys_delay includes sys_delay_ms and sys_delay_us, and the time_usec_add takes a value of 10.

[0040] Preferably, in S66:

[0041] If the sum of the current time_msec, local_delay_ms, sys_delay_ms, and gri_ms in BPL timing message 2 is 999, and the sum of time_usec, local_delay_us, sys_delay_us, and gri_us is also 999, then a bpl_pps second pulse is output with a pulse width of 1 clock cycle of high level.

[0042] Preferably, automatic compensation is performed for the output bpl_pps pulses per second, including:

[0043] (1) By judging the high level of bpl_pps, the second pulse arrival flag pps_has_arrived and the second pulse input timer pps_in_cnt are started, and the high level of pps_has_arrived is valid;

[0044] (2) By judging the count value of the pulse-per-second timer pps_in_cnt, the compensation cycle counter pps_in_cycle is started;

[0045] (3) Compare pps_in_cnt with the default maximum offset value MAX_OFF at the current bpl_pps high level moment, confirm the temporary compensation value max_offset_tmp, and compare pps_in_cnt with the default maximum offset value MAX_OFF at the current bpl_pps high level moment;

[0046] (4) Determine the maximum compensation value max_offset at the high level of the clock 10MHz, and compare the maximum compensation value max_offset with the temporary offset value max_offset_tmp;

[0047] (5) Determine the bpl_pps locking and compensation mode based on the current bpl_pps high level moment;

[0048] (6) The pps_out compensation output is performed through the compensation pulse level.

[0049] Preferably, in step 3:

[0050] If pps_in_cnt < MAX_OFF, the temporary compensation value max_offset_tmp is pps_in_cnt / 2. If (SECOND-pps_in_cnt) < MAX_OFF, the temporary compensation value max_offset_tmp is (SECOND-pps_in_cnt) / 2, where SECOND is the whole second value 1s and MAX_OFF can be 10us.

[0051] In step 4:

[0052] If max_offse<max_offset_tmp, the maximum compensation value is max_offset=max_offset_tmp, otherwise it remains unchanged;

[0053] In step 5:

[0054] If the current bpl_pps high level moment is (SECOND-2×max_offset-error)<pps_in_cnt<(SECOND-2×max_offset+error), then the delay compensation signal pps_in_cnt_cmp_0=1; if the current bpl_pps high level moment is (2×max_offset-error)<pps_in_cnt<(2×max_offset+error), then the advance compensation signal pps_in_cnt_cmp_1=1;

[0055] In step 6:

[0056] If the current pps_in_cnt_cmp_0=1, the starting value of pps_out_cnt is SECOND-max_offset, that is, the pps_out output second pulse is delayed by max_offset; if pps_in_cnt_cmp_1=1, the starting value of pps_out_cnt is max_offset+1, that is, the compensation is advanced by max_offset to output the pps_out second pulse, and the pps_out_cnt count is SECOND, and the second pulse pps_out is output at a high level.

[0057] Preferably, the second pulse state pps_state and the second pulse output high level pulse width, quantity, etc. are designed according to the pps_out second pulse output starting level, such as outputting pps.

[0058] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: digital long-wave timing time processing and reception are realized through the programmable device FPGA, and the automatic compensation high-stability output second pulse method is adopted in the design process to dynamically compensate the second pulse output starting position of the received long-wave timing telegram information, thereby improving the stability of the second pulse and time code information for other systems; the device of the present invention has the characteristics of miniaturization, modularization, and board-based, and can be embedded in the timing equipment or expanded separately into an independent long-wave timing receiver. Through actual engineering development and verification, the specific values ​​of the second pulse judgment, compensation parameters, etc. in the device have been verified, as well as the characteristics of high decoding accuracy, stable second pulse, and easy expansion. It can be applied to various industries such as wireless communications, electronic reconnaissance, digital instruments, navigation, transportation, and electricity. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 This is a schematic diagram of the hardware design principle of the device of the present invention;

[0060] Figure 2 Schematic diagram of the signal processing flow of the present invention;

[0061] Figure 3 This is a flow chart of the BPL timing analysis and bpl_pps pulse-per-second extraction process of the present invention. DETAILED DESCRIPTION

[0062] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0063] like Figure 1 As shown, a digital BPL long-wave timing receiver capable of automatically compensating for highly stable output second pulses includes an FPGA unit, an A / D conversion unit, a program burning storage unit, a storage unit, and a constant temperature crystal oscillator. The storage unit is coupled to the FPGA unit, the A / D conversion unit and the program burning storage unit are coupled to the control signal terminal of the FPGA unit, and the output terminal of the constant temperature crystal oscillator is coupled to the clock input terminal of the FPGA unit.

[0064] The FPGA unit uses the EP3C40F484 FPGA chip to receive wireless digital long-wave analog signals and convert the 14-bit digital signals into pulse-per-second signals and standard time. The signal processing process adopts a modular design concept, including ADC control unit, FIR filter unit, Roland C decoding unit, RS decoding unit, CRC check unit, time and pulse-per-second compensation unit, DDR storage control unit and serial port transceiver unit. Figure 2 As shown:

[0065] The FIR filter unit mainly uses the IP core of the EP3C40F484 development tool QUARTUS II to design a bandpass window filter. The window design type is Hamming window, the sampling rate is 1MHz, the bandpass frequency Fc1=90KHz, Fc2=110KHz, the filter order is 256, and the clock frequency is 10MHz.

[0066] The A / D conversion unit uses the AD9241 ADC chip to convert the wireless digitized long-wave analog signal into a digital signal with a width of 14 bits.

[0067] The program burning storage unit uses the M25P64 Flash chip for program burning and storage of the FPGA unit.

[0068] The storage unit uses the MT47H64M16HR DDR2 chip to store the data of the FPGA unit during the long-wave timing reception and processing process.

[0069] Oven-controlled crystal oscillator, used to provide 10MHz standard clock frequency for the FPGA module.

[0070] A digital BPL long-wave timing receiving method capable of automatically compensating for highly stable output second pulses comprises the following steps:

[0071] S1, A / D conversion unit receives wireless digitized long-wave analog signal and converts it into a digital signal with a width of 14 bits.

[0072] S2. The ADC control unit initializes the AD9241 according to the timing requirements of the AD9241 chip and reads 14-bit data according to the timing. A dual-clock FIFO memory with a width of 14 bits and a depth of 8 bytes is designed using the IP core of the EP3C40F484 development tool, QUARTUS II. The AD9241 data is read and written into the FIFO with a write clock of 10 MHz. The clock for reading the FIFO and inputting it into the FIR filter unit is 1 MHz. The data reading and writing of the FIFO are controlled by the write enable wrreg and write enable rdreg. The FIR filter unit filters the data adc_data_in[13:00] read from the FIFO in the ADC control unit, extracts the valid data BPL_DATA[15:00] from the 100 kHz carrier of the long-wave timing system, and controls the data to be sent to the Roland C decoding unit for Roland C decoding through the BPL_DATA_valid enable signal.

[0073] S3, the Roland C decoding unit performs Roland C decoding on the filtered BPL_DATA[15:00] data, and sends the Roland C-decoded asc_data_out[6:0] data to the RS decoding unit;

[0074] The Roland C decoding unit uses a clock rate of 10MHz and judges the start of the filtered BPL pulse and confirms the decoded data according to the GRI pulse group period. First, the starting bpl_pulse of a single pulse in the GRI pulse group is confirmed by the input BPL_DATA[15:00] data, and the high level is valid; then the state machine method is used to time the two adjacent pulses bpl_pulse and demodulate the modulation data information of the last six pulses of the eight pulses in each pulse group (GRI) period. The modulation data information "+" is 2'b01, "0" is 2'b00, and "-" is 0. " is 2'b11. In the design, the phase judgment window is set to TIME_PHRASE_WINDOW. Considering the delay error and other issues, the counting time error TIME_WINDOW_WIDTH, the adjustment time error TIME_20US, and the pulse modulation start error TIME_0P5US are added. For example, when judging the third single pulse data information in the GRI pulse group, the time_count_all from the start value of the first single pulse bpl_pulse to the arrival value of the third single pulse bpl_pulse is used to confirm the single pulse data information:

[0075] (1) TIME_1MS×2-TIME_20US-TIME_0P5US-TIME_PHRASE_WINDOW<time_count_all<TIME_1MS×2-TIME_20US-TIME_0P5US or TIME_1MS×2+TIME_20US-TIME_0P5US-TIME_PHRASE_WINDOW<time_count_all<TIME_1MS×2+TIME_20US-TIME_0P5US, the pulse data information sign_value3=2'b11;

[0076] (2)TIME_1MS×2-TIME_20US+TIME_0P5US<time_count_all<TIME_1MS×2-TIME_20US+TIME_0P5US+TIME_PHRASE_WINDOW or TIME_1MS×2+TIME_20US+TIME_0P5US<time_count_all<TIME_1MS×2+TIME_20US+TIME_0P5US+TIME_PHRASE_WINDOW, the pulse data information sign_value3=2'b01;

[0077] (3)TIME_1MS×2-TIME_20US-TIME_0P5US<time_count_all<TIME_1MS×2-TIME_20US+TIME_0P5US or TIME_1MS×2+TIME_20US-TIME_0P5US<time_count_all<TIME_1MS×2+TIME_0P5US, the pulse data information sign_value3=2'b00;

[0078] Similarly, the pulse data information of sign_value4, sign_value5, sign_value6, sign_value7, and sign_value8 can be obtained. The data information of the last 6 single pulses in the GRI pulse group is combined to obtain the decoded data as phrase_decode[11:0]. Then, 7-bit confirmation is performed according to the modulation pattern corresponding to phrase_decode[11:0]. For example, phrase_decode[11:0]=12'b111100010100, then asc_data_out[6:0]=7'd2, and the default value of asc_data_out[6:0] is 7'd127. The obtained 7-bit data asc_data_out[6:0] is effectively sent to the RS decoding unit for RS decoding through the asc_data_valid enable signal control signal.

[0079] S4, the RS decoding unit performs RS decoding on the received data asc_data_out[6:0], and sends the RS decoded data rsout[7:1] to the CRC check unit;

[0080] The RS decoding unit uses the IP core of the EP3C40F484 development tool QUARTUS II to design an RS (30, 10) decoder. The decoder clock is 10MHz and the width is 7bit. The valid data input is controlled according to the decoder timing. The data valid source_val signal, the output start source_sop signal, and the output end source_eop signal control the output of 10 valid rsout[7:1] data to the CRC check unit.

[0081] S5. The CRC check unit performs CRC check on the rsout[7:1] data input by the RS decoding unit to obtain 56-bit BPL valid data in the 8 GRI pulse groups, and forms a frame group frame_out[55:00] according to the BPL timing message format, and controls the output to the time and second pulse locking unit through the enable signal frame_out_en. The high bit of the data in the frame group is in front and the low bit is in the back.

[0082] S6, the time and second pulse compensation unit parses and processes the received frame group frame_out[55:00] data, and obtains the current year, month, day, hour, minute, and second time information. At the same time, it obtains the millisecond and microsecond information and GRI compensation time according to the BPL time message 2, thereby calculating the start time of the second pulse and automatically compensating the second pulse, providing a reliable and stable second pulse output method for the BPL time receiving device. The specific processing flow is as follows: Figure 3 As shown:

[0083] (1) The received frame group frame_out[55:00] data is judged as a message type according to the BPL message format. If frame[55:52] = 4'b0100, it is a timing message.

[0084] (2) The BPL message format of the frame group frame_out[55:00] data is used to determine the message subtype. Frame[51:50]=2'b01 is BPL timing message 1, and frame[51:50]=2'b10 is BPL timing message 2.

[0085] (3) If the received frame group frame[55:0] data message subtype is timing message 1, the year, month, and day are parsed according to the frame group frame[55:0] data to obtain the current year, month, and day information, where frame[30:25] is the year information time_year, frame[24:21] is the month information time_month, and frame[20:16] is the day information time_day.

[0086] (4) If the received frame group frame[55:0] data message subtype is timing message 2, then the hour, minute, second, millisecond, and microsecond are parsed according to the frame group frame[55:0] data to obtain the current hour, minute, second, millisecond, and microsecond information, where frame[47:43] is the hour information time_hour, frame[42:37] is the minute information time_mini, frame[36:31] is the second information time_seco, frame[30:21] is the millisecond information time_msec, and frame[20:11] is the microsecond information time_usec.

[0087] (5) The received BPL timing message 2 frame group frame[3:0] data is judged by the transmitting station. In the design, the gri time, gri_ms millisecond time, and gri_us microsecond time can be confirmed according to the transmitting station. For example, if the transmitting station number is 9, gri<=32'd743000, gri_ms<=10'd74, and gri_us<=10'd300;

[0088] (6) Extract the received BPL timing pulse according to the currently calculated gri time, gri_ms millisecond time, gri_us microsecond time, local delay time local_delay, system delay time sys_delay and compensation clock deviation time_usec_add, where the local delay is adjusted according to the geographical situation of the receiving device. local_delay includes local_delay_ms and local_delay_us, system delay time sys_delay includes sys_delay_ms and sys_delay_us, and compensation clock deviation time_usec_add takes the value of 10. If the current time_msec, If the sum of local_delay_ms, sys_delay_ms, and gri_ms is 999, and the sum of time_usec, local_delay_us, sys_delay_us, and gri_us is also 999, then bpl_pps second pulses are output, i.e., bpl_pps <= ((time_msec + local_delay_ms + sys_delay_ms + gri_ms)) = = 10'd999 & ((time_usec + local_delay_us + sys_delay_us + gri_us) = = 10'd999) & time_usec_add; the pulse width is a high level of 1 clock cycle;

[0089] (7) To ensure the stability of the received BPL long-wave timing time information and second pulses, the present invention adopts a design idea of ​​automatically compensating the extracted bpl_pps second pulses to improve the stability of the output second pulses and lock the received BPL timing second pulses. The specific processing flow is as follows:

[0090] (1) By judging the high level of bpl_pps, the second pulse arrival flag pps_has_arrived and the second pulse input timer pps_in_cnt are started. The second pulse timer pps_in_cnt has a period of 1s, that is, the clock is 10MHz. The count value is reset after reaching 10000000, and the high level of pps_has_arrived is valid;

[0091] (2) By judging the count value of the second pulse timer pps_in_cnt, the compensation cycle counter pps_in_cycle is started. The compensation cycle is T0, that is, the compensation calculation is recalculated every T0 seconds. That is, when T0=10, the pps_in_cycle count value is 10 and then reset to zero, and the compensation value calculation is restarted. This can effectively avoid the error caused by the system clock;

[0092] (3) Compare pps_in_cnt with the default maximum offset value MAX_OFF at the current bpl_pps high level moment to confirm the temporary compensation value max_offset_tmp. At the current bpl_pps high level moment, compare pps_in_cnt with the default maximum offset value MAX_OFF. If pps_in_cnt < MAX_OFF, the temporary compensation value max_offset_tmp is pps_in_cnt / 2. If (SECOND-pps_in_cnt) < MAX_OFF, the temporary compensation value max_offset_tmp is (SECOND-pps_in_cnt) / 2. SECOND is the whole second value 1s, and MAX_OFF can be 10us.

[0093] (4) Determine the maximum compensation value max_offset at the high level of the clock 10MHz, and compare the maximum compensation value max_offset with the temporary offset value max_offset_tmp. If max_offset<max_offset_tmp, the maximum compensation value is max_offset=max_offset_tmp, otherwise it remains unchanged.

[0094] (5) Determine the bpl_pps locking and compensation mode based on the current bpl_pps high level moment. If the current bpl_pps high level moment is (SECOND-2×max_offset-error)<pps_in_cnt<(SECOND-2×max_offset+error), then the delay compensation signal pps_in_cnt_cmp_0=1. If the current bpl_pps high level moment is (2×max_offset-error)<pps_in_cnt<(2×max_offset+error), then the advance compensation signal pps_in_cnt_cmp_1=1.

[0095] (6) Compensate the output of pps_out by using the pulse level compensation method. If the current pps_in_cnt_cmp_0 = 1, the starting value of pps_out_cnt is SECOND-max_offset, that is, the output second pulse of pps_out is delayed by max_offset; if pps_in_cnt_cmp_1 = 1, the starting value of pps_out_cnt is max_offset+1, that is, the compensation advances the output of pps_out second pulse by max_offset. When the pps_out_cnt count is SECOND, the output second pulse pps_out is high level;

[0096] (7) The second pulse state pps_state and the second pulse output high level pulse width and quantity can be further designed according to the pps_out second pulse output starting level. For example, the output pps_state state is a flashing pulse, the high level is 450ms, the pps_out high level is 133us, and the output pps_out number of channels is 2.

[0097] S7. The asynchronous serial port transceiver unit is triggered by the time and second pulse locking unit receiving the second pulse, delays for a fixed time T, and completes the sending of the BPL time information TOD. Considering the time information sending and the asynchronous serial port sending rate, in the specific implementation, T is set to 50ms, that is, the asynchronous serial port transceiver unit starts sending the time code information 50ms after the second pulse high level arrives.

[0098] S8 and DDR storage control units realize the backup storage of each unit's data and the storage of received BPL timing information. On the one hand, they are used for data analysis and problem location of each process during the debugging process, and on the other hand, they provide BPL timing information for the asynchronous serial port transceiver unit.

[0099] This invention proposes a digital BPL long-wave timing receiver device and method capable of automatically compensating for highly stable second pulse output. The device's hardware is designed based on a programmable field-programmable (FPGA) device and uses the universal hardware description language Verilog HDL to receive and process BPL long-wave timing information. This automatic compensation method dynamically compensates for the starting position of the second pulse output based on received long-wave timing telegrams, improving the stability of the second pulse output for other systems. This method can effectively supplement satellite and wired timing, providing users with real-time standard time information and second pulse signals within the coverage area of ​​long-wave timing systems. Furthermore, the system utilizes the hardware description language Verilog HDL to receive and process BPL long-wave timing information, reducing development and maintenance workload compared to FPGA+DSP or FPGA+ARM solutions. It also provides an effective alternative for subsequent porting and domestic programmable device design.

Claims

1. A digital BPL long-wave timing receiver capable of automatically compensating for highly stable output second pulses, characterized in that: The device comprises an FPGA unit, an A / D conversion unit, a program burning storage unit, a storage unit and a constant temperature crystal oscillator. The storage unit is coupled to the FPGA unit. The A / D conversion unit and the program burning storage unit are coupled to the control signal terminal of the FPGA unit. The output terminal of the constant temperature crystal oscillator is coupled to the clock input terminal of the FPGA unit. FPGA unit, used to receive wireless digitized long-wave analog signals and convert 14-bit digital signals into pulse-per-second signals and standard time; A / D conversion unit, used to convert wireless digitized long-wave analog signals into digital signals with a width of 14 bits; Program burning storage unit, used for program burning storage of FPGA unit; A storage unit, used to store data of the FPGA unit during the long-wave timing reception processing; Oven-controlled crystal oscillator, used to provide standard clock frequency for FPGA modules.

2. The BPL long-wave timing receiving device according to claim 1, wherein: The FPGA unit includes an ADC control unit, an FIR filter unit, a Roland C decoding unit, an RS decoding unit, a CRC check unit, a time and pulse per second compensation unit, a DDR storage control unit and a serial port transceiver unit.

3. The BPL long-wave timing receiving device according to claim 2, wherein: The ADC control unit is used to read a digital signal with a width of 14 bits in a time sequence, and read and write a dual-clock FIFO memory, wherein the dual-clock FIFO memory has a width of 14 bits and a depth of 8 bytes; The FIR filtering unit is used to read the 14-bit digital signal from the dual-clock FIFO memory and filter it to extract the valid data in the long-wave timing signal; The Roland C decoding unit is used to perform Roland C decoding on the filtered data; The RS decoding unit is used to perform RS decoding on the data decoded by the Roland C decoding unit; The CRC check unit is used to perform CRC check on the data input by the RS decoding unit to obtain 56-bit BPL valid data in the GRI pulse group and form a frame group according to the BPL timing message format; The time and pulse-second compensation unit is used to analyze and perform algorithmic processing on the received frame group data, calculate the start time of the pulse-second and perform automatic compensation; The serial port transceiver unit is used to delay a fixed time and send BPL time information TOD when the time and second pulse locking unit receives the second pulse as a trigger; The DDR storage control unit is used to store the backup of each unit data and the received BPL timing information.

4. A digital BPL long-wave timing receiving method capable of automatically compensating for highly stable output second pulses, characterized in that: The following steps are involved: S1, A / D conversion unit receives wireless digitized long-wave analog signal and converts it into a digital signal with a width of 14 bits; S2, the ADC control unit reads the 14-bit digital signal in time sequence, and the FIR filter unit filters the 14-bit digital signal; S3, determine the BPL pulse start of the filtered data and confirm the decoded data, the Loran C decoding unit performs Loran C decoding and sends it to the RS decoding unit; S4, the RS decoding unit performs RS decoding on the received data, and then sends the RS decoded data to the CRC check unit; S5, the CRC check unit performs CRC check on the data input by the RS decoding unit to obtain the 56-bit BPL valid data in the GRI pulse group, forms a frame group according to the BPL timing message format, and outputs it to the time and second pulse locking unit through the enable signal control; S6, the time and second pulse compensation unit parses and processes the received frame group data, obtains the current time information, and simultaneously obtains the millisecond, microsecond information and GRI compensation time according to the BPL timing message 2, calculates the start time of the second pulse, and automatically compensates the second pulse; S7, the asynchronous serial port transceiver unit is triggered by the time and second pulse locking unit receiving the second pulse, delays for a fixed time, and completes the sending of the BPL time information TOD; S8, DDR storage control unit stores the backup of each unit's data and the received BPL timing information, and finally the FPGA unit outputs the second pulse signal and standard time.

5. The BPL long-wave timing receiving method according to claim 4, wherein: Said S3 comprises: judging the start of the filtered BPL pulse and confirming the decoded data according to the GRI pulse group as a period; S31, confirm the starting bpl_pulse of a single pulse in the GRI pulse group through the input filtered data, high level is valid; S32, timing two adjacent pulses bpl_pulse by a state machine, and demodulating the modulation data information of the last six pulses of the eight pulses in each GRI pulse group period; S33, combining the last 6 single pulse data information in the GRI pulse group to obtain decoded data, then performing 7-bit confirmation according to the modulation pattern, and effectively sending the obtained 7-bit data to the RS decoding unit for RS decoding through the enable signal control data.

6. The BPL long-wave timing receiving method according to claim 4, wherein: The S6 includes: S61. The received frame group data is judged as a message type according to the BPL message format. Frame[55:52]=4'b0100 is a timing message. S62, the frame group data BPL message format is used to determine the message subtype. Frame[51:50]=2'b01 is BPL timing message 1, and frame[51:50]=2'b10 is BPL timing message 2. S63: If the received frame group data message subtype is timing message 1, perform year-month-day parsing based on the frame group data to obtain the current year-month-day information; S64. If the received frame group data message subtype is timing message 2, the hour, minute, second, millisecond, and microsecond information is parsed based on the frame group data to obtain the current hour, minute, second, millisecond, and microsecond information. S65, judging the transmitting station of the received BPL timing message 2-frame data, and confirming the gri time, gri_ms millisecond time, and gri_us microsecond time according to the transmitting station; S66. Extract the received BPL timing second pulse based on the currently calculated gri time, gri_ms millisecond time, gri_us microsecond time, local delay time local_delay, system delay time sys_delay, and compensated clock deviation time_usec_add. The local delay is adjusted and assigned a value based on the geographical situation of the receiving device. The local_delay includes local_delay_ms and local_delay_us, the sys_delay includes sys_delay_ms and sys_delay_us, and the time_usec_add takes a value of 10.

7. The BPL long-wave timing receiving method according to claim 6, wherein: In the S66: If the sum of the current time_msec, local_delay_ms, sys_delay_ms, and gri_ms in BPL timing message 2 is 999, and the sum of time_usec, local_delay_us, sys_delay_us, and gri_us is also 999, then a bpl_pps second pulse is output with a pulse width of 1 clock cycle of high level.

8. The BPL long-wave timing receiving method according to claim 7, wherein: Automatic compensation for the output bpl_pps pulses per second, including: (1) By judging the high level of bpl_pps, the second pulse arrival flag pps_has_arrived and the second pulse input timer pps_in_cnt are started, and the high level of pps_has_arrived is valid; (2) By judging the count value of the pulse-per-second timer pps_in_cnt, the compensation cycle counter pps_in_cycle is started; (3) Compare pps_in_cnt with the default maximum offset value MAX_OFF at the current bpl_pps high level moment, confirm the temporary compensation value max_offset_tmp, and compare pps_in_cnt with the default maximum offset value MAX_OFF at the current bpl_pps high level moment; (4) Determine the maximum compensation value max_offset at the high level of the clock 10MHz, and compare the maximum compensation value max_offset with the temporary offset value max_offset_tmp; (5) Determine the bpl_pps locking and compensation mode based on the current bpl_pps high level moment; (6) The pps_out compensation output is performed through the compensation pulse level.

9. The BPL long-wave timing receiving method according to claim 8, wherein: In step 3: If pps_in_cnt < MAX_OFF, the temporary compensation value max_offset_tmp is pps_in_cnt / 2. If (SECOND-pps_in_cnt) < MAX_OFF, the temporary compensation value max_offset_tmp is (SECOND-pps_in_cnt) / 2, where SECOND is the whole second value 1s and MAX_OFF can be 10us. In step 4: If max_offse<max_offset_tmp, the maximum compensation value is max_offset=max_offset_tmp, otherwise it remains unchanged; In step 5: If the current bpl_pps high level moment is (SECOND-2×max_offset-error)<pps_in_cnt<(SECOND-2×max_offset+error), then the delay compensation signal pps_in_cnt_cmp_0=1; if the current bpl_pps high level moment is (2×max_offset-error)<pps_in_cnt<(2×max_offset+error), then the advance compensation signal pps_in_cnt_cmp_1=1; In step 6: If the current pps_in_cnt_cmp_0=1, the starting value of pps_out_cnt is SECOND-max_offset, that is, the pps_out output second pulse is delayed by max_offset; if pps_in_cnt_cmp_1=1, the starting value of pps_out_cnt is max_offset+1, that is, the compensation is advanced by max_offset to output the pps_out second pulse, and the pps_out_cnt count is SECOND, and the second pulse pps_out is output at a high level.

10. The BPL long-wave timing receiving method according to claim 8, wherein: According to the pps_out second pulse output starting level, the second pulse state pps_state and the second pulse output high level pulse width, quantity, etc. are designed, such as output pps.

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