Method for extracting pin wiring length from packaging file

Abstract

The invention discloses a method for extracting a pin routing length from a packaging file, which comprises the following steps of: obtaining a matching group generation tool, and placing the matching group generation tool in an environment configuration folder of PCB (Printed Circuit Board) design software; calling a matching group generation tool and an automatic creation function module in sequence to generate a matching window; selecting a bus network in the matching window, setting an initial position and an end position of a signal according to requirements to serve as a signal line for matching of the matching group generation tool, and creating a matching rule; and checking the established matching rule in the rule manager, and obtaining the information of the pin routing length. According to the method, the pin routing length information in the packaging design file is read through the matching group generation tool, the matching rule with the pin routing length information is created, and the packaging physical pin attribute is mapped to the packaging attribute layer, so that PCB design software directly obtains the pin routing length information; pin wiring length information can be exported through an output function of PCB design software.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB wiring design, and more particularly to a method for extracting pin trace lengths from a package file. Background Art

[0002] In the field of PCB design, with the prevalence of high-speed digital signal transmission technologies, bus architectures such as DDR, PCIe, and USB are placing increasingly stringent demands on signal equivalence. The equivalence of bus signal lengths directly impacts the timing consistency of signals reaching each receiving end. Deviations in pin trace length (pin delay) can cause phase shifts between the clock and data signals, leading to setup or hold time violations, which in turn can cause data transmission errors and increased system bit error rates. As the initial path for signal transmission, the length variations of internal chip pin traces can contribute up to 30%-50% to overall signal delay. This is especially true in advanced packaging with process technology below 28nm, where pin traces may traverse multi-layer substrates, vias, and BGA solder joints. The parasitic effects of their three-dimensional structure further complicate delay calculations.

[0003] In traditional PCB design workflows, PCB designers typically rely on customer-provided package internal length table files (.csv) to import into PCB design files (such as .brd files) to accurately account for the actual transmission lengths of each signal during layout and routing. However, in practice, customers may only provide package design versions in .mcm format, rather than directly usable .csv files. This forces designers to extract the required pin trace length information from the .mcm file.

[0004] The .mcm file contains complete structural information inside the package, covering details such as the wafer DIE surface, BGA metal surface, and layout and wiring inside the substrate. However, this information is stored in a specific package design format and cannot be directly recognized by PCB design tools as usable pin trace length data. If the .csv file is missing, designers will have to manually search for the trace length of each pin inside the package one by one. This is not only a huge workload and inefficient, but may also lead to data extraction errors due to human omissions, affecting subsequent signal equal length design. Therefore, there is a need to use automated methods to extract key data from .mcm files and generate standardized .csv files. Summary of the Invention

[0005] In order to extract a .csv file from a .mcm file, that is, to extract a pin trace length information file from a package design file, the present invention provides a method for extracting pin trace length from a package file.

[0006] The technical solution of the present invention is as follows: A method for extracting pin trace lengths from a package file, obtaining a matching group generation tool, and placing the matching group generation tool in an environment configuration folder of a PCB design software; Trigger the predefined command of the PCB design software to obtain the attribute table in the current design database, set the selection filter in the attribute editing panel to the network object type, so that the PCB design software locks the data of the network object type and generates a bus network based on it; The matching group generation tool and the automatic creation function module are called in sequence to generate a matching window; Select the bus network in the matching window and set the starting and ending positions of the signal as required to create a matching rule for the matching group generation tool to match the signal line. View the matching rules created in the Rule Manager to obtain information about the pin trace length.

[0007] The above method of extracting the pin trace length from the package file, the content of the matching group generation tool includes Get the package file and set the default parameters; Read the package file and extract the data of pin trace length, wiring length and impedance in the package file; Based on the pin trace length data, the signals are sorted and grouped in ascending order.

[0008] Furthermore, the package file is opened through the fopen function, the gets function reads the attribute-level content of the package file line by line, and regular matching is implemented through the rexMatch function to extract the data of the pin trace length, wiring length, and impedance in the package file.

[0009] Furthermore, the matching group generation tool maintains a two-dimensional state array size[i][j], which represents the maximum number of groups of the first i signals within the tolerance threshold j. If the current signal delay difference |delay i −group min ∣≤tolerance, then inherit the previous state size[i-1][j], otherwise execute state transition size[i][j]=max(size[i-1][j],size[i-1][j-tolerance]+1), and determine whether the signal should be included in the current group by comparing size[i][j] with size[i-1][j]. This process cooperates with the axlDBCreateConstraintGroup function to directly generate PCB design constraint rules.

[0010] In the above-mentioned method of extracting pin trace length from a package file, when the PCB design software is triggered to call a predefined command, the PCB design software loads the attribute table in the current design database, retrieves all defined attributes of the object storage structure from the attribute table, creates an attribute editing panel and dynamically generates editable fields in the attribute editing panel, and creates a selection filter at the same time. When the designer sets the object type through the selection filter, the PCB design software only allows the selection of signals of the set object type and shields objects of non-set object types.

[0011] The above-mentioned method of extracting pin trace length from a package file is to call the matching group tool by inputting the file name of the matching group generation tool through the command window of the PCB design software, and then to call the automatically created function module by inputting the file name of the automatically created function module through the command window of the PCB design software.

[0012] The above-mentioned method of extracting the pin trace length from the package file, the interface of the matching window includes a network list selection box, a starting position selection box, an ending position selection box, a matching group name setting box, an error setting box, and a create button. The network list selection box is used to select the matching signal range, the starting position selection box is used to clarify the starting source of the signal, the ending position selection box is used to clarify the ending position of the signal transmission path, the matching group name setting box is used to input a custom name for the matching group or matching rule to be created, and the error setting box is used to set the allowable error range.

[0013] The above-mentioned method of extracting pin trace length from a package file, the matching rules are displayed in the form of a list, including a pin name column, a length column, a first pin trace length column that has a mapping relationship with the package physical pin attribute, and a second pin trace length column that has a mapping relationship with the package physical pin attribute.

[0014] Furthermore, if the pin name is BGA first and DIE second, then the contents of the length column are copied to the first pin long queue; if the pin name is DIE first and BGA second, then the contents of the length column are copied to the second pin long queue. The above-mentioned method of extracting pin trace length from a package file maps the pin trace length information to the package physical pin attributes of the package information, and outputs the content of the package physical pin attributes in the package information as a .csv file through the output function of the PCB design software.

[0015] The present invention according to the above scheme has the beneficial effect that the present invention uses a matching group generation tool to automatically read the pin trace length information in the package design file, and creates a list of information about each pin in the form of matching rules through predefined commands of the PCB design software, and maps the pin trace length information in the list to the package physical pin attributes at the package attribute level, so that the PCB design software can directly obtain the pin trace length information of this surface attribute, so as to export the pin trace length information, that is, a .csv file, through the output function of the PCB design software. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the interface structure of the matching window.

[0018] Figure 2 A schematic diagram of the interface structure of matching rules.

[0019] Figure 3 for Figure 2 Local magnification Figure 1 , showing the pin name column.

[0020] Figure 4 for Figure 2 Local magnification Figure 2 , which shows the first pin long queue and the second pin trace length column.

[0021] Figure 5 for Figure 2 Local magnification Figure 3 , which shows the length column. DETAILED DESCRIPTION

[0022] In order to make the technical problem 7, technical solution and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] A method for extracting pin trace lengths from a package file involves obtaining a matching group generation tool and placing it in the environment configuration folder of PCB design software. The method triggers a predefined command in the PCB design software to obtain a property table in the current design database. The selection filter in the property editing panel is set to the network object type, causing the PCB design software to lock onto the data of the network object type and generate a bus network based on this. The matching group generation tool and the automatic creation function module are then called to generate a matching window. In the matching window, the bus network is selected and the start and end positions of the signal are set as required to serve as the signal line for the matching group generation tool to match, thereby creating a matching rule. The method then views the created matching rules in the rule manager to obtain pin trace length information. The details are shown below.

[0024] Obtain the matching group generation tool and place it in the environment configuration folder of the PCB design software.

[0025] The match group generation tool is in the .il format and exists as a single file, allowing the matching function to exist independently and be called. The match group generation tool file is placed in the env folder of the PCB design software so that the match group generation tool can be called by the PCB design file. The env folder is the environment configuration folder, storing configuration information and script files related to the PCB design software's operating environment. Specifically, it contains files that define design environment parameters such as design rules, stackup structures, and electrical rule checking (ERC) rules, as well as various customized scripts and plug-in files, such as scripts for automated routing and batch modification of component properties. In the present invention, the match group generation tool is a customized script file.

[0026] The contents of the match group generator include the following.

[0027] Get the package file and set the default parameters.

[0028] The existence of the package file (a PCB package design file in the format of .mcm in the present invention) is searched according to the preset file path, and the package file is locked (the package file to be processed is locked by obtaining the name of the package file).

[0029] In this embodiment, the isFile function is used to determine whether the package file exists. If the corresponding package file does not exist, a pop-up window appears, and the axlUIConfirm function is used to set the pop-up window to prompt that the package file is not found.

[0030] Set default parameters, including the allowed delay error, match group name, etc.

[0031] Read the package file and extract the data of pin trace length (Pin Delay), wiring length (Length), and impedance (Impedance) in the package file.

[0032] In this embodiment, the package file (packaged in the PCB design file) is opened by the fopen function, the gets function reads the attribute-level content of the package file line by line, and then the rexMatch function is used to implement regular matching, thereby extracting the data of the pin trace length, wiring length, and impedance from the package file (at the same time, the signal name, corresponding pin name, connection network name, and other parameter data are also extracted).

[0033] Based on the pin trace length data, the signals are sorted and grouped in ascending order.

[0034] Specifically, delay parameters are extracted from the .mcm file using regular expressions, converted to a list of floating-point numbers, and sorted in ascending order using a quick sort algorithm (O(nlogn) time complexity). This ensures that the timing characteristics of adjacent signals naturally cluster when grouped (i.e., matching groups). A maximum delay difference (e.g., 0.05ns) is pre-set; this value determines whether signals can be grouped together, effectively establishing a time difference threshold. Starting with the first signal in the sorted list, the system traverses the group. If the delay difference between the current signal and the last signal in the group is less than or equal to the threshold, the signal remains in the current group. If the delay difference exceeds the threshold, a new group is created, with the signal as the first member. This process generates multiple matching groups, with the maximum time difference within each group not exceeding the threshold. PCB design constraints are automatically generated for each output group. Signals in the same group must maintain equal routing lengths (consistent timing characteristics), and timing differences between groups are permitted.

[0035] In this embodiment, the matching group generation tool maintains a two-dimensional state array size[i][j], which represents the maximum number of groups of the first i signals within the tolerance threshold j. Grouping is achieved through a recursive formula. If the current signal delay difference |delay i −group minIf tolerance is less than or equal to the delay difference between the current signal and the last signal in the group, the previous state size[i-1][j] is inherited. Otherwise, the state transition size[i][j]=max(size[i-1][j],size[i-1][j-tolerance]+1) is executed. Maintaining this two-dimensional state array transforms the grouping problem into a typical optimal substructure problem, similar to the dynamic programming solution to the knapsack problem. Tracing backward from the end of the sorted signal sequence, the signal's inclusion in the current group is determined by comparing size[i][j] with size[i-1][j]. This process, combined with the axlDBCreateConstraintGroup function, directly generates PCB design constraint rules (i.e., the grouping / sorting results are saved as PCB design constraint rules).

[0036] Furthermore, preferably, a strict tolerance of ±0.02ns is adopted for clock signals (such as CLK), and a loose tolerance of ±0.05ns is adopted for common signals (such as DATA), and hierarchical processing is implemented through priority queues; when differential pair signals (such as D+ / -) are detected, the intra-pair delay difference is forced to be guaranteed to be <0.01ns, and pairing lock is implemented through the setq(group (cons diffPairP(findMatchingN diffPairN))) function (according to the positive end of the differential signal, the corresponding negative end of the differential signal is found, the positive end of the differential signal and the negative end of the differential signal are combined into a unit, and this combined unit is added to the current group, thereby ensuring that the differential signals are divided into the same group, and can be processed in pairs later); the parMap function is used to perform parallel grouping processing on different banks (storage banks, referring to the independently divided storage areas inside the memory chip) of the DDR signal lines, which can be measured to improve the operating efficiency by 40% (compared to serial processing).

[0037] After editing the script file, name it and save it. The file can be used alone or placed in the environment configuration folder of the PCB design software for easy calling by the PCB design software.

[0038] Trigger the predefined command of the PCB design software, obtain the attribute table in the current design database, set the selection filter in the attribute editing panel to the network object type, so that the PCB design software locks the data of the network object type and generates a bus network based on it.

[0039] By selecting a filter, the object type of the current operation is limited to the network object type, and non-network design elements such as devices and text are automatically excluded, so that subsequent processing is only targeted at conductive paths formed by copper foil traces or vias, that is, electrical networks.

[0040] Specifically, the PCB design software extracts the attribute table from the object storage structure of the current design database and obtains a set of attributes. These attributes include not only predefined attributes but also user-defined attributes. The attribute data structure is organized as key-value pairs, with each attribute containing three basic fields: attribute name, data type, and value.

[0041] After the PCB design software obtains the attribute table in the current design database, it enters the attribute editing stage. Based on the retrieved attribute set, the PCB design software dynamically builds the attribute editing panel. During the construction process, the interface element type will automatically match the attribute data type. For Boolean attributes, the software will generate a check box; for numeric attributes, it will generate an input box with range validation function; for enumeration attributes, it will generate a drop-down selector. At the same time, the PCB design software performs validity checks on the attribute values ​​of the objects in the current design database (that is, the attribute information transmitted by the attribute set received by the PCB design software), including: (1) type matching verification, ensuring that data types such as strings, numbers, and Booleans are not mixed with each other; (2) value range verification, checking whether the attribute value is within the allowed value range; (3) association rule verification, evaluating the logical consistency between the attribute value and other network attributes.

[0042] When the designer triggers the PCB design software to call a predefined command, the PCB design software loads the property table in the current design database, retrieves all defined properties of the object storage structure from the property table, creates a property editing panel and dynamically generates editable fields in the property editing panel, displays the basic parameters of the object in the property table, such as name, topology structure and user-defined properties, etc., and creates a selection filter (that is, the check box, input box, drop-down selector, etc. mentioned above).

[0043] When designers set the net object type using a selection filter, the PCB design software only allows selection of electrical nets, blocking the selection of non-net objects. Simultaneously, the PCB design software performs real-time data validation to check whether the filter inputs comply with design rules. It also updates the attribute data of the object storage structure in memory, marking the corresponding PCB design file as modified. This ultimately generates a candidate net list containing all net signals with attributes that are net object types.

[0044] The PCB design software integrates and constructs these selected network signals to form a new bus network (that is, a Bus is created. In the property editing panel, there is a Bus name input box where you can name the created Bus. In this example, the Bus name is 0224). This bus network is like a "data channel aggregate," combining multiple related network signals to facilitate subsequent design work and more efficiently manage and process these network signals.

[0045] The matching group generation tool and the automatic creation function module are called successively to generate a matching window.

[0046] In the command window of the PCB design software, enter the file name of the match group generation tool to call the match group tool. Then, in the command window of the PCB design software, enter the file name of the automatic creation function module (i.e., auto_create_matchgroup) to call the automatic creation function module.

[0047] The automatic creation function module is a predefined function module of the PCB design software. It is a function module used to automatically process circuit design data. Its main function is to group and manage signal lines and networks according to specific rules.

[0048] Invoking the Match Group Generator tool sets up the foundation for subsequent operations. By importing the specified Match Group Generator script file into the PCB design software's runtime environment through the PCB design software's command window, the Match Group Generator code and functionality are integrated into the software's runtime environment, providing the necessary support for subsequent operations.

[0049] Once the command to invoke the match group generation tool is successfully executed and the script file for invoking the tool is loaded into the PCB design software environment, the PCB design software will be able to automatically create match groups. At this point, entering a second command to invoke the automatic creation module is equivalent to issuing an execution command to the PCB design software. This command triggers the previously loaded script file and initiates the execution of the code logic within it. The PCB design software will analyze and process the networks in the PCB design according to the rules and algorithms pre-set in the script file, automatically selecting qualified networks and grouping them into match groups. After the match groups are created, the software will pop up a matching window.

[0050] like Figure 1As shown, the interface of the matching window includes a network list selection box, a starting position selection box, an ending position selection box, a matching group name setting box, an error setting box, a create button, an exit button, a refresh button, and a help button. The network list selection box lists all the networks in the current PCB design that can be used to create matching groups. These are not the networks that have been established in the PCB design file, but the networks established during the PCB design process. In the present invention, they specifically refer to the bus network (Bus) created previously. The starting position selection box is used to clarify the starting source of the signal and provide a starting reference point for signal transmission for subsequent matching group creation. In PCB design, signals usually start transmission from a specific component pin or network node. Users can select the starting position in this selection box. The ending position selection box is used to clarify the ending position of the signal transmission path. Together with the starting position selection box, it completely defines the signal transmission path. After determining the end position, the PCB design software can create a match group (effectively providing a range for the match group generation tool to match) based on the signal characteristics between the starting position (not necessarily a point, but can be a surface) and the ending position (not necessarily a point, but can be a surface). This ensures that the signal transmission path within the match group meets design requirements and improves the stability and accuracy of signal transmission. The Match Group Name setting box is used to enter a custom name for the match group to be created. The Tolerance setting box is used to set the allowable tolerance range. Reasonable tolerance settings can automatically group signals with similar parameters, ensuring that the grouping is accurate and reducing manual intervention. The Create button triggers the creation of the match group, the Exit button closes the window, the Refresh button updates all information within the window and clears the contents of the Match Group Name setting box and the Tolerance setting box. The Help button displays the instructions provided with the match group generation tool.

[0051] In the matching window, select the bus network and set the starting and ending positions of the signal as required to create matching rules for the matching group generation tool to match the signal line.

[0052] A bus network is a collection of network signals that have been screened and integrated. These signals usually undertake important functions such as data transmission. Selecting a created bus network allows the software to focus on the core signals that need to be processed, avoiding the inclusion of irrelevant signals in the processing range, thereby improving processing efficiency and reducing unnecessary calculations and analysis. Set the starting and ending positions of the signal to determine the scope and direction of information extraction. In the present invention, the starting position is set to the BGA surface, and the ending position is set to the DIE surface, that is, a signal transmission line is set from the BGA surface to the DIE surface. BGA is an important interface for connecting the chip to the external circuit, and DIE is the core part of the chip that performs specific functions. The quality of the signal connection between the two directly affects the performance of the entire circuit system. At the same time, in the present invention, the signal error is set to 50 mils. Click the Create button to complete the setting.

[0053] At this point, the call and application of the matching group generation tool is complete, automatically creating a matching rule (the aforementioned PCB design constraint rule, which can also be described as the grouping of signal groups and the ordering of signals). Specifically, based on the selected bus network and the determined signal transmission line direction from BGA to DIE, signals with similar characteristics or sharing the same transmission path are grouped and saved in the PCB design constraint rule.

[0054] View the matching rules created in the Rule Manager to obtain information about the pin trace length.

[0055] The matching group generation tool has called out and generated PCB design constraint rules for all signals that have similar characteristics or are in the same transmission path based on the selected bus network and the determined signal transmission line direction from BGA to DIE. Therefore, the relevant pin trace length information can be obtained through the rule manager of the PCB design software.

[0056] Specifically, find the previously created matching rule in the Relative Propagation Delay column of the Rule Manager of the PCB design software (search by name, where the name is the matching group name entered in the Match Group Name setting box, and is also the name of the matching rule generated by calling the Match Group Generation Tool).

[0057] The matching rules are displayed as a list, including a pin name column (Name column), a length column (Length column), a first pin trace length column (Pin 1 column) that maps to the physical pin attributes of the package, and a second pin trace length column (Pin 2 column) that maps to the physical pin attributes of the package.

[0058] The matching rules here are displayed in the form of a list. Figure 2-Figure 5As shown, one column in the list is named Name, which is the pin name. The pin name here contains the starting position (point), end position (point) and signal name. The other column is named Length, which contains the pin trace length.

[0059] In addition, the matching rules include inherent columns that are automatically generated when processing pins. When processing pin information in the PCB design software, a fixed column is automatically generated that maps to the physical pin attributes of the package. Because the matching rules are created by the matching group generation tool rather than automatically generated by the PCB design file, the fixed column that maps to the physical pin attributes of the package is empty when the matching rules are generated. Therefore, the data in the length column needs to be copied to the first pin long queue or the second pin trace length column.

[0060] Specifically, the Length column contains the trace length data corresponding to the pin name. The matching rules include the first and second pin trace length columns, which are mapped to the package's physical pin attributes. (Both are automatically generated fixed columns, a feature inherent in the PCB design software.) When the matching rules are generated, the values ​​in the first and second pin trace length columns are empty. Therefore, you need to manually copy the trace length data in the Length column to the first or second pin trace length columns. This will then assign the same values ​​to the package's physical pin attributes due to the mapping relationship (i.e., the contents in the first and second pin trace length columns will also become the package's physical pin attributes), effectively modifying the package's physical pin attributes. During this operation, if the pin name is BGA first and DIE second, the Length column contents are copied to the first pin long column. If the pin name is DIE first and BGA second, the Length column contents are copied to the second pin long column. (This involves a vector direction issue: since the length data is displayed in the package's physical pin attributes, the direction must be from BGA to DIE.)

[0061] After completing the copying of the pin trace length data, the package physical pin properties displayed on the package information interface will contain the pin trace length data content. At this time, you can use the output function of the PCB design software to select the file to output the pin trace length and output the content of the package physical pin properties on the package information interface as a .csv file.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for extracting pin trace length from a package file, characterized in that: Obtain the matching group generation tool and place it in the environment configuration folder of the PCB design software; Trigger the predefined command of the PCB design software, obtain the attribute table in the current design database, set the selection filter in the attribute editing panel to the network object type, so that the PCB design software locks the data of the network object type and generates a bus network based on it; The matching group generation tool and the automatic creation function module are called in sequence to generate a matching window; Select the bus network in the matching window and set the starting and ending positions of the signal as required to create a matching rule for the matching group generation tool to match the signal line. View the matching rules created in the Rule Manager to obtain information about the pin trace length.

2. The method for extracting pin trace length from a package file according to claim 1, characterized in that: The contents of the match group generator include Get the package file and set the default parameters; Read the package file and extract the data of pin trace length, wiring length and impedance in the package file; Based on the pin trace length data, the signals are sorted and grouped in ascending order.

3. The method for extracting the lead trace length from the package file according to claim 2, characterized in that: The package file is opened through the fopen function, the gets function reads the attribute-level content of the package file line by line, and the rexMatch function is used to implement regular matching, thereby extracting the data of pin trace length, wiring length, and impedance from the package file.

4. The method for extracting the lead trace length from the package file according to claim 2, wherein: The matching group generation tool maintains a two-dimensional state array size[i][j], which represents the maximum number of groups of the first i signals within the tolerance threshold j. If the current signal delay difference |delayi−groupmin|≤tolerance, the previous state size[i-1][j] is inherited. Otherwise, the state transition size[i][j]=max(size[i-1][j],size[i-1][j-tolerance]+1) is executed. By comparing size[i][j] with size[i-1][j], it is determined whether the signal should be included in the current group. This process is combined with the axlDBCreateConstraintGroup function to directly generate PCB design constraint rules.

5. The method for extracting pin trace length from a package file according to claim 1, characterized in that: When the PCB design software is triggered to call a predefined command, the PCB design software loads the attribute table in the current design database, retrieves all defined attributes of the object storage structure from the attribute table, creates an attribute editing panel and dynamically generates editable fields in the attribute editing panel, and creates a selection filter at the same time. When the designer sets the object type through the selection filter, the PCB design software only allows the selection of signals of the set object type and blocks objects of non-set object types.

6. The method for extracting pin trace length from a package file according to claim 1, characterized in that: Through the command window of the PCB design software, enter the file name of the matching group generation tool to call the matching group tool, and then through the command window of the PCB design software, enter the file name of the automatic creation function module to call the automatic creation function module.

7. The method for extracting pin trace length from a package file according to claim 1, characterized in that: The interface of the matching window includes a network list selection box, a starting position selection box, an ending position selection box, a matching group name setting box, an error setting box, and a create button. The network list selection box is used to select the matching signal range, the starting position selection box is used to clarify the starting source of the signal, the ending position selection box is used to clarify the ending position of the signal transmission path, the matching group name setting box is used to enter a custom name for the matching group or matching rule to be created, and the error setting box is used to set the allowable error range.

8. The method for extracting pin trace length from a package file according to claim 1, characterized in that: The matching rules are displayed in a list, including a pin name column, a length column, a first pin trace length column that is mapped to the package physical pin attributes, and a second pin trace length column that is mapped to the package physical pin attributes.

9. The method for extracting pin trace length from a package file according to claim 8, characterized in that: If the pin name is BGA first and DIE second, then copy the contents of the length column to the first pin long queue. If the pin name is DIE first and BGA second, then copy the contents of the length column to the second pin long queue.

10. The method for extracting pin trace length from a package file according to claim 1, characterized in that: The pin trace length information is transferred to the package physical pin attributes of the package information through mapping. The content of the package physical pin attributes in the package information is output as a .csv file through the output function of the PCB design software.

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