Pixel circuit and display panel

Abstract

The embodiment of the invention discloses a pixel circuit and a display panel. The pixel circuit comprises a driving module, a data writing module, an initialization module and a compensation module, the initialization module is connected with the first end or the second end of the driving module and is used for enabling initialization voltage to be transmitted to the control end of the driving module at least through the compensation module in an initialization stage; the data write-in module is connected with a first end of the driving module, the compensation module is connected between a second end and a control end of the driving module, and the data write-in module is used for transmitting data voltage to the control end of the driving module through the driving module and the compensation module in a data write-in stage; the light-emitting module is connected with the second end of the driving module. The driving module is used for driving the light-emitting module to emit light in the light-emitting stage. According to the scheme, on the basis that key node reset and threshold voltage compensation of the driving module are achieved, the pixel circuit structure is simplified, high PPI can be achieved, and the display effect cannot be reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] With the rapid development of display technology, the display requirements for display panels are becoming increasingly higher.

[0003] At present, the array driving scheme in the display panel is relatively complex, the number of transistors in the pixel is large, and the array wiring is dense, which is not conducive to improving the PPI. Summary of the Invention

[0004] Embodiments of the present invention provide a pixel circuit and a display panel to simplify the pixel circuit and improve PPI.

[0005] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a driving module, a data writing module, an initialization module, a compensation module and a light emitting module;

[0006] The initialization module is used to transmit the initialization voltage to the control end of the driving module via the compensation module during the initialization phase;

[0007] The data writing module is connected to the first end of the driving module, and the compensation module is connected between the second end of the driving module and the control end. The data writing module is used to transmit the data voltage to the control end of the driving module through the driving module and the compensation module during the data writing phase;

[0008] The light emitting module is connected to the second end of the driving module, and the driving module is used to drive the light emitting module to emit light in the light emitting phase.

[0009] Optionally, the initialization module is connected between the first power line and the first end of the driving module, the data writing module is connected between the data line and the first end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line;

[0010] The first power line is configured to transmit an initialization voltage during an initialization phase and transmit a first power voltage at least during a light-emitting phase;

[0011] Optionally, the initialization voltage is less than the first power supply voltage;

[0012] Optionally, the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light emitting phase;

[0013] Optionally, the second power supply voltage of the first level is greater than the second power supply voltage of the second level;

[0014] Optionally, within the same display cycle, the initialization phase precedes the data writing phase.

[0015] Optionally, the control end of the driving module includes a first control end and a second control end, the compensation module is connected to the first control end of the driving module, the second control end of the driving module is connected to the data line, and the driving module is further configured to adjust its own threshold voltage according to the voltage of the second control end during the initialization phase;

[0016] Optionally, the data line is configured to transmit a first voltage during an initialization phase and to transmit a data voltage during a data writing phase;

[0017] Optionally, the data line is further configured to transmit a second voltage during the light emitting phase;

[0018] Optionally, the second voltage is greater than the first voltage;

[0019] Optionally, the pixel circuit further includes a storage module connected between the third power line and the first control terminal of the driving module;

[0020] Optionally, the driving module includes a first transistor, the data writing module includes a second transistor, the compensation module includes a third transistor, the initialization module includes a fourth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode;

[0021] a gate of the fourth transistor connected to the third control signal line, a first electrode of the fourth transistor connected to the first power line, a second electrode of the fourth transistor connected to the first electrode of the first transistor, a second electrode of the first transistor connected to the first electrode of the light-emitting diode, a second electrode of the light-emitting diode connected to the second power line, a gate of the second transistor connected to the second control signal line, a first electrode of the second transistor connected to the data line, a second electrode of the second transistor connected to the first electrode of the first transistor, a gate of the third transistor connected to the first control signal line, a first electrode of the third transistor connected to the second electrode of the first transistor, a second electrode of the third transistor connected to the first gate of the first transistor, a first electrode of the storage capacitor connected to the third power line, and a second electrode of the storage capacitor connected to the first gate of the first transistor;

[0022] Optionally, the second gate of the first transistor is connected to the data line, or the second gate of the first transistor is connected to the first electrode of the first transistor;

[0023] Optionally, at least one of the second transistor, the third transistor and the fourth transistor is a metal oxide transistor.

[0024] Optionally, the control end of the driving module includes a first control end and a second control end, the compensation module is connected to the first control end of the driving module, and the second control end of the driving module is connected to the first end of the driving module, and the driving module is further configured to adjust its own threshold voltage according to the voltage of the second control end during an initialization phase;

[0025] Optionally, the data line is configured to transmit a second voltage during an initialization phase and to transmit a data voltage during a data writing phase;

[0026] Optionally, the data line is further configured to transmit a second voltage during the light emitting phase;

[0027] Optionally, the pixel circuit further includes a storage module, and the storage module is connected between the third power line and the first control terminal of the driving module.

[0028] Optionally, the data writing module is connected between the data line and the first end of the driving module, the initialization module is connected between the initialization signal line and the second end of the driving module, the first end of the light emitting module is connected to the second end of the driving module, and the second end of the light emitting module is connected to the second power line;

[0029] Optionally, the data line is configured to transmit a data voltage in a data writing phase, and to transmit a first power voltage in an initialization phase and a light emitting phase;

[0030] Optionally, the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light emitting phase;

[0031] Optionally, the second power supply voltage of the first level is greater than the second power supply voltage of the second level;

[0032] Optionally, the pixel circuit further includes a storage module connected between the third power line and the first control terminal of the driving module;

[0033] Optionally, the driving module includes a first transistor, the data writing module includes a second transistor, the compensation module includes a third transistor, the initialization module includes a fourth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode;

[0034] The gate of the second transistor is connected to the third control signal line, the first electrode of the second transistor is connected to the data line, the second electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first electrode of the light-emitting diode, the second electrode of the light-emitting diode is connected to the second power line, the gate of the third transistor is connected to the first control signal line, the first electrode of the third transistor is connected to the second electrode of the first transistor, the second electrode of the third transistor is connected to the gate of the first transistor, the gate of the fourth transistor is connected to the second control signal line, the first electrode of the fourth transistor is connected to the initialization signal line, and the second electrode of the fourth transistor is connected to the second electrode of the first transistor;

[0035] Optionally, the third transistor and / or the fourth transistor is a metal oxide transistor;

[0036] Optionally, the initialization phase includes a first initialization phase and a second initialization phase. In the same display cycle, the first initialization phase is located before the data writing phase, and the second initialization phase is located between the data writing phase and the light emitting phase.

[0037] Optionally, the initialization voltage transmitted on the initialization signal line is adjustable.

[0038] According to another aspect of the present invention, a display panel is provided, comprising the pixel circuit provided by any embodiment of the present invention.

[0039] Optionally, the initialization module is connected between the first power line and the first end of the driving module, the data writing module is connected between the data line and the first end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line;

[0040] The display panel further includes a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of third control signal lines, each row of pixel circuits being connected to one first control signal line, one second control signal line, and one third control signal line, the plurality of first control signal lines being used to simultaneously transmit the effective level of the first control signal to the control terminals of the compensation modules in all rows of pixel circuits during an initialization phase, and to transmit the effective level of the first control signal to the control terminals of the compensation modules in the pixel circuits row by row during a data writing phase; the plurality of second control signal lines being used to transmit the effective level of the second control signal to the control terminals of the data writing modules in the pixel circuits row by row during the data writing phase; and the plurality of third control signal lines being used to simultaneously transmit the effective level of the third control signal to all rows of pixel circuits during the initialization phase and the light-emitting phase;

[0041] Optionally, the first power line is configured to transmit an initialization voltage during an initialization phase and to transmit the first power voltage at least during a light-emitting phase, and the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light-emitting phase; wherein the initialization voltage is lower than the first power voltage, and the first-level second power voltage is higher than the second-level second power voltage;

[0042] Optionally, the data line is configured to transmit a first voltage or a second voltage in an initialization phase, and to transmit a data voltage in a data writing phase; the second voltage is greater than the first voltage;

[0043] Optionally, the duration of the effective level of the first control signal transmitted on the same first control signal line in the initialization phase is longer than the duration in the data writing phase;

[0044] Optionally, in the data writing phase, in the same row of pixel circuits, the effective level of the first control signal and the effective level of the second control signal overlap for at least part of the time.

[0045] Optionally, the data writing module is connected between the data line and the first end of the driving module, the initialization module is connected between the initialization signal line and the second end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line; the initialization phase includes a first initialization phase and a second initialization phase;

[0046] The display panel further includes a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of third control signal lines. Each row of pixel circuits is connected to a first control signal line, a second control signal line, and a third control signal line. The plurality of first control signal lines are used to simultaneously transmit the effective level of the first control signal to the control end of the compensation module in all rows of pixel circuits in a first initialization phase, and to transmit the effective level of the first control signal to the control end of the compensation module in the pixel circuit row by row in a data writing phase; the plurality of second control signal lines are used to simultaneously transmit the effective level of the second control signal to the control end of the initialization module in all rows of pixel circuits in the first initialization phase, and to transmit the effective level of the second control signal to the pixel circuit row by row or to the control end of the initialization module in the row of pixel circuits at the same time in a second initialization phase; the plurality of third control signal lines are used to transmit the effective level of the third control signal to the control end of the data writing module in the pixel circuit row by row in the data writing phase, and to simultaneously transmit the effective level of the third control signal to the control end of the data writing module in all rows of pixel circuits in a light-emitting phase;

[0047] Optionally, the data line is configured to transmit a data voltage in a data writing phase, and to transmit a first power voltage in an initialization phase and a light emitting phase;

[0048] Optionally, the second power line is configured to transmit a first-level second power voltage during the initialization phase and the data writing phase, and to transmit a second-level second power voltage during the light-emitting phase; the first-level second power voltage is greater than the second-level second power voltage.

[0049] Optionally, when the plurality of second control signal lines transmit the effective level of the second control signal to the control terminal of the initialization module in the pixel circuit row by row in the second initialization phase, the effective level of the first control signal and the effective level of the second control signal both include a first-level pulse and a second-level pulse, the first-level pulse of the first control signal is in the first initialization phase, the second-level pulse of the first control signal is in the data writing phase, the first-level pulse of the second control signal is in the first initialization phase, and the second-level pulse of the second control signal is in the second initialization phase;

[0050] Optionally, in the same row of pixel circuits, the first level pulse of the first control signal coincides with the first level pulse of the second control signal, and the end time of the second level pulse of the first control signal is before the start time of the second level pulse of the second control signal;

[0051] Optionally, the effective level of the third control signal includes a first level pulse and a second level pulse, the first level pulse of the third control signal is in the data writing stage, the second level pulse of the third control signal is in the light emitting stage, and for the same row of pixel circuits, the end time of the first level pulse of the third control signal is after the end time of the second level pulse of the first control signal and before the start time of the second level pulse of the second control signal.

[0052] Optionally, when the plurality of second control signal lines simultaneously transmit the effective level of the second control signal to the control end of the initialization module in all rows of pixel circuits in the second initialization phase, the effective level of the first control signal and the effective level of the second control signal both include a first-level pulse and a second-level pulse, the first-level pulse of the first control signal is in the first initialization phase, the second-level pulse of the first control signal is in the data writing phase, the first-level pulse of the second control signal is in the first initialization phase, and the second-level pulse of the second control signal is in the second initialization phase; the effective level of the third control signal includes a first-level pulse and a second-level pulse, the first-level pulse of the third control signal is in the data writing phase, and the second-level pulse of the third control signal is in the light-emitting phase;

[0053] Optionally, in the same row of pixel circuits, the first level pulse of the first control signal coincides with the first level pulse of the second control signal;

[0054] Optionally, the start time of the second level pulse of the second control signal is located after the end time of the first level pulse of the third control signal of the last row of pixel circuits, and the end time of the second level pulse of the second control signal is located before the start time of the second level pulse of the third control signal;

[0055] Optionally, in the same row of pixel circuits, the duration of the first level pulse of the third control signal overlaps the duration of the second level pulse of the first control signal.

[0056] The technical solution provided by the embodiment of the present invention sets an initialization module to initialize the control end of the driving module through the compensation module, and the data writing module realizes data writing and threshold voltage compensation through the compensation module. It can simplify the pixel circuit structure on the basis of realizing key node reset and threshold voltage compensation of the driving module, which is conducive to achieving high PPI without reducing the display effect.

[0057] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0060] Figure 2 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0061] Figure 3 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0062] Figure 4 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0063] Figure 5 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0064] Figure 6 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0065] Figure 7A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Figure 8 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0067] Figure 9 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0068] Figure 10 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0069] Figure 11 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0070] Figure 12 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0071] Figure 13 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0072] Figure 14 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0073] Figure 15 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0075] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0076] Figure 1 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 1 The pixel circuit provided in this embodiment includes: a driving module 110, a data writing module 120, an initialization module 130 and a compensation module 140; the initialization module 130 is connected to the first end or the second end of the driving module 110, and the initialization module 130 is used to transmit the initialization voltage Vref to the control end of the driving module 110 at least via the compensation module 140 during the initialization stage; the data writing module 120 is connected to the first end of the driving module 110, and the compensation module 140 is connected between the second end and the control end of the driving module 110, and the data writing module 120 is used to transmit the data voltage Vdata to the control end of the driving module 110 via the driving module 120 and the compensation module 140 during the data writing stage; the light-emitting module 150 is connected to the second end of the driving module 110, and the driving module 110 is used to drive the light-emitting module 150 to emit light during the light-emitting stage.

[0077] During the initialization phase, the compensation module 140 is turned on, short-circuiting the control terminal and the second terminal of the driver module 110. The initialization module 130 transmits the initialization voltage Vref to the first terminal of the driver module 110, and then transmits it to the second terminal of the driver module 110 via the driver module 110, thereby initializing the potential of the control terminal of the driver module 110. During the data writing phase, the data writing module 120 transmits the data voltage Vdata to the control terminal of the driver module 110 via the driver module 110 and the compensation module 140, thereby implementing data writing and threshold voltage compensation. During the light-emitting phase, the initialization module 130 or the data writing module 120 can be controlled to be turned on, applying a power supply voltage to the first terminal of the driver module 110 (here, the initialization voltage Vref or the data voltage Vdata needs to be set to an adjustable voltage to output the power supply voltage), thereby driving the light-emitting module 150 to emit light.

[0078] The technical solution provided by the embodiment of the present invention sets an initialization module 130 to initialize the control end of the driving module 110 through the compensation module 140, and the data writing module 120 realizes data writing and threshold voltage compensation through the compensation module 140. It can simplify the pixel circuit structure on the basis of realizing key node reset and threshold voltage compensation of the driving module 110, which is conducive to achieving high PPI without reducing the display effect.

[0079] In an optional implementation provided by an embodiment of the present invention, the initialization module 130 is connected between the first power line and the first end of the driving module 110, the data writing module 120 is connected between the data line and the first end of the driving module 110, and the light-emitting module 150 is connected between the second end of the driving module 110 and the second power line, wherein the first power line and the second power line both transmit AC signals, that is, the voltage transmitted on the first power line and the second power line is a variable voltage. Figure 2 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 2 Based on the above embodiment, optionally, the first power line L1 is configured to transmit an initialization voltage Vref during the initialization phase and transmit a first power voltage VDD at least during the light-emitting phase, wherein the initialization voltage Vref is lower than the first power voltage VDD.

[0080] The second power line L2 is configured to transmit a first-level second power voltage VSSH during the initialization phase and the data writing phase, and to transmit a second-level second power voltage VSSL during the light-emitting phase, wherein the first-level second power voltage VSSH is greater than the second-level second power voltage VSSL.

[0081] Optionally, a storage module 160 is further included, which is connected between the third power line and the first control terminal of the driving module 110 and is used to store the voltage of the first control terminal of the driving module 110. The third power line is used to transmit the reference voltage V0.

[0082] Figure 3 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, specifically Figure 2 The pixel circuit shown is a structural diagram of the device, refer to Figure 3The driving module 110 includes a first transistor Q1, the data writing module 120 includes a second transistor Q2, the compensation module 140 includes a third transistor Q3, the initialization module 130 includes a fourth transistor Q4, the storage module 160 includes a storage capacitor C0, and the light-emitting module 150 includes a light-emitting diode D1. The gate of the fourth transistor Q4 is connected to a third control signal line and is configured to be turned on or off in response to a third control signal EM transmitted on the third control signal line. A first electrode of the fourth transistor Q4 is connected to a first power line L1, a second electrode of the fourth transistor Q4 is connected to a first electrode of the first transistor Q1, a second electrode of the first transistor Q1 is connected to a first electrode of the light-emitting diode D1, and a second electrode of the light-emitting diode D1 is connected to a second power line L2. The gate of the second transistor Q2 is connected to a second control signal line and is configured to be turned on or off in response to a second control signal S2 transmitted on the second control signal line. The first electrode of the second transistor Q2 is connected to a data line DL, and the second electrode of the second transistor Q2 is connected to the first electrode of the first transistor Q1. The gate of the third transistor Q3 is connected to the first control signal line, and is used to turn on or off in response to the first control signal S1 transmitted on the first control signal line. The first electrode of the third transistor Q3 is connected to the second electrode of the first transistor Q1, and the second electrode of the third transistor Q3 is connected to the first gate of the first transistor Q1. The first electrode of the storage capacitor C0 is connected to the third power line, and the second electrode of the storage capacitor C0 is connected to the first gate of the first transistor Q1.

[0083] Figure 4 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention can be used to drive Figure 3 The pixel circuit shown, refer to Figure 3 and Figure 4 The operation process of the pixel circuit provided in this embodiment includes an initialization phase T1, a data writing phase T2, and a light emitting phase T3. In the same display cycle, the initialization phase T1 is located before the data writing phase T2. Taking all transistors as P-type transistors as an example, the operation process of the pixel circuit provided in this embodiment is as follows:

[0084] During the initialization phase T1, the first power line L1 transmits an initialization voltage Vref, and the second power line L2 transmits a second power voltage VSSH at a first level to ensure that the light-emitting module 150 does not emit light. During the initialization phase T1, the first control signal S1 is at a low level, the second control signal S2 is at a high level, and the third control signal EM is at a low level. Therefore, the third transistor Q3 and the fourth transistor Q4 are turned on, and the initialization voltage Vref is transmitted to the first electrode of the first transistor Q1 via the fourth transistor Q4, causing the first electrode of the first transistor Q1 to be at a low potential. At this time, the second electrode of the first transistor Q1 serves as the source. Since the third transistor Q3 is turned on, the first gate and the second electrode of the first transistor Q1 are short-circuited, that is, the gate-source voltage difference VGS of the first transistor Q1 is 0V. Therefore, under the action of the initialization voltage Vref, the first electrode of the first transistor Q1 leaks electricity to its second electrode, thereby initializing the first gate of the first transistor Q1.

[0085] The initialization effect can be ensured by lengthening the time of the initialization stage T1.

[0086] During the data writing phase T2, the first power line L1 transmits the first power supply voltage VDD, the second power line L2 transmits the second power supply voltage VSSH of the first level, the first control signal S1 is at a low level, the second control signal S2 is at a low level, and the third control signal EM is at a high level. Therefore, the second transistor Q2 and the third transistor Q3 are turned on. The data voltage Vdata on the data line DL is transmitted to the first gate of the first transistor Q1 via the second transistor Q2, the first transistor Q1, and the third transistor Q3. When the voltage at the first gate of the first transistor Q1 reaches Vdata + Vth1, the first transistor Q1 is turned off, thus achieving data writing and threshold voltage compensation. Vth1 is the threshold voltage of the first transistor Q1.

[0087] During the light-emitting phase T3, the first power line L1 transmits the first power supply voltage VDD, the second power line L2 transmits the second power supply voltage VSSL of the second level, the first control signal S1 is at a high level, the second control signal S2 is at a high level, and the third control signal EM is at a low level. Therefore, the fourth transistor Q4 is turned on. At this time, the first electrode of the first transistor Q1 serves as the source. Under the action of the voltages at its first electrode and first gate, the first transistor Q1 generates a driving current to drive the light-emitting diode D1 to emit light.

[0088] Compared with the existing technology, the technical solution provided in this embodiment, combined with the driving timing, can achieve the effects of initializing key nodes (such as the first gate of the first transistor Q1 and the first pole of the light-emitting diode D1), as well as data writing and threshold voltage compensation through 4 transistors, which greatly simplifies the structure of the pixel circuit, thereby making the wiring structure inside the pixel simpler, which is beneficial to improving PPI and improving display quality.

[0089] Figure 5 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 5 Based on the above embodiments, optionally, the control end of the driving module 110 includes a first control end and a second control end, the compensation module 140 is connected to the first control end of the driving module 110, and the second control end of the driving module 110 is connected to the first end of the driving module 110. The driving module 110 is further used to adjust its own threshold voltage according to the voltage of the second control end during the initialization stage.

[0090] Optionally, the data writing module 120 is in an off state during the initialization phase, and the data line DL is configured to transmit the second voltage during the initialization phase and transmit the data voltage Vdata during the data writing phase.

[0091] in, Figure 4 The driving timing shown is also applicable to Figure 5 The pixel circuit shown, Figure 5 The pixel circuit shown is Figure 3 The different stages of the working process of the pixel circuit shown are the initialization stage T1, Figure 5In the illustrated pixel circuit, during initialization phase T1, an initialization voltage Vref is transmitted on the first power line L1, and a second power supply voltage VSSH of a first level is transmitted on the second power line L2 to ensure that the light-emitting module 150 does not emit light. During initialization phase T1, the first control signal S1 is at a low level, the second control signal S2 is at a high level, and the third control signal EM is at a low level. Therefore, the fourth transistor Q4 is turned on, and the initialization voltage Vref is transmitted to the first electrode and the second gate of the first transistor Q1 via the fourth transistor Q4, causing the first electrode of the first transistor Q1 to be at a low potential. At this time, the second electrode of the first transistor Q1 serves as the source. In addition, the third transistor Q3 is turned on, shorting the first gate and the second electrode of the first transistor Q1, i.e., the gate-source voltage difference VGS of the first transistor Q1 = 0V. Under the control of the initialization voltage Vref on the second gate of the first transistor Q1, the threshold voltage VTH1 of the first transistor Q1 is forward biased, making the threshold voltage VTH1 of the first transistor Q1 greater than 0, thereby enabling the first transistor Q1 (the first transistor Q1 is a P-type transistor) to be turned on when VGS of the first transistor Q1 = 0V. The initialization voltage Vref is transmitted to the first gate of the first transistor Q1 via the first transistor Q1 and the third transistor Q3 , thereby initializing the first gate of the first transistor Q1 .

[0092] Figure 6 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, Figure 7 Another driving timing diagram of a pixel circuit provided by an embodiment of the present invention is applicable to Figure 6 The pixel circuit shown, refer to Figure 6 and Figure 7 Based on the above embodiments, optionally, the control end of the driving module 110 includes a first control end and a second control end, the compensation module 140 is connected to the first control end of the driving module 110, and the second control end of the driving module 110 is connected to the data line DL. The driving module 110 is also used to adjust its own threshold voltage according to the voltage of the second control end during the initialization stage.

[0093] The data line DL is configured to transmit a first voltage V1 during an initialization phase and transmit a data voltage Vdata during a data writing phase.

[0094] Figure 6 The pixel circuit shown is Figure 3 The different stages of the working process of the pixel circuit shown are the initialization stage T1, Figure 6In the illustrated pixel circuit, during initialization phase T1, the first power line L1 transmits an initialization voltage Vref, and the second power line L2 transmits a second power voltage VSSH of a first level to ensure that the light-emitting module 150 does not emit light. The data line DL transmits a first voltage V1, which is at a low level. During initialization phase T1, the first control signal S1 is at a low level, the second control signal S2 is at a high level, and the third control signal EM is at a low level. Therefore, the fourth transistor Q4 is turned on, and the initialization voltage Vref is transmitted to the first electrode and the second gate of the first transistor Q1 via the fourth transistor Q4, causing the first electrode of the first transistor Q1 to be at a low potential. At this time, the second electrode of the first transistor Q1 serves as the source. Furthermore, the third transistor Q3 is turned on, short-circuiting the first gate and the second electrode of the first transistor Q1, i.e., the gate-source voltage difference VGS of the first transistor Q1 equals 0V. Under the regulation of the first voltage V1 on the second gate of the first transistor Q1, the threshold voltage VTH1 of the first transistor Q1 is forward biased, so that the threshold voltage VTH1 of the first transistor Q1 is greater than 0, thereby turning on the first transistor Q1 (the first transistor Q1 is a P-type transistor) when VGS of the first transistor Q1 is 0V. The initialization voltage Vref is transmitted to the first gate of the first transistor Q1 through the first transistor Q1 and the third transistor Q3, thereby initializing the first gate of the first transistor Q1.

[0095] Optionally, in each of the above embodiments, at least one of the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 is a metal oxide transistor, such as an IGZO transistor, which is beneficial for reducing leakage current. For example, the second transistor Q2 and the third transistor Q3 are metal oxide transistors, or the second transistor Q2 and the fourth transistor Q4 are metal oxide transistors, or the third transistor Q3 and the fourth transistor Q4 are metal oxide transistors, or the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all metal oxide transistors.

[0096] In this embodiment, the semiconductor layer of the P-type transistor is usually a polysilicon layer, and the semiconductor layer of the metal oxide transistor is usually a metal oxide layer. In the layout design, the polysilicon layer and the metal oxide layer are arranged in different layers. Therefore, the film layers of different types of transistors can be stacked, which can further reduce the occupied area of ​​the pixel circuit and further improve the PPI.

[0097] Figure 8 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 8In another optional implementation provided by an embodiment of the present invention, the data writing module 120 is connected between the data line DL and the first end of the driving module 110, the initialization module 130 is connected between the initialization signal line and the second end of the driving module 110, the first end of the light-emitting module 150 is connected to the second end of the driving module 110, and the second end of the light-emitting module 150 is connected to the second power line L2.

[0098] The data line DL is configured to transmit a data voltage Vdata during a data writing phase, and to transmit a first power supply voltage VDD during an initialization phase and a light-emitting phase. The second power line L2 is configured to transmit a first-level second power supply voltage VSSH during an initialization phase and a data writing phase, and to transmit a second-level second power supply voltage VSSL during a light-emitting phase.

[0099] Optionally, the first-level second power voltage VSSH is greater than the second-level second power voltage VSSL.

[0100] Optionally, the reference voltage V0 transmitted on the third power line may be the same as the initialization voltage Vref, so as to save the number of signal lines.

[0101] Figure 9 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, specifically Figure 8 The pixel circuit shown is a structural diagram of the device, refer to Figure 9 The driving module 110 includes a first transistor Q1, the data writing module 120 includes a second transistor Q2, the compensation module 140 includes a third transistor Q3, the initialization module 130 includes a fourth transistor Q4, the storage module 160 includes a storage capacitor C0, and the light emitting module 150 includes a light emitting diode D1. The gate of the second transistor Q2 is connected to the third control signal line, the first electrode of the second transistor Q2 is connected to the data line DL, the second electrode of the second transistor Q2 is connected to the first electrode of the first transistor Q1, the second electrode of the first transistor Q1 is connected to the first electrode of the light emitting diode D1, and the second electrode of the light emitting diode D1 is connected to the second power line L2. The gate of the third transistor Q3 is connected to the first control signal line, the first electrode of the third transistor Q3 is connected to the second electrode of the first transistor Q1, the second electrode of the third transistor Q3 is connected to the gate of the first transistor Q1, the gate of the fourth transistor Q4 is connected to the second control signal line, the first electrode of the fourth transistor Q4 is connected to the initialization signal line, and the second electrode of the fourth transistor Q4 is connected to the second electrode of the first transistor Q1.

[0102] Figure 10 Another driving timing diagram of a pixel circuit provided by an embodiment of the present invention is applicable to Figure 9 The pixel circuit shown, combined with Figure 9 and Figure 10Taking the case where all transistors are P-type tubes as an example, the working process of the pixel circuit includes an initialization phase T1, a data writing phase and a light emitting phase T3.

[0103] During the initialization phase T1, the first control signal S1 is at a low level, the second control signal S2 is at a low level, and the third control signal EM is at a high level. The first power supply voltage VDD is transmitted on the data line DL, and the second power supply voltage VSSH of the first level is transmitted on the second power line L2. Therefore, the third transistor Q3 and the fourth transistor Q4 are turned on. The initialization voltage Vref on the initialization signal line is transmitted to the first electrode of the light-emitting diode D1 via the fourth transistor Q4, and is transmitted to the gate of the first transistor Q1 via the third transistor Q3, thereby initializing the first electrode of the light-emitting diode D1 and the gate of the first transistor Q1.

[0104] In the data writing phase T2, the first control signal S1 is at a low level, the second control signal S2 is at a high level, the third control signal EM is at a low level, the data voltage Vdata is transmitted on the data line DL, and the second power supply voltage VSSH of the first level is transmitted on the second power line L2. Therefore, the second transistor Q2 and the third transistor Q3 are turned on, and the data voltage Vdata on the data line DL is transmitted to the gate of the first transistor Q1 via the second transistor Q2, the first transistor Q1, and the third transistor Q3. When the gate voltage of the first transistor Q1 is equal to Vdata+Vth1, the first transistor Q1 is turned off, thereby realizing data writing and threshold voltage compensation.

[0105] In the light-emitting stage T3, the first control signal S1 is at a high level, the second control signal S2 is at a high level, the third control signal EM is at a low level, the first power supply voltage VDD is transmitted on the data line DL, and the second power supply voltage VSSL of a second level is transmitted on the second power line L2. Therefore, the second transistor Q2 is turned on, and the first transistor Q1 generates a driving current to drive the light-emitting diode D1 to emit light.

[0106] Compared with the existing technology, the technical solution provided in this embodiment, combined with the driving timing, can achieve the effects of initializing key nodes (such as the gate of the first transistor Q1 and the first electrode of the light-emitting diode D1), as well as data writing and threshold voltage compensation through 4 transistors, which greatly simplifies the structure of the pixel circuit, thereby making the wiring structure inside the pixel simpler, which is beneficial to improving PPI and improving display quality.

[0107] Figure 11 Another driving timing diagram of a pixel circuit provided by an embodiment of the present invention is applicable to Figure 9 The pixel circuit shown, combined with Figure 9 and Figure 11The initialization phase T1 includes a first initialization phase T11 and a second initialization phase T12. Within the same display cycle, the first initialization phase T11 is located before the data writing phase T2, and the second initialization phase T12 is located between the data writing phase T2 and the light-emitting phase T3. During the first initialization phase T11, the first control signal S1 is at a low level, the second control signal S2 is at a low level, and the third control signal EM is at a high level. The first power supply voltage VDD is transmitted on the data line DL, and the second power supply voltage VSSH of the first level is transmitted on the second power line L2. Therefore, the third transistor Q3 and the fourth transistor Q4 are turned on. The initialization voltage Vref on the initialization signal line is transmitted to the first electrode of the light-emitting diode D1 via the fourth transistor Q4, and is transmitted to the gate of the first transistor Q1 via the third transistor Q3, thereby initializing the first electrode of the light-emitting diode D1 and the gate of the first transistor Q1.

[0108] During the second initialization phase T12, the first control signal S1 is at a high level, the second control signal S2 is at a low level, and the third control signal EM is at a high level. The first power supply voltage VDD is transmitted on the data line DL, and the second power supply voltage VSSH of the first level or the second power supply voltage VSSL of the second level is transmitted on the second power line L2. Therefore, the fourth transistor Q4 is turned on. The initialization voltage Vref on the initialization signal line is transmitted to the first electrode of the light-emitting diode D1 via the fourth transistor Q4, thereby initializing the first electrode of the light-emitting diode D1.

[0109] In this embodiment, since the voltage of the first electrode of the light-emitting diode D1 will change during the data writing process, initializing the first electrode of the light-emitting diode D1 after the data writing stage T2 and before the light-emitting stage T3 is beneficial to ensure the normal light emission of the light-emitting diode D1 and improve the display effect.

[0110] It should be noted that, in the second initialization stage T12, the voltage on the second power line L2 may be the second power supply voltage VSSL of the second level. When the voltage on the second power line L2 jumps from the second power supply voltage VSSH of the first level to the second power supply voltage VSSL of the second level, the voltage at the first electrode of the light-emitting diode D1 is pulled down due to the action of the parasitic capacitance. At this time, by initializing the first electrode of the light-emitting diode D1, the phenomenon of the voltage at the first electrode of the light-emitting diode D1 being too low due to the voltage jump on the second power line L2 can be avoided, which is conducive to improving the light emission of the light-emitting diode D1.

[0111] Optionally, in this embodiment, the initialization voltage transmitted on the initialization signal line is adjustable, that is, in the first initialization phase T11 and the second initialization phase T12, the initialization voltage transmitted on the initialization signal line may be different, and may be set according to actual needs.

[0112] Optionally, in Figure 9 In the pixel circuit shown, the third transistor Q3 and / or the fourth transistor Q4 may also be metal oxide transistors, which is beneficial to reducing leakage current.

[0113] It should be noted that in the above embodiments, the metal oxide transistor is an N-type transistor, whose on-level is high and off-level is low, while the on-level of the P-type transistor is low and off-level is high.

[0114] Optionally, an embodiment of the present invention further provides a display panel, which includes the pixel circuit provided by any of the above embodiments. Therefore, the display panel provided by this embodiment also has the beneficial effects described in any of the above embodiments.

[0115] Figure 12 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figure 12 The display panel 300 includes multiple first control signal lines GL1, multiple second control signal lines GL2 and multiple third control signal lines GL3, and each row of pixel circuits is connected to a first control signal line GL1, a second control signal line GL2 and a third control signal line GL3.

[0116] When the initialization module 130 is connected between the first power line L1 and the first end of the driving module 110, the data writing module 120 is connected between the data line DL and the first end of the driving module 110, and the light emitting module 150 is connected between the second end of the driving module 110 and the second power line L2, the first power line L1 is configured to transmit the initialization voltage Vref in the initialization phase and transmit the first power supply voltage VDD at least in the light emitting phase, and the second power line L2 is configured to transmit the first level second power supply voltage VSSH in the initialization phase and the data writing phase, and transmit the second level second power supply voltage VSSL in the light emitting phase; wherein the first level second power supply voltage VSSH is greater than the second level second power supply voltage VSSL. The data line DL is configured to transmit the first voltage V1 (corresponding to VDD) in the initialization phase. Figure 6 Structure shown) or the second voltage V2 (corresponding to Figure 3 and Figure 5 The second voltage V2 is greater than the first voltage V1. Optionally, the second voltage V2 may be the same as the first power supply voltage VDD.

[0117] Among them, multiple first control signal lines GL1 are used to simultaneously transmit the effective level of the first control signal S1 to the control end of the compensation module 140 in all rows of pixel circuits in the initialization stage, and to transmit the effective level of the first control signal S1 to the control end of the compensation module 140 in the pixel circuit row by row in the data writing stage; multiple second control signal lines GL2 are used to transmit the effective level of the second control signal S2 to the control end of the data writing module 120 in the pixel circuit row by row in the data writing stage, and multiple third control signal lines GL3 are used to simultaneously transmit the effective level of the third control signal EM to all rows of pixel circuits in the initialization stage and the light-emitting stage.

[0118] Specifically, Figure 13 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, combined with Figure 6 and Figure 13 In the initialization stage T1, the first control signal S1-1 output by the first control signal line GL1 connected to the first row of pixel circuits is at a low level (i.e., an effective level), the first control signal S1-N output by the first control signal line GL1 connected to the Nth row of pixel circuits is at a low level (i.e., an effective level), the compensation modules 140 in the first to Nth row of pixel circuits are all turned on, the third control signal EM transmitted on the third control signal line GL3 connected to each row of pixel circuits is at a low level (i.e., an effective level), and the initialization modules 130 in the first to Nth row of pixel circuits are all turned on. Therefore, all row pixel circuits in the display panel simultaneously initialize the control end of the driving module 110.

[0119] In the data writing stage T2, the third control signal EM transmitted on the third control signal line GL3 connected to each row of pixel circuits is a high level (i.e., an invalid level), the initialization modules 130 in the first to N-th row pixel circuits are all turned off, and multiple first control signal lines GL1 transmit the low level (i.e., an invalid level) of the first control signal S1 to the compensation module 140 in the pixel circuit row by row, and multiple second control signal lines GL2 transmit the low level (i.e., an invalid level) of the second control signal S2 to the data writing module 120 in the pixel circuit row by row, that is, the effective levels of the first control signal S1-1 corresponding to the first row of pixel circuits to the first control signal S1-N corresponding to the N-th row of pixel circuits are transmitted step by step, and the effective levels of the second control signal S2-1 corresponding to the first row of pixel circuits to the second control signal S1-N corresponding to the N-th row of pixel circuits are transmitted step by step, thereby realizing the row-by-row writing of the data voltage Vdata.

[0120] Optionally, in the data writing phase T2, in the same row of pixel circuits, the effective level of the first control signal S1 and the effective level of the second control signal S2 overlap at least partially, so that the data writing module 120 and the compensation module 140 are turned on at the same time.

[0121] Furthermore, in the data writing phase T2, in the same row of pixel circuits, the effective level of the first control signal S1 and the effective level of the second control signal S2 completely overlap, so that the compensation time is long enough to provide a threshold voltage compensation effect.

[0122] Optionally, the duration of the effective level of the first control signal S1 transmitted on the same first control signal line GL1 in the initialization phase T1 is longer than that in the data writing phase T2, which helps to ensure complete initialization.

[0123] In the light-emitting phase T3 , the third control signal lines GL3 corresponding to all rows of pixel circuits simultaneously transmit the effective level of the third control signal EM, and the light-emitting modules 150 in all rows of pixel circuits simultaneously emit light.

[0124] In another embodiment, when the data writing module 120 is connected between the data line DL and the first end of the driving module 110, and the initialization module 130 is connected between the initialization signal line and the second end of the driving module 150, the data line DL is configured to transmit the data voltage Vdata in the data writing phase T2, and to transmit the first power supply voltage VDD in the initialization phase T1 and the light-emitting phase T3, and the second power supply line L2 is configured to transmit the second power supply voltage VSSH of the first level in the initialization phase T1 and the data writing phase T2, and to transmit the second power supply voltage VSSL of the second level in the light-emitting phase T3.

[0125] Among them, multiple first control signal lines GL1 are used to simultaneously transmit the effective level of the first control signal S1 to the control end of the compensation module 140 in all rows of pixel circuits in the first initialization stage T11, and to transmit the effective level of the first control signal S1 to the control end of the compensation module 140 in the pixel circuit row by row in the data writing stage T2; multiple second control signal lines GL2 are used to simultaneously transmit the effective level of the second control signal S2 to the control end of the initialization module 130 in all rows of pixel circuits in the first initialization stage T11, and to transmit the effective level of the second control signal S2 to the control end of the initialization module 130 in the pixel circuit row by row in the second initialization stage T12; multiple third control signal lines GL3 are used to transmit the effective level of the third control signal EM to the control end of the data writing module 120 in the pixel circuit row by row in the data writing stage T2, and to simultaneously transmit the effective level of the third control signal EM to the control end of the data writing module 120 in all rows of pixel circuits in the light-emitting stage T3.

[0126] Specifically, Figure 14 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, combined with Figure 9 and Figure 14The effective level of the first control signal S1 and the effective level of the second control signal S2 both include first-level pulses and second-level pulses. The first-level pulse P1 of the first control signal S1 is in the first initialization phase T11, and the second-level pulse P2 of the first control signal S1 is in the data writing phase T2. The first-level pulse P11 of the second control signal S2 is in the first initialization phase T11, and the second-level pulse P21 of the second control signal S2 is in the second initialization phase T12. Here, after the data writing is completed for each row of pixel circuits, the second initialization phase T12 is performed for that row of pixel circuits.

[0127] Optionally, the effective level of the third control signal EM includes a first-level pulse and a second-level pulse. The first-level pulse P12 of the third control signal EM is in the data writing phase T2, and the second-level pulse P22 of the third control signal EM is in the light-emitting phase T3. For the same row of pixel circuits, the end time of the first-level pulse P12 of the third control signal EM is after the end time of the second-level pulse P2 of the first control signal S1 and before the start time of the second-level pulse P21 of the second control signal S2. Furthermore, for the same row of pixel circuits, the first-level pulse P1 of the first control signal S1 coincides with the first-level pulse P11 of the second control signal S2, and the end time of the second-level pulse P2 of the first control signal S1 is before the start time of the second-level pulse P21 of the second control signal S2. This configuration is intended to ensure that the initialization of the first end of the light-emitting module 150 is performed after the data writing of the pixel circuits in the current row is completed, thereby avoiding affecting the data writing process.

[0128] Optionally, Figure 15 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, combined with Figure 9 and Figure 15In the second initialization phase T12, when the effective level of the second control signal S2 is simultaneously transmitted to the control terminal of the initialization module 130 in the row pixel circuit, the effective level of the first control signal S1 and the effective level of the second control signal S2 both include a first-level pulse and a second-level pulse, the first-level pulse P1 of the first control signal S1 is in the first initialization phase T11, the second-level pulse P2 of the first control signal S1 is in the data writing phase T2, the first-level pulse P11 of the second control signal S2 is in the first initialization phase T11, and the second-level pulse P21 of the second control signal S2 is in the second initialization phase T12; the effective level of the third control signal EM includes a first-level pulse and a second-level pulse, the first-level pulse P12 of the third control signal EM is in the data writing phase T2, and the second-level pulse P22 of the third control signal EM is in the light-emitting phase. Here, after all row pixel circuits complete data writing, the second initialization phase T12 is entered, and all row pixel circuits simultaneously initialize the first electrode of the light-emitting module 150.

[0129] In the second initialization stage T12, by initializing the first electrode of the light emitting diode D1, the voltage drop due to the voltage jump on the second power line L2 can be avoided, which is beneficial to improving the light emitting condition of the light emitting diode D1.

[0130] Optionally, in the same row of pixel circuits, the first level pulse P1 of the first control signal S1 coincides with the first level pulse P11 of the second control signal S2 .

[0131] The starting time of the second level pulse P21 of the second control signal S2 is after the ending time of the first level pulse P12 of the third control signal EM of the last row of pixel circuits, and the ending time of the second level pulse P21 of the second control signal S2 is before the starting time of the second level pulse P22 of the third control signal EM.

[0132] In the same row of pixel circuits, the duration of the first level pulse P12 of the third control signal EM overlaps the duration of the second level pulse P2 of the first control signal S1 , so as to maintain the voltage of the first terminal of the driving module 110 after the compensation module 140 is turned off.

[0133] The technical solution provided by the embodiment of the present invention, through the combination of specific driving timing, can greatly simplify the pixel circuit structure, help reduce the wiring structure inside the pixel, and thus improve the PPI.

[0134] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0135] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: a driving module, wherein a second end of the driving module is connected to the light-emitting module and is used to drive the light-emitting module to emit light in a light-emitting phase; a data writing module and a compensation module, wherein the data writing module is connected to the first end of the driving module, and the compensation module is connected between the second end of the driving module and the control end of the driving module; the data writing module is configured to transmit the data voltage to the control end of the driving module via the driving module and the compensation module during a data writing phase; The initialization module is connected to the first terminal or the second terminal of the driving module, and is used to transmit the initialization voltage to the control terminal of the driving module at least via the compensation module during the initialization phase.

2. The pixel circuit according to claim 1, wherein: The initialization module is connected between the first power line and the first end of the driving module, the data writing module is connected between the data line and the first end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line; The first power line is configured to transmit the initialization voltage in the initialization phase and transmit the first power voltage at least in the light-emitting phase; Preferably, the initialization voltage is less than the first power supply voltage; Preferably, the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light emitting phase; Preferably, the second power supply voltage of the first level is greater than the second power supply voltage of the second level; Preferably, within the same display cycle, the initialization phase precedes the data writing phase.

3. The pixel circuit according to claim 2, wherein: The control end of the driving module includes a first control end and a second control end, the compensation module is connected to the first control end of the driving module, and the second control end of the driving module is connected to the data line. The driving module is further used to adjust its own threshold voltage according to the voltage of the second control end during the initialization phase; Preferably, the data line is configured to transmit a first voltage during the initialization phase and to transmit the data voltage during the data writing phase; Preferably, the data line is further configured to transmit a second voltage during the light emitting phase; Preferably, the second voltage is greater than the first voltage; Preferably, the pixel circuit further comprises a storage module, wherein the storage module is connected between the third power line and the first control terminal of the driving module; Preferably, the driving module includes a first transistor, the data writing module includes a second transistor, the compensation module includes a third transistor, the initialization module includes a fourth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode; The gate of the fourth transistor is connected to the third control signal line, the first electrode of the fourth transistor is connected to the first power line, the second electrode of the fourth transistor is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is connected to the second power line. The gate of the second transistor is connected to the second control signal line, the first electrode of the second transistor is connected to the data line, the second electrode of the second transistor is connected to the first electrode of the first transistor, the gate of the third transistor is connected to the first control signal line, the first electrode of the third transistor is connected to the second electrode of the first transistor, and the second electrode of the third transistor is connected to the first gate of the first transistor. The first electrode of the storage capacitor is connected to the third power line, and the second electrode of the storage capacitor is connected to the first gate of the first transistor. Preferably, the second gate of the first transistor is connected to the data line, or the second gate of the first transistor is connected to the first electrode of the first transistor; Preferably, at least one of the second transistor, the third transistor and the fourth transistor is a metal oxide transistor.

4. The pixel circuit according to claim 2, wherein: The control end of the driving module includes a first control end and a second control end, the compensation module is connected to the first control end of the driving module, and the second control end of the driving module is connected to the first end of the driving module. The driving module is further used to adjust its own threshold voltage according to the voltage of the second control end during the initialization phase; Preferably, the data line is configured to transmit a second voltage during the initialization phase and to transmit the data voltage during the data writing phase; Preferably, the data line is further configured to transmit the second voltage during the light emitting phase; Preferably, the pixel circuit further includes a storage module, and the storage module is connected between the third power line and the first control terminal of the driving module.

5. The pixel circuit according to claim 1, wherein: The data writing module is connected between the data line and the first end of the driving module, the initialization module is connected between the initialization signal line and the second end of the driving module, the first end of the light emitting module is connected to the second end of the driving module, and the second end of the light emitting module is connected to the second power line; Preferably, the data line is configured to transmit the data voltage in the data writing phase, and to transmit the first power supply voltage in the initialization phase and the light emitting phase; Preferably, the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light emitting phase; Preferably, the second power supply voltage of the first level is greater than the second power supply voltage of the second level; Preferably, the pixel circuit further comprises a storage module, wherein the storage module is connected between the third power line and the first control terminal of the driving module; Preferably, the driving module includes a first transistor, the data writing module includes a second transistor, the compensation module includes a third transistor, the initialization module includes a fourth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode; The gate of the second transistor is connected to the third control signal line, the first electrode of the second transistor is connected to the data line, the second electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is connected to the second power line. The gate of the third transistor is connected to the first control signal line, the first electrode of the third transistor is connected to the second electrode of the first transistor, and the second electrode of the third transistor is connected to the gate of the first transistor. The gate of the fourth transistor is connected to the second control signal line, the first electrode of the fourth transistor is connected to the initialization signal line, and the second electrode of the fourth transistor is connected to the second electrode of the first transistor. Preferably, the third transistor and / or the fourth transistor is a metal oxide transistor; Preferably, the initialization phase includes a first initialization phase and a second initialization phase. In the same display cycle, the first initialization phase is located before the data writing phase, and the second initialization phase is located between the data writing phase and the light emitting phase. Preferably, the initialization voltage transmitted on the initialization signal line is adjustable.

6. A display panel, characterized in that: The pixel circuit comprises the pixel circuit according to any one of claims 1 to 5.

7. The display panel according to claim 6, wherein: The initialization module is connected between the first power line and the first end of the driving module, the data writing module is connected between the data line and the first end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line; The display panel further includes a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of third control signal lines, each row of the pixel circuits being connected to one of the first control signal lines, one of the second control signal lines, and one of the third control signal lines, the plurality of first control signal lines being used to simultaneously transmit the effective level of the first control signal to the control end of the compensation module in all rows of the pixel circuits during the initialization phase, and to transmit the effective level of the first control signal to the control end of the compensation module in the pixel circuits row by row during the data writing phase; the plurality of second control signal lines being used to transmit the effective level of the second control signal to the control end of the data writing module in the pixel circuits row by row during the data writing phase, and the plurality of third control signal lines being used to simultaneously transmit the effective level of the third control signal to all rows of the pixel circuits during the initialization phase and the light-emitting phase; Preferably, the first power line is configured to transmit an initialization voltage during the initialization phase and to transmit a first power voltage at least during the light-emitting phase, and the second power line is configured to transmit a second power voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power voltage of a second level during the light-emitting phase; wherein the initialization voltage is lower than the first power voltage, and the first-level second power voltage is higher than the second-level second power voltage; Preferably, the data line is configured to transmit a first voltage or a second voltage in the initialization phase, and transmit the data voltage in the data writing phase; the second voltage is greater than the first voltage; Preferably, the duration of the effective level of the first control signal transmitted on the same first control signal line in the initialization phase is longer than the duration in the data writing phase; Preferably, in the data writing phase, in the pixel circuits of the same row, the effective level of the first control signal and the effective level of the second control signal overlap for at least part of the time.

8. The display panel according to claim 6, wherein: The data writing module is connected between the data line and the first end of the driving module, the initialization module is connected between the initialization signal line and the second end of the driving module, and the light emitting module is connected between the second end of the driving module and the second power line; the initialization stage includes a first initialization stage and a second initialization stage; The display panel further includes a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of third control signal lines, each row of the pixel circuits being connected to one of the first control signal lines, one of the second control signal lines, and one of the third control signal lines, the plurality of first control signal lines being used to simultaneously transmit the effective level of the first control signal to the control end of the compensation module in all rows of the pixel circuits in the first initialization phase, and to transmit the effective level of the first control signal to the control end of the compensation module in the pixel circuits row by row in the data writing phase; the plurality of second control signal lines being used to simultaneously transmit the effective level of the second control signal to the control end of the initialization module in all rows of the pixel circuits in the first initialization phase, and to transmit the effective level of the second control signal to the control end of the initialization module in the pixel circuits row by row or simultaneously in the second initialization phase; The plurality of third control signal lines are used to transmit the effective level of the third control signal to the control terminals of the data writing modules in the pixel circuits row by row during the data writing phase, and to simultaneously transmit the effective level of the third control signal to the control terminals of the data writing modules in the pixel circuits in all rows during the light emitting phase; Preferably, the data line is configured to transmit the data voltage in the data writing phase, and to transmit the first power supply voltage in the initialization phase and the light emitting phase; Preferably, the second power line is configured to transmit a second power supply voltage of a first level during the initialization phase and the data writing phase, and to transmit a second power supply voltage of a second level during the light emitting phase; the second power supply voltage of the first level is greater than the second power supply voltage of the second level.

9. The display panel according to claim 8, wherein: When the plurality of second control signal lines transmit the effective levels of the second control signals to the control terminals of the initialization modules in the pixel circuits row by row in the second initialization phase, the effective levels of the first control signals and the effective levels of the second control signals both include a first-level pulse and a second-level pulse, the first-level pulse of the first control signal is in the first initialization phase, the second-level pulse of the first control signal is in the data writing phase, the first-level pulse of the second control signal is in the first initialization phase, and the second-level pulse of the second control signal is in the second initialization phase; Preferably, in the pixel circuits of the same row, the first level pulse of the first control signal coincides with the first level pulse of the second control signal, and the end time of the second level pulse of the first control signal is before the start time of the second level pulse of the second control signal; Preferably, the effective level of the third control signal includes a first level pulse and a second level pulse, the first level pulse of the third control signal is located in the data writing stage, the second level pulse of the third control signal is located in the light emitting stage, and for the pixel circuits in the same row, the end time of the first level pulse of the third control signal is after the end time of the second level pulse of the first control signal, and before the start time of the second level pulse of the second control signal.

10. The display panel according to claim 8, wherein When the plurality of second control signal lines simultaneously transmit the effective levels of the second control signals to the control terminals of the initialization modules in all rows of the pixel circuits in the second initialization phase, the effective levels of the first control signal and the second control signal both include a first-level pulse and a second-level pulse, the first-level pulse of the first control signal is in the first initialization phase, the second-level pulse of the first control signal is in the data writing phase, the first-level pulse of the second control signal is in the first initialization phase, and the second-level pulse of the second control signal is in the second initialization phase; The effective level of the third control signal includes a first level pulse and a second level pulse, the first level pulse of the third control signal is in the data writing phase, and the second level pulse of the third control signal is in the light emitting phase; Preferably, in the pixel circuits of the same row, the first level pulse of the first control signal coincides with the first level pulse of the second control signal; Preferably, the start time of the second level pulse of the second control signal is located after the end time of the first level pulse of the third control signal of the pixel circuit of the last row, and the end time of the second level pulse of the second control signal is located before the start time of the second level pulse of the third control signal; Preferably, in the same row of pixel circuits, the duration of the first level pulse of the third control signal overlaps the duration of the second level pulse of the first control signal.

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