Pixel circuit of display panel

Abstract

A pixel circuit of the display panel comprises a first sub-pixel circuit, a second sub-pixel circuit and a splicing enabling transistor. Each of the first sub-pixel circuit and the second sub-pixel circuit comprises a light-emitting element, a light-emitting control transistor and a brightness improving transistor, wherein the light-emitting control transistor and the brightness improving transistor are connected in parallel. One end of the light-emitting element is connected with the first end of the light-emitting control transistor and the first end of the brightness improving transistor. The control end of the light-emitting control transistor of the first sub-pixel circuit receives a first light-emitting control signal, and the control end of the light-emitting control transistor of the second sub-pixel circuit receives a second light-emitting control signal. The control end of the splicing enabling transistor receives a splicing enabling signal, and the first end of the splicing enabling transistor is connected with the control end of the brightness improving transistor of the first sub-pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit of a display panel, and more particularly to a pixel circuit of a display panel for improving the visual effect of a spliced ​​edge. Background Art

[0002] Large format displays (LFDs) allow users to enjoy a large-screen viewing experience, but they are difficult to produce and their production costs and selling prices are quite staggering. Therefore, splicing multiple display panels into a large-size spliced ​​display device has become a common alternative. Light-emitting diode (LED) display panels, micro-LED display panels, or sub-millimeter light-emitting diodes (Mini-LEDs) are quite suitable for use in spliced ​​display devices due to their narrow bezel characteristics. However, current splicing technology and narrow bezel technology still have their limitations, which will inevitably cause visual discontinuities (such as dark lines) at the splicing points of spliced ​​display devices. Therefore, how to improve the splicing visual effect is an important issue in enhancing the viewing experience. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a pixel circuit of a display panel, comprising a first sub-pixel circuit, a second sub-pixel circuit, and a first stitching enabling transistor. The first sub-pixel circuit comprises a first light-emitting control transistor, a first brightness-boosting transistor, and a first light-emitting element. The first light-emitting control transistor has a control terminal for receiving a first light-emitting control signal, a first brightness-boosting transistor is connected in parallel to the first light-emitting control transistor, and one end of the first light-emitting element is connected to the first end of the first light-emitting control transistor and the first end of the first brightness-boosting transistor. The second sub-pixel circuit comprises a second light-emitting control transistor, a second brightness-boosting transistor, and a second light-emitting element. The second light-emitting control transistor has a control terminal for receiving a second light-emitting control signal, a second brightness-boosting transistor is connected in parallel to the second light-emitting control transistor, and one end of the second light-emitting element is connected to the first end of the second light-emitting control transistor and the first end of the second brightness-boosting transistor. The first stitching enabling transistor has a control terminal for receiving the first stitching enabling signal and a first end connected to the control terminal of the first brightness-boosting transistor.

[0004] In at least one embodiment of the present disclosure, the first stitching enabling transistor is turned off in the standard mode and turned on in the stitching mode. The brightness of the first light emitting element in the stitching mode is higher than the brightness of the first light emitting element in the standard mode.

[0005] In at least one embodiment of the present disclosure, in standard mode, the first light emitting element emits light during the conduction period of the first light emitting control transistor. In stitching mode, the first light emitting element emits light during the conduction period of the first light emitting control transistor and the conduction period of the first brightness boosting transistor.

[0006] In at least one embodiment of the present disclosure, the first light emitting element and the second light emitting element are adjacent to each other and close to the splicing edge of the display panel, and the arrangement direction of the first light emitting element and the second light emitting element is parallel to the extension direction of the splicing edge.

[0007] In at least one embodiment of the present disclosure, the second terminal of the first stitching enable transistor receives a second light emitting control signal. In the stitching mode, the first light emitting element emits light in response to the first light emitting control signal and the second light emitting control signal.

[0008] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a third sub-pixel circuit. The third sub-pixel circuit includes a third emission control transistor, a third brightness boosting transistor, and a third light-emitting element. The third emission control transistor has a control terminal that receives a third emission control signal. The third brightness boosting transistor is connected in parallel to the third emission control transistor. One terminal of the third light-emitting element is connected to the first terminal of the third emission control transistor and the first terminal of the third brightness boosting transistor. The first terminal of the first splicing enabling transistor is connected to the control terminal of the second brightness boosting transistor.

[0009] In at least one embodiment of the present disclosure, the first light-emitting element is adjacent to the second light-emitting element, and the second light-emitting element is adjacent to the third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element are adjacent to a splicing edge of the display panel, and the first light-emitting element, the second light-emitting element, and the third light-emitting element are arranged in a direction parallel to an extension direction of the splicing edge.

[0010] In at least one embodiment of the present disclosure, the second terminal of the first stitching enable transistor receives a third light control signal. In a stitching mode, the first light-emitting element emits light in response to the first and third light control signals, and the second light-emitting element emits light in response to the second and third light control signals.

[0011] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a first transistor, a second transistor, and a third transistor. The first transistor has a control terminal that receives a first clock signal, the second transistor has a control terminal that receives a second clock signal, and the third transistor has a control terminal that receives a third clock signal. The first terminal of each of the first, second, and third transistors is connected to the second terminal of the first stitching enable transistor. The second terminal of the first transistor and the second terminal of the second transistor receive a reference voltage, and the second terminal of the third transistor receives a second light-emitting control signal.

[0012] In at least one embodiment of the present disclosure, in the splicing mode, the first light-emitting element emits light in response to the first light-emitting control signal and the second light-emitting control signal.

[0013] In at least one embodiment of the present disclosure, the first clock signal is positively correlated with the first light-emitting control signal. The enable period of the second clock signal partially overlaps with the enable period of the scan signal of the first sub-pixel circuit. The enable periods of the first clock signal, the second clock signal, and the third clock signal are different and staggered.

[0014] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a fourth transistor. The fourth transistor has a control terminal that receives a fourth clock signal. A first terminal of the fourth transistor is connected to the second terminal of the first stitching enable transistor, and a second terminal of the fourth transistor receives a third light-emitting control signal.

[0015] In at least one embodiment of the present disclosure, in the splicing mode, the first light-emitting element emits light in response to the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal.

[0016] In at least one embodiment of the present disclosure, the first clock signal is positively correlated with the first light-emitting control signal. The enable period of the second clock signal partially overlaps with the enable period of the scan signal of the first sub-pixel circuit. The enable periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different and staggered.

[0017] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a first transistor. The first transistor has a control terminal that receives a first clock signal. The first terminal of the first transistor is connected to the second terminal of the first stitching enable transistor. The second terminal of the first transistor receives a second light-emitting control signal. In stitching mode, the first light-emitting element emits light in response to the first light-emitting control signal and the second light-emitting control signal. The enabling periods of the first clock signal and the first light-emitting control signal are different and staggered.

[0018] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a second transistor. The second transistor has a control terminal that receives a second clock signal. The first terminal of the second transistor is connected to the second terminal of the first stitching enable transistor. The second terminal of the first transistor receives a third light-emitting control signal. In stitching mode, the first light-emitting element emits light in response to the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal. The enable periods of the first clock signal, the second clock signal, and the first light-emitting control signal are different and staggered.

[0019] In at least one embodiment of the present disclosure, the pixel circuit of the display panel further includes a second stitching enable transistor, a first transistor, and a second transistor. The second stitching enable transistor has a control end for receiving a second stitching enable signal and a first end connected to the control end of the first brightness boost transistor. The first transistor has a control end for receiving a first clock signal. The second transistor has a control end for receiving a second clock signal. The first end of the first transistor is connected to the second end of the first stitching enable transistor. The second end of the first transistor receives a second light-emitting control signal. The first end of the second transistor is connected to the second end of the second stitching enable transistor. The second end of the second transistor receives a third light-emitting control signal. In stitching mode, when the second stitching enable signal turns on the second stitching enable transistor, the first light-emitting element emits light in response to the first light-emitting control signal and the third light-emitting control signal. The enabling periods of the second clock signal and the first light-emitting control signal are different and staggered.

[0020] In at least one embodiment of the present disclosure, no bank is provided between each of the first and second light-emitting elements and the splicing edge, but a bank is provided between two adjacent light-emitting elements included in the display panel away from the splicing edge.

[0021] In at least one embodiment of the present disclosure, the display panel includes a fourth light-emitting element, the first light-emitting element and the fourth light-emitting element are adjacent to each other, and the arrangement direction of the first light-emitting element and the fourth light-emitting element is perpendicular to the extension direction of the splicing edge, and no retaining wall is provided between the first light-emitting element and the fourth light-emitting element.

[0022] In at least one embodiment of the present disclosure, each of the first light-emitting element and the second light-emitting element is surrounded by a microlens.

[0023] In at least one embodiment of the present disclosure, no retaining wall is provided between each of the first and second light-emitting elements and the splicing edge, but a retaining wall is provided between two adjacent light-emitting elements included in the display panel away from the splicing edge.

[0024] In at least one embodiment of the present disclosure, the display panel includes a fourth light-emitting element. The first and fourth light-emitting elements are adjacent to each other, and the first and fourth light-emitting elements are arranged perpendicular to the extension direction of the splicing edge. A retaining wall is provided between the first and fourth light-emitting elements. The fourth light-emitting element is not surrounded by the microlenses, and the retaining wall is used to limit the formation area of ​​the microlenses surrounding the first light-emitting element.

[0025] In order to make the above features and advantages of the present disclosure more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] A better understanding of the present disclosure can be gained from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to facilitate clarity of discussion.

[0027] Figure 1 is a circuit diagram of a pixel circuit according to a first embodiment of the present disclosure.

[0028] Figure 2 FIG. 4 is a schematic diagram of a light-emitting element provided on a display panel of a display device according to an embodiment of the present disclosure.

[0029] Figure 3 FIG. 1 is a timing diagram of various signals of the pixel circuit according to the first embodiment of the present disclosure.

[0030] Figure 4 is a circuit diagram of a pixel circuit according to a second embodiment of the present disclosure.

[0031] Figure 5 FIG. 4 is a timing diagram of various signals of a pixel circuit according to the second embodiment of the present disclosure.

[0032] Figure 6A is a circuit diagram of a pixel circuit according to a third embodiment of the present disclosure.

[0033] Figure 6B is a circuit diagram of a pixel circuit according to a fourth embodiment of the present disclosure.

[0034] Figure 7 1 is a timing diagram of various signals of the pixel circuit according to the third embodiment and the fourth embodiment of the present disclosure.

[0035] Figure 8 is a circuit diagram of a pixel circuit according to a fifth embodiment of the present disclosure.

[0036] Figure 9 FIG. 5 is a timing diagram of various signals of a pixel circuit according to a fifth embodiment of the present disclosure.

[0037] Figure 10 According to some embodiments of the present disclosure Figure 2 A cross-sectional view of the display device in the line segment view.

[0038] Figure 11 According to other embodiments of the present disclosure Figure 2 A cross-sectional view of the display device in the line segment view.

[0039]

Explanation of symbols

[0040] 10, 20, 30, 40, 50: Pixel circuit

[0041] AA : Line segment

[0042] BK : Retaining Wall

[0043] CK1, CK2, CK3, CK4, CK5, CK6: clock signals

[0044] Data n ,Data n+1 ,Data n+2 : Data signal

[0045] D1, D2: Direction

[0046] DE : Display Device

[0047] EG : Edge stitching

[0048] EM n , EM n+1 , EM n+2 , EM n+3 , EM n+4 , EM n+5 , EM n+6 : Lighting control signal

[0049] ID n , ID n+1 : Drive current

[0050] LD1, LD2, LD3, LD n , LD n+1 , LD n+2 , LD n+3 : Light-emitting element

[0051] ML : Microlens

[0052] PL : Display Panel

[0053] PX n , PX n+1 , PX n+2 , PX n+3 : Sub-pixel circuit

[0054] Scan n , Scan n+1 , Scan n+2 , Scan n+3 , Scan n+4 , Scan n+5 : Scan signal

[0055] T1, T2, T3, T4, T5, T6: transistors

[0056] TCn , TC n+1 , TC n+2 , TC n+3 : Control circuit

[0057] T B : Brightness boost transistor

[0058] T D : Driver transistor

[0059] T EM : Light Emitting Control Transistor

[0060] T tiling , T tiling1 , T tiling2 : Stitching Enable Transistor

[0061] T W : Data writing transistor

[0062] VDD, VSS: system voltage

[0063] VGH : Reference voltage

[0064] V tiling , V tiling1 , V tiling2 : Splicing enable signal DETAILED DESCRIPTION

[0065] The following is a detailed discussion of the embodiments of the present disclosure. However, it will be appreciated that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present disclosure. As used herein, the terms "first," "second," etc., do not specifically refer to an order or sequence; they are intended solely to distinguish between elements or operations described using the same technical terms.

[0066] Figure 1 FIG. 1 is a circuit diagram of a pixel circuit 10 according to a first embodiment of the present disclosure. The pixel circuit 10 includes a sub-pixel circuit PX n , sub-pixel circuit PX n+1 and the stitching enabling transistor T tiling . Sub-pixel circuit PX n Including control circuit TC n , light emitting control transistor T EM , Brightness Enhancement Transistor T B With light emitting element LD n . Sub-pixel circuit PX n+1 Including control circuit TC n+1 , light emitting control transistor T EM , Brightness Enhancement Transistor TB With light emitting element LD n+1 It is worth mentioning that in order to make the drawings concise, Figure 1 Only two sub-pixel circuits are shown. However, in practice, a single sub-pixel circuit corresponds to a single sub-pixel adjacent to the splicing edge of the display panel. Therefore, the number of sub-pixel circuits is not limited to Figure 1 Two shown.

[0067] Control circuit TC n Including data writing transistor T W With the driving transistor T D . Control circuit TC n Data is written into transistor T W Controlled by the scan signal Scan n In the control circuit TC n During the data writing period, the control circuit TC n Data is written into transistor T W In response to the scan signal Scan n And conduction, control circuit TC n Data is written into transistor T W The data signal it receives is Data n Transmitted to the control circuit TC n The driving transistor T D Control terminal of control circuit TC n The driving transistor T D A capacitor is provided between the control terminal and the system voltage VDD to store the data signal Data n The voltage difference between the MOSFET and the system voltage VDD.

[0068] Control circuit TC n+1 Including data writing transistor T W With the driving transistor T D . Control circuit TC n+1 Data is written into transistor T W Controlled by the scan signal Scan n+1 In the control circuit TC n+1 During the data writing period, the control circuit TC n+1 Data is written into transistor T W In response to the scan signal Scan n+1 And conduction, control circuit TC n+1 Data is written into transistor T W The data signal it receives is Data n+1 Transmitted to the control circuit TC n+1 The driving transistor T D control terminal.

[0069] Sub-pixel circuit PX n The light emitting control transistor T EM The control end receives the light emitting control signal EM n In other words, the sub-pixel circuit PX n The light emitting control transistor T EM Having a receiving light emission control signal EM n Control terminal of sub-pixel circuit PX n The driving transistor T D , light emitting control transistor T EM With light emitting element LD n Connected in series between system voltage VDD and VSS. Light emitting element LD n One end is connected to the sub-pixel circuit PX n The light emitting control transistor T EM The first end (eg, drain end) of the light emitting element LD n The other end is connected to the system voltage VSS.

[0070] Sub-pixel circuit PX n+1 The light emitting control transistor T EM The control end receives the light emitting control signal EM n+1 In other words, the sub-pixel circuit PX n+1 The light emitting control transistor T EM Having a receiving light emission control signal EM n+1 Control terminal of sub-pixel circuit PX n+1 The driving transistor T D , light emitting control transistor T EM With light emitting element LD n+1 Connected in series between system voltage VDD and VSS. Light emitting element LD n+1 One end is connected to the sub-pixel circuit PX n+1 The light emitting control transistor T EM The first end (eg, drain end) of the light emitting element LD n The other end is connected to the system voltage VSS.

[0071] Regarding the sub-pixel circuit PX of the pixel circuit 10 n Control circuit TC n , light emitting control transistor T EM With light emitting element LD n Driving control method and sub-pixel circuit PX of pixel circuit 10 n+1 Control circuit TC n+1 , light emitting control transistor T EM With light emitting element LD n+1The driving control mode (hereinafter referred to as "standard mode") is similar to the driving control mode of the sub-pixel circuit of the known light-emitting diode display panel, and therefore will not be described in detail herein. In addition, in other embodiments of the present disclosure, based on the sub-pixel circuit of the known light-emitting diode display panel, the control circuit TC n Or control circuit TC n+1 It may also include a reset circuit (for example, for resetting the voltage at the anode terminal of the light-emitting element), a compensation circuit (for example, for setting the voltage at the control terminal of the driving transistor) and / or other electronic components (for example, transistors and / or capacitors, etc.). In other words, the control circuit of the present disclosure is not limited to Figure 1 The composition shown.

[0072] Compared with the pixel circuit of the conventional light emitting diode display panel, the pixel circuit 10 of the present disclosure further includes a brightness enhancement transistor T B and the stitching enabling transistor T tiling . Splicing enable transistor T tiling The control end receives the splicing enable signal V tiling In other words, the splicing enable transistor T tiling With receiving splicing enable signal V tiling control terminal.

[0073] Sub-pixel circuit PX n With sub-pixel circuit PX n+1 Each of the brightness boost transistors T B Connect the light emitting control transistor T in parallel EM , brightness enhancement transistor T B The control end of the splicing enable transistor T tiling In other words, the first end (eg, drain end) of the splicing enable transistor T tiling With a brightness boost transistor T B The first end of the control terminal of the sub-pixel circuit PX n The driving transistor T D , Brightness Enhancement Transistor T B With light emitting element LD n Connected in series between system voltage VDD and VSS. Light emitting element LD n One end is connected to the sub-pixel circuit PX n Brightness boost transistor T B The first end (eg, drain end) of the sub-pixel circuit PX n+1 The driving transistor T D , Brightness Enhancement Transistor T B With light emitting element LD n+1 Connected in series between system voltage VDD and VSS. Light emitting element LD n+1One end is connected to the sub-pixel circuit PX n+1 Brightness boost transistor T B a first end (eg, a drain end) of the circuit.

[0074] like Figure 1 As shown, in the first embodiment of the present disclosure, for connecting the sub-pixel circuit PX n The stitching enable transistor T tiling The second end (eg, source end) receives the next stage sub-pixel circuit (ie, sub-pixel circuit PX n+1 ) of the light emitting control signal (ie, the light emitting control signal EM n+1 ). For the connection sub-pixel circuit PX n+1 The stitching enable transistor T tiling The second end (eg, source end) receives the next stage sub-pixel circuit (ie, sub-pixel circuit PX n+2 , not shown) of the light emitting control signal (ie, the light emitting control signal EM n+2 , not shown), and so on.

[0075] Figure 2 Schematic diagram of a light emitting element provided on a display panel PL of a display device DE according to an embodiment of the present disclosure. The display device DE is composed of a plurality of display panels PL spliced ​​together. In other words, the display device DE is a spliced ​​display device. Figure 2 As shown, the light emitting element LD n With light emitting element LD n+1 adjacent to each other and adjacent to the splicing edge EG of the display panel PL along the direction D2, and the light emitting element LD n With light emitting element LD n+1 The arrangement direction of the light emitting element LD is parallel to the extension direction of the splicing edge EG, that is, the direction D1. n With light emitting element LD n+1 Each of them is a light emitting diode (LED), a micro light emitting diode (Micro-LED) or a sub-millimeter light emitting diode (Mini-LED).

[0076] Since the spliced ​​display device has a visual discontinuity (e.g., dark line) at the splicing edge EG, the present disclosure uses pixel circuits (e.g., pixel circuits 10, 20, 30) to allow the light-emitting elements adjacent to the splicing edge EG to emit light at least twice in one splicing mode cycle to increase the brightness and improve the splicing visual effect. It is worth mentioning that, Figure 2 The light emitting element LD shown n With light emitting element LD n+1The setting position is the light-emitting element closest to the stitching edge EG, but this is only an example, and the present disclosure is not limited to this. As long as the light-emitting element is adjacent to the stitching edge EG, it can be applied to the pixel circuit of the present disclosure (in other words, the pixel circuit of the present disclosure is applicable to pixels adjacent to the stitching edge EG), thereby improving the stitching visual effect.

[0077] In the embodiments of the present disclosure, Figure 2 The colors of the adjacent light emitting elements in the direction D1 are different from each other. For example, the light emitting element LD n The color is red, the light emitting element LD n+1 The color is green, the light emitting element LD n+2 The color is blue, the light emitting element LD n+3 The color is red, and so on.

[0078] Figure 3 FIG. 1 is a timing diagram of various signals of the pixel circuit 10 according to the first embodiment of the present disclosure. Figure 1 and Figure 3 As shown, in standard mode, the enabling transistor T tiling The control terminal receives the splicing enable signal V tiling A high voltage level is used to turn off the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In standard mode, the brightness is increased by transistor T B The sub-pixel circuit at this time is equivalent to the sub-pixel circuit of the known light-emitting diode display panel. n The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n During the period of low voltage level), the light emitting control transistor T EM Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n Luminescence, light-emitting element LD n+1 In the sub-pixel circuit PX n+1 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+1 is a low voltage level), and so on.

[0079] like Figure 1 and Figure 3 As shown, in the stitching mode, the stitching enabling transistor T tiling The control terminal receives the splicing enable signal V tilingA low voltage level is used to turn on the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In the splicing mode, the brightness is increased by transistor T B Controlled by the stitching enable transistor T tiling For example, the sub-pixel circuit PX n Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+1 , accordingly, in the sub-pixel circuit PX n The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n During the period of low voltage level), the light emitting control transistor T EM Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n Light is emitted, and in the sub-pixel circuit PX n Brightness boost transistor T B During the conduction period (ie, the light emitting control signal EM n+1 During the period of low voltage level), the brightness enhancement transistor T B Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n In other words, in the splicing mode, the light emitting element LD n In response to the light emitting control signal EM n and the light emission control signal EM n+1 For example, the sub-pixel circuit PX n+1 Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+2 (not shown), accordingly, the light emitting element LD n+1 In the sub-pixel circuit PX n+1 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+1 is a period of low voltage level) and the sub-pixel circuit PX n+1 Brightness boost transistor T B During the conduction period (ie, the light emitting control signal EM n+2(not shown) is a period of low voltage level) to emit light, in other words, in the splicing mode, the light emitting element LD n+1 In response to the light emitting control signal EM n+1 and the light emission control signal EM n+2 (not shown) and emit light, and so on.

[0080] From the above, it can be seen that the light emitting element LD n With light emitting element LD n+1 Each of them emits light twice in one cycle of the splicing mode and once in one cycle of the standard mode, so the light emitting element LD n With light emitting element LD n+1 The brightness of each in the splicing mode is higher than that in the standard mode, so as to improve the splicing visual effect by increasing the brightness in the splicing mode.

[0081] Figure 4 FIG. 2 is a circuit diagram of a pixel circuit 20 according to a second embodiment of the present disclosure. The pixel circuit 20 includes a sub-pixel circuit PX n , sub-pixel circuit PX n+1 , sub-pixel circuit PX n+2 , sub-pixel circuit PX n+3 and the stitching enabling transistor T tiling . Sub-pixel circuit PX n+2 Including control circuit TC n+2 , light emitting control transistor T EM , Brightness Enhancement Transistor T B With light emitting element LD n+2 . Sub-pixel circuit PX n+3 Including control circuit TC n+3 , light emitting control transistor T EM , Brightness Enhancement Transistor T B With light emitting element LD n+3 It is worth mentioning that in order to make the drawings concise, Figure 4 Only four sub-pixel circuits are shown. However, in practice, a single sub-pixel circuit corresponds to a single sub-pixel adjacent to the splicing edge of the display panel. Therefore, the number of sub-pixel circuits is not limited to Figure 4 Four shown.

[0082] Control circuit TC n+2 and control circuit TC n+3 The composition is similar to the control circuit TC n and control circuit TC n+1 , also include data write transistors T W With the driving transistor T D . Control circuit TC n+2 Data is written into transistor T WControlled by the scan signal Scan n+2 (not shown), control circuit TC n+2 Data is written into transistor T W The data signal it receives is Data n+2 (not shown) transmitted to the control circuit TC n+2 The driving transistor T D Control terminal of control circuit TC n+2 The driving transistor T D A capacitor is also provided between the control terminal and the system voltage VDD. n+3 Data is written into transistor T W Controlled by the scan signal Scan n+3 (not shown), control circuit TC n+3 Data is written into transistor T W The data signal it receives is Data n+3 (not shown) transmitted to the control circuit TC n+3 The driving transistor T D Control terminal of control circuit TC n+3 The driving transistor T D A capacitor is further provided between the control terminal and the system voltage VDD.

[0083] Sub-pixel circuit PX n+2 The light emitting control transistor T EM The control end receives the light emitting control signal EM n+2 In other words, the sub-pixel circuit PX n+2 The light emitting control transistor T EM Having a receiving light emission control signal EM n+2 Control terminal of sub-pixel circuit PX n+2 The driving transistor T D , light emitting control transistor T EM With light emitting element LD n+2 Connected in series between system voltage VDD and VSS. Light emitting element LD n+2 One end is connected to the sub-pixel circuit PX n+2 The light emitting control transistor T EM The first end (eg, drain end) of the light emitting element LD n+2 The other end is connected to the system voltage VSS.

[0084] Sub-pixel circuit PX n+3 The light emitting control transistor T EM The control end receives the light emitting control signal EM n+3 In other words, the sub-pixel circuit PX n+3 The light emitting control transistor T EMHaving a receiving light emission control signal EM n+3 Control terminal of sub-pixel circuit PX n+3 The driving transistor T D , light emitting control transistor T EM With light emitting element LD n+3 Connected in series between system voltage VDD and VSS. Light emitting element LD n+3 One end is connected to the sub-pixel circuit PX n+3 The light emitting control transistor T EM The first end (eg, drain end) of the light emitting element LD n+3 The other end is connected to the system voltage VSS.

[0085] Compared with the pixel circuit of the conventional light emitting diode display panel, the pixel circuit 20 of the present disclosure further includes a brightness enhancement transistor T B and the stitching enabling transistor T tiling . Splicing enable transistor T tiling The control end receives the splicing enable signal V tiling In other words, the splicing enable transistor T tiling With receiving splicing enable signal V tiling control terminal.

[0086] Sub-pixel circuit PX n+2 With sub-pixel circuit PX n+3 Each of the brightness boost transistors T B Connect the light emitting control transistor T in parallel EM , brightness enhancement transistor T B The control end of the splicing enable transistor T tiling In other words, the first end (eg, drain end) of the splicing enable transistor T tiling With a brightness boost transistor T B The first end of the control terminal of the sub-pixel circuit PX n+2 The driving transistor T D , Brightness Enhancement Transistor T B With light emitting element LD n+2 Connected in series between system voltage VDD and VSS. Light emitting element LD n+2 One end is connected to the sub-pixel circuit PX n+2 Brightness boost transistor T B The first end (eg, drain end) of the sub-pixel circuit PX n+3 The driving transistor T D , Brightness Enhancement Transistor T B With light emitting element LD n+3 Connected in series between system voltage VDD and VSS. Light emitting element LD n+3 One end is connected to the sub-pixel circuit PXn+3 Brightness boost transistor T B a first end (eg, a drain end) of the circuit.

[0087] like Figure 4 As shown, in the second embodiment of the present disclosure, for connecting the sub-pixel circuit PX n With sub-pixel circuit PX n+1 The stitching enable transistor T tiling The second end (eg, source end) receives the next stage sub-pixel circuit (ie, sub-pixel circuit PX n+3 ) of the light emitting control signal (ie, the light emitting control signal EM n+3 ). For the connection sub-pixel circuit PX n+2 With sub-pixel circuit PX n+3 The stitching enable transistor T tiling The second end (eg, source end) receives the next stage sub-pixel circuit (ie, sub-pixel circuit PX n+4 , not shown) of the light emitting control signal (ie, the light emitting control signal EM n+4 , not shown), and so on.

[0088] like Figure 2 As shown, the light emitting element LD n Adjacent to the light emitting element LD n+1 , light emitting element LD n+1 Adjacent to the light emitting element LD n+2 , light emitting element LD n+2 Adjacent to the light emitting element LD n+3 , light emitting element LD n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 Along the direction D2, adjacent to the splicing edge EG of the display panel PL, and the light emitting element LD n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 The arrangement direction is parallel to the extension direction of the splicing edge EG, that is, the direction D1.

[0089] Figure 2 The colors of the adjacent light emitting elements in the direction D1 are different from each other. For example, the light emitting element LD n The color is red, the light emitting element LD n+1 The color is green, the light emitting element LD n+2 The color is blue, the light emitting element LD n+3 The color is red, and so on.

[0090] Figure 5FIG. 1 is a timing diagram of various signals of the pixel circuit 10 according to the second embodiment of the present disclosure. Figure 4 and Figure 5 As shown, in standard mode, the enabling transistor T tiling The control terminal receives the splicing enable signal V tiling A high voltage level is used to turn off the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In standard mode, the brightness is increased by transistor T B The sub-pixel circuit at this time is equivalent to the sub-pixel circuit of the known light-emitting diode display panel. n The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n is a low voltage level period), the sub-pixel circuit PX n The light emitting control transistor T EM Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n Light emission, in the sub-pixel circuit PX n+1 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+1 is a low voltage level period), the sub-pixel circuit PX n+1 The light emitting control transistor T EM Provided for driving the light emitting element LD n+1 The driving current ID n+1 Flowing through the light emitting element LD n+1 So that the light emitting element LD n+1 Luminescence, light-emitting element LD n+2 In the sub-pixel circuit PX n+2 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+2 During the period of low voltage level), the light emitting element LD emits light. n+3 In the sub-pixel circuit PX n+3 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+3 is a low voltage level), and so on.

[0091] like Figure 4 and Figure 5 As shown, in the stitching mode, the stitching enabling transistor T tiling The control terminal receives the splicing enable signal V tilingA low voltage level is used to turn on the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In the splicing mode, the brightness is increased by transistor T B Controlled by the stitching enable transistor T tiling For example, the sub-pixel circuit PX n Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+2 , accordingly, in the sub-pixel circuit PX n The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n is a low voltage level period), the sub-pixel circuit PX n The light emitting control transistor T EM Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n Light is emitted, and in the sub-pixel circuit PX n Brightness boost transistor T B During the conduction period (ie, the light emitting control signal EM n+2 is a low voltage level period), the sub-pixel circuit PX n Brightness boost transistor T B Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n In other words, in the splicing mode, the light emitting element LD n In response to the light emitting control signal EM n and the light emission control signal EM n+2 For example, the sub-pixel circuit PX n+1 Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+2 (not shown), accordingly, in the sub-pixel circuit PX n+1 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+1 is a low voltage level period), the sub-pixel circuit PX n+1 The light emitting control transistor T EM Provided for driving the light emitting element LD n+1 The driving current IDn+1 Flowing through the light emitting element LD n+1 So that the light emitting element LD n+1 Light is emitted, and in the sub-pixel circuit PX n+1 Brightness boost transistor T B During the conduction period (ie, the light emitting control signal EM n+2 is a low voltage level period), the sub-pixel circuit PX n+1 Brightness boost transistor T B Provided for driving the light emitting element LD n+1 The driving current ID n+1 Flowing through the light emitting element LD n+1 So that the light emitting element LD n+1 In other words, in the splicing mode, the light emitting element LD n+1 In response to the light emitting control signal EM n+1 and the light emission control signal EM n+2 For example, the sub-pixel circuit PX n+2 Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+4 (not shown), accordingly, the light emitting element LD n+2 In the sub-pixel circuit PX n+2 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+2 is a period of low voltage level) and the sub-pixel circuit PX n+2 Brightness boost transistor T B During the conduction period (ie, the light emitting control signal EM n+4 (not shown) is a period of low voltage level) to emit light, in other words, in the splicing mode, the light emitting element LD n+2 In response to the light emitting control signal EM n+2 and the light emission control signal EM n+4 (not shown) and emit light. For example, the sub-pixel circuit PX n+3 Brightness boost transistor T B Controlled by the stitching enable transistor T tiling The light emitting control signal EM received by the second end n+4 (not shown), accordingly, the light emitting element LD n+3 In the sub-pixel circuit PX n+3 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+3 is a period of low voltage level) and the sub-pixel circuit PX n+3 Brightness boost transistor T BDuring the conduction period (ie, the light emitting control signal EM n+4 (not shown) is a period of low voltage level) to emit light, in other words, in the splicing mode, the light emitting element LD n+3 In response to the light emitting control signal EM n+3 and the light emission control signal EM n+4 (not shown) and emit light, and so on.

[0092] From the above, it can be seen that the light emitting element LD n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 Each of them emits light twice in one cycle of the splicing mode and once in one cycle of the standard mode, so the light emitting element LD n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 The brightness of each in the splicing mode is higher than that in the standard mode, so as to improve the splicing visual effect by increasing the brightness in the splicing mode.

[0093] It is worth mentioning that in Figure 4 In the pixel circuit 20 shown, a single stitching enabling transistor T tiling The first end is connected to two sub-pixel circuits (eg, sub-pixel circuit PX n With sub-pixel circuit PX n+1 ) of the brightness enhancement transistor T B The control terminal of the present disclosure is not limited thereto. In other embodiments of the present disclosure, a single splicing enabling transistor T tiling The first end of can also be connected to three or more sub-pixel circuits. For example, if a single stitching enable transistor T tiling The first end is connected to three sub-pixel circuits (eg, sub-pixel circuit PX n , sub-pixel circuit PX n+1 With sub-pixel circuit PX n+2 ) of the brightness enhancement transistor T B The control terminal of this single splicing enable transistor T tiling The second end will receive the next level of sub-pixel circuit (sub-pixel circuit PX n+3 ) of the light emitting control signal EM n+3 , and so on.

[0094] Figure 6A 3 is a circuit diagram of a pixel circuit 30 according to a third embodiment of the present disclosure. The pixel circuit 30 includes a sub-pixel circuit PX n , sub-pixel circuit PX n+1 , splicing enable transistor T tiling, transistor T1, transistor T2, transistor T3, transistor T4, transistor T5 and transistor T6. It is worth mentioning that in order to make the drawings simple, Figure 6A Only two sub-pixel circuits are shown. However, in practice, a single sub-pixel circuit corresponds to a single sub-pixel adjacent to the splicing edge of the display panel. Therefore, the number of sub-pixel circuits is not limited to Figure 6A Two shown.

[0095] Compared with the pixel circuit of the conventional light emitting diode display panel, the pixel circuit 30 of the present disclosure further includes a brightness enhancement transistor T B , splicing enable transistor T tiling And transistors T1 to T6. Splicing enable transistor T tiling The control end receives the splicing enable signal V tiling In other words, the splicing enable transistor T tiling With receiving splicing enable signal V tiling control terminal.

[0096] The control terminal of transistor T1 receives clock signal CK1. In other words, transistor T1 has a control terminal that receives clock signal CK1. The control terminal of transistor T2 receives clock signal CK2. In other words, transistor T2 has a control terminal that receives clock signal CK2. The control terminal of transistor T3 receives clock signal CK3. In other words, transistor T3 has a control terminal that receives clock signal CK3. The control terminal of transistor T4 receives clock signal CK4. In other words, transistor T4 has a control terminal that receives clock signal CK4. The control terminal of transistor T5 receives clock signal CK5. In other words, transistor T5 has a control terminal that receives clock signal CK5. The control terminal of transistor T6 receives clock signal CK6. In other words, transistor T6 has a control terminal that receives clock signal CK6.

[0097] The first terminal (eg, drain terminal) of each of the transistors T1, T2, T3, T4, T5, and T6 is connected to the enabling transistor T tiling The second end (eg, source end) of transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, and transistor T6 receives a reference voltage VGH having a high voltage level at the second end. Figure 6A The upper half of the sub-pixel circuit PX n For example, the second end of the transistor T1 and the second end of the transistor T5 receive a reference voltage VGH having a high voltage level. Figure 6A The lower half of the sub-pixel circuit PX n+1For example, the second end of transistor T2 and the second end of transistor T6 receive a reference voltage VGH having a high voltage level. The rest of transistors T1, T2, T3, T4, T5 and T6 receive a light emitting control signal having a different enabling period from the light emitting control signal of the sub-pixel circuit. Figure 6A The upper half of the sub-pixel circuit PX n For example, the second terminal of the transistor T2 receives the light emitting control signal EM. n+1 The second end of the transistor T3 receives the light emitting control signal EM n+2 The second end of the transistor T4 receives the light emitting control signal EM n+3 The second end of the transistor T6 receives the light emitting control signal EM n+5 For example, Figure 6A The lower half of the sub-pixel circuit PX n+1 For example, the second terminal of the transistor T3 receives the light emitting control signal EM. n+2 The second end of the transistor T4 receives the light emitting control signal EM n+3 The second end of the transistor T5 receives the light emitting control signal EM n+4 The second end of the transistor T1 receives the light emitting control signal EM n+6 .

[0098] Figure 6B FIG4 is a circuit diagram of a pixel circuit 40 according to a fourth embodiment of the present disclosure. Pixel circuit 40 is similar to pixel circuit 30, except that pixel circuit 40 does not include a transistor having a second terminal for receiving a reference voltage VGH having a high voltage level. Thus, compared to pixel circuit 30, pixel circuit 40 includes fewer electronic components, thereby increasing layout space.

[0099] Figure 7 1 is a timing diagram of various signals of the pixel circuit 30 and the pixel circuit 40 according to the third embodiment and the fourth embodiment of the present disclosure. Figure 7 As shown, the clock signal CK1 is positively correlated with the light emitting control signal EM. n , the clock signal CK2 is positively correlated with the light emitting control signal EM n+1 , the clock signal CK3 is positively correlated with the light emitting control signal EM n+2 , the clock signal CK4 is positively correlated with the light emitting control signal EM n+3 , the clock signal CK5 is positively correlated with the light emitting control signal EM n+4 , the clock signal CK6 is positively correlated with the light emitting control signal EM n+5 .like Figure 7 As shown, the enabling period of the clock signal CK5 partially overlaps with the sub-pixel circuit PX n Scan signal Scann The enabling period. Figure 7 As shown, the enabling periods of the clock signals CK1, CK2, CK3, CK4, CK5 and CK6 are different and staggered. Figure 7 As shown, the light emitting control signal EM n The enabling periods of the clock signal CK2, the clock signal CK3, the clock signal CK4, the clock signal CK5 and the clock signal CK6 are different from each other and staggered with each other.

[0100] like Figure 6A 、 Figure 6B and Figure 7 As shown, in standard mode, the enabling transistor T tiling The control terminal receives the splicing enable signal V tiling A high voltage level is used to turn off the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In standard mode, the brightness is increased by transistor T B The sub-pixel circuit at this time is equivalent to the sub-pixel circuit of the known light-emitting diode display panel. n The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n is a low voltage level period), the sub-pixel circuit PX n The light emitting control transistor T EM Provided for driving the light emitting element LD n The driving current ID n Flowing through the light emitting element LD n So that the light emitting element LD n Light emission, in the sub-pixel circuit PX n+1 The light emitting control transistor T EM During the conduction period (ie, the light emitting control signal EM n+1 is a low voltage level period), the sub-pixel circuit PX n+1 The light emitting control transistor T EM Provided for driving the light emitting element LD n+1 The driving current ID n+1 Flowing through the light emitting element LD n+1 So that the light emitting element LD n+1 Glow, and so on.

[0101] like Figure 6A 、 Figure 6B and Figure 7 As shown, in the stitching mode, the stitching enabling transistor T tiling The control terminal receives the splicing enable signal V tilingA low voltage level is used to turn on the stitching enable transistor T tiling (ie, splicing enabling transistor T tiling In the splicing mode, the brightness is increased by transistor T B Controlled by the stitching enable transistor T tiling The signal received by the second end.

[0102] For example, for the sub-pixel circuit PX n For example, during the enabling period of the clock signal CK1, the sub-pixel circuit PX n The light emitting control transistor T EM In response to the light emitting control signal EM n And conduction, so that the light emitting element LD n In response to the light emitting control signal EM n At the same time, the transistor T1 is turned on in response to the clock signal CK1, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T1 is connected to the enabling transistor T tiling Receive the reference voltage VGH, thereby turning off the brightness enhancement transistor T B Then, during the enabling period of the clock signal CK2, the transistor T2 is turned on in response to the clock signal CK2, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T2 is connected to the splicing enabling transistor T tiling Receives the light emission control signal EM n+1 , so that the light emitting element LD n In response to the light emitting control signal EM n+1 Then, during the enabling period of the clock signal CK3, the transistor T3 is turned on in response to the clock signal CK3, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T3 is connected to the splicing enabling transistor T tiling Receives the light emission control signal EM n+2 , so that the light emitting element LD n In response to the light emitting control signal EM n+2 Then, during the enabling period of the clock signal CK4, the transistor T4 is turned on in response to the clock signal CK4, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T4 is connected to the splicing enabling transistor T tiling Receives the light emission control signal EM n+3 , so that the light emitting element LD n In response to the light emitting control signal EMn+3 Then, during the enabling period of the clock signal CK5, the transistor T5 is turned on in response to the clock signal CK5, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T5 is connected to the splicing enabling transistor T tiling Receive the reference voltage VGH, thereby turning off the brightness enhancement transistor T B Then, during the enabling period of the clock signal CK6, the transistor T6 is turned on in response to the clock signal CK6, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T6 is connected to the splicing enabling transistor T tiling Receives the light emission control signal EM n+5 , so that the light emitting element LD n In response to the light emitting control signal EM n+5 And glow.

[0103] In other words, in the splicing mode, the light emitting element LD n In response to the light emitting control signal EM n , light control signal EM n+1 , light control signal EM n+2 , light control signal EM n+3 and the light emission control signal EM n+5 Specifically, since the clock signal CK1 is positively correlated with the light-emitting control signal EM n , and the light emitting element LD n Based on the light emitting control transistor T EM In response to the light emitting control signal EM n The second terminal of the transistor T1 controlled by the clock signal CK1 has a high voltage level reference voltage VGH, thereby turning off the brightness enhancement transistor T during the enabling period of the clock signal CK1. B In addition, since the enabling period of the clock signal CK5 partially overlaps with the sub-pixel circuit PX n Scan signal Scan n During the enabling period of the clock signal CK5, the second end of the transistor T5 controlled by the clock signal CK5 has a high voltage level reference voltage VGH, thereby turning off the brightness enhancement transistor T during the enabling period of the clock signal CK5. B .

[0104] From the above, it can be seen that the light emitting element LD n In one cycle of the splicing mode, the light is emitted five times, while in one cycle of the standard mode, the light is emitted once. Therefore, the light emitting element LD nThe brightness in the splicing mode is higher than that in the standard mode, so as to improve the splicing visual effect by increasing the brightness in the splicing mode.

[0105] It is worth mentioning that in Figure 6A In the pixel circuit 30 shown, a single stitching enabling transistor T tiling The second end of is connected to the first end of each of the six transistors, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, a single stitching enabling transistor T tiling The second end of can also be connected to the first end of each of three, four, five or more transistors, and the second ends of at least two of these transistors receive a reference voltage VGH with a high voltage level, and the rest of at least two of these transistors receive a light-emitting control signal that is different from the enable period of the light-emitting control signal of the sub-pixel circuit of that level.

[0106] Figure 8 is a circuit diagram of a pixel circuit 50 according to a fifth embodiment of the present disclosure. The pixel circuit 50 is similar to the pixel circuit 40, except that the stitching enable transistor T tiling In the pixel circuit 50, the two enabling transistors T tiling1 With T tiling2 , which are respectively controlled by the splicing enable signal V tiling1 With V tiling2 . Sub-pixel circuit PX n The stitching enable transistor T tiling1 The second end of the sub-pixel circuit PX is connected to the transistors T2 and T3. n The stitching enable transistor T tiling2 The second end of the sub-pixel circuit PX is connected to the transistors T4 and T6. n+1 The stitching enable transistor T tiling1 The second end of the sub-pixel circuit PX is connected to the transistors T3 and T4. n+1 The stitching enable transistor T tiling2 The second end of the transistor T5 is connected to the transistor T1. Specifically, the pixel circuit 50 is connected by splicing the enabling transistor T tiling1 With T tiling2 To control different transistors in groups, the edge lighting time can be adjusted according to the visual effect, which makes the pixel circuit 50 more flexible in visual effect adjustment than the pixel circuit 40.

[0107] Figure 9 is a timing diagram of various signals of the pixel circuit 50 according to the fifth embodiment of the present disclosure, and Figure 9 The figure shows the stitching mode, where the stitching enable transistor T tiling1 To turn off and connect the enabling transistor T tiling2 For example, Figure 8 and Figure 9 As shown, in the stitching mode, the stitching enabling transistor T tiling2 The control terminal receives the splicing enable signal V tiling2 A low voltage level is used to turn on the stitching enable transistor T tiling2 (ie, splicing enabling transistor T tiling2 In the splicing mode, the brightness is increased by transistor T B Controlled by the stitching enable transistor T tiling2 The signal received by the second end of Figure 9 As shown, the light emitting control signal EM n The enabling periods of the clock signal CK2, the clock signal CK3, the clock signal CK4, the clock signal CK5 and the clock signal CK6 are different from each other and staggered with each other.

[0108] For example, for the sub-pixel circuit PX n For example, during the enabling period of the clock signal CK1, the sub-pixel circuit PX n The light emitting control transistor T EM In response to the light emitting control signal EM n And conduction, so that the light emitting element LD n In response to the light emitting control signal EM n Then, during the enabling period of the clock signal CK4, the transistor T4 is turned on in response to the clock signal CK4, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T4 is connected to the splicing enabling transistor T tiling2 Receives the light emission control signal EM n+3 , so that the light emitting element LD n In response to the light emitting control signal EM n+3 Then, during the enabling period of the clock signal CK6, the transistor T6 is turned on in response to the clock signal CK6, so that the sub-pixel circuit PX n Brightness boost transistor T B The control terminal of the transistor T6 is connected to the splicing enabling transistor T tiling2 Receives the light emission control signal EM n+5 , so that the light emitting element LD n In response to the light emitting control signal EM n+5 And glow.

[0109] In other words, in Figure 9 In the example shown, in the splicing mode, the light emitting element LD n In response to the light emitting control signal EM n , light control signal EM n+3 and the light emission control signal EMn+5 From the above, it can be seen that the light emitting element LD n In one cycle of the splicing mode, light is emitted three times, while in one cycle of the standard mode, light is emitted once. Therefore, the light emitting element LD n The brightness in the splicing mode is higher than that in the standard mode, so as to improve the splicing visual effect by increasing the brightness in the splicing mode.

[0110] Similarly, in the splicing mode, if the splicing enabling transistor T tiling1 With T tiling2 All are conducting, then the light emitting element LD n In one cycle of the splicing mode, the light is emitted five times, so it will be Figure 9 In other words, the edge lighting time can be adjusted according to the visual effect, thereby providing greater flexibility in adjusting the visual effect.

[0111] The first, second, third, fourth and fifth embodiments described above improve the splicing visual effect by increasing the brightness in the splicing mode through circuit design. Figure 10 or Figure 11 As described above, the visual effect of splicing is improved through structural design.

[0112] Figure 10 According to some embodiments of the present disclosure Figure 2 sectional view of the display device DE along the line segment AA. Figure 10 As shown, there is no bank (eg, Figure 10 (marked by a dotted box in the figure), but a barrier wall BK is provided between two light emitting elements (such as light emitting element LD2 and light emitting element LD3) away from the splicing edge EG. Figure 10 The light emitting element LD1 and the light emitting element LD2 are adjacent to the splicing edge EG, so the light emitting element LD1 or the light emitting element LD2 can be the light emitting element LD of the first embodiment, the second embodiment and the third embodiment. n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 One of them.

[0113] like Figure 10 As shown, the light emitting element LD1 and the light emitting element LD2 are adjacent to each other, and the arrangement direction of the light emitting element LD1 and the light emitting element LD2 (i.e., direction D2) is perpendicular to the extension direction of the splicing edge EG (i.e., direction D1), and there is no retaining wall between the light emitting element LD1 and the light emitting element LD2. Figure 10The method is to increase the light output angle of the light emitting element near the splicing edge EG by removing the blocking wall, thereby improving the splicing visual effect.

[0114] Figure 11 According to other embodiments of the present disclosure Figure 2 sectional view of the display device DE along the line segment AA. Figure 11 As shown, the light emitting element LD1 is surrounded by a micro-lens ML. There is no barrier (e.g. Figure 11 (marked by a dotted box in the figure), but a barrier wall BK is provided between two light emitting elements (such as light emitting element LD2 and light emitting element LD3) away from the splicing edge EG. Figure 11 The light emitting element LD1 is adjacent to the splicing edge EG, so the light emitting element LD1 can be the light emitting element LD of the first embodiment, the second embodiment and the third embodiment. n , light-emitting element LD n+1 , light-emitting element LD n+2 With light emitting element LD n+3 One of them.

[0115] like Figure 11 As shown, the light emitting element LD1 and the light emitting element LD2 are adjacent to each other, and the arrangement direction of the light emitting element LD1 and the light emitting element LD2 (i.e., direction D2) is perpendicular to the extension direction of the splicing edge EG (i.e., direction D1). A retaining wall is provided between the light emitting element LD1 and the light emitting element LD2. The light emitting element LD2 is not surrounded by the micro lens, and the retaining wall BK is used to limit the formation area of ​​the micro lens ML surrounding the light emitting element LD1. Specifically, Figure 11 The method is to remove the retaining wall and set micro lenses to surround the light emitting elements to make the light more concentrated, thereby increasing the light output angle of the light emitting elements near the splicing edge EG, thereby improving the splicing visual effect.

[0116] The above summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same goals and / or obtain the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A pixel circuit of a display panel, comprising: The first sub-pixel circuit includes: A first light emitting control transistor having a control terminal receiving a first light emitting control signal; A first brightness boosting transistor connected in parallel to the first light emitting control transistor; and A first light-emitting element, wherein one end of the first light-emitting element is connected to the first end of the first light-emitting control transistor and the first end of the first brightness-enhancing transistor; The second sub-pixel circuit includes: a second light emitting control transistor having a control terminal for receiving a second light emitting control signal; A second brightness boosting transistor connected in parallel to the second light emitting control transistor; and A second light-emitting element, wherein one end of the second light-emitting element is connected to the first end of the second light-emitting control transistor and the first end of the second brightness-enhancing transistor; and The first splicing enabling transistor has a control terminal receiving a first splicing enabling signal and a first terminal connected to the control terminal of the first brightness enhancing transistor.

2. The pixel circuit of the display panel as claimed in claim 1, wherein the first stitching enabling transistor is turned off in the standard mode and turned on in the stitching mode, wherein the brightness of the first light-emitting element in the stitching mode is higher than the brightness of the first light-emitting element in the standard mode.

3. The pixel circuit of the display panel as described in claim 2, wherein in the standard mode, the first light-emitting element emits light during the conduction period of the first light-emitting control transistor, and wherein in the splicing mode, the first light-emitting element emits light during the conduction period of the first light-emitting control transistor and the conduction period of the first brightness enhancement transistor.

4. The pixel circuit of a display panel as claimed in claim 1 , wherein the first light-emitting element and the second light-emitting element are adjacent to each other and close to a splicing edge of the display panel, and an arrangement direction of the first light-emitting element and the second light-emitting element is parallel to an extension direction of the splicing edge.

5. The pixel circuit of the display panel as claimed in claim 2, wherein the second end of the first stitching enabling transistor receives the second light-emitting control signal, wherein in the stitching mode, the first light-emitting element emits light in response to the first light-emitting control signal and the second light-emitting control signal.

6. The pixel circuit of the display panel according to claim 2 , further comprising a third sub-pixel circuit, wherein the third sub-pixel circuit comprises: a third light emitting control transistor having a control terminal receiving a third light emitting control signal; a third brightness boosting transistor connected in parallel with the third light emitting control transistor; and a third light-emitting element, wherein one end of the third light-emitting element is connected to the first end of the third light-emitting control transistor and the first end of the third brightness-enhancing transistor; The first end of the first splicing enabling transistor is connected to the control end of the second brightness enhancing transistor.

7. The pixel circuit of a display panel as described in claim 6, wherein the first light-emitting element is adjacent to the second light-emitting element, and the second light-emitting element is adjacent to the third light-emitting element, the first light-emitting element, the second light-emitting element and the third light-emitting element are adjacent to a splicing edge of the display panel, and an arrangement direction of the first light-emitting element, the second light-emitting element and the third light-emitting element is parallel to an extension direction of the splicing edge.

8. A pixel circuit of a display panel as described in claim 6, wherein the second end of the first stitching enable transistor receives the third light-emitting control signal, wherein in the stitching mode, the first light-emitting element emits light in response to the first light-emitting control signal and the third light-emitting control signal, and the second light-emitting element emits light in response to the second light-emitting control signal and the third light-emitting control signal.

9. The pixel circuit of the display panel according to claim 2, further comprising: A first transistor having a control terminal receiving a first clock signal; a second transistor having a control terminal receiving a second clock signal; and a third transistor having a control terminal receiving a third clock signal; The first end of each of the first transistor, the second transistor and the third transistor is connected to the second end of the first stitching enabling transistor, the second end of the first transistor and the second end of the second transistor receive a reference voltage, and the second end of the third transistor receives the second light-emitting control signal. 10 . The pixel circuit of the display panel as claimed in claim 9 , wherein in the splicing mode, the first light-emitting element emits light in response to the first light-emitting control signal and the second light-emitting control signal.

11. The pixel circuit of the display panel as described in claim 9, wherein the first clock signal is positively correlated with the first light-emitting control signal, wherein the enabling period of the second clock signal partially overlaps with the enabling period of the scanning signal of the first sub-pixel circuit, wherein the enabling periods of the first clock signal, the second clock signal and the third clock signal are different from each other and staggered with each other.

12. The pixel circuit of the display panel according to claim 9, further comprising: a fourth transistor having a control terminal receiving a fourth clock signal; The first end of the fourth transistor is connected to the second end of the first stitching enabling transistor, and the second end of the fourth transistor receives a third light emitting control signal. 13 . The pixel circuit of the display panel as claimed in claim 12 , wherein in the splicing mode, the first light-emitting element emits light in response to the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal.

14. The pixel circuit of the display panel as described in claim 12, wherein the first clock signal is positively correlated with the first light-emitting control signal, wherein the enabling period of the second clock signal partially overlaps with the enabling period of the scanning signal of the first sub-pixel circuit, wherein the enabling periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are different from each other and staggered with each other.

15. The pixel circuit of the display panel according to claim 2, further comprising: A first transistor having a control terminal receiving a first clock signal; The first end of the first transistor is connected to the second end of the first splicing enabling transistor, and the second end of the first transistor receives the second light emitting control signal; In the splicing mode, the first light emitting element emits light in response to the first light emitting control signal and the second light emitting control signal; The enabling periods of the first clock signal and the first light-emitting control signal are different and staggered with each other.

16. The pixel circuit of the display panel according to claim 15, further comprising: a second transistor having a control terminal receiving a second clock signal; The first terminal of the second transistor is connected to the second terminal of the first stitching enabling transistor, and the second terminal of the second transistor receives a third light emitting control signal; In the splicing mode, the first light emitting element emits light in response to the first light emitting control signal, the second light emitting control signal, and the third light emitting control signal; The enabling periods of the first clock signal, the second clock signal and the first light-emitting control signal are different and staggered with each other.

17. The pixel circuit of the display panel according to claim 2, further comprising: A second splicing enabling transistor has a control terminal receiving a second splicing enabling signal and a first terminal connected to the control terminal of the first brightness enhancing transistor; A first transistor having a control terminal receiving a first clock signal; a second transistor having a control terminal receiving a second clock signal; The first end of the first transistor is connected to the second end of the first splicing enabling transistor, and the second end of the first transistor receives the second light emitting control signal; The first terminal of the second transistor is connected to the second terminal of the second stitching enabling transistor, and the second terminal of the second transistor receives a third light emitting control signal; In the splicing mode, when the second splicing enable signal turns on the second splicing enable transistor, the first light emitting element emits light in response to the first light emitting control signal and the third light emitting control signal; The enabling periods of the second clock signal and the first light-emitting control signal are different and staggered with each other.

18. The pixel circuit of the display panel as claimed in claim 4, wherein no bank is provided between each of the first light-emitting element and the second light-emitting element and the splicing edge, but the bank is provided between two adjacent light-emitting elements included in the display panel away from the splicing edge.

19. The pixel circuit of the display panel as described in claim 18, wherein the display panel includes a fourth light-emitting element, the first light-emitting element and the fourth light-emitting element are adjacent to each other, and the arrangement direction of the first light-emitting element and the fourth light-emitting element is perpendicular to the extension direction of the splicing edge, and the retaining wall is not provided between the first light-emitting element and the fourth light-emitting element. 20 . The pixel circuit of the display panel as claimed in claim 4 , wherein each of the first light-emitting element and the second light-emitting element is surrounded by a microlens.

21. The pixel circuit of the display panel as claimed in claim 20, wherein no barrier is provided between each of the first light-emitting element and the second light-emitting element and the splicing edge, but the barrier is provided between two adjacent light-emitting elements included in the display panel away from the splicing edge.

22. The pixel circuit of a display panel as described in claim 20, wherein the display panel includes a fourth light-emitting element, the first light-emitting element and the fourth light-emitting element are adjacent to each other, and the arrangement direction of the first light-emitting element and the fourth light-emitting element is perpendicular to the extension direction of the splicing edge, a retaining wall is provided between the first light-emitting element and the fourth light-emitting element, the fourth light-emitting element is not surrounded by the microlens, and the retaining wall is used to limit the formation area of ​​the microlens surrounding the first light-emitting element.

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