Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area and a non-display area at least partially surrounding the display area. The non-display area comprises a multi-stage driving chip setting area and at least one cascade signal line group; the cascade signal line group comprises a plurality of cascade signal lines; the driving chip setting area is used for setting a driving chip; the driving chip setting area comprises a plurality of input bonding pads and a plurality of output bonding pads; in two adjacent stages of driving chip setting areas, each output bonding pad of the previous stage of driving chip setting area is correspondingly and electrically connected with the first end of each cascade signal line in the same stage of cascade signal line group, and each input bonding pad of the next stage of driving chip setting area is electrically connected with the second end of each cascade signal line in the same stage of cascade signal line group; wherein each cascade signal line is electrically connected with an electrostatic protection structure. According to the display panel, the production yield and the display effect of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of information technology, display devices have become widely used in people's daily lives. Liquid crystal displays (LCDs), as the most widely used flat-panel displays, occupy a key position among display devices. In some display products, such as industrial control display products, a synchronization signal line connects two integrated circuits (ICs) to enable cascade connection between the two driver chips to achieve signal synchronization. However, during the manufacturing process, the signal line connecting two adjacent driver chips may accumulate static electricity, affecting the signal transmitted by the driver chips and, in turn, the display quality of the display panel. Summary of the Invention

[0003] The present invention provides a display panel and a display device to improve the accuracy and reliability of a driving chip providing a driving signal to a display area, thereby facilitating improvement in the production yield and display effect of the display panel.

[0004] The present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area;

[0005] The non-display area includes a multi-stage driver chip setting area and at least one cascade signal line group; the cascade signal line group includes a plurality of cascade signal lines; the driver chip setting area is used to set a driver chip; the driver chip setting area includes a plurality of input pads and a plurality of output pads;

[0006] In two adjacent driver chip arrangement areas, each output pad of the preceding driver chip arrangement area is electrically connected to the first end of each cascade signal line in the same cascade signal line group, and each input pad of the succeeding driver chip arrangement area is electrically connected to the second end of each cascade signal line in the same cascade signal line group;

[0007] Wherein, each cascade signal line is electrically connected to an electrostatic protection structure.

[0008] Based on the same inventive concept, the present invention further provides a display device, comprising: a driving chip and the above-mentioned display panel;

[0009] The driving chip is bound to the driving chip setting area of ​​the display panel.

[0010] The technical solution provided by the present invention electrically connects an electrostatic protection structure to the cascade signal line connecting two adjacent levels of drive signal setting areas, so that the static charge generated on the cascade signal line can be attracted to the electrostatic protection structure and released or conducted by the electrostatic protection structure, thereby preventing the presence of large static electricity on the cascade signal line from affecting the accuracy of signal transmission, affecting the normal operation and service life of electronic components in the driver chip electrically connected to the cascade signal line, or causing damage to other conductive structures, etc., thereby improving the accuracy and reliability of the driver chip in providing the drive signal to the display area, thereby facilitating improving the production yield and display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic structural diagram of a display panel in related technology;

[0012] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 5 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 6 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 7 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0018] Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 9 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 10 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0021] Figure 11 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0022] Figure 12 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 13 A schematic structural diagram of a driver chip provided by an embodiment of the present invention;

[0024] Figure 14 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0025] Figure 15 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0026] Figure 16 for Figure 2 A schematic diagram of the local structure of the display panel;

[0027] Figure 17 for Figure 3 A schematic diagram of the local structure of the display panel;

[0028] Figure 18 for Figure 4 A schematic diagram of the local structure of the display panel;

[0029] Figure 19 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0030] Figure 20 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0031] Figure 21 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0032] Figure 22 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0033] Figure 23 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0034] Figure 24 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0035] Figure 25 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0036] Figure 26 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0037] Figure 27 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0038] Figure 28A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0039] Figure 29 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0040] Figure 30 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0041] Figure 31 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0042] Figure 32 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0043] Figure 33 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0044] Figure 34 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0045] Figure 35 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0046] Figure 36 A schematic diagram of the partial structure of another display panel provided by an embodiment of the present invention;

[0047] Figure 37 A schematic structural diagram of a driver chip provided by an embodiment of the present invention;

[0048] Figure 38 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0049] Figure 39 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0050] Figure 40 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0051] Figure 41 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0052] Figure 42 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0053] Figure 43 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0054] Figure 44 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0055] Figure 45 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0056] Figure 46 A schematic diagram of a partial film layer structure of a display panel provided by an embodiment of the present invention;

[0057] Figure 47 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0058] Figure 48 A schematic structural diagram of a driver chip provided by an embodiment of the present invention;

[0059] Figure 49 A schematic structural diagram of another driver chip provided by an embodiment of the present invention;

[0060] Figure 50 A schematic structural diagram of a display device provided by an embodiment of the present invention;

[0061] Figure 51 A schematic structural diagram of another display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0063] Figure 1 A schematic diagram of the structure of a display panel in related technology is shown in FIG. Figure 1 As shown, the display panel 001 includes a display area 011 and a non-display area 012 that at least partially surrounds the display area 011. The display area 011 may include a plurality of pixels arranged in an array, and a driver chip may be provided in the non-display area 012. The driver chip is used to drive each pixel to display and emit light, so that the display panel 001 can present a corresponding display image. Since the number of pixels in the display panel 001 is set to be large, a single driver chip cannot complete the scanning and signal transmission of all pixels within a limited time. By providing multiple driver chips, each driver chip drives the display and emission of pixels in different areas of the display area 011 to reduce the signal transmission distance, reduce delay and power consumption, and ensure the refresh rate of the display panel 001.

[0064] In the prior art, each driver chip is usually placed on the same circuit board. However, in order to reduce the overall size of the circuit board and optimize the layout design of the non-display area 012, each driver chip is placed in the non-display area 012 of the display panel, and two adjacent driver chips are connected via a cascade signal line 041. However, when the cascade signal line 041 passes through a stepped area of ​​the non-display area 012, or when the cascade signal line 041 connecting two driver chips is long, static electricity may accumulate in the cascade signal line 041 when the display panel 001 is cut or transported. This static electricity can be transmitted along the cascade signal line 041 to the driver chip. The static electricity will generate instantaneous high voltage and high current inside the driver chip, damaging the functional circuit inside the driver chip, causing the driver chip to malfunction or transmit the drive signal incorrectly, and affecting the yield and display effect of the display panel 001.

[0065] To solve the above problems, an embodiment of the present invention provides a display panel, comprising a display area and a non-display area that at least partially surrounds the display area; the non-display area comprises a multi-level driver chip setting area and at least one cascade signal line group; the cascade signal line group comprises a plurality of cascade signal lines; the driver chip setting area is used to set a driver chip; the driver chip setting area comprises a plurality of input pads and a plurality of output pads; in two adjacent driver chip setting areas, the output pads of the previous driver chip setting area are respectively electrically connected to the first ends of the cascade signal lines in the same cascade signal line group, and the input pads of the next driver chip setting area are respectively electrically connected to the second ends of the cascade signal lines in the same cascade signal line group; wherein, each cascade signal line is electrically connected with an electrostatic protection structure.

[0066] By adopting the above technical solution, an electrostatic protection structure is electrically connected to the cascade signal line connecting two adjacent drive signal setting areas, so that the static charge generated on the cascade signal line can be attracted to the electrostatic protection structure and released or conducted by the electrostatic protection structure, thereby preventing the presence of large static electricity on the cascade signal line from affecting the accuracy of signal transmission, affecting the normal operation and service life of electronic components in the driver chip electrically connected to the cascade signal line, or causing damage to other conductive structures, etc., thereby improving the accuracy and reliability of the driver chip in providing the drive signal to the display area, thereby facilitating improving the production yield and display effect of the display panel.

[0067] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0068] Figure 2A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the display panel 100 includes a display area 11 and a non-display area 12 that at least partially surrounds the display area 11; the non-display area 12 includes a multi-stage driver chip setting area 20 and at least one cascade signal line group 40; the cascade signal line group 40 includes a plurality of cascade signal lines 41; the driver chip setting area 20 is used to set a driver chip (not shown in the figure). The driver chip setting area 20 includes a plurality of input pads I and a plurality of output pads O; in two adjacent driver chip setting areas 20, each output pad O of the previous driver chip setting area 20 is electrically connected to the first end of each cascade signal line 41 in the same cascade signal line group 40, and each input pad I of the next driver chip setting area 20 is electrically connected to the second end of each cascade signal line 41 in the same cascade signal line group 40. Among them, each cascade signal line 41 is electrically connected to an electrostatic protection structure ESD.

[0069] It can be understood that the display area 11 is an effective area for realizing image display in the display panel 100, and the non-display area 12 is an area in the display panel where no picture is displayed. The display area 11 may include a plurality of sub-pixels, and the sub-pixels include electrically connected pixel circuits and light-emitting elements. The pixel circuit is used to drive the light-emitting elements to emit light and realize the display function. The pixel circuit can be any pixel circuit known to those skilled in the art composed of devices such as transistors and capacitors. The specific type is not limited in the embodiment of the present invention. The light-emitting element can be a light-emitting diode, including but not limited to micro LED, OLED and mini LED. The non-display area 12 is usually provided with a driving circuit, signal line, support structure, etc. that drives the display area 11 to display.

[0070] Among them, the non-display area 12 at least partially surrounds the display area 11. It can be understood that the non-display area 12 is arranged around the display area 11, or the non-display area 12 is located on one side or multiple sides of the display area 11. It can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0071] A driver chip can be set in the same driver chip setting area 20, so that when the driver chip is bonded in the driver chip setting area 20, each driver chip can be bonded separately at the driver chip setting area 20, thereby improving the alignment bonding accuracy between the driver chip and the driver chip setting area 20. The driver chip is used to drive each pixel in the display area 11 to display and emit light, so that the display panel 100 can present a corresponding display screen. When the number of pixels in the display panel 100 is set to be large, a single driver chip cannot complete the scanning and signal transmission of all pixels within a limited time. By setting multiple driver chips, each driver chip can drive the display and light emission of pixels in different areas of the display area 11, so as to reduce the signal transmission distance, reduce delay and power consumption, and ensure the refresh rate of the display panel 100.

[0072] The number of cascade signal lines 41 provided within the same cascade signal line group 40 can be set according to the number of input pads 1 or output pads O in the driver chip setting area. In an optional embodiment, if the same driver chip setting area 20 includes three input pads 1 that need to be electrically connected to other driver chips and three output pads O that need to be electrically connected to other driver chips, then the same cascade signal line group 40 includes three cascade signal lines 41. The number of cascade signal lines 41 provided can also be other, and is not specifically limited here. The material of the cascade signal line 41, the input pads 1, and the output pads O can include at least one of aluminum, titanium, tantalum, molybdenum, indium tin oxide, and the like.

[0073] Cascade signal lines 41 in the same cascade signal line group 40 connect the output pads O of the previous driver chip arrangement area 20 and the input pads I of the next driver chip arrangement area 20, thereby synchronously transmitting the drive signal from the previous driver chip arrangement area 20 to the next driver chip arrangement area 20. This ensures synchronization of the signals received by the driver chips in each driver chip arrangement area 20, thereby improving the driving capability of the display panel 100. Furthermore, by providing multiple driver chip arrangement areas 20 to accommodate multiple driver chips, overload issues that may occur when a single driver chip is used to transmit signals are avoided, the stability of the signals transmitted by each driver chip is improved, and the display effect of the display panel 100 is thereby enhanced.

[0074] When the cascade signal line 41 passes through the stepped area of ​​the non-display area 12, or the cascade signal line 41 is long, static electricity may accumulate in the cascade signal line 41 when the display panel 100 is cut or transported. This static electricity can be transmitted along the cascade signal line 41 to the driver chip, generating instantaneous high voltage and high current inside the driver chip, affecting the driver reliability of the driver chip. This solution electrically connects each cascade signal line 41 to the electrostatic protection structure ESD, so that the static charge on the cascade signal line 41 can be discharged or guided through the electrostatic protection structure ESD, thereby preventing the static charge from affecting the normal operation of the driver chip and ensuring the display effect of the display panel 100.

[0075] Specifically, the electrostatic protection structure ESD can attract or conduct static charges on the cascade signal lines 41. By providing an electrostatic protection structure ESD electrically connected to each cascade signal line 41, the static charges generated on the cascade signal lines 41 can be attracted to the electrostatic protection structure ESD and released by the electrostatic protection structure ESD, thereby preventing the presence of large static electricity on the cascade signal lines 41 from affecting the accuracy of signal transmission, as well as affecting the normal operation and service life of the driver chip electrically connected to the cascade signal lines 41, thereby improving the production yield and display effect of the display panel 100. The electrostatic protection structure ESD can include any conductive material or any conductive circuit, etc., and can be set according to actual needs, and is not specifically limited here.

[0076] The technical solution of the present invention electrically connects an electrostatic protection structure to the cascade signal line connecting two adjacent levels of drive signal setting areas, so that the static charge generated on the cascade signal line can be attracted to the electrostatic protection structure and released or conducted by the electrostatic protection structure, thereby preventing the presence of large static electricity on the cascade signal line from affecting the accuracy of signal transmission, affecting the normal operation and service life of electronic components in the drive chip electrically connected to the cascade signal line, or causing damage to other conductive structures, etc., thereby improving the accuracy and reliability of the drive signal provided by the drive chip to the display area, thereby facilitating improving the production yield and display effect of the display panel.

[0077] It can be understood that the specific implementation method of electrically connecting the electrostatic protection structure ESD to each cascade signal line 41 can be set according to actual needs, for example, the electrostatic protection structure ESD is set in series with the cascade signal line 41, etc. The following uses a typical example to exemplify the specific structure of the electrostatic protection structure ESD electrically connected to each cascade signal line 41 in an embodiment of the present invention.

[0078] Optional, Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Figures 2 to 4The electrostatic protection structure ESD is electrically connected to the first end and / or the second end of the cascade signal line 41 .

[0079] The electrostatic protection structure ESD is electrically connected to the first end and / or the second end of the cascade signal line 41, and can be specifically Figure 2 The electrostatic protection structure ESD is only electrically connected to the first end of the cascade signal line 41, and can also be Figure 3 The electrostatic protection structure ESD is only electrically connected to the second end of the cascade signal line 41, and can also be Figure 4 The electrostatic protection structure ESD is electrically connected to the first end and the second end of the cascade signal line 41 respectively, and can be specifically configured according to actual needs, which is not specifically limited here.

[0080] Specifically, due to the tip discharge effect, static electricity in the cascade signal line 41 is concentrated toward the first end and / or the second end, thereby generating a strong electric field at the first end and / or the second end. By electrically connecting the electrostatic protection structure ESD to the first end and / or the second end of the cascade signal line 41, the static charge accumulated in the cascade signal line 41 can be quickly released through the electrostatic protection structure ESD located at the first end and / or the second end, thereby increasing the rate of static discharge on the cascade signal line 41, reducing the risk of damage to electronic components within the driver chip caused by static electricity on the cascade signal line 41, and ensuring the operational reliability of the driver chip.

[0081] It should be noted that Figures 2 to 4 The structure in which the electrostatic protection structure ESD is electrically connected to the first end and / or the second end of the cascade signal line 41 is only shown as an example. In the embodiment of the present invention, the manner in which the electrostatic protection structure ESD is electrically connected to the cascade signal line 41 is not limited to this, that is, the electrostatic protection structure ESD can be directly or indirectly electrically connected to the first end and / or the second end of the cascade signal line 41.

[0082] In an optional embodiment, Figure 5 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 6 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figure 5 and Figure 6 The electrostatic protection structure ESD is located on a side of the output pad O away from the first end of the cascade signal line 41; the electrostatic protection structure ESD is electrically connected to the first end of the cascade signal line 41 through the output pad O. Alternatively, the electrostatic protection structure ESD is located on a side of the input pad I away from the second end of the cascade signal line 41; the electrostatic protection structure ESD is electrically connected to the second end of the cascade signal line 41 through the input pad I.

[0083] Specifically, the electrostatic protection structure ESD can be electrically connected only to the output pad O and then electrically connected to the first end of the cascade signal line 41 via the output pad O. This allows the static charge concentrated at the first end of the cascade signal line 41 to be released into the electrostatic protection structure ESD via the output pad O, thereby reducing the residual static charge in the cascade signal line 41 and ensuring the signal transmission reliability of the cascade signal line 41. Correspondingly, the electrostatic protection structure ESD can be electrically connected only to the input pad I and then electrically connected to the second end of the cascade signal line 41 via the input pad I. This allows the static charge concentrated at the second end of the cascade signal line 41 to be released into the electrostatic protection structure ESD via the input pad I, thereby reducing the residual static charge in the cascade signal line 41 and ensuring the signal transmission reliability of the cascade signal line 41.

[0084] It is understandable that Figure 7 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the electrostatic protection structure ESD is located on the side of the output pad O away from the first end of the cascade signal line 41; the electrostatic protection structure ESD is electrically connected to the first end of the cascade signal line 41 through the output pad O; and, the electrostatic protection structure ESD is located on the side of the input pad I away from the second end of the cascade signal line 41; the electrostatic protection structure ESD is electrically connected to the second end of the cascade signal line 41 through the input pad I.

[0085] Specifically, by providing an electrostatic protection structure ESD electrically connected to the output pad O and an electrostatic protection structure ESD electrically connected to the input pad I, the electrostatic protection structure ESD can be electrically connected to the first end of the cascade signal line 41 through the output pad O, and the electrostatic protection structure ESD can be electrically connected to the second end of the cascade signal line 41 through the input pad I. In this way, when static charge exists in the cascade signal line 41, the static charge can be released into the electrostatic protection structure ESD through the first end of the cascade signal line 41 and the output pad O, or released into the electrostatic protection structure ESD through the second end of the cascade signal line 41 and the input pad I, thereby increasing the path for the cascade signal line 41 to release static charge, increasing the release rate of static charge in the cascade signal line 41, and further improving the signal transmission reliability of the cascade signal line 41. The electrostatic protection structure ESD is located on the side of the output pad O away from the first end of the cascade signal line 41, and the electrostatic protection structure ESD is located on the side of the input pad I away from the second end of the cascade signal line 41, so that the cascade signal line 41 has a larger setting space, and there can be a larger gap between two adjacent cascade signal lines 41, thereby improving the signal anti-interference ability of the cascade signal line 41.

[0086] It should be noted that Figures 5 to 7The figure only exemplifies a structure in which the electrostatic protection structure ESD is disposed on a side of the input pad 1 away from the first end of the cascade signal line 41, and the electrostatic protection structure ESD is electrically connected to the first end of the cascade signal line 41 via the input pad 1, and / or a structure in which the electrostatic protection structure ESD is disposed on a side of the output pad O away from the second end of the cascade signal line 41, and the electrostatic protection structure ESD is electrically connected to the second end of the cascade signal line 41 via the output pad O. However, in the embodiment of the present invention, the manner in which the electrostatic protection structure ESD is electrically connected to the cascade signal line 41 is not limited thereto, that is, the electrostatic protection structure ESD may be electrically connected to the cascade signal line 41 via a connecting wire.

[0087] In an optional embodiment, Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 9 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 10 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figures 8 to 10 , the non-display area 12 also includes a plurality of first connection signal lines 51; each first connection signal line 51 is electrically connected between the first end of each cascade signal line 41 and each output pad O; the electrostatic protection structure ESD is located between the first end of the cascade signal line 41 and the output pad O, and the electrostatic protection structure ESD is electrically connected to the first end of the cascade signal line 41 through the first connection signal line 51; and / or, the non-display area 12 also includes a plurality of second connection signal lines 52; each second connection signal line 52 is electrically connected between the second end of each cascade signal line 41 and each input pad I; the electrostatic protection structure ESD is located between the second end of the cascade signal line 41 and the input pad I, and the electrostatic protection structure ESD is electrically connected to the second end of the cascade signal line 41 through the second connection signal line 52.

[0088] The materials of the first connection signal line 51 and the second connection signal line 52 can be the same as or different from the materials of the cascade signal line 41, and can be set according to actual needs. For example, the first connection signal line 51 and the second connection signal line 52 can include conductive materials such as aluminum, titanium, tantalum, molybdenum, etc., and can also be other materials, which are not specifically limited here.

[0089] Specifically, by setting a first connecting line 51 between the first end of the cascade signal line 41 and each output pad O, the electrostatic protection structure ESD is located between the first end of the cascade signal line 41 and the output pad O. The electrostatic protection structure ESD can be set along the extension direction of the first connecting line 51, reducing the occupancy rate of the electrostatic protection structure ESD in the horizontal space and improving space utilization. When the electrostatic protection structure ESD is specifically a circuit structure, it may be necessary to provide the electrostatic protection structure ESD with the electrical signal required for operation. When the working signal line that provides the electrostatic protection structure ESD with the electrical signal required for operation is set on a different layer from the cascade signal line 41, the first connecting line 51 and / or the second connecting line 52 can be set on the same layer as the cascade signal line 41. The first connecting line 51 or the second connecting line 52 can be made simultaneously with the cascade signal line 41 using the same preparation process, thereby improving the connection reliability of the first connecting line 51 and / or the second connecting line 52. The line width of the first connecting line 51 or the second connecting line 52 can be consistent with that of the cascade signal line 41.

[0090] Accordingly, when the working signal line that provides the electrical signal required for the electrostatic protection structure ESD is arranged on the same layer as the cascade signal line 41, if the first connecting line 51 and / or the second connecting line 52 are arranged on the same layer as the cascade signal line 41, the cascade signal line 41 will be short-circuited with the working signal line, and the electrostatic protection structure ESD cannot attract the static charge on the cascade signal line 41. At this time, the first connecting signal line 51 and / or the second connecting signal line 52 can be arranged on a different layer from the cascade signal line 41 to ensure the electrostatic discharge reliability of the electrostatic protection structure ESD. Among them, the line width of the first connecting signal line 51 or the second connecting signal line 52 can be larger than the line width of the cascade signal line 41 to increase the cross-sectional area of ​​the first connecting signal line 51 or the second connecting signal line 52, reduce the line impedance, and improve the transmission efficiency of the drive signal.

[0091] It should be noted that the specific structure in which the first connection signal line 51 and / or the second connection signal line 52 and the cascade signal line 41 are arranged in different layers can be set according to actual needs. In an optional embodiment, Figure 11 A partial structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 11 As shown, the cascade signal line 41 is located in the second metal layer M2, the first connection signal line 51 is located in the first metal layer M1, and the working signal line E1 that provides the electrostatic protection structure ESD with the required electrical signal is located in the second metal layer M2. The square resistance of the first metal layer M1 is greater than the square resistance of the second metal layer M2.

[0092] Specifically, by placing the cascade signal line 41, which has a longer routing, in the second metal layer M2, which has a smaller square resistance, the overall impedance of the cascade signal line 41 is reduced, and the attenuation of the cascade electrical signal of the cascade signal line 41 during transmission is reduced, thereby improving the signal transmission efficiency and accuracy of the cascade signal line 41. Similarly, the working signal line E1 needs to transmit a working electrical signal to the electrostatic protection structure (ESD) electrically connected to each cascade signal line 41. Therefore, the line length of the working signal line E1 is also relatively long. Placing the working signal line E1 in the second metal layer M2, which has a smaller square resistance, can also reduce the attenuation of the working electrical signal of the working signal line E1 during transmission, thereby improving the signal transmission efficiency and accuracy of the working signal line E1. The first connection signal line 51 only connects the electrostatic protection structure ESD and the output pad O, as well as the electrostatic protection structure ESD and the first end of the cascade signal line 41. Therefore, the line length of the first connection signal line 51 is relatively short. Setting the first connection signal line 51 in the first metal layer M1 with a larger square resistance will not affect the efficiency of the first connection signal line 51 in transmitting signals, thereby ensuring the working reliability of the electrostatic protection structure ESD.

[0093] Optional, Figure 12 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 12 As shown, the electrostatic protection structure ESD includes multiple electrostatic protection substructures 07 arranged in a one-to-one correspondence with the cascade signal line group 40, and the electrostatic protection substructure 07 includes multiple electrostatic protection units 70 respectively electrically connected to multiple cascade signal lines 41 in the same cascade signal line group 40.

[0094] Specifically, an electrostatic protection substructure 07 is set for each cascade signal line group 40, and in the same cascade signal line group 40, the electrostatic protection substructure 07 includes a plurality of electrostatic protection units 70 arranged in a one-to-one correspondence with each cascade signal line 41, and then a separate electrostatic protection unit 70 is set for each cascade signal line 41, so that the static charge on each cascade signal line 41 can be absorbed by the electrostatic protection unit 70 accordingly, thereby improving the timeliness and reliability of the cascade signal line 41 in releasing static electricity.

[0095] Optional, Figure 13 A schematic diagram of the structure of a driver chip provided by an embodiment of the present invention is shown in FIG. Figure 14 A schematic diagram of the structure of another driver chip provided by an embodiment of the present invention, Figure 15 A schematic diagram of the structure of another driver chip provided by an embodiment of the present invention, referring to Figures 13 to 15Each electrostatic protection substructure 07 is disposed in each driver chip 30. The driver chip 30 includes a plurality of cascade input terminals N and a plurality of cascade output terminals U. Each cascade input terminal N is electrically connected to a corresponding input pad I, and each cascade output terminal U is electrically connected to a corresponding output pad O. The electrostatic protection substructure 07 is electrically connected to the first end of the cascade signal line 41 via the cascade output terminal U and the output pad O, and / or the electrostatic protection substructure 07 is electrically connected to the second end of the cascade signal line 41 via the cascade input terminal N and the input pad I.

[0096] The materials of the cascade input terminal N and the cascade output terminal U may include conductive materials such as copper, and may be set according to actual needs.

[0097] Specifically, by disposing the electrostatic protection substructure 07 within the driver chip 30, the manufacturing process of the display panel 100 is simplified, while the occupancy rate of the electrostatic protection substructure 07 in the non-display area 12 of the display panel 100 is reduced, thereby improving the space utilization rate of the non-display area 12. In addition, when the electrostatic protection substructure 07 is electrically connected to the cascade output terminal U, after the driver chip 30 is bonded within the driver chip installation area 20 and the cascade output terminal U within the driver chip 30 is electrically connected to the output pad O, the electrostatic protection substructure 07 located within the driver chip 30 can be electrically connected to the cascade signal line 41 via the cascade output terminal U and the output pad O. This allows the electrostatic protection substructure 07 to absorb static charge on the cascade signal line 41, thereby improving the reliability and accuracy of signal transmission by the cascade signal line 41. Correspondingly, when the electrostatic protection substructure 07 is electrically connected to the cascade input terminal N, after the driver chip 30 is placed in the driver chip setting area 20 and the cascade input terminal N in the driver chip 30 is electrically connected to the input pad I, the electrostatic protection substructure 07 located inside the driver chip 30 can be electrically connected to the cascade signal line 41 through the cascade input terminal N and the input pad I, so that the electrostatic protection substructure 07 can absorb the static charge on the cascade signal line 41, thereby improving the reliability and accuracy of the signal transmission by the cascade signal line 41.

[0098] It is understandable that the electrostatic protection unit 70 may include a circuit structure, and the specific components and connection structure of the circuit may be configured according to actual needs. The following only describes the circuit structure of the electrostatic protection unit 70 using a typical example.

[0099] In an optional embodiment, Figure 16 for Figure 2 The schematic diagram of the local structure of the display panel is shown in the figure. Figure 17 for Figure 3 The schematic diagram of the local structure of the display panel is shown in the figure. Figure 18 for Figure 4 The partial structure diagram of the display panel is shown in the figure. Figures 16 to 18The electrostatic protection unit 70 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first end of the cascade signal line 41; and / or, the electrostatic protection unit 70 includes a second transistor T2, a first electrode of the second transistor T2 is electrically connected to the second end of the cascade signal line 41.

[0100] The first transistor T1 and the second transistor T2 may include P-type field effect transistors or N-type field effect transistors, etc., and may be configured according to actual needs, which is not specifically limited here.

[0101] Specifically, by setting the electrostatic protection unit 70 to include a first transistor T1, and electrically connecting the first electrode of the first transistor T1 to the first end of the cascade signal line 41, when there is electrostatic charge at the first end of the cascade signal line 41, the first transistor T1 can be controlled to be in an on state, thereby conducting the electrostatic charge at the first end of the cascade signal line 41 to the second electrode of the first transistor T1, thereby releasing the electrostatic charge on the cascade signal line 41.

[0102] Accordingly, by setting the electrostatic protection unit 70 to include a second transistor T2, and electrically connecting the first electrode of the second transistor T2 to the second end of the cascade signal line 41, when there is electrostatic charge at the second end of the cascade signal line 41, the second transistor T2 can be controlled to be in an on state, thereby conducting the electrostatic charge at the second end of the cascade signal line 41 to the second electrode of the second transistor T2, thereby releasing the electrostatic charge on the cascade signal line 41.

[0103] It is understandable that Figures 16 to 18 The structure in which the electrostatic protection unit 70 is located in the driver chip setting area 20 is shown. In other optional embodiments, the electrostatic protection unit 70 can also be located in an area other than the driver chip setting area 20 in the non-display area 12. It can be set according to actual needs and is not specifically limited here.

[0104] Optional, Figure 19 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention is provided. Figure 20 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention, Figure 21 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 19 to 21 The display panel 100 further includes a first power pad H1 and a control pad C0; the first power pad H1 is electrically connected to the second electrode of the first transistor T1, and the control pad C0 is electrically connected to the control electrode of the first transistor T1; and / or the first power pad H1 is electrically connected to the second electrode of the second transistor T2, and the control pad C0 is electrically connected to the control electrode of the second transistor T2.

[0105] The first power pad H1 can provide a first power signal, and the control pad C0 can provide a control signal. The voltage values ​​of the first power signal and the control signal can be set according to the type of the first transistor T1 or the second transistor T2, and are not specifically limited here. The first transistor T1 and the second transistor T2 are of the same type, so that when the first power pad H1 and the control pad C0 provide the first power signal and the control signal to the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor T1 can be turned on or off at the same time.

[0106] Specifically, when the first transistor T1 and the second transistor T2 are both N-type transistors, the voltage difference between the control signal provided by the pad C0 and the first power signal provided by the first power pad H1 can be controlled to be greater than the threshold voltage of the first transistor T1 or the second transistor T2, so that under the action of the first power signal and the control signal, the first transistor T1 and the second transistor T2 are in the on state, and then the static charge existing on the first end and / or the second end of the cascade signal line 41 can be conducted to the second electrode through the first electrode of the first transistor T1 and the second transistor T2 to release the static charge on the cascade signal line 41.

[0107] Optional, Figure 22 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 23 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention is provided. Figure 24 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 21 to 24 The display panel 100 further includes a flexible circuit board setting area 60 ; the flexible circuit board setting area 60 includes a first power supply pad H1 .

[0108] The flexible circuit board setting area 60 is used to set a flexible circuit board, and the flexible circuit board can provide power signals and the like for controlling the pixels in the display panel 100 to display.

[0109] Specifically, by disposing the first power pad H1 in the flexible circuit board disposition area 60 , the first power pad H1 is avoided from being disposed in other non-display areas 12 of the display panel 100 , thereby occupying the space of the non-display area 12 , thereby improving the space utilization of the non-display area 12 .

[0110] Optional, Figure 25 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention is shown. Figure 26 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 27 A partial structural diagram of a display panel provided by an embodiment of the present invention, with reference to Figures 25 to 27The display panel 100 further includes a common signal line P0; the control electrode of the first transistor T1 and / or the second transistor T2 is electrically connected to the common signal line P0; the common signal provided by the common signal line P0 is used to control the conduction state of the first transistor T1 and / or the second transistor T2.

[0111] The common signal provided by the common signal line P0 may be a fixed low level or other levels.

[0112] Specifically, when the common signal provided by the common signal line P0 is a fixed low level, the common signal can serve as a reference ground point for the current loop and drive the light-emitting element to emit light together with the anode voltage of the light-emitting element. In addition, the common signal line P0 can absorb noise in the circuit, such as power supply ripple and coupling interference, thereby improving display uniformity. In this way, by using the common signal provided by the common signal line P0 as a control signal for controlling the conduction state of the first transistor T1 and / or the second transistor T2, there is no need to separately set a terminal or pad in the display panel 100 for providing a control signal to the first transistor T1 and / or the second transistor T2, thereby reducing the design complexity of the display panel 100 and simplifying the structure of the display panel 100.

[0113] In another alternative embodiment, Figure 28 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention, Figure 29 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention is shown. Figure 30 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 28 to 30 The electrostatic protection unit 70 includes a first diode D1 and a second diode D2; the anode of the first diode D1 and the cathode of the second diode D2 are both electrically connected to the first end of the cascade signal line 41, and / or, the electrostatic protection unit 70 includes a third diode D3 and a fourth diode D4; the anode of the third diode D3 and the cathode of the fourth diode D4 are both electrically connected to the second end of the cascade signal line 41.

[0114] The first diode D1 , the second diode D2 , the third diode D3 and the fourth diode D4 include silicon diodes or germanium diodes, etc., and can be configured according to actual needs, which is not specifically limited here.

[0115] Specifically, the electrical signal at the first or second end of the cascade signal line 41 serves as the input signal for the electrostatic protection unit 70. When the voltage at the first end of the cascade signal line 41 is greater than the voltage at the cathode of the first diode D1, it indicates that electrostatic charge exists in the electrical signal at the first end of the cascade signal line 41. The electrostatic charge at the first end can be transferred to the cathode of the first diode D1 via the first diode D1, thereby conducting away the electrostatic charge. When the voltage at the cascade signal line 42 is less than the voltage at the anode of the second diode D2, the voltage signal at the first end is abnormal. At this time, the second diode D2 is turned on, and the abnormal electrostatic charge at the first end is conducted away by the second diode D2, ensuring that the voltage at the first end of the cascade signal line 41 is within a safe range, thereby providing electrostatic protection.

[0116] Accordingly, when the voltage at the second end of the cascade signal line 41 is greater than the voltage at the cathode of the third diode D3, it indicates that static charge exists in the electrical signal at the second end of the cascade signal line 41. The static charge at the second end can be transferred to the cathode of the third diode D3 via the third diode D3, thereby conducting away the static charge. When the voltage at the cascade signal line 42 is less than the voltage at the anode of the fourth diode D4, the voltage signal at the second end is abnormal. At this time, the fourth diode D4 is turned on, and the abnormal static charge at the second end is conducted away by the fourth diode D4, ensuring that the voltage at the second end of the cascade signal line 41 is within a safe range, thus providing electrostatic protection.

[0117] Optional, Figure 31 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention is provided. Figure 32 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention, Figure 33 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 31 to 33 The display panel 100 further includes a first power pad H1 and a second power pad H2; the first power pad H1 is electrically connected to the anode of the second diode D2, and the second power pad H2 is electrically connected to the cathode of the first diode D1; and / or the first power pad H1 is electrically connected to the anode of the fourth diode D4, and the second power pad H2 is electrically connected to the cathode of the third diode D3.

[0118] The first power pad H1 can provide a first power signal, and the second power pad H2 can provide a second power signal. The voltage values ​​of the first power signal and the second power signal can be set according to actual needs and are not specifically limited here. For example, the first power signal is greater than the second power signal, the first power signal provided by the first power pad H1 is a high level, and the second power signal provided by the second power pad H2 is a low level.

[0119] Specifically, when the voltage at the first end of the cascade signal line 41 is greater than the second power signal provided by the second power pad H2, it indicates that static charge exists in the electrical signal at the first end of the cascade signal line 41. The static charge at the first end can be transferred to the cathode of the first diode D1 via the first diode D1, thereby conducting away the static charge. When the voltage at the first end of the cascade signal line 42 is less than the first power signal provided by the first power pad H1, the voltage signal at the first end is abnormal. At this time, the second diode D2 is turned on, and the abnormal static charge at the first end is conducted away by the second diode D2, ensuring that the voltage at the first end of the cascade signal line 41 is within a safe range, thus providing electrostatic protection.

[0120] Accordingly, when the voltage at the second end of the cascade signal line 41 is greater than the second power signal provided by the second power pad H2, it indicates that there is static charge in the electrical signal at the second end of the cascade signal line 41. The static charge at the second end can be transferred to the cathode of the third diode D3 via the third diode D3, thereby conducting away the static charge. When the voltage at the second end of the cascade signal line 42 is less than the first power signal provided by the first power pad H1, the voltage signal at the second end is abnormal. At this time, the fourth diode D4 is turned on, and the abnormal static charge at the second end is conducted away by the fourth diode D4, ensuring that the voltage at the second end of the cascade signal line 41 is within a safe range, thus providing electrostatic protection.

[0121] Optional, Figure 34 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 35 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention is provided. Figure 36 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 34 to 36 The display panel 100 further includes a flexible circuit board setting area 60 ; the flexible circuit board setting area 60 includes a first power supply pad H1 and a second power supply pad H2 .

[0122] The flexible circuit board setting area 60 is used to set a flexible circuit board, and the flexible circuit board can provide power signals and the like for controlling the pixels in the display panel 100 to display.

[0123] Specifically, by setting the first power pad H1 and the first power pad H2 in the flexible circuit board setting area 60, after the flexible circuit board is subsequently fixed in the flexible circuit board setting area 60, the flexible circuit board can provide a first power signal to the first power pad H1 and provide a second power signal to the first power pad H2. The first power signal and the second power signal can be multiplexed with the power signal provided in the flexible circuit board, and there is no need to set up separate power supply modules for the first power pad H1 and the second power pad H2.

[0124] Optional, Figure 37A schematic diagram of the structure of a driver chip provided by an embodiment of the present invention is shown in FIG. Figure 38 A schematic diagram of the structure of another driver chip provided by an embodiment of the present invention, Figure 39 A schematic diagram of the structure of another driver chip provided by an embodiment of the present invention, referring to Figures 37 to 39 The electrostatic protection unit 70 is disposed in the driver chip 30 ; the driver chip 30 includes a first power pad H1 and a second power pad H2 .

[0125] Specifically, by disposing the electrostatic protection unit 70, the first power pad H1, and the second power pad H2 within the driver chip 30, the occupancy rate of the electrostatic protection unit 70, the first power pad H1, and the second power pad H2 in the non-display area 12 of the display panel 100 is reduced, thereby improving the space utilization rate of the non-display area 12. After the driver chip 30 is placed in the driver chip setting area 20 and the cascade output terminal U within the driver chip 30 is electrically connected to the output pad O, the electrostatic protection unit 70 within the driver chip 30 can be electrically connected to the cascade signal line 41 via the cascade output terminal U and the output pad O, so that the electrostatic protection unit 70 can absorb the static charge on the cascade signal line 41, thereby improving the reliability and accuracy of the signal transmission of the cascade signal line 41. Correspondingly, after the driver chip 30 is placed in the driver chip setting area 20 and the cascade input terminal N in the driver chip 30 is electrically connected to the input pad I, the electrostatic protection unit 70 located inside the driver chip 30 can be electrically connected to the cascade signal line 41 through the cascade input terminal N and the input pad I, so that the electrostatic protection unit 70 can absorb the static charge on the cascade signal line 41, thereby improving the reliability and accuracy of the signal transmission of the cascade signal line 41.

[0126] Optional, Figure 40 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention is shown. Figure 41 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 42 A partial structural diagram of a display panel provided by an embodiment of the present invention, with reference to Figures 40 to 42 The display panel 100 further includes a flexible circuit board setting area 60 ; the flexible circuit board setting area 60 includes a first power pad H1 ; the display panel 100 further includes a common signal line P0 ; the common signal line P0 is electrically connected to the second power pad H2 .

[0127] Specifically, by arranging the first power pad H1 within the flexible circuit board arrangement area 60, the flexible circuit board can provide a first power signal to the first power pad H1 after the flexible circuit board is subsequently secured thereto. This first power signal can be reused with the power signal provided by the flexible circuit board, eliminating the need for a separate power supply module for the first power pad H1. The common signal line P0 is used as a signal line to provide an electrical signal to the second power pad H2, eliminating the need for a separate signal line to provide an electrical signal to the second power pad H2. This reduces the number of signal lines within the display panel 100 and simplifies the structure of the display panel 100.

[0128] In other optional embodiments, the electrostatic protection unit 70 may further include structures such as a resistor. Figure 43 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention, Figure 44 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention is shown. Figure 45 A partial structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 43 to 45 The electrostatic protection unit 70 includes a first resistor R1, one end of which is electrically connected to the first end of the cascade signal line 41; and / or the electrostatic protection unit 70 includes a second resistor R2, one end of which is electrically connected to the second end of the cascade signal line 41.

[0129] The first resistor R1 and / or the second resistor R2 include chip resistors, resistor blocks, or bow-wound resistors. Chip resistors are small and lightweight and can be quickly mounted using a chip mounter, improving mounting efficiency. The resistor block has a large cross-sectional area, and the bow-wound resistor has a large length. Therefore, both the resistor block and the bow-wound resistor have large resistance values, can absorb more static charge, and increase the release rate of static charge on the cascade signal line 41.

[0130] Specifically, because resistors have the characteristic of hindering the flow of current and can absorb static charge, by configuring the electrostatic protection unit 70 to include a first resistor R1 or a second resistor R2, static charge at the first end of the cascade signal line 41 can be absorbed by the first resistor R1, and static charge at the second end of the cascade signal line 41 can be absorbed by the second resistor R2, thereby reducing or preventing the accumulation of static charge on the cascade signal line 41 and improving the accuracy and reliability of the signal transmitted by the cascade signal line 41.

[0131] Optional, Figure 46 A schematic diagram of a partial film layer structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 46 As shown, the display panel 100 further includes a base substrate 10 and a metal layer M located on one side of the base substrate 10 ; the metal layer M includes a first resistor R1 and / or a second resistor R2 .

[0132] The metal layer M includes one or more metal conductive materials such as aluminum, molybdenum, titanium or silver, and can be set according to actual needs, which is not specifically limited here.

[0133] Specifically, by disposing the first resistor R1 and / or the second resistor R2 in the metal layer M, the first resistor R1 and / or the second resistor R2 can be manufactured during the manufacturing process of the display panel 100, thereby improving the manufacturing efficiency of the display panel 100. Specifically, when the first resistor R1 and / or the second resistor R2 are bow-shaped wire-wound resistors, the metal in the metal layer M can be etched to form the bow-shaped wire-wound resistors.

[0134] Optional, Figure 47 A schematic diagram of the structure of another driver chip provided by an embodiment of the present invention is shown. Figure 48 A schematic diagram of the structure of a driver chip provided by an embodiment of the present invention is shown in FIG. Figure 49 A schematic diagram of another driver chip provided by an embodiment of the present invention, referring to Figures 47 to 49 , the first resistor R1 and / or the second resistor R2 are arranged in the driver chip 30; the first resistor R1 is electrically connected to the first end of the cascade signal line 41 through the output pad O; the second resistor R2 is electrically connected to the second end of the cascade signal line 41 through the input pad I.

[0135] In which, a metal layer can be set inside the driver chip 30 to form the first resistor R1 and / or the second resistor R2 in the metal layer inside the driver chip 30; alternatively, after the driver chip 30 is prepared, the prepared first resistor R1 and / or the second resistor R2 are attached to the surface of the driver chip 30. The method of setting the first resistor R1 and / or the second resistor R2 in the driver chip 30 can also be other, which is not specifically limited here.

[0136] Specifically, by disposing the first resistor R1 and / or the second resistor R2 within the driver chip 30, the occupancy rate of the first resistor R1 and / or the second resistor R2 in the non-display area 12 of the display panel 100 is reduced, thereby improving the space utilization rate of the non-display area 12. In addition, when the first resistor R1 is electrically connected to the cascade output terminal U, after the driver chip 30 is placed in the driver chip setting area 20 and the cascade output terminal U within the driver chip 30 is electrically connected to the output pad O, the first resistor R1 located within the driver chip 30 can be electrically connected to the cascade signal line 41 via the cascade output terminal U and the output pad O, so that the first resistor R1 can absorb static charge on the cascade signal line 41, thereby improving the reliability and accuracy of signal transmission by the cascade signal line 41. Correspondingly, when the second resistor R2 is electrically connected to the cascade input terminal N, after the driver chip 30 is placed in the driver chip setting area 20 and the cascade input terminal N in the driver chip 30 is electrically connected to the input pad I, the second resistor R2 located inside the driver chip 30 can be electrically connected to the cascade signal line 41 through the cascade input terminal N and the input pad I, so that the electrostatic protection substructure 07 can absorb the static charge on the cascade signal line 41, thereby improving the reliability and accuracy of the signal transmission by the cascade signal line 41.

[0137] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising a driver chip and a display panel provided by any embodiment of the present invention; the driver chip is bound to the driver chip mounting area of ​​the display panel. Therefore, this display device possesses the technical features of the curved display module provided by embodiments of the present invention and can achieve the beneficial effects of the display panel provided by embodiments of the present invention. Similarities can be found in the above description of the display panel provided by embodiments of the present invention and will not be repeated here.

[0138] For example, Figure 50 A schematic structural diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 50 As shown, the display device 200 includes a display panel 100 provided in an embodiment of the present invention, and includes a driver chip 30 and the display panel 100 provided in any embodiment of the present invention; the driver chip 30 is bound to the driver chip installation area 20 of the display panel 100. The display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0139] Optional, Figure 51 A structural diagram of another display device provided by an embodiment of the present invention is shown in FIG. Figure 51As shown, the display device 200 further includes a flexible circuit board 61; the display panel 100 further includes a flexible circuit board placement area 60; and the flexible circuit board 61 is disposed in the flexible circuit board placement area 60. Thus, the flexible circuit board 60 disposed in the flexible circuit board placement area 60 can provide driving signals to the driver chip 30 or other signal lines to enable the display panel 100 to display normally.

[0140] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area at least partially surrounding the display area; The non-display area includes a multi-stage driver chip setting area and at least one cascade signal line group; the cascade signal line group includes a plurality of cascade signal lines; the driver chip setting area is used to set a driver chip; the driver chip setting area includes a plurality of input pads and a plurality of output pads; In two adjacent driver chip arrangement areas, the output pads of the driver chip arrangement area of ​​the previous level are electrically connected to the first ends of the cascade signal lines in the same cascade signal line group, and the input pads of the driver chip arrangement area of ​​the next level are electrically connected to the second ends of the cascade signal lines in the same cascade signal line group. Wherein, each of the cascade signal lines is electrically connected to an electrostatic protection structure.

2. The display panel according to claim 1, wherein: The electrostatic protection structure is electrically connected to the first end and / or the second end of the cascade signal line.

3. The display panel according to claim 1, wherein: The electrostatic protection structure is located on a side of the output pad away from the first end of the cascade signal line; the electrostatic protection structure is electrically connected to the first end of the cascade signal line through the output pad, and / or, The electrostatic protection structure is located on a side of the input pad away from the second end of the cascade signal line; the electrostatic protection structure is electrically connected to the second end of the cascade signal line through the input pad.

4. The display panel according to claim 1, wherein: The non-display area further includes a plurality of first connection signal lines; each of the first connection signal lines is electrically connected between the first end of each of the cascade signal lines and each of the output pads; the electrostatic protection structure is located between the first end of the cascade signal line and the output pad, and the electrostatic protection structure is electrically connected to the first end of the cascade signal line through the first connection signal line; and / or, The non-display area also includes a plurality of second connecting signal lines; each of the second connecting signal lines is electrically connected between the second end of each of the cascade signal lines and each of the input pads; the electrostatic protection structure is located between the second end of the cascade signal line and the input pad, and the electrostatic protection structure is electrically connected to the second end of the cascade signal line through the second connecting signal line.

5. The display panel according to claim 1, wherein: The electrostatic protection structure includes a plurality of electrostatic protection substructures arranged in one-to-one correspondence with the cascade signal line groups, and the electrostatic protection substructure includes a plurality of electrostatic protection units respectively electrically connected to the plurality of cascade signal lines in the same cascade signal line group.

6. The display panel according to claim 5, wherein: Each of the electrostatic protection substructures is respectively arranged in each of the driver chips, and the driver chip includes a plurality of cascade input terminals and a plurality of cascade output terminals; each of the cascade input terminals is respectively electrically connected to each of the input pads, and each of the cascade output terminals is respectively electrically connected to each of the output pads; The electrostatic protection substructure is electrically connected to the first end of the cascade signal line through the cascade output terminal and the output pad in sequence, and / or the electrostatic protection substructure is electrically connected to the second end of the cascade signal line through the cascade input terminal and the input pad in sequence.

7. The display panel according to claim 5, wherein: The electrostatic protection unit includes a first transistor, a first electrode of the first transistor is electrically connected to the first end of the cascade signal line; and / or, The electrostatic protection unit includes a second transistor, and a first electrode of the second transistor is electrically connected to the second end of the cascade signal line.

8. The display panel according to claim 5, wherein: The electrostatic protection unit includes a first diode and a second diode; the anode of the first diode and the cathode of the second diode are both electrically connected to the first end of the cascade signal line, and / or, The electrostatic protection unit includes a third diode and a fourth diode; an anode of the third diode and a cathode of the fourth diode are both electrically connected to the second end of the cascade signal line.

9. The display panel according to claim 7, wherein: Also includes: a first power supply pad and a control pad; The first power pad is electrically connected to the second electrode of the first transistor, and the control pad is electrically connected to the control electrode of the first transistor; and / or, The first power pad is electrically connected to the second electrode of the second transistor, and the control pad is electrically connected to the control electrode of the second transistor.

10. The display panel according to claim 8, wherein Also includes: a first power supply pad and a second power supply pad; The first power supply pad is electrically connected to the anode of the second diode, and the second power supply pad is electrically connected to the cathode of the first diode; and / or, The first power pad is electrically connected to the anode of the fourth diode, and the second power pad is electrically connected to the cathode of the third diode.

11. The display panel according to claim 5, wherein: The electrostatic protection unit includes: a first resistor, one end of the first resistor is electrically connected to the first end of the cascade signal line; and / or, The electrostatic protection unit includes a second resistor, one end of the second resistor is electrically connected to the second end of the cascade signal line; The first resistor and / or the second resistor include a chip resistor, a resistor block or a bow-wound resistor.

12. The display panel according to claim 11, wherein: Also includes: a base substrate and a metal layer located on one side of the base substrate; The metal layer includes the first resistor and / or the second resistor.

13. The display panel according to claim 11, wherein: The first resistor and / or the second resistor are arranged in the driver chip; The first resistor is electrically connected to the first end of the cascade signal line through the output pad; the second resistor is electrically connected to the second end of the cascade signal line through the input pad.

14. The display panel according to claim 9, wherein: Also includes: Flexible circuit board setting area; The flexible circuit board setting area includes the first power supply pad.

15. The display panel according to claim 9, wherein Also includes: common signal line; The control electrode of the first transistor and / or the second transistor is electrically connected to the common signal line; the common signal provided by the common signal line is used to control the conduction state of the first transistor and / or the second transistor.

16. The display panel according to claim 10, wherein: Also includes: Flexible circuit board setting area; The flexible circuit board arrangement area includes the first power supply pad and the second power supply pad.

17. The display panel according to claim 10, wherein: The electrostatic protection unit is provided in the driver chip; The driving chip includes the first power pad and the second power pad.

18. The display panel according to claim 10, wherein: Also includes: Flexible circuit board setting area; The flexible circuit board setting area includes the first power supply pad; The display panel further includes a common signal line; the common signal line is electrically connected to the second power supply pad.

19. A display device, characterized in that: include: A driver chip and a display panel according to any one of claims 1 to 18; The driving chip is bound to the driving chip setting area of ​​the display panel.

20. The display device according to claim 19, wherein Also includes: Flexible circuit boards; The display panel further includes a flexible circuit board arrangement area; a flexible circuit board is arranged in the flexible circuit board arrangement area.

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