Driving circuit, driving method, and display device

Abstract

The application discloses a driving circuit, a driving method and a display device. The driving circuit is used for driving a display panel. The display panel comprises a plurality of data lines arranged along a horizontal direction and a plurality of gate lines arranged along a vertical direction. The driving circuit comprises a gate driving module, a source driving module and a plurality of chip on film (COF) modules. The gate driving module outputs a gate driving signal to the gate lines. The source driving module outputs a data driving signal to the COF modules. The data driving signal is output to the data lines through the COF modules and fan-out lines. The COF modules are arranged in a plurality of groups. The length of the fan-out lines of the fan-out area corresponding to each COF module gradually increases along the transmission direction of the gate driving signal. The application considers the influence of the impedance of the gate lines, the data lines and the fan-out lines on signal transmission, especially the obvious boundary line caused by the COF modules at the junction of the fan-out lines. The fan-out lines are rearranged to reduce the light and dark difference caused by the boundary line.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, driving method and display device. Background Technology

[0002] As LCD panel sizes increase, the fanout area of ​​the LCD panel becomes more limited in terms of trace space. Consequently, some data lines located in the fanout area exhibit a shorter middle section and longer sides. This results in lower RC loading on the data lines near the center of the chip-on-film (COF) and higher RC loading on the data lines on the sides.

[0003] Due to the RC differences in the data lines in the fanout area and the distance between pixels on the gate line, the charging differences of pixels at different positions on the left and right are different. The overall charging time of the channels on both sides is shorter than that in the middle. However, the charging time of the data line (source line) in the middle of each COF is longer, while the charging time of the data lines (source lines) on both sides is shorter. This will result in color shift on both sides of the display panel. In special images, there will be a brightness difference between the pixels corresponding to the source line in the middle of the COF and the pixels corresponding to the source lines on both sides (because it is related to the fanout impedance, it is called fanout mura). Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, driving method, and display device that can improve the brightness difference at the junction of data lines connected by flip-chip films.

[0005] This application discloses a driving circuit for driving a display panel. The display panel includes multiple data lines arranged horizontally and multiple gate lines arranged vertically. The driving circuit includes a gate driving module, a source driving module, and a flip-chip film. The gate driving module outputs a gate driving signal to the gate lines; the source driving module outputs a data driving signal to the flip-chip film; the data driving signal then passes through the flip-chip film and the fan-out traces of the fan-out region and is output to the data lines. Multiple flip-chip films are provided, and along the transmission direction of the gate driving signal, the length of the fan-out traces corresponding to the fan-out region of each flip-chip film gradually increases.

[0006] Optionally, the gate driving module includes a first gate driving circuit and a second gate driving circuit disposed on both sides of the display panel, with one end of the gate line connected to the first gate driving circuit and the other end connected to the second gate driving circuit.

[0007] The source drive module includes a first source drive module and a second source drive module. The flip-chip film includes multiple first flip-chip films and multiple second flip-chip films. The output terminal of the first source drive module is connected to multiple first flip-chip films, and the output terminal of the second source drive module is connected to multiple second flip-chip films.

[0008] The display panel includes a fan-out area, which includes a first fan-out area and a second fan-out area. The first fan-out area is provided with a first fan-out sub-area for each first flip-chip film. The length of the fan-out trace in each first fan-out sub-area gradually increases along a first direction. The second fan-out area is provided with a second fan-out sub-area for each flip-chip film. The length of the fan-out trace in each second fan-out sub-area gradually increases along a second direction.

[0009] Wherein, the first direction and the second direction are opposite, the first direction is the direction from the first gate driving circuit to the second gate driving circuit, and the second direction is the direction from the second gate driving circuit to the first gate driving circuit.

[0010] Optionally, the driving circuit includes a timing control module, which is connected to the first source driving module and the second source driving module respectively.

[0011] The slope of the delay time of the data drive signal output from the first source drive module to the data line is the same as the slope of the delay time of the scan signal output from the first gate drive module to the gate line. The slope of the delay time of the data drive signal output from the second source drive module to the data line is the same as the slope of the delay time of the scan signal output from the second gate drive module to the gate line. The timing control module adjusts the charging time of each flip-chip connected data line to be consistent through a data delay algorithm.

[0012] Optionally, the driving circuit further includes a first delay adjustment circuit and a second delay adjustment circuit;

[0013] The first delay adjustment circuit is disposed on the first source drive module. The first delay adjustment circuit includes multiple sub-adjustment circuits. Each sub-adjustment circuit is provided with a resistor and a capacitor for each fan-out trace connected to each flip-chip thin film. Along the first direction, the resistance value of the resistor and the capacitance value of the capacitor gradually increase.

[0014] The second delay adjustment circuit is disposed on the second source drive module. The second delay adjustment circuit includes multiple sub-adjustment circuits. Each sub-adjustment circuit is provided with a resistor and a capacitor for each fan-out trace connected to each flip-chip thin film. Along the second direction, the resistance value of the resistor and the capacitance value of the capacitor gradually increase.

[0015] Optionally, the display panel is divided into at least two regions along the first direction, namely a first region and a second region. The data lines of the first region are connected one-to-one with the fan-out traces of the first fan-out region, and the data lines of the second region are connected one-to-one with the fan-out traces of the second fan-out region.

[0016] Multiple pixels are provided in both the first region and the second region. The number of compensations for the pixels in the first region and the compensation coefficients for the pixels in the second region are K1 and K2, respectively.

[0017] In this process, the compensation coefficient of each pixel on each data line is obtained by linearly interpolating the compensation coefficients of adjacent areas to obtain the compensation coefficient of the pixel to be compensated, thereby adjusting the charging time of each column of pixels to be consistent.

[0018] Optionally, the gate driving module includes a first gate driving circuit, which is connected to the gate line;

[0019] The source drive module includes a first source drive module and a second source drive module. The flip-chip film includes multiple first flip-chip films and multiple second flip-chip films. The output terminal of the first source drive module is connected to multiple first flip-chip films, and the output terminal of the second source drive module is connected to multiple second flip-chip films.

[0020] The display panel includes a fan-out area, which includes a first fan-out area and a second fan-out area. The first fan-out area is provided with a first fan-out sub-area for each first flip-chip film. The length of the fan-out trace in each first fan-out sub-area gradually increases along a first direction. The second fan-out area is provided with a second fan-out sub-area for each flip-chip film. The length of the fan-out trace in each second fan-out sub-area gradually increases along a first direction.

[0021] The first direction is the direction in which the first gate drive circuit outputs the gate drive signal to the gate line.

[0022] This application also discloses a driving method for using the driving circuit described in any of the above to drive a display panel, the driving method comprising:

[0023] Generate a gate drive signal and output it to the gate line; generate a data drive signal and output it to the data line via the flip-chip film, the fan-out trace of the fan-out region, and the data line.

[0024] The slope of the delay time of the data drive signal on the control data line is the same as the slope of the delay time of the scan signal on the gate line.

[0025] The charging time of each data line connected to the flip-chip film is controlled to be the same.

[0026] Optionally, each fan-out trace connected to the flip-chip film is provided with a resistor and a capacitor, and the step of controlling the slope of the delay time change of the data drive signal on the data line to be the same as the slope of the delay time change of the scan signal on the gate line includes:

[0027] Along the first direction, the delay time of the data line connected to the first fan-out trace of each flip-chip film and the delay time of the data line connected to the last fan-out trace are obtained, and the first change slope of the corresponding flip-chip film connected data line is calculated by the first preset formula.

[0028] Along the second direction, the delay time of the gate line connected to the first fan-out line and the delay time of the gate line connected to the last fan-out line of each flip-chip film are obtained, and the second change slope of the corresponding flip-chip film connected data line is calculated by the second preset formula.

[0029] The control determines whether to connect resistors and capacitors based on the first and second slope changes in order to compensate for the delay of the data drive signal.

[0030] Optionally, the display panel is divided into at least two regions along the first direction, namely a first region and a second region. The data lines of the first region are connected one-to-one with the fan-out traces of the first fan-out region, and the data lines of the second region are connected one-to-one with the fan-out traces of the second fan-out region. Multiple pixels are provided in both the first region and the second region. The compensation number of the pixels in the first region and the compensation coefficient of the pixels in the second region are K1 and K2, respectively.

[0031] The driving method further includes the following steps:

[0032] Locate the area where the compensation pixels are located and determine the compensation coefficient;

[0033] Based on the compensation coefficients of adjacent regions and the pixel column of the intermediate pixels between the compensated pixel and the adjacent region, a linear difference is made using the compensation coefficient formula to obtain the compensation coefficient of the pixel to be compensated and generate a compensation table.

[0034] Where m is the pixel column from the compensated pixel to the middle pixel in the first region, and n is the pixel column from the compensated pixel to the middle pixel in the second region. The compensation coefficient formula is as follows:

[0035] K = (K1*n + K2*m) / (m + n).

[0036] This application also discloses a display device, which includes a display panel and a driving circuit as described above, wherein the driving circuit drives the display panel using a driving method as described above.

[0037] Compared to the scheme of transmitting data to the source drive module with different reverse delays to compensate for the signal delay at the near and far ends of the gate line, this application provides a drive circuit that adjusts the data lines located in the fan-out region, i.e., the fan-out traces. Along the transmission direction of the gate drive signal, the length of the fan-out trace corresponding to the fan-out region of each flip-chip film gradually increases. The longer the delay on the gate line, the longer the pixel charging time; the longer the data signal delay, the shorter the charging time. By changing the arrangement of the fan-out traces and adjusting the overall impedance of the gate line and fanout traces, the slope of the data delay on the source line cancels the slope of the gate signal delay, thereby making the charging time of the pixels at the COF junction closer, thus reducing the brightness difference at the junction and improving the display effect and user experience. Attached Figure Description

[0038] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0039] Figure 1 This is a schematic diagram of the drive circuit of the first embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the drive circuit of the second embodiment of this application;

[0041] Figure 3 This is a waveform diagram of the data drive signal delay according to the second embodiment of this application;

[0042] Figure 4 This is a waveform diagram of the gate drive signal delay according to the second embodiment of this application;

[0043] Figure 5 This is a charging time adjustment diagram according to the second embodiment of this application;

[0044] Figure 6This is a schematic diagram of the drive circuit according to the third embodiment of this application;

[0045] Figure 7 This is an enlarged schematic diagram of the first delay adjustment circuit according to the third embodiment of this application;

[0046] Figure 8 This is an enlarged schematic diagram of the second delay adjustment circuit according to the third embodiment of this application;

[0047] Figure 9 This is a schematic diagram of the drive circuit according to the fourth embodiment of this application;

[0048] Figure 10 This is a schematic diagram of the drive circuit according to the fifth embodiment of this application;

[0049] Figure 11 This is a schematic flowchart of the driving method according to the sixth embodiment of this application;

[0050] Figure 12 This is a schematic flowchart of the driving method according to the seventh embodiment of this application;

[0051] Figure 13 This is a schematic flowchart of the driving method according to the eighth embodiment of this application;

[0052] Figure 14 This is a schematic diagram of the structure of the display device according to the ninth embodiment of this application.

[0053] Among them, 100 is a driving circuit; 110 is a gate driving module; 111 is a first gate driving circuit; 112 is a second gate driving circuit; 120 is a source driving module; 121 is a first source driving module; 122 is a second source driving module; 130 is a flip-chip film; 131 is a first flip-chip film; 132 is a second flip-chip film; 140 is a fan-out region; 141 is a first fan-out region; 1411 is a first fan-out sub-region; 142 is a second fan-out sub-region. Fan-out area; 1421, Second fan-out sub-area; 150, Timing control module; 160, First delay adjustment circuit; 170, Second delay adjustment circuit; 180, Sub-adjustment circuit; 200, Display panel; 201, Gate line; 202, Data line; 203, Pixel; 204, Fan-out trace; 210, First area; 220, Second area; 300, Display device; Resistor - R0~960R; Capacitor - C0~960C0. Detailed Implementation

[0054] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0055] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0056] refer to Figure 1 As shown, as a first embodiment of this application, a driving circuit 100 is disclosed. The driving circuit 100 is used to drive a display panel 200. The display panel 200 includes crisscrossing data lines 202 and gate lines 201. That is, when the display panel 200 is normally placed, multiple data lines 202 are arranged horizontally and multiple gate lines 201 are arranged vertically. The driving circuit 100 includes a gate driving module 110, a source driving module, and a flip-chip thin film 130. The gate driving module 110 outputs a gate driving signal to the gate line 201, and the source driving module 120 outputs a data driving signal to the flip-chip thin film 130. The signal is output through the flip-chip thin film 130 to the fan-out trace 204 of the fan-out area 140 to output to the data line 202. There are multiple flip-chip thin films 130. Along the transmission direction of the gate driving signal, the length of the fan-out trace 204 of the fan-out area 140 of each flip-chip thin film 130 gradually increases.

[0057] In this embodiment, adjustments are made to a portion of the data lines 202 located within the fan-out region 140, namely the fan-out traces 204. The arrangement of the fan-out traces 204 is changed from the original arrangement where multiple fan-out traces 204 corresponding to each flip-chip film 130 gradually increase from the middle to both sides. Instead, the length of the traces in the fan-out region 140 corresponding to each flip-chip film 130 gradually increases along the transmission direction of the gate drive signal. This adjusts the overall impedance of the gate line 201 and the fan-out traces 204, allowing the slope of the signal delay change on the data line 202 to offset the slope of the gate drive signal delay. This makes the charging time of the pixels 203 at the COF junction closer, thereby reducing the brightness difference at the junction and improving the display effect and user experience.

[0058] refer to Figure 2 As shown, the second embodiment of this application is a further refinement and improvement of the first embodiment described above. (Refer to...) Figures 1 to 4As shown, the gate driving module 110 includes a first gate driving circuit 111 and a second gate driving circuit 112 disposed on both sides of the display panel 200. One end of the gate line 201 is connected to the first gate driving circuit 111, and the other end is connected to the second gate driving circuit 112; that is, the display panel 200 is a dual-side driven display panel 200. The source driving module 120 includes a first source driving module 121 and a second source driving module 122. The flip-chip film 130 includes a plurality of first flip-chip films 131 and a plurality of second flip-chip films 132. The output end of the first source driving module 121 is connected to the plurality of first flip-chip films 131, and the output end of the second source driving module 122 is connected to the plurality of second flip-chip films 132. One end of each flip-chip film 130 is connected to the output end of the source driving module, that is, the data output channel CH1-CH960, and the other end is connected to the trace of the fan-out area 140, that is, a part of the data line segment distributed in the fan-out area 140.

[0059] The display panel 200 includes a fan-out area 140, which includes a first fan-out area 141 and a second fan-out area 142. The first fan-out area 141 is provided with a first fan-out sub-area 1411 for each first flip-chip film 131. The length of the fan-out trace 204 in each first fan-out sub-area 1411 gradually increases along a first direction. The second fan-out area 142 is provided with a second fan-out sub-area 1421 for each flip-chip film 130. The length of the fan-out trace 204 in each second fan-out sub-area 1421 gradually increases along a second direction. The first direction and the second direction are opposite. The first direction is the direction from the first gate driving circuit 111 to the second gate driving circuit 112, and the second direction is the direction from the second gate driving circuit 112 to the first gate driving circuit 111. The first direction is also the direction in which the first gate driving circuit 111 outputs the gate driving signal, and the second direction is also the direction in which the second gate driving circuit 112 outputs the gate driving signal.

[0060] As a dual-sided driven display panel 200, the COF bonding position has been changed from being centered to being positioned to the left of the left half of the screen and to the right of the right half. This results in the source line trace of a COF on the left half of the screen becoming increasingly longer from left to right, and the RC loading also increasing from left to right; similarly, the source line trace of a COF on the right half of the screen becomes increasingly longer from right to left, and the RC loading also increases from right to left. In other words, the length of the fan-out trace 204 in each of the first fan-out sub-regions 1411 gradually increases along the first direction, and the length of the fan-out trace 204 in each of the second fan-out sub-regions 1421 gradually increases along the second direction. Figure 3As shown, each COF corresponds to the delay time of the data signals on all source lines. Figure 4 The delay time of the Gate signal on the corresponding pixel of each source line, according to... Figure 3 and Figure 4 It is known that the longer the gate delay, the longer the pixel charging time; conversely, the longer the data signal delay, the shorter the charging time. Therefore, by adjusting the overall impedance of the gate line and fanout traces, we can make the slope of the data delay change on the source line exactly equal to the slope of the gate signal delay. After these mutual cancellations, the charging time is as follows: Figure 5 As shown, the charging time of all source lines in each COF is equal, and the charging time of COFs towards the middle is longer, thus ensuring that the charging time of the source lines connected to each COF is consistent, improving the color shift and fanout mura on both sides of the COF, and preventing the generation of COF boundary lines.

[0061] Furthermore, the driving circuit 100 includes a timing control module 150, which is connected to the first source driving module 121 and the second source driving module 122 respectively. The slope of the delay time of the data driving signal output by the first source driving module 121 to the data line 202 is the same as the slope of the delay time of the scan signal output by the first gate driving module 110 to the gate line 201. The slope of the delay time of the data driving signal output by the second source driving module 122 to the data line 202 is the same as the slope of the delay time of the scan signal output by the second gate driving module 110 to the gate line 201. With the same slope, the timing control module 150 adjusts the charging time of the data lines 202 connected to each flip-chip film 130 to be consistent through a data delay algorithm. In order to make the slope of the delay time of the scan signal on the gate line 201 the same as the slope of the delay time of the data drive signal on the data line 202, the gate line is also modified. Under the condition that other conditions remain unchanged, the resistance of different gate line segments in the gate line is adjusted by changing the line width of the gate line. For example, the line width of the gate line decreases from the middle to both sides, so that the impedance in the middle region of the gate line is smaller. Of course, corresponding capacitors and resistors can also be set for the gate line to adjust the delay time of the drive signal on the gate line.

[0062] refer to Figure 6 As shown, the third embodiment of this application is a further refinement and improvement of the second embodiment described above. (Refer to...) Figures 6 to 8As shown, the driving circuit 100 further includes a first delay adjustment circuit 160 and a second delay adjustment circuit 170. The first delay adjustment circuit 160 is disposed on the first source driving module 121. The first delay adjustment circuit 160 includes a plurality of sub-adjustment circuits 180. Each sub-adjustment circuit 180 is provided with a resistor and a capacitor for each fan-out trace 204 connected to each flip-chip film 130. Along the first direction, the resistance value and the capacitance value gradually increase. The second delay adjustment circuit 170 is disposed on the second source driving module 122. The second delay adjustment circuit 170 includes a plurality of sub-adjustment circuits 180. Each sub-adjustment circuit 180 is provided with a resistor R and a capacitor C for each fan-out trace 204 connected to each flip-chip film 130. Along the second direction, the resistance value and the capacitance value gradually increase.

[0063] Considering that in the second embodiment, when the RC delay of the gate line 201 of the display panel 200 and the impedance difference of each COF source line cannot be completely offset due to process fluctuations, the charging time may vary with process fluctuations. For some display panels 200, the charging time of the left COF source line increases from left to right, and the charging time of the right COF source line increases from right to left; for others, the charging time of the left COF source line increases from right to left, and the charging time of the right COF source line increases from left to right. This results in a slight dividing line at the COF boundary of the display panel 200. In this embodiment, a right-increasing RC delay circuit and a left-increasing RC delay circuit are added to the source driver, namely the first delay adjustment circuit 160 and the second delay adjustment circuit 170. In the two delay adjustment circuits, the right-increasing RC delay circuit, i.e., the first delay adjustment circuit 160, adds an RC delay element in series at the source driver output, with the values ​​of R and C increasing from left to right. The reference value of RC can be selected from multiple sets according to the factory process. The left-increasing RC delay circuit... The delay circuit, namely the second delay adjustment circuit 170, inserts an RC delay element in series with the source driver output. The values ​​of R and C increase from right to left, and the reference value of RC can be selected in multiple groups according to the factory process. In this way, it can compensate for the actual charging direction difference of the source line on each COF on the panel, so as to achieve the same charging time for the source line connected to each COF.

[0064] refer to Figure 9As shown, as the fourth embodiment of this application, and a further refinement and improvement of the second embodiment described above, the display panel 200 is divided into at least two regions along a first direction, namely a first region 210 and a second region 220. The data lines 202 of the first region 210 are connected one-to-one with the fan-out traces 204 of the first fan-out area 141, and the data lines 202 of the second region 220 are connected one-to-one with the fan-out traces 204 of the second fan-out area 142. Multiple pixels 203 are provided in both the first region 210 and the second region 220. The number of compensations for the pixels 203 in the first region 210 and the compensation coefficients for the pixels 203 in the second region 220 are K1 and K2, respectively. The compensation coefficient of the pixel 203 on each data line 202 is linearly subtracted from the compensation coefficients of adjacent regions to obtain the compensation coefficient of the pixel 203 to be compensated, thereby adjusting the charging time of each column of pixels 203 to be consistent.

[0065] This embodiment is a further improvement on the second embodiment. Unlike the third embodiment, this embodiment considers that in the third embodiment, adding an RC delay circuit to the source driver improves the mura problem at the COF boundary by adding an RC delay to each source line (or adding a set of RC delays to several source lines), which increases the wafer size of the source driver and thus the cost of the source driver module 120. Therefore, this application makes another improvement by proposing a novel linear OD compensation to improve the charging difference problem of each COF source line. The OD algorithm generally uses a common compensation table, which specifies that when switching from gray level A in the previous frame to gray level B in the next frame, the second gray level compensates gray level B to gray level C for output. This compensation table applies to all pixels 203 of the entire panel. Furthermore, the panel is divided into several regions, each with many pixels 203, and each region has a separate compensation coefficient Kn. The compensation coefficient for the first region 210 is K1, and the compensation coefficient for the second region 220 is K2. During compensation, the compensated value of the second gray level is A + Kn * (BA) based on the compensation coefficient Kn of the region where the panel is located.

[0066] This scheme, based on partitioned compensation, calculates the compensation coefficient for each source line corresponding to pixel 203 by linearly interpolating the compensation coefficients of adjacent regions. For example, if the compensation coefficients of two adjacent OD partitions are K1 and K2, and considering the two columns of pixels 203 at the center point Q1 of the left partition in the horizontal direction of pixel 203 P, and the distance to the center point Q2 of the right partition is 9 columns of pixels 203, then the OD compensation coefficient for pixel 203 P is K = (K1*9 + K2*2) / 11. If, after the OD compensation table is adjusted, the charging time of the center point of each OD partition is compensated to a consistent level, then according to this linear OD algorithm, the charging time of each column of pixels 203 can be adjusted to be consistent.

[0067] refer to Figure 10 As shown, this fifth embodiment of the present application is a further improvement on the first embodiment described above. Unlike the second embodiment, the display panel 200 in this embodiment is a single-sided driven display panel 200. The gate driving module 110 includes a first gate driving circuit 111, which is connected to the gate line 201. The source driving module 120 includes a first source driving module 121 and a second source driving module 122. The flip-chip film 130 includes multiple first flip-chip films 131 and multiple second flip-chip films 132. The output terminal of the first source driving module 121 is connected to the multiple first flip-chip films 131, and the output terminal of the second source driving module 122 is connected to the multiple second flip-chip films 132. The display panel 200 includes a fan-out region 140, which includes a first fan-out region 141 and a second fan-out region 142. The first fan-out region 141 is provided with a first fan-out sub-region corresponding to each first flip-chip film 131. The length of the fan-out trace 204 in each first fan-out sub-region gradually increases along the first direction. The second fan-out region 142 is provided with a second fan-out sub-region corresponding to each flip-chip film 130. The length of the fan-out trace 204 in each second fan-out sub-region gradually increases along the first direction. The first direction is the direction in which the first gate drive circuit 111 outputs the gate drive signal to the gate line 201. It is divided into two source drive modules, which may correspond to different regions, such as upper and lower parts. Each part uses a different COF and fan-out region 140. In this way, each source drive module only needs to process half of the data line 202, which may reduce the signal load and improve the driving capability. At the same time, separate processing may make it easier to adjust their respective delays, because the wiring conditions of different regions are different and different compensations are required.

[0068] Furthermore, the driving circuit 100 includes a timing control module 150, which is connected to the first source driving module 121 and the second source driving module 122 respectively. The slope of the delay time of the data driving signal output by the first source driving module 121 to the data line 202 is the same as the slope of the delay time of the scan signal output by the first gate driving module 110 to the gate line 201. The slope of the delay time of the data driving signal output by the second source driving module 122 to the data line 202 is the same as the slope of the delay time of the scan signal output by the first gate driving module 110 to the gate line 201. The timing control module 150 adjusts the charging time of the data line 202 connected to each flip-chip film 130 to be consistent through a data delay algorithm. By compensating for delay through structured wiring and dynamically adjusting through timing control algorithm, the core problems of signal delay mismatch and inconsistent charging time in single-sided driven display panel 200 are solved, while optimizing wiring space and production yield.

[0069] Referring to Figure 11, as a sixth embodiment of this application, a driving method is disclosed for driving a display panel using the driving circuit described in any of the above embodiments, the driving method comprising:

[0070] S1: Generates a gate drive signal and outputs it to the gate line; generates a data drive signal and outputs it to the data line via the flip-chip film, the fan-out trace of the fan-out region, and the data line.

[0071] S2: The slope of the delay time of the data drive signal on the control data line is the same as the slope of the delay time of the scan signal on the gate line;

[0072] S3: Ensures that the charging time of each flip-chip film connected to the data line is the same.

[0073] The driving method in this embodiment is mainly used in the driving circuit that has changed the fan-out area wiring arrangement. Normally, the gate driving signal and the data driving signal are generated and output separately. The change in the fan-out area wiring arrangement can reduce the delay problem caused by the load. In order to ensure the display effect, the slope of the delay time of the data driving signal is the same as the slope of the delay time of the scan signal on the gate line. Even if there is a delay, it is a synchronous delay, which ensures uniform brightness.

[0074] Referring to Figure 12, as the seventh embodiment of this application, a driving method is disclosed, which is a further refinement and improvement of the fifth embodiment described above, and is mainly used in the driving circuit 100 in the fourth embodiment. Figure 9 and Figure 12As shown, the gate driving module 110 includes a first gate driving circuit 111 and a second gate driving circuit 112 disposed on both sides of the display panel 200. One end of the gate line 201 is connected to the first gate driving circuit 111, and the other end is connected to the second gate driving circuit 112. The source driving module 120 includes a first source driving module 121 and a second source driving module 122. The flip-chip film 130 includes a plurality of first flip-chip films 131 and a plurality of second flip-chip films 132. The output terminal of the first source driving module 121 is connected to the plurality of first flip-chip films 131. The output terminal of the dual-source drive module 122 is connected to multiple second flip-chip films 132; the display panel 200 includes a fan-out region 140, which includes a first fan-out region 141 and a second fan-out region 142. The first fan-out region 141 is provided with a first fan-out sub-region for each first flip-chip film 131. The length of the fan-out trace 204 in each first fan-out sub-region gradually increases along a first direction. The second fan-out region 142 is provided with a second fan-out sub-region for each flip-chip film 130. The length of the fan-out trace 204 in each second fan-out sub-region gradually increases along a second direction.

[0075] Wherein, the first direction and the second direction are opposite, the first direction is the direction from the first gate driving circuit 111 toward the second gate driving circuit 112, and the second direction is the direction from the second gate driving circuit 112 toward the first gate driving circuit 111; the display panel 200 is divided into at least two regions along the first direction, namely the first region 210 and the second region 220, the data lines 202 of the first region 210 are connected one-to-one with the fan-out traces 204 of the first fan-out area 141, and the data lines 202 of the second region 220 are connected one-to-one with the fan-out traces 204 of the second fan-out area 142; a plurality of pixels 203 are provided in both the first region 210 and the second region 220, and the compensation number of the pixels 203 in the first region 210 and the compensation coefficient of the pixels 203 in the second region 220 are K1 and K2, respectively.

[0076] The driving method further includes the following steps:

[0077] S4: Locate the area where the compensation pixel is located and determine the compensation coefficient;

[0078] S5: Based on the compensation coefficients of adjacent regions and the pixel column of the intermediate pixels between the compensation pixel and the adjacent regions, linear difference is made through the compensation coefficient formula to obtain the compensation coefficient of the pixel to be compensated and generate a compensation table.

[0079] Where m is the pixel column from the compensated pixel to the middle pixel in the first region, and n is the pixel column from the compensated pixel to the middle pixel in the second region. The compensation coefficient formula is as follows:

[0080] K = (K1*n + K2*m) / (m + n).

[0081] This scheme calculates the compensation coefficient for pixel 203 in each source line by linearly interpolating the compensation coefficients of adjacent regions. Taking two adjacent OD partitions with compensation coefficients of K1 and K2 respectively, and pixel 203 point P horizontally specifically two columns of pixels 203 at the center point Q1 of the left partition and nine columns of pixels 203 at the center point Q2 of the right partition as an example, the OD compensation coefficient K for pixel 203 point P is (K1*9+K2*2) / 11. If the charging time of the center point of each OD partition is compensated to a consistent level after the OD compensation table is adjusted, then according to this linear OD algorithm, the charging time of each column of pixels 203 can be adjusted to be consistent.

[0082] Referring to Figure 13, as the eighth embodiment of this application, a driving method is disclosed, which is a further refinement and improvement of the sixth embodiment described above. The difference from the sixth embodiment is that... Figure 2 and Figure 13As shown, the gate driving module 110 includes a first gate driving circuit 111 and a second gate driving circuit 112 disposed on both sides of the display panel 200. One end of the gate line 201 is connected to the first gate driving circuit 111, and the other end is connected to the second gate driving circuit 112. The source driving module 120 includes a first source driving module 121 and a second source driving module 122. The flip-chip film 130 includes a plurality of first flip-chip films 131 and a plurality of second flip-chip films 132. The output terminal of the first source driving module 121 is connected to the plurality of first flip-chip films 131. The output terminal of the dual-source driving module 122 is connected to multiple second flip-chip films 132; the display panel 200 includes a fan-out region 140, which includes a first fan-out region 141 and a second fan-out region 142. The first fan-out region 141 is provided with a first fan-out sub-region corresponding to each first flip-chip film 131. The length of the fan-out trace 204 in each first fan-out sub-region gradually increases along a first direction. The second fan-out region 142 is provided with a second fan-out sub-region corresponding to each flip-chip film 130. The length of the fan-out trace 204 in each second fan-out sub-region gradually increases along a second direction. The first direction and the second direction are opposite. The first direction is the direction from the first gate driving circuit 111 toward the second gate driving circuit 112, and the second direction is the direction from the second gate driving circuit 112 toward the first gate driving circuit 111. The driving circuit 100 includes a timing control module 150, which is connected to the first source driving module 121 and the second source driving module 122 respectively.

[0083] Further reference Figures 6 to 8 As shown, the driving circuit 100 further includes a first delay adjustment circuit 160 and a second delay adjustment circuit 170; the first delay adjustment circuit 160 is disposed on the first source driving module 121, and the first delay adjustment circuit 160 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 corresponding to each fan-out trace 204 connected to each flip-chip film 130 is provided with a resistor and a capacitor, and along the first direction, the resistance value and the capacitance value gradually increase; the second delay adjustment circuit 170 is disposed on the second source driving module 122, the second delay adjustment circuit 170 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 corresponding to each fan-out trace 204 connected to each flip-chip film 130 is provided with a resistor R and a capacitor C, and along the second direction, the resistance value and the capacitance value gradually increase; the step of controlling the slope of the delay time of the data driving signal on the data line to be the same as the slope of the delay time of the scan signal on the gate line includes:

[0084] S21: Along the first direction, obtain the delay time of the data line connected by the first fan-out trace of each flip-chip film and the delay time of the data line connected by the last fan-out trace, and calculate the first change slope of the corresponding flip-chip film connected data line by the first preset formula.

[0085] S22: Along the second direction, obtain the delay time of the gate line connected to the first fan-out line of each flip-chip thin film and the delay time of the gate line connected to the last fan-out line, and calculate the second change slope of the corresponding flip-chip thin film connected data line by the second preset formula.

[0086] S23: Control whether to connect resistors and capacitors according to the first and second slope changes in order to compensate for the delay of the data drive signal.

[0087] Considering that the slope of the delay time change of the data drive signal on the control data line may not be completely canceled out when it is the same as the slope of the delay time change of the scan signal on the gate line, the delay change slope of the flip-chip (COF) fan-out trace is calculated in two directions (first direction / second direction), and delay compensation is performed by dynamically adding resistors and capacitors based on the slope. By analyzing the slope in two directions and dynamic RC compensation, the timing problem caused by the delay gradient of the fan-out trace is solved. By inserting an RC delay element in series on the source driver output, the values ​​of R and C are selected according to the actual situation, and compensation is performed based on the actual difference in the charging direction of the source line on each COF, so that the actual charging of the source line of each COF is consistent.

[0088] Step S3 further includes the following steps:

[0089] S31: The timing control module adjusts the charging time of the data lines connected to each flip-chip film to be consistent through a data delay algorithm.

[0090] In this embodiment, step S31 is performed after step S2. In step S1, a gate drive signal is generated to the gate line 201, and a data drive signal is sequentially generated to the die-on-film 130, the fan-out area 140 trace, and the data line 202. The gate drive signal is used to control the selection of the gate line 201, lighting up the pixels 203 line by line, while the data drive signal transmits image data to the pixels 203. The die-on-film 130 (COF) refers to the chip being directly mounted on a flexible film. The fan-out area 140 trace may be used to connect the COF to a denser wiring area, such as reducing signal delay or improving accuracy. In step S2, the delay slope of the data drive signal is controlled to be the same as the delay slope of the scan signal, so that the timing of the data and scan signals is synchronized, avoiding data errors caused by the gate line 201 not being selected when the data arrives. If the delay slopes of the two are the same, the synchronization of the signals may be better at different gray levels or different positions, reducing image anomalies such as ghosting or color difference. In step S31, considering that the charging time of different data lines 202 is different due to differences in physical length or load, the charging time of all data lines 202 is made the same through algorithm compensation, thereby ensuring the consistency of the voltage of the pixel 203 and improving the uniformity of display. Therefore, the timing control module 150 uses a data delay algorithm to adjust the charging time of the data lines 202 connected to each flip-chip film 130 to be consistent.

[0091] Referring to Figure 14, as a ninth embodiment of this application, a display device 300 is disclosed. The display device 300 includes a display panel 200 and a driving circuit 100 as described in any of the above embodiments. The driving circuit 100 drives the display panel 200 using the driving method described in any of the above embodiments.

[0092] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0093] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A drive circuit for driving a display panel, the display panel comprising a plurality of data lines arranged in a horizontal direction and a plurality of gate lines arranged in a vertical direction, characterized by, The driving circuit comprises a gate driving module, a source driving module and a plurality of chip on film (COF) modules, the gate driving module outputs gate driving signals to gate lines, the source driving module outputs data driving signals to the COF modules, the data driving signals are output to data lines through the COF modules and fan-out lines of fan-out areas, the COF modules are arranged in a plurality of groups, the length of the fan-out lines of the fan-out areas corresponding to each COF module gradually increases in the transmission direction of the gate driving signals, the driving circuit controls the variation slope of the delay time of the data driving signals on the data lines to be the same as the variation slope of the delay time of the scanning signals on the gate lines, and controls the charging time of the data lines connected to each COF module to be the same.

2. The drive circuit of claim 1, wherein, The gate driving module comprises a first gate driving circuit and a second gate driving circuit arranged on both sides of the display panel, one end of the gate line is connected to the first gate driving circuit, and the other end is connected to the second gate driving circuit. The source driving module comprises a first source driving module and a second source driving module, the COF modules comprise a plurality of first COF modules and a plurality of second COF modules, the output end of the first source driving module is connected to the plurality of first COF modules, and the output end of the second source driving module is connected to the plurality of second COF modules. The display panel comprises a fan-out area, the fan-out area comprises a first fan-out area and a second fan-out area, the first fan-out area is provided with a first fan-out sub-area corresponding to each first COF module, the length of the fan-out lines in each first fan-out sub-area gradually increases in a first direction, and the second fan-out area is provided with a second fan-out sub-area corresponding to each COF module, the length of the fan-out lines in each second fan-out sub-area gradually increases in a second direction. The first direction and the second direction are opposite, the first direction is the direction of the first gate driving circuit towards the second gate driving circuit, and the second direction is the direction of the second gate driving circuit towards the first gate driving circuit.

3. The drive circuit of claim 2, wherein, The driving circuit comprises a timing control module, the timing control module is connected to the first source driving module and the second source driving module respectively. The variation slope of the delay time of the data driving signals output by the first source driving module to the data lines is the same as the variation slope of the delay time of the scanning signals output by the first gate driving module to the gate lines, the variation slope of the delay time of the data driving signals output by the second source driving module to the data lines is the same as the variation slope of the delay time of the scanning signals output by the second gate driving module to the gate lines, and the timing control module adjusts the charging time of the data lines connected to each COF module to be consistent through a data delay algorithm.

4. The drive circuit of claim 2, wherein, The driving circuit further comprises a first delay adjustment circuit and a second delay adjustment circuit. The first delay adjustment circuit is arranged on the first source driving module, the first delay adjustment circuit comprises a plurality of sub-adjustment circuits, each sub-adjustment circuit is provided with a resistor and a capacitor corresponding to all the fan-out lines connected to each COF module, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase in the first direction. The second delay adjustment circuit is arranged on the second source driving module, and the second delay adjustment circuit comprises a plurality of sub-adjustment circuits, each sub-adjustment circuit is provided with a resistor and a capacitor for each fan-out wire of each CTF, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the second direction.

5. The drive circuit of claim 2, wherein, The display panel is divided into at least two regions along the first direction, and the two regions are a first region and a second region respectively, the data lines in the first region are connected to the fan-out wires in the first fan-out area one by one, and the data lines in the second region are connected to the fan-out wires in the second fan-out area one by one. A plurality of pixels are arranged in the first region and the second region, and the compensation coefficients of the pixels in the first region and the second region are K1 and K2 respectively. The compensation coefficient of each pixel on each data line is obtained by linear difference of the compensation coefficients of adjacent regions, and the charging time of each column of pixels is adjusted to be consistent.

6. The drive circuit of claim 1, wherein, The gate driving module comprises a first gate driving circuit, and the first gate driving circuit is connected to the gate lines. The source driving module comprises a first source driving module and a second source driving module, the CTF comprises a plurality of first CTFs and a plurality of second CTFs, the output end of the first source driving module is connected to the plurality of first CTFs, and the output end of the second source driving module is connected to the plurality of second CTFs. The display panel comprises a fan-out area, the fan-out area comprises a first fan-out area and a second fan-out area, the first fan-out area is provided with a first fan-out sub-area corresponding to each first CTF, the length of the fan-out wire in each first fan-out sub-area gradually increases along the first direction, the second fan-out area is provided with a second fan-out sub-area corresponding to each CTF, and the length of the fan-out wire in each second fan-out sub-area gradually increases along the first direction. The first direction is the direction in which the first gate driving circuit outputs the gate driving signal to the gate line.

7. A driving method for driving the driving circuit according to any one of claims 1 to 6, wherein The driving method comprises: generating a gate driving signal output to a gate line and generating a data driving signal through a CTF, fan-out wires of a fan-out area and output to a data line; controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line; and controlling the charging time of the data line connected to each CTF to be the same.

8. The driving method according to claim 7, wherein Each CTF is connected to a resistor and a capacitor, and the step of controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line comprises: along the first direction, obtaining the delay time of the data line connected to the first fan-out wire and the delay time of the data line connected to the last fan-out wire corresponding to each CTF, and calculating the first change slope of the data line connected to the corresponding CTF through a first preset formula. In the second direction, the delay time of the gate line connected with the first fan-out wire of each fan-out thin film and the delay time of the gate line connected with the last fan-out wire are obtained, and a second change slope of the data line connected with the corresponding fan-out thin film is calculated by using a second preset formula; The first change slope and the second change slope are used to control whether to connect the resistance and the capacitance to compensate the delay of the data driving signal.

9. The driving method according to claim 7, wherein The display panel is divided into at least two regions in the first direction, and the two regions are a first region and a second region. The data lines in the first region are connected with the fan-out wires in the first fan-out area one by one, and the data lines in the second region are connected with the fan-out wires in the second fan-out area one by one. A plurality of pixels are arranged in the first region and the second region. The compensation coefficient of the pixels in the first region and the compensation coefficient of the pixels in the second region are K1 and K2 respectively. The driving method further comprises the following steps: The region where the compensation pixel is located is positioned, and the compensation coefficient is determined; The compensation coefficient of the compensation pixel is obtained by linear difference of the compensation coefficient formula according to the compensation coefficient of the adjacent region and the pixel column of the intermediate pixel between the compensation pixel and the adjacent region, and a compensation table is generated; Wherein, m is the pixel column of the intermediate pixel between the compensation pixel and the first region, n is the pixel column of the intermediate pixel between the compensation pixel and the second region, and the compensation coefficient formula is as follows: K= (K1*n+K2*m) / (m+n).

10. A display device, characterized by comprising: The display device comprises a display panel and a driving circuit according to any one of claims 1-6, and the driving circuit is driven by the driving method according to any one of claims 7-9.

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