Chip packaging structure and electronic equipment

Abstract

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of packaging, and can solve the problem that the area of an adapter plate is increased due to the arrangement of a connector. The chip packaging structure comprises an adapter plate, at least one first chip, at least one second chip, a supporting structure and a connector. The first chip is arranged on the front face of the adapter plate and electrically connected with the adapter plate. And the second chip is arranged on the back surface of the adapter plate and is electrically connected with the adapter plate. The supporting structure is arranged on the edge of the adapter plate and forms a fan-out area. The connector is used for being connected with an external device, is located on the back face of the supporting structure and is electrically connected with the back face of the adapter plate, that is, the connector is borne through the supporting structure, so that the area of the adapter plate can be reduced, and the cost of the packaging structure is reduced.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] System-in-a-package (SiP) technology is an integrated circuit packaging technology that integrates multiple dies and passive components into a single package. In the post-Moore era, SiP technology can help increase the integration density of finished chips, reduce their size, and lower power consumption.

[0003] refer to Figure 1 As shown, in existing system-integrated packaging structures, the need for both backside vertical power delivery and direct-outlet connector technology requires a power module to be placed on the backside of the adapter board, corresponding to the vertical projection area of ​​the chip. This power module competes with the connector for the limited backside area of ​​the package. This means that the connector mounted on the backside of the adapter board inevitably expands the overall package area. Without changing the package structure, a larger adapter board area is required to accommodate the connector.

[0004] Due to the complex structure of the adapter board, as the area of ​​the adapter board increases, the packaging cost will increase significantly and bring about a worse structural stress risk. Summary of the Invention

[0005] The present application provides a chip packaging structure and an electronic device, which can solve the problem of an increase in the area of ​​an adapter board due to the provision of a connector.

[0006] The present application provides a chip packaging structure, comprising an adapter board, at least one first chip, at least one second chip, a support structure, and a connector. The first chip is disposed on the front of the adapter board and electrically connected to the adapter board. The second chip is disposed on the back of the adapter board and electrically connected to the adapter board. The support structure is disposed at the edge of the adapter board and forms a fan-out region. The connector is used to connect to an external device and is located on the back of the support structure and electrically connected to the back of the adapter board.

[0007] The chip packaging structure is configured to extend a fan-out area at the edge of the adapter board by setting a support structure on the side of the adapter board, and the connector located on the back of the adapter board is set in the fan-out area. In this case, the connector can be supported by the support structure, thereby reducing the area occupied by the adapter board and the area of ​​at least part of the film layer in the adapter board, thereby reducing the production cost of the adapter board (or packaging structure).

[0008] In some possible implementations, the support structure is on the side of the adapter plate, thereby reducing the overall area of ​​the adapter plate and lowering the manufacturing cost of the adapter plate.

[0009] In some possible implementations, the adapter board includes an upper connection layer and a lower connection layer that are stacked together, and the first chip is disposed on a surface of the upper connection layer and electrically connected to the upper connection layer. The edge of the lower connection layer protrudes from the edge of the upper connection layer, and the support structure is disposed on the lower connection layer that protrudes from the edge of the upper connection layer. Because the upper connection layer uses a routing layer with a smaller line width, line spacing, and line thickness, while the lower connection layer uses a routing layer with a larger line width, line spacing, and line thickness, the manufacturing cost of the upper connection layer is much higher than that of the lower connection layer. In this configuration, the support structure can be disposed on the side of the upper connection layer to reduce the area of ​​the upper connection layer.

[0010] In some possible implementations, the chip packaging structure further includes a substrate, which is located between the connector and the adapter board, and the connector is electrically connected to the back surface of the adapter board through the substrate.

[0011] In some possible implementations, the support structure is a dummy die.

[0012] In some possible implementations, the support structure includes one or more of silicon, metal, ceramic, organic sheet, resin, or thermosetting adhesive.

[0013] In some possible implementations, the adapter board includes a silicon interposer and a redistribution layer. The redistribution layer is disposed on the backside of the silicon interposer and electrically connected to the silicon interposer. The edges of the silicon interposer and the redistribution layer are flush, and support structures are located on the sides of the silicon interposer and the redistribution layer to form a fan-out area on the side of the adapter board. This fan-out area provides sufficient support for the connector, thereby reducing the area of ​​the silicon interposer and the redistribution layer.

[0014] In some possible implementations, the adapter board includes: a silicon interposer and a redistribution layer. The redistribution layer is arranged on the back of the silicon interposer and is electrically connected to the silicon interposer. The silicon interposer serves as all or part of the above-mentioned upper connection layer, and the redistribution layer serves as all or part of the above-mentioned lower connection layer. In this case, the edge of the redistribution layer protrudes from the edge of the silicon interposer, and the support structure is arranged on the redistribution layer protruding from the edge of the silicon interposer to form a fan-out area on the side of the silicon interposer. In this case, the connector can be arranged on the back of the redistribution layer corresponding to the fan-out area (that is, the side away from the support structure) to reduce the area of ​​the silicon interposer.

[0015] In some possible implementations, the adapter board includes: a first redistribution layer and a second redistribution layer arranged in a stacked manner. The first redistribution layer is closer to the first chip than the second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected. The edges of the first redistribution layer and the second redistribution layer are flush, and support structures are provided on the sides of the first and second redistribution layers to form a fan-out area on the side of the adapter board. The fan-out area satisfies the load requirements of the connector, thereby reducing the area of ​​the first and second redistribution layers.

[0016] In some possible implementations, the adapter board includes: a first redistribution layer and a second redistribution layer that are stacked. The first redistribution layer is close to the first chip relative to the second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected. The first redistribution layer serves as all or part of the upper connection layer, and the second redistribution layer serves as all or part of the lower connection layer. In this case, the edge of the second redistribution layer protrudes from the edge of the first redistribution layer, and the support structure is provided on the redistribution layer that protrudes from the edge of the first redistribution layer to form a fan-out area on the side of the first redistribution layer. In this case, the connector can be provided on the back side of the second redistribution layer corresponding to the fan-out area (that is, the side away from the support structure) to reduce the area of ​​the first redistribution layer.

[0017] In some possible implementations, the adapter board further includes a bridge chip disposed between the first redistribution layer and the second redistribution layer, wherein an active surface of the bridge chip faces the first redistribution layer and is electrically connected to the first redistribution layer.

[0018] In some possible implementations, the adapter board further includes a metal through-hole disposed between the first redistribution layer and the second redistribution layer, wherein the first redistribution layer is electrically connected to the second redistribution layer through the metal through-hole.

[0019] In some possible implementations, the metal via is a molded via or a through-glass via.

[0020] In some possible implementations, the line width, line spacing, and line thickness of the metal lines in the first redistribution are all less than 5 μm.

[0021] In some possible implementations, the line width, line spacing, and line thickness of the metal traces in the second redistribution layer are all greater than 5 μm.

[0022] In some possible implementations, the at least one first chip includes one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0023] In some possible implementations, the at least one second chip includes one or more of a power supply module, a control module, a clock device, a rectifier, and a resistor, capacitor, and inductor.

[0024] In some possible implementations, the chip packaging structure includes multiple first chips and multiple second chips. The multiple second chips include multiple power supply modules, each of which is disposed opposite the multiple first chips. The power supply modules are electrically connected to the oppositely disposed first chips via an adapter board and provide power to the first chips.

[0025] The present application also provides an electronic device, which includes a circuit board and a chip packaging structure provided in any of the possible implementation methods described above, and the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a chip packaging structure provided in the prior art;

[0027] Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of the distribution of support structures in a chip packaging structure provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the distribution of support structures in a chip packaging structure provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of the distribution of support structures in a chip packaging structure provided in an embodiment of the present application;

[0031] Figure 6 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0033] Figure 8 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0034] Figure 9 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0035] Figure 10 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0036] Figure 11 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0037] Figure 12A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0038] Figure 13 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0039] Figure 14 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0040] Figure 15 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0041] Figure 16 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0042] Figure 17 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0043] Figure 18 A schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application;

[0044] Figure 19 A schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application;

[0045] Figure 20 A schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application;

[0046] Figure 21 A schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0049] An embodiment of the present application provides an electronic device that adopts a new chip packaging structure. The chip packaging structure forms a fan-out area by setting a support structure (also called a placeholder structure) at the edge of the adapter board, and sets the connector in the fan-out area, thereby solving the problem of increased area of ​​the adapter board due to the setting of the connector and reducing the stress risk of the packaging structure.

[0050] This application does not limit the setting form of the above-mentioned electronic device. The electronic device can be any electronic product with a chip packaging structure, such as consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0051] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0052] According to actual needs, the above-mentioned electronic device may also be provided with other devices electrically connected to the chip packaging structure, such as a printed circuit board (PCB; also called a printed circuit board), input and output devices, etc., and this application does not impose any restrictions on this.

[0053] The novel chip packaging structure provided by the present application is described in detail below through specific embodiments.

[0054] Example 1

[0055] Indicative, such as Figure 2 As shown, this embodiment provides a chip package structure 01, which includes an adapter board 10, at least one first chip D, and at least one second chip 20. The first chip D is disposed on the front surface of the adapter board 10 and is electrically connected to the front surface of the adapter board 10. The second chip 20 is disposed on the back surface of the adapter board 10 and is electrically connected to the back surface of the adapter board 10.

[0056] The above-mentioned first chip D can be a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output chip (I / O), an integrated passive device (IPD), etc., or it can be an integrated packaged functional module such as HBM (high bandwidth memory), DOI (die on silicon interposer), FOI (fan out RDL interpose), etc. In practice, multiple first chips D can be set as needed.

[0057] The second chip 20 can be a power supply module, a control module, a clock device, a rectifier, a resistor, a capacitor, etc. In practice, multiple second chips 20 can be provided as needed. Schematically, the second chip 20 can include a bare chip and other electronic components connected to the bare chip.

[0058] The embodiments of the present application are described by taking the chip package structure 10 provided with multiple first chips D and multiple second chips 20 as an example, but the present invention is not limited thereto.

[0059] As shown, in some possible implementations, the multiple second chips 20 on the back of the adapter board 10 may include multiple power supply modules, and the multiple power supply modules are respectively arranged opposite the multiple first chips D above. That is, the multiple power supply modules are respectively located directly below the multiple first chips D, and the multiple power supply modules are respectively located in the vertical projection area of ​​the multiple chips. The multiple power supply modules are vertically electrically connected to the multiple first chips D above through the adapter board 10, so that the multiple power supply modules can respectively provide vertical power to the multiple first chips D located above.

[0060] For illustration, the power supply module may be a VRM (voltage regulator module) or other modules related to electrical transmission, voltage transformation, and rectification, and this application does not impose any restrictions on this.

[0061] On this basis, continue to refer to Figure 2As shown, the chip package structure 01 further includes a connector 21 and a support structure 30. The support structure 30 is provided on the side of the adapter board 10, thereby extending to form a fan-out area F1 on the side of the adapter board 10. The connector 21 is provided on the back of the support structure 30 (i.e., located in the fan-out area F1), and the connector 21 is connected to the back of the adapter board 10. In this case, a substrate 40 can be provided between the connector 21 and the support structure 30, and the substrate 40 extends laterally from the fan-out area F1 to the back of the adapter board 10. In this way, the connector 21 can be electrically connected to the back of the adapter board 10 through the substrate 40, so that the signal of the first chip D (such as IO die) can be transmitted outward through the adapter board 10.

[0062] The connector 21 being located on the back of the support structure 30 means that the connector 21 is located in the fan-out area F1 formed by the support structure 30 at the edge of the package structure, and the connector 21 is located in the vertical projection area corresponding to the support structure 30 .

[0063] The above-mentioned connector can be an electrical connector for transmitting electrical signals, or it can be an optoelectronic conversion connector (ie, an optical connector) for transmitting optical signals. This application does not impose any restrictions on this, and it can be set up according to actual needs.

[0064] To sum up, in the chip packaging structure provided in the first embodiment, a support structure 30 is provided on the side of the adapter board 10, thereby extending the side of the adapter board 10 to form a fan-out area F1, and the connector 21 located on the back of the adapter board 10 is provided in the fan-out area F1. In this case, the connector 10 can be supported by the support structure 30 without occupying the area of ​​the adapter board 10, thereby reducing the area of ​​the adapter board 10 and reducing the production cost of the adapter board 10 (or the packaging structure).

[0065] The following is a brief description of the arrangement of the support structure 30 .

[0066] Indicative, reference Figure 2 As shown, during the manufacturing process of the chip packaging structure, a thermosetting material may be used to fill the gap between the support structure 30, the first chip D, and the adapter plate 10. After filling, the back surface of the first chip D and the surface of the support structure 30 may be exposed by grinding. In this case, the first chip D and the upper surface of the support structure 30 (i.e., the surface away from the adapter plate 10) are flush.

[0067] Of course, in other possible implementations, the upper surface of the first chip D may protrude from the upper surface of the support structure 30, that is, the upper surface of the support structure 30 is lower than the upper surface of the first chip D. In this case, the thermosetting material may fill the gap between the surface of the support structure 30 and the surface of the first chip D.

[0068] In addition, the support structure 30, the first chip D and the adapter plate 10 can be plastic-sealed using a multiple filling process. This application does not impose any restrictions on this, and in practice, they can be selected and set according to production needs.

[0069] The thermosetting materials mentioned in this application may include underfill (UF), molded underfill (MUF), epoxy molding compound, etc. The thermosetting materials mentioned below are all the same and will not be described again.

[0070] The present application does not impose any limitation on the specific material of the support structure 30 , as long as the support structure 30 can be filled on the side of the adapter board 10 to form a fan-out area.

[0071] For example, in some possible implementations, the support structure 30 may be made of one or more materials selected from silicon, metal, ceramic, organic sheet, resin, or other thermosetting adhesives.

[0072] For example, in some possible implementations, the support structure 30 may be a dummy die, that is, the support structure 30 is made of the same material as a conventional chip (such as a silicon wafer), but does not have any circuit or logic functions.

[0073] In addition, the present application does not impose any restrictions on the shape, quantity, specifications, size, etc. of the support structure 30, and it can be set according to actual needs.

[0074] For example, in some possible implementations, Figure 3 As shown, the support structure 30 may be an annular structure. In this case, the adapter plate 10 is disposed inside the annular structure.

[0075] For example, in some possible implementations, Figure 4 、 Figure 5 As shown, the support structure 30 can be block-shaped or strip-shaped. In this case, the support structure 30 is distributed along the side of the adapter plate 10. According to actual needs, one support structure 30 can be set on one side of the adapter plate 10, or multiple support structures 30 can be set.

[0076] In addition, reference Figure 6 As shown, in order to meet the different electrical requirements of the multiple electrode elements 20 and the connector 21, in some possible implementations, the multiple electrode elements 20 and the connector 21 can be electrically connected to the adapter board 10 through multiple separate substrates 40. The number of layers and specifications of the multiple substrates 40 may not be exactly the same.

[0077] In practice, the assembly correspondence between the electrode element 20 and the connector 21 and the substrate 40 can be set according to the needs. For example, a single substrate 40 can be mounted with one second chip 20 or one connector 21, or multiple second chips 20 or multiple connectors 21, or a second chip 20 and a second connector 22 at the same time.

[0078] It should be understood that by providing multiple discrete substrates 40, the types of the multiple substrates 40 can be flexibly selected based on the electrical requirements of the electrode elements 20 and connectors 21, thereby improving the performance of the entire system. For example, a multi-layer substrate may be configured only for the second chip 20 requiring a complex multi-layer substrate, while a simple substrate may be configured for the second chip 20 requiring a simple substrate.

[0079] In addition, the use of multiple discrete substrates 40 can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought about by a large continuous substrate, which is more friendly to system assembly and service reliability.

[0080] The present application does not impose any restrictions on the electrical connection method between the substrate 40 and the adapter board 10 , and it can be set as needed in practice.

[0081] As an illustration, in some possible implementations, the plurality of substrates 40 and the adapter plate 10 may be connected to each other by one or a combination of connection methods such as welding, crimping, and plugging.

[0082] The above-mentioned multiple substrates 40 can be manufactured using one or more of the following processes: substrate process, carrier-like process, printed circuit board (PCB) process or other intermediate transition board processes, and this application does not impose any restrictions on this.

[0083] In addition, reference Figure 6 As shown, in some possible implementations, the chip packaging structure may further include a first heat sink 41 and a second heat sink 42. The first heat sink 41 is disposed on a side of the plurality of first chips D away from the adapter plate 10, and the second heat sink 42 is disposed on a side of the plurality of second chips 20 away from the adapter plate 10. The two heat sinks (41, 42) are provided to meet the heat dissipation requirements of the chip packaging structure.

[0084] As shown, the gap between the first chip D and the first heat sink 41 can be filled with thermal interface materials (TIM). The TIM can be a heat dissipation medium such as thermal gel, thermal grease, graphene, or liquid metal, and is not limited here. Similarly, the gap between the second chip 20 and the second heat sink 42 can also be filled with TIM.

[0085] The present application does not impose any restrictions on the arrangement of the heat dissipation plates (41, 42), which can be arranged as needed in practice.

[0086] For example, in some possible implementations, the heat dissipation plates (41, 42) may be metal cover plates.

[0087] For another example, in some possible implementations, the heat sinks (41, 42) may be hollow structures to support water cooling or liquid cooling.

[0088] For another example, the heat sink (41, 42) may have a hollow structure such as a through-hole structure or a grid. In this case, the heat sink can meet the heat dissipation requirements while supporting the external power supply system to be vertically interconnected with the electrical components 20 on the back of the chip through the hollow area.

[0089] The thickness, material and structure of the first heat dissipation plate 41 and the second heat dissipation plate 42 may be the same or different, and this application does not impose any limitation thereto.

[0090] In addition, reference Figure 6 As shown, in some possible implementation methods, in order to ensure balanced force inside the chip packaging structure, a support frame 43 can be set in the chip packaging structure. The support frame 43 is located in the gap between the second chips 20, and the upper end of the support frame 43 can contact the substrate 40, and the lower end can contact the second heat sink 42.

[0091] On this basis, in order to fix the first heat sink 41, the second heat sink 42 and the packaging system, as shown in FIG. Figure 6 As shown, in some possible implementations, a fixing structure 50 may be provided to penetrate the first heat dissipation plate 41 , the second heat dissipation plate 42 and the adapter plate 10 to support and fix the first heat dissipation plate 41 , the second heat dissipation plate 42 and the adapter plate 10 .

[0092] Indicative, such as Figure 6 As shown, in some possible implementations, the fixing structure 50 may include bolts and nuts. The bolts pass through the first heat sink 41, the second heat sink 42, and the adapter plate 10, and the nuts are fixed to one end of the bolts, thereby securing the first heat sink 41, the second heat sink 42, and the adapter plate 10. In this case, the first heat sink 41 and the second heat sink 42 not only provide heat dissipation but also stabilize the structure.

[0093] In addition, in the first embodiment, there is no limitation on the configuration of the adapter board 10 , and in practice, the configuration can be made according to the requirements of the packaging structure.

[0094] For illustration, five different configurations of the adapter plate 10 are provided below.

[0095] Setting method 1

[0096] Indicative, reference Figure 7 As shown, in some possible implementations, the adapter board 10 may include a silicon interposer 1 (Si interposer) and a redistribution layer RDL (redistribution layer) arranged on the back of the silicon interposer 1. The silicon interposer 1 (Si interposer) includes a silicon wafer a1 (wafer) and a metal routing layer a2 arranged on the front side of the silicon wafer a1 (i.e., the surface away from the RDL side). A plurality of through silicon vias TSV (through silicon via) are provided in the silicon wafer a1. The metal routing layer a2 is connected to the redistribution layer RDL through a plurality of through silicon vias TSV. The first chip D is provided on the front side of the silicon interposer (Si interposer) and is electrically connected to the metal routing layer a2. The second chip 20 and the connector 21 are located below the redistribution layer RDL (i.e., on the side away from the silicon wafer a1) and are electrically connected to the redistribution layer RDL through the substrate 40.

[0097] It should be understood that the front side of the silicon interposer is the surface on which the metal trace layer a2 is disposed. The back side of the silicon interposer is the surface on the side of the silicon wafer a1 that is not provided with the metal trace layer a2, i.e., the side connected to the redistribution layer RDL.

[0098] refer to Figure 7 As shown, in the first setting mode, the edge of the silicon interposer 1 can be flush with the edge of the redistribution layer RDL, and the support structure 30 is arranged outside the edge of the silicon interposer 1 and the redistribution layer RDL to form a fan-out area F1. The fan-out area F1 meets the bearing capacity of the connector 21, thereby reducing the area of ​​the silicon interposer 1 and the redistribution layer RDL.

[0099] The following briefly describes the configuration of the silicon interposer 1, the metal routing layer a2, the redistribution layer RDL, the through silicon via TSV, and the like.

[0100] For the metal routing layer a2 on the surface of the silicon interposer 1 (Si interposer), the metal routing layer a2 can be processed through a silicon-based process, so that the line width / line spacing / line thickness in the metal routing layer a2 can be less than 5μm, thereby being able to meet the high bandwidth density interconnection requirements between multiple first chips D, such as an interconnection bandwidth density of more than 2Tbps / mm.

[0101] For example, in some possible implementations, the metal wiring layer a2 may be implemented using a damascene process including deposition, exposure, etching, electroplating, chemical mechanical polishing (CMP), and other processes.

[0102] As an illustration, in some possible implementations, the line width / line spacing / line thickness in the metal routing layer a2 can be ≥0.4 μm, and the number of layers can be processed to more than 3 layers.

[0103] Illustratively, in some possible implementations, the wiring layer in the metal routing layer a2 may be made of copper (Cu), but is not limited thereto.

[0104] In some possible implementations, the dielectric layer in the metal wiring layer a2 can be made of one or more insulating dielectric materials such as polyimide (PI), polybenzoxazoles (PBO), silicon dioxide SiO2, silicon nitride SiN, and silicon carbon nitride SiCN, but is not limited thereto.

[0105] The above-mentioned redistribution layer RDL can adopt a thick metal layer and a thick dielectric layer with better current sharing capability. For example, the line width / line spacing / line thickness of the redistribution layer RDL can be above 5μm, thereby being able to meet the second chip 20 and the connector 21 for high-speed serdes (serializer / deserializer, serializer / deserializer) driving requirements with large current sharing capability, low impedance, and long distance (such as above 5mm).

[0106] For example, in some possible implementations, the redistribution layer (RDL) may be implemented through a yellow light process including steps such as coating / filming, exposure, development, and curing.

[0107] For example, in some possible implementations, the wiring layer in the redistribution layer RDL may be made of copper (Cu), but is not limited thereto.

[0108] For example, in some possible implementations, the dielectric layer in the redistribution layer RDL may be made of one or more dielectric materials such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but is not limited thereto.

[0109] Illustratively, in some possible implementations, the thickness of the silicon interposer 1 may be in the range of 5 μm to 200 μm.

[0110] For example, in some possible implementations, the aperture of the through silicon via (TSV) may be in the range of 1 μm to 30 μm.

[0111] Setting method 2

[0112] Indicative, such as Figure 8 As shown, in some possible implementations, the adapter board 10 may include: a first redistribution layer RDL1 and a second redistribution layer RDL2 that are stacked. The first redistribution layer RDL1 is closer to the first chip D than the second redistribution layer RDL2. A plurality of first chips D are arranged on the upper surface of the first redistribution layer RDL1 (that is, the surface away from the side of the second redistribution layer RDL2) and are electrically connected to the first redistribution layer RDL1. A plurality of second chips 20 and connectors 21 are arranged below the second redistribution layer RDL2 (that is, away from the side of the first redistribution layer RDL1) and are electrically connected to the second redistribution layer RDL2 through the substrate 40.

[0113] refer to Figure 8 As shown, in the second setting method, the edge of the first rewiring layer RDL1 and the edge of the second rewiring layer RDL2 can be flush, and the support structure 30 forms a fan-out area F1 outward from the edge of the first rewiring layer RDL1 and the second rewiring layer RDL2. In this fan-out area F1, the support structure 20 can meet the bearing capacity of the connector 21, thereby reducing the area of ​​the adapter board 10.

[0114] The first redistribution layer RDL1 and the second redistribution layer RDL2 are briefly described below.

[0115] In some possible implementations, the first redistribution layer RDL1 may be formed of a thin metal layer and a thin dielectric layer, with line width, line spacing, and line thickness of less than 5 μm. In this case, the first redistribution layer RDL1 can meet the high-bandwidth interconnection requirements between the first chips D.

[0116] Schematically, in some possible implementations, the second redistribution layer RDL2 can use thick metal layers and thick dielectric layers, such as line width / line spacing / line thickness can be above 5μm, thereby meeting the requirements of large current sharing and long routing capabilities of the second chip 20 and connector 21.

[0117] For example, in some possible implementations, the first redistribution layer RDL1 and the second redistribution layer RDL2 can be implemented using a photolithography process including steps such as coating / laminating, exposure, development, and curing.

[0118] Illustratively, in some possible implementations, the wiring layers in the first redistribution layer RDL1 and the second redistribution layer RDL2 may be made of copper (Cu), but the present invention is not limited thereto.

[0119] Schematically, in some possible implementations, the dielectric layer in the first redistribution layer RDL1 and the second redistribution layer RDL2 can adopt one or more dielectric materials such as polyimide polymer (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), etc., but is not limited to this.

[0120] Setting method three

[0121] Indicative, such as Figure 9 As shown, in some possible implementations, the adapter board 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a molded interposer 100. The molded interposer 100 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and the molded interposer 100 includes at least one molded through-molding via TMV (throughmolding via) and at least one bridge chip BG (bridge die). The second redistribution layer RDL2 can be electrically connected to the first redistribution layer RDL1 through the bridge chip BG and the metal pillar P. According to actual needs, a through-silicon via can be provided in the bridge chip BG, and electrically connected to the second redistribution layer RDL2 through the through-silicon via.

[0122] The configuration of the first redistribution layer RDL1, the second redistribution layer RDL2, the first chip D, and the second chip 20 may refer to the corresponding description in the aforementioned configuration method 2, which will not be repeated here.

[0123] It should be understood that the bridge chip BG has a similar structure to the aforementioned Si interposer. The bridge chip BG can be manufactured using a silicon-based process or a glass process, so that the line width / line spacing / line thickness can meet the high bandwidth density interconnection requirements between the first chips D.

[0124] In this setting method three, refer to Figure 9 As shown, the edges of the first redistribution layer RDL1, the molded interposer 100 and the second redistribution layer RDL2 can be flush, and the support structure 30 forms a fan-out area F1 outward from the edges of the first redistribution layer RDL1, the molded interposer 100 and the second redistribution layer RDL2. In this fan-out area F1, the support structure 30 can meet the bearing capacity of the connector 21, thereby reducing the area of ​​the adapter board 10.

[0125] Setting method four

[0126] Indicative, such as Figure 10As shown, in some possible implementations, the adapter board 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200. The glass interposer 200 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and the glass interposer 200 includes at least one through-glass via TGV (throughglass via) and at least one bridge chip BG (bridge die). The bridge chip BG is embedded in a groove provided on the glass wafer. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the bridge chip BG and the through-glass via TGV. According to actual needs, a through-silicon via may be provided in the bridge chip BG, and electrically connected to the second redistribution layer RDL2 through the through-silicon via.

[0127] The configuration of the first redistribution layer RDL1, the second redistribution layer RDL2, the first chip D, and the second chip 20 may refer to the corresponding description in the aforementioned configuration method 2, which will not be repeated here.

[0128] It should be understood that the bridge chip BG has a similar structure to the aforementioned Si interposer. Since the bridge chip BG can be manufactured using a silicon-based process, the line width / line spacing / line thickness can meet the high bandwidth density interconnection requirements between the first chips D.

[0129] In this setting method 4, refer to Figure 10 As shown, the edges of the first redistribution layer RDL1, the glass interposer 200 and the second redistribution layer RDL2 can be flush, and the support structure 30 forms a fan-out area F1 outward from the edges of the first redistribution layer RDL1, the glass interposer 200 and the second redistribution layer RDL2. In this fan-out area F1, the support structure 30 can meet the load-bearing requirements of the connector 21, thereby reducing the area of ​​the adapter board 10.

[0130] Setting method five

[0131] Indicative, such as Figure 11 As shown, in some possible implementations, the interposer 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200. The glass interposer 200 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and includes a plurality of through glass vias (TGVs) in the glass interposer 200. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 via the plurality of through glass vias (TGVs).

[0132] The configuration of the first redistribution layer RDL1, the second redistribution layer RDL2, the first chip D, and the second chip 20 may refer to the corresponding description in the aforementioned configuration method, which will not be repeated here.

[0133] As shown, in some cases, the first redistribution layer RDL1 may be realized using an inorganic medium through a Damascus process including deposition, exposure, etching, electroplating, CMP and other processes; or an organic medium may be realized through a yellow light process including coating / filming, exposure, development, curing and other processes; for details, please refer to the relevant description in the previous text.

[0134] In the fifth setting, refer to Figure 10 As shown, the edges of the first redistribution layer RDL1, the glass interposer 200 and the second redistribution layer RDL2 can be flush, and the support structure 30 forms a fan-out area F1 outward from the edges of the first redistribution layer RDL1, the glass interposer 200 and the second redistribution layer RDL2. In this fan-out area F1, the support structure 30 can meet the load-bearing requirements of the connector 21, thereby reducing the area of ​​the adapter board 10.

[0135] Example 2

[0136] The main difference between the second embodiment and the first embodiment is that the support structure 30 is disposed at a different position on the edge of the adapter plate 10 . The following mainly describes the difference between the second embodiment and the first embodiment.

[0137] refer to Figure 12 As shown, for the adapter board 10, its front side is connected to the first chip D, and its back side is connected to the second chip 20 and the connector 21. In order to meet the high bandwidth density interconnection requirements between the first chip D, a routing layer with smaller line width, line spacing, and line thickness is used in the upper connection layer 101 located on the front side of the adapter board 10. And a routing layer with larger line width, line spacing, and line thickness is used in the lower connection layer 102 located on the back side of the adapter board 10 to meet the high-speed serdes drive requirements of the second chip 20 and the connector 21 for large current sharing capability, low impedance, and long distance (such as more than 5mm).

[0138] The manufacturing cost of upper connection layer 101 is much higher than that of lower connection layer 102. Therefore, in the package structure provided in the second embodiment, the area of ​​upper connection layer 101 can be left unchanged, and support structure 30 can be positioned at the edge of upper connection layer 101 to form fan-out region F1. In this case, connector 21 is positioned on the back of lower connection layer 102 at a position corresponding to fan-out region F1. This reduces the area of ​​upper connection layer 101, thereby reducing the manufacturing cost of upper connection layer 101 and, consequently, the cost of adapter board 10.

[0139] Of course, in this second embodiment, the connector 21 can be connected to the adapter board 10 through the substrate 40, or can be directly connected to the adapter board 10, and this application does not impose any restrictions on this.

[0140] For other configurations in the chip packaging structure of the second embodiment, such as the first chip D, the second chip 20, the substrate 40, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., please refer to the corresponding description in the first embodiment and will not be repeated here.

[0141] The following further describes the configuration of the support structure 30 in the second embodiment in combination with different configurations of the adapter plate 10 .

[0142] Setting method six

[0143] Indicative, reference Figure 13 As shown, in some possible implementations, the interposer 10 may include a silicon interposer 1 and a redistribution layer (RDL) disposed on the back side of the silicon interposer 1. The silicon interposer 1 may serve as an upper connection layer 101 to electrically connect to the first chip D, and the redistribution layer (RDL) may serve as a lower connection layer 102 to electrically connect to the second chip 20 and the connector 21.

[0144] Continue to refer Figure 13 As shown, in this sixth configuration, the edge of the redistribution layer (RDL) can protrude beyond the edge of the silicon interposer 1, and the support structure 30 is disposed on the protruding RDL, thereby forming a fan-out region F1 on the side of the silicon interposer 1. In this case, the connector 21 can be disposed on the back side of the RDL corresponding to the fan-out region F1 (i.e., on the side away from the support structure 20). This can reduce the area of ​​the silicon interposer 1 and lower the manufacturing cost of the silicon interposer 1.

[0145] The other relevant settings in Setting Method 6 are basically the same as those in the aforementioned "Setting Method 1". For details, please refer to the corresponding instructions in the aforementioned Setting Method 1 and will not be repeated here.

[0146] Setting method seven

[0147] Indicative, such as Figure 14 As shown, in some possible implementations, the interposer 10 may include: a first redistribution layer RDL1 and a second redistribution layer RDL2 stacked together. The first redistribution layer RDL1 may serve as an upper connection layer 101 electrically connected to the first chip D, and the second redistribution layer RDL2 may serve as a lower connection layer 102 electrically connected to the second chip 20 and the connector 21.

[0148] Continue to refer Figure 14As shown, in this seventh arrangement, the edge of the second redistribution layer RDL2 can protrude beyond the edge of the first redistribution layer RDL1, and the support structure 30 is disposed on the protruding second redistribution layer RDL2, thereby forming a fan-out region F1 on the side of the first redistribution layer RDL1. In this case, the connector 21 can be disposed on the back side of the second redistribution layer RDL2 corresponding to the fan-out region F1 (i.e., on the side away from the support structure 20). This can reduce the area of ​​the first redistribution layer RDL1 and reduce the manufacturing cost of the first redistribution layer RDL1.

[0149] The other relevant settings in Setting Method 7 are basically the same as those in the aforementioned "Setting Method 2". For details, please refer to the corresponding instructions in the aforementioned Setting Method 2 and will not be repeated here.

[0150] Setting method eight

[0151] Indicative, such as Figure 15 As shown, in some possible implementations, the adapter board 10 may include: the adapter board 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a molded interposer 100. The molded interposer 100 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and the molded interposer 100 includes at least one molded through-molding via TMV (through molding via) and at least one bridge chip BG (bridge die). The second redistribution layer RDL2 can be electrically connected to the first redistribution layer RDL1 through the bridge chip BG and the metal pillar P. According to actual needs, a through-silicon via can be provided in the bridge chip BG, and electrically connected to the second redistribution layer RDL2 through the through-silicon via.

[0152] The first redistribution layer RDL1 and the molded interposer 100 may serve as an upper connection layer 101 to be electrically connected to the first chip D, and the second redistribution layer RDL2 may serve as a lower connection layer 102 to be electrically connected to the second chip 20 and the connector 21 .

[0153] Continue to refer Figure 15 As shown, in this arrangement eight, the edges of the first redistribution layer RDL1 and the molded interposer 100 can be flush, the edges of the second redistribution layer RDL2 can protrude from the edges of the first redistribution layer RDL1 and the molded interposer 100, and the support structure 30 is disposed on the protruding second redistribution layer RDL2, thereby forming a fan-out area F1 on the side of the first redistribution layer RDL1 and the molded interposer 100. In this case, the connector 21 can be disposed on the back side of the second redistribution layer RDL2 corresponding to the fan-out area F1 (i.e., the side away from the support structure 20). In this way, the area of ​​the first redistribution layer RDL1 and the molded interposer 100 can be reduced, thereby reducing the manufacturing cost of the first redistribution layer RDL1 and the molded interposer 100.

[0154] The other relevant settings in Setting Method 8 are basically the same as those in the aforementioned "Setting Method 3". For details, please refer to the corresponding instructions in the aforementioned Setting Method 3 and will not be repeated here.

[0155] Setting method nine

[0156] Indicative, such as Figure 16 As shown, in some possible implementations, the adapter board 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200. The glass interposer 200 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and the glass interposer 200 includes at least one through-glass via TGV (throughglass via) and at least one bridge chip BG (bridge die). The bridge chip BG is embedded in a groove provided on the glass wafer. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the bridge chip BG and the through-glass via TGV. According to actual needs, a through-silicon via may be provided in the bridge chip BG, and electrically connected to the second redistribution layer RDL2 through the through-silicon via.

[0157] The first redistribution layer RDL1 and the glass interposer 200 may serve as an upper connection layer 101 to be electrically connected to the first chip D, and the second redistribution layer RDL2 may serve as a lower connection layer 102 to be electrically connected to the second chip 20 and the connector 21 .

[0158] Continue to refer Figure 16 As shown, in this ninth arrangement, the edges of the first redistribution layer RDL1 and the glass interposer 200 can be flush, while the edges of the second redistribution layer RDL2 can protrude beyond the edges of the first redistribution layer RDL1 and the glass interposer 200. The support structure 30 is disposed on the protruding second redistribution layer RDL2, thereby forming a fan-out region F1 on the sides of the first redistribution layer RDL1 and the glass interposer 200. In this case, the connector 21 can be disposed on the back side of the second redistribution layer RDL2 corresponding to the fan-out region F1 (i.e., on the side away from the support structure 20). In this way, the area of ​​the first redistribution layer RDL1 and the glass interposer 200 can be reduced, thereby reducing the manufacturing cost of the first redistribution layer RDL1 and the glass interposer 200.

[0159] The other relevant settings in Setting Method 9 are basically the same as those in the aforementioned "Setting Method 4". For details, please refer to the corresponding instructions in the aforementioned Setting Method 4, which will not be repeated here.

[0160] Setting method ten

[0161] Indicative, such as Figure 17As shown, in some possible implementations, the interposer 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200. The glass interposer 200 is located between the first redistribution layer RDL1 and the second redistribution layer RDL2, and includes a plurality of through glass vias (TGVs) in the glass interposer 200. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 via the plurality of through glass vias (TGVs).

[0162] The first redistribution layer RDL1 and the glass interposer 200 may serve as an upper connection layer 101 to be electrically connected to the first chip D, and the second redistribution layer RDL2 may serve as a lower connection layer 102 to be electrically connected to the second chip 20 and the connector 21 .

[0163] Continue to refer Figure 17 As shown, in this arrangement ten, the edges of the first redistribution layer RDL1 and the glass interposer 200 can be flush, the edges of the second redistribution layer RDL2 can protrude beyond the edges of the first redistribution layer RDL1 and the glass interposer 200, and the support structure 30 is disposed on the protruding second redistribution layer RDL2, thereby forming a fan-out area F1 on the side of the first redistribution layer RDL1 and the glass interposer 200. In this case, the connector 21 can be disposed on the back side of the second redistribution layer RDL2 corresponding to the fan-out area F1 (i.e., on the side away from the support structure 20). In this way, the area of ​​the first redistribution layer RDL1 and the glass interposer 200 can be reduced, thereby reducing the manufacturing cost of the first redistribution layer RDL1 and the glass interposer 200.

[0164] The other relevant settings in the setting method 10 are basically the same as those in the aforementioned "setting method 5". For details, please refer to the corresponding instructions in the aforementioned setting method 5, and no further details will be given here.

[0165] In addition, in the second embodiment, there is no restriction on the material, shape, quantity, size, etc. of the support structure 30. In practice, it can be set as needed. For details, please refer to the corresponding description in the first embodiment.

[0166] The present application does not impose any restrictions on the method for manufacturing the chip packaging structure provided in the aforementioned embodiments. In practice, the chip packaging structure can be manufactured according to needs and in combination with relevant technologies.

[0167] Indicatively, in the above setting method 1 Figure 7 Taking the chip packaging structure as an example, the manufacturing method of the chip packaging structure provided by the present application is described, and the specific process steps can be as follows:

[0168] 1. Chip Preparation: The first chip D with different functions can include a single chip such as a CPU, GPU, memory, IO die, or IPD. Alternatively, it can be a pre-packaged integrated module using HBM, DOI, or FOI. The front of the chip has microbumps for interconnection, and the bump pitch can range from 20μm to 200μm.

[0169] 2. Wafer preparation:

[0170] First, a Si interposer is fabricated. Figure 18 As shown in (a), a silicon wafer a1 is provided, and multiple through-silicon vias (TSVs) are fabricated in the silicon wafer a1. A Damascene process, including deposition, exposure, etching, electroplating, and CMP, is then used to fabricate a metal wiring layer a2 on the surface of the silicon wafer a1, thereby forming a silicon interposer. Micropads are fabricated on the surface of the metal wiring layer a2. Depending on actual needs, active devices, deep trench capacitors (DTCs), and metal-insulator-metal (MIM) capacitors can be fabricated in the silicon interposer. The thickness of the silicon interposer can range from 5μm to 200μm.

[0171] Next, refer to Figure 18 As shown in (b), the silicon interposer is temporarily bonded to the first carrier 01 on the side of the metal wiring layer a2.

[0172] The carriers involved in this application (such as the first carrier, the second carrier, the third carrier, the fourth carrier, etc.) can be metal plates, glass, organic plates, thermosetting resin plates, etc. This application does not impose any restrictions on this, and can be set as needed in practice.

[0173] The temporary bonding involved in this application can be performed by temporary bonding glue, but it is not limited to this. In practice, it can be set as needed.

[0174] Next, refer to Figure 18 As shown in (b), the back side of the silicon wafer a1 is thinned to expose the through silicon vias (TSV). The specific process may include: grinding - chemical mechanical polishing (CMP) - Si etching to expose copper - insulating dielectric material deposition - CMP to expose copper, etc.

[0175] Next, refer to Figure 18As shown in (c), a redistribution layer (RDL) is fabricated on the side of silicon wafer a1 where the TSV is exposed, leading out the TSV signals to form an adapter board 10. The number of routing layers in the RDL can range from 3 to 6, and the fabrication process for a single routing layer may include: surface pretreatment, organic material coating - exposure - development - curing - seed layer deposition - organic material coating - exposure - development - electroplating - photoresist removal - seed layer etching, etc. After the last routing layer is completed, a metal pad is fabricated as an interface for subsequent external interconnection.

[0176] Next, refer to Figure 18 As shown in (d), the surface of the redistribution layer RDL is temporarily bonded to the second carrier 02, and the first carrier 01 is debonded to expose the micropads on the surface of the metal wiring layer a2.

[0177] The debonding and separation involved in this application can be laser debonding, thermal debonding, etc., but is not limited thereto and can be set as needed in practice.

[0178] 3. DOI (dieon silicon interposer, silicon transfer board module) chip last assembly process:

[0179] First, chip placement. Figure 19 As shown in (a), multiple first chips D (CPU, GPU, memory, IOdie, IPD or HBM chips and chip modules) are mounted on the front of the silicon interposer, and the first chip D is connected to the micropad on the surface of the metal wiring layer a2 through microbumps.

[0180] Next, refer to Figure 19 As shown in (a), a thermosetting material is used to fill the bottoms and gaps of the plurality of first chips D, and then the molding compound is ground. The thermosetting material may include underfill, molding compound, molding underfill, etc.

[0181] Next, refer to Figure 19 As shown in (b), the second carrier 02 and the Si interposer are debonded and a dicing tape is mounted thereon. Then, a bladesaw is used to cut the DOI unit into individual DOI units.

[0182] 4. FOP (fanout RDL interpose, RDL adapter board module) chip first assembly process:

[0183] First, a support structure 30 is provided. The support structure 30 mainly plays the role of occupying space and providing support. For the relevant configuration, please refer to the relevant description above.

[0184] Then, refer to Figure 20 As shown in (a), the DOI unit and the support structure 30 formed by the above process are mounted on a third carrier 03 (such as a metal carrier). The support structure 30 is mounted on the side of the DOI unit to form a fan-out region F1.

[0185] Next, refer to Figure 20 As shown in (b), a thermosetting material is used for secondary plastic packaging to wrap the DOI unit and the support structure 30 as a whole, and the gap between the first chip D and the support structure 30 is filled; then, refer to Figure 20 As shown in (c), the plastic compound is ground to thin and expose the back side of the first chip D. In this case, the support structure 30 and the DOI unit are packaged as an integrated structure, and the support structure 30 forms a fan-out region F1 on the side of the DOI unit.

[0186] It should be understood that after thinning and exposing the back side of the first chip D, the top of the support structure 30 may or may not be exposed. For example, after the support structure 30 is mounted on the side of the DOI unit, if the height of the support structure 30 is higher than the back side of the first chip D, the support structure 30 will be exposed while thinning the first chip D, and the support structure 30 and the surface of the first chip D will be flush (see Figure 7 For another example, after the support structure 30 is mounted on the side of the DOI unit, if the top of the support structure 30 is lower than the back of the first chip D, the support structure 30 may not be exposed after the first chip D is thinned, and the support structure 30 is wrapped in the plastic compound (see Figure 20 ).

[0187] Next, refer to Figure 20 As shown in (d), the third carrier board 03 is debonded.

[0188] Of course, in other possible implementations, the back surface of the first chip D may be temporarily bonded to the fourth carrier first, and then the third carrier 03 may be debonded.

[0189] Next, through-holes are machined on the adapter board system using laser or mechanical methods, so that fixing structures (such as bolts) can pass through the holes to form reliable mechanical support during subsequent system assembly. Of course, the location of the through-holes should reasonably avoid the chip layout.

[0190] Next, remove the ineffective areas of the adapter board and plastic package structure and cut and separate the effective area.

[0191] 5. Mounting and mechanical fixing of the connector 21 and the second chip 20:

[0192] First, refer to Figure 21 As shown in (a), multiple substrates 40 are welded to the pads exposed on the surface of the redistribution layer RDL. Among them, the multiple substrates 40 can be processed by the substrate process of the substrate factory, or they can be obtained by the process of the PCB board factory, and the morphology, number of layers, and material of different substrates 40 may be different, which depends on the electrical characteristics of the devices that the substrate 40 needs to be connected to. Of course, according to actual needs, after welding the multiple substrates 40 to the pads on the surface of the redistribution layer RDL, in some possible implementation methods, a thermosetting material can be used to fill the bottom of the multiple substrates 40 and the gaps between the substrates 40, and the multiple substrates 40 can be plastic-encapsulated in the plastic layer for protection.

[0193] Next, refer to Figure 21 As shown in (b), the second chip 20 (such as a power module, clock, and passive components) is soldered or crimped to the back of multiple substrates 40. For example, by soldering multiple power modules, vertical power supply interconnection with the front chip can be achieved. Connector 21 is assembled to the back of substrate 40 in the reserved area of ​​fan-out area F1 by soldering or crimping.

[0194] Next, refer to Figure 6 As shown, a support frame 43 having a size matching that of the adapter board system (ie, including the first chip D, the adapter board 10, the connector 21, the second chip 20, and the substrate 40) can be used to support the adapter board system.

[0195] Next, refer to Figure 6As shown, under the support of the support frame 43, the first heat sink 41 is mounted on the side of the hybrid adapter plate system located on the first chip D, and the second heat sink 42 is mounted on the side of the second chip 20. The heat sinks (41, 42) and the support frame 43 can be pre-drilled. The adapter plate system, the support frame 43, the first heat sink 41, and the second heat sink 42 are fixed at the position by bolts (50). In this case, the heat sinks (41, 42) not only play the role of heat dissipation, but also play the role of stabilizing the structure. Of course, as needed, a thermal interface material can be filled between the back of the chip and the heat sink, and the thickness can be in the range of 50μm to 150μm.

[0196] Next, bolts, clamps and other components are used to fasten the front heat sink, plastic packaging structure and back heat sink to finally obtain a system-level packaging structure.

[0197] It should be understood that the size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0198] For other relevant contents in the above-mentioned manufacturing method, you can refer to the corresponding parts in the above-mentioned packaging structure embodiment, which will not be repeated here; for other setting structures in the above-mentioned packaging structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0199] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: adapter plate; at least one first chip, disposed on the front surface of the adapter board and electrically connected to the adapter board; at least one second chip, disposed on the back side of the adapter board and electrically connected to the adapter board; A supporting structure is provided at an edge of the adapter plate; A connector is located on the back side of the supporting structure and is electrically connected to the back side of the adapter board, and the connector is used to connect to external devices.

2. The chip packaging structure according to claim 1, wherein: The supporting structure is on the side of the adapter plate.

3. The chip packaging structure according to claim 1, wherein: The adapter plate includes an upper connection layer and a lower connection layer stacked together, and the first chip is arranged on the surface of the upper connection layer and electrically connected to the upper connection layer; The edge of the lower connection layer protrudes from the edge of the upper connection layer, and the support structure is arranged on the lower connection layer protruding from the edge of the upper connection layer and on the side of the upper connection layer; the connector is located on the side of the lower connection layer away from the support structure.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes a substrate; The substrate is located between the connector and the adapter board, and the connector is electrically connected to the back surface of the adapter board through the substrate.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The supporting structure is a dummy chip.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The support structure includes one or more of silicon, metal, ceramic, organic plate, resin or thermosetting adhesive.

7. The chip packaging structure according to any one of claims 1, 2, 4-6, characterized in that: The adapter plate includes: a silicon interposer and a redistribution layer; the redistribution layer is arranged on the back side of the silicon interposer and is electrically connected to the silicon interposer; The edge of the silicon interposer is flush with the edge of the redistribution layer, and the support structure is located on the sides of the silicon interposer and the redistribution layer.

8. The chip packaging structure according to any one of claims 1, 3, 4-6, characterized in that: The adapter plate includes: a silicon interposer and a redistribution layer; the redistribution layer is arranged on the back side of the silicon interposer and is electrically connected to the silicon interposer; The upper connection layer includes the silicon interposer, and the lower connection layer includes the redistribution layer; The edge of the redistribution layer protrudes from the edge of the silicon interposer, and the support structure is arranged on the redistribution layer protruding from the edge of the silicon interposer; the connector is located on a side of the redistribution layer away from the support structure.

9. The chip packaging structure according to any one of claims 1, 2, 4-6, characterized in that: The adapter board includes: a first redistribution layer and a second redistribution layer stacked together; wherein the first redistribution layer is closer to the first chip than the second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected; The edge of the first redistribution layer is flush with the edge of the second redistribution layer, and the support structure is arranged on the sides of the first redistribution layer and the second redistribution layer.

10. The chip packaging structure according to any one of claims 1, 3, 4-6, characterized in that: The adapter board includes: a first redistribution layer and a second redistribution layer stacked together; wherein the first redistribution layer is closer to the first chip than the second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected; The upper connection layer includes the first redistribution layer, and the lower connection layer includes the second redistribution layer; The edge of the second redistribution layer protrudes from the edge of the first redistribution layer, and the support structure is arranged on the redistribution layer protruding from the edge of the first redistribution layer; the connector is located on a side of the second redistribution layer away from the support structure.

11. The chip packaging structure according to claim 9 or 10, characterized in that: The adapter board further includes: a bridge chip disposed between the first redistribution layer and the second redistribution layer; The active surface of the bridge chip faces the first redistribution layer and is electrically connected to the first redistribution layer.

12. The chip packaging structure according to any one of claims 9 to 11, characterized in that: The adapter plate further includes: a metal through hole provided between the first redistribution layer and the second redistribution layer; The first redistribution layer is electrically connected to the second redistribution layer through the metal via.

13. The chip packaging structure according to claim 12, wherein: The metal through-hole is a molded through-hole or a glass through-hole.

14. The chip packaging structure according to any one of claims 9 to 13, characterized in that: The line width, line spacing and line thickness of the metal lines in the first redistribution are all less than 5 μm; The line width, line spacing and line thickness of the metal wiring in the second redistribution layer are all greater than 5 μm.

15. The chip packaging structure according to any one of claims 1 to 14, characterized in that: The at least one first chip includes one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

16. The chip packaging structure according to any one of claims 1 to 15, characterized in that: The at least one second chip includes: one or more of a power supply module, a control module, a clock device, a rectifier, and a resistor, capacitor, and inductor.

17. The chip packaging structure according to any one of claims 1 to 16, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of the second chips; Among them, the multiple second chips include multiple power supply modules, and the multiple power supply modules are respectively arranged opposite to the multiple first chips; the power supply modules are electrically connected to the relatively arranged first chips through the adapter board and supply power to the first chips.

18. An electronic device, characterized in that: It comprises a circuit board and the chip packaging structure according to any one of claims 1 to 17, wherein the chip packaging structure is electrically connected to the circuit board.

Images