Chip stacking structure and packaging structure

Abstract

The invention discloses a chip stacking structure and a packaging structure. The chip stacking structure comprises a substrate; the first chip group comprises first chips which are stacked on the substrate and deviate in a first deviation direction, a first upper chip at the uppermost part in the first chip group is provided with a rewiring layer, and the first upper chip is electrically connected with the substrate through the rewiring layer; the second chip set comprises a second chip which is arranged on the first upper chip and deviates in a second deviation direction, the first deviation direction corresponds to the opposite direction of the second deviation direction, and the second chip is electrically connected with the rewiring layer through a conductive column. The packaging size of the chip stacking structure is small.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a chip stacking structure and a packaging structure. Background Art

[0002] Multi-chip packaging (MCP) stacking integrates multiple semiconductor chips into a single package structure, which can increase the density of electronic components. However, stacking multiple semiconductor chips in a semiconductor package increases the thickness of the semiconductor package. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a chip stacking structure, comprising:

[0004] substrate;

[0005] A first chipset includes first chips stacked on the substrate and offset in a first offset direction, wherein a redistribution layer is provided on a first upper chip at the top of the first chipset, and the first upper chip is electrically connected to the substrate through the redistribution layer;

[0006] The second chipset includes a second chip disposed on the first upper chip and offset in a second offset direction, the first offset direction being opposite to the second offset direction, and the second chip being electrically connected to the redistribution layer via a conductive column.

[0007] In some embodiments, an offset amount of the first upper chip in the first offset direction is smaller than an offset amount of the second upper chip in the second offset direction.

[0008] In some embodiments, a first data pad and a first control pad are provided on the first upper chip, and the redistribution layer includes a first redistribution layer and a second redistribution layer, the first redistribution layer is connected to the first data pad, and the second redistribution layer is connected to the first control pad, wherein the length of the first redistribution layer is less than the length of the second redistribution layer.

[0009] In some embodiments, there are multiple first data pads, there are multiple first redistribution layers, and the multiple first data pads are parallel to each other.

[0010] In some embodiments, the first data pad and the first control pad are connected to the substrate through wires, respectively.

[0011] In some embodiments, a second data pad is provided on the second chip, a first conductive column is provided on the second data pad, and the second data pad is connected to the first redistribution layer through the first conductive column.

[0012] In some embodiments, a contact area between the first conductive pillar and the first redistribution layer is smaller than a contact area between the first redistribution layer and the first data pad.

[0013] In some embodiments, the second chip has a second control pad and a third redistribution layer, the second control pad is connected to one end of the third redistribution layer, a second conductive column is provided on the other end of the third redistribution layer, and the second conductive column is connected to the second redistribution layer.

[0014] In some embodiments, a contact area between the second conductive pillar and the second redistribution layer is smaller than a contact area between the second redistribution layer and the first control pad.

[0015] In some embodiments, a dummy conductive column is provided on the second chip, and an end portion of the dummy conductive column is welded to the first upper chip.

[0016] In some embodiments, a contact area between the dummy conductive pillar and the first upper chip is greater than a contact area between the first conductive pillar and the first data pad.

[0017] In some embodiments, it further includes:

[0018] a plastic encapsulation layer, the plastic encapsulation layer covering the first chip group and the second chip group, and the plastic encapsulation layer containing fillers;

[0019] The heat sink is located on the plastic packaging layer.

[0020] In some embodiments, a portion of the filler is located between the heat sink and the second chip, and a maximum diameter of the filler is smaller than a thickness of the heat sink.

[0021] In some embodiments, the filler between the heat sink and the second chip contacts the heat sink.

[0022] In some embodiments, the plastic packaging layer is further provided with an electromagnetic shielding layer, and the electromagnetic shielding layer covers the heat sink.

[0023] In some embodiments, the thickness of the second chip is greater than the thickness of the first upper chip.

[0024] In some embodiments, the first upper chip is electrically connected to the second chip, and the first upper chip and the second chip belong to the same signal channel and belong to different columns under the same signal channel.

[0025] According to a second aspect of an embodiment of the present disclosure, there is provided a packaging structure, including:

[0026] A mainboard and at least one chip stacking structure, wherein at least one chip stacking structure is arranged on the mainboard.

[0027] In summary, the embodiments of the present disclosure propose a chip stacking structure and a packaging structure, wherein the chip stacking structure includes a first chip group and a second chip group, wherein the second chip group is arranged on the first chip group. The first chip group includes a plurality of first chips that are stacked and offset in a first offset direction, and the second chip group includes a second chip that is offset in a second offset direction, and the first offset direction and the second offset direction are opposite directions. A redistribution layer is provided on the surface of the first upper chip at the top of the first chip group, and the first upper chip can be electrically connected to the substrate through the redistribution layer and the leads, and the second chip is electrically connected to the redistribution layer through the conductive pillars, and then electrically connected to the first upper chip, thereby eliminating the need for leads to interconnect the first upper chip and the second chip. Since the first upper chip and the second chip are interconnected through the conductive pillars, the overall thickness of the plastic encapsulation layer can be reduced during plastic encapsulation, thereby reducing the packaging volume of the chip stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram showing a semiconductor package according to an exemplary embodiment;

[0029] Figure 2 is a schematic diagram showing a chip stacking structure according to an exemplary embodiment;

[0030] Figure 3 is a top view of a first upper chip and a second chip according to an exemplary embodiment;

[0031] Figure 4 is a schematic diagram showing a redistribution layer according to an exemplary embodiment;

[0032] Figure 5 is a schematic diagram of a first conductive column according to an exemplary embodiment;

[0033] Figure 6 is a schematic diagram showing contact between a first conductive pillar and a first redistribution layer according to an exemplary embodiment;

[0034] Figure 7 is another schematic diagram showing contact between a first conductive pillar and a first redistribution layer according to an exemplary embodiment;

[0035] Figure 8 is a schematic diagram showing a third redistribution layer according to an exemplary embodiment;

[0036] Figure 9 is a schematic diagram showing contact between a second conductive pillar and a second redistribution layer according to an exemplary embodiment;

[0037] Figure 10 is a schematic diagram of a virtual conductive column according to an exemplary embodiment;

[0038] Figure 11 is another schematic diagram showing a chip stacking structure according to an exemplary embodiment;

[0039] Figure 12 is a schematic diagram showing a packaging structure according to an exemplary embodiment. DETAILED DESCRIPTION

[0040] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0042] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0043] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0044] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0045] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0046] A semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor die. The semiconductor chip or semiconductor die may be obtained by dividing a semiconductor substrate such as a wafer into a plurality of pieces using a die sawing process. The semiconductor chip may correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip), or a system on a chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. The semiconductor package may be used in communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems.

[0047] like Figure 1 As shown, an embodiment of the present disclosure provides a semiconductor package 100. The semiconductor package 100 includes a substrate 101 and a plurality of semiconductor chips 102 stacked sequentially on the substrate 101. The semiconductor chips 102 are connected to the substrate 101 via leads 103, thereby enabling signal transmission. The semiconductor package 100 also includes a plastic encapsulation layer 104, which can cover the semiconductor chips 102 and the leads 103. The plastic encapsulation layer 104 can protect the semiconductor chips 102 and the leads 103. Because the top semiconductor chip 102 is interconnected with the next-highest semiconductor chip 102 via the leads 103, and the leads 103 have a certain arc height, when the plastic encapsulation layer 104 is formed, it also needs to cover the arc height of the leads 103. Consequently, the plastic encapsulation layer 104 must maintain a relatively high thickness, resulting in a relatively large package height for the semiconductor package 100, which can be between 650 and 700 microns.

[0048] like Figure 2As shown, an embodiment of the present disclosure proposes a chip stacking structure 200, which can have a lower package height. The chip stacking structure 200 includes a substrate 201, a first chipset 202, and a third chipset 203. The first chipset 202 is arranged on the substrate 201, and the second chipset 203 is arranged on the first chipset 202. The substrate 201 can be used as an interconnect structure for electrically connecting the first chipset 202 and the second chipset 203 embedded in the chip stacking structure 200 to an external device or an external system. The structure and shape of the substrate 201 can be designed to be different according to the embodiment. For example, the substrate 201 can be a printed circuit board (PCB), an insert, or a flexible printed circuit board (FPCB). The substrate 201 can also be an interposer.

[0049] like Figure 2 As shown, the first chipset 202 may include multiple first chips stacked on a substrate 201, with these first chips offset sequentially in a first offset direction. In this embodiment, the first chipset 202 may include a first lower chip 2021, a first middle chip 2022, and a first upper chip 2023. The first lower chip 2021 may be the first chip located at the bottom of the first chipset 202, the first middle chip 2022 may be the first chip located in the middle of the first chipset 202, and the first upper chip 2023 may be the first chip located at the top of the first chipset 202. The first upper chip 2021, the second middle chip 2022, and the first upper chip 2023 may be the same first chip. The first lower chip 2021, the first middle chip 2022, and the first upper chip 2023 are connected to the substrate 201 via wires 204. The pads on the first lower chip 2021 and the first middle chip 2022 are arranged in the same manner, so that the first middle chip 2022 can be connected to the first lower chip 2021 via the leads 204, and the first lower chip 2021 is electrically connected to the substrate 201 via the leads 204. Since the pads on the first upper chip 2023 and the first middle chip 2022 are positioned differently, the first upper chip 2023 can be electrically connected to the substrate 201 via the leads 204 alone. The substrate 201 has pads, so that the first upper chip 2023 and the first lower chip 2021 can be connected separately via the leads 204.

[0050] like Figure 2As shown, the second chipset 203 is disposed on the first chipset 202. Specifically, the second chipset 203 is disposed on the first upper chip 2023. The second chipset 203 may include a second chip 2031, which may be a chip of the same specifications as the first upper chip 2023. The second chip 2031 is electrically connected to the first upper chip 2023 via conductive pillars 205. Since the first upper chip 2023 has a redistribution layer, the conductive pillars 205 can be soldered to the redistribution layer. Since the first upper chip 2023 is electrically connected to the leads 204 via the redistribution layer, the first upper chip 2023 is electrically connected to the substrate 201. Since the second chip 2031 is electrically connected to the first upper chip 2023 via the conductive pillars 205, the second chip 2031 no longer needs to transmit signals to the first upper chip 2023 via leads.

[0051] like Figure 2 As shown, after the first chipset 202 is placed on the substrate 201, a wiring process is performed to electrically connect the first chipset 202 to the substrate 201. Then, the second chipset 203 is soldered to the first chipset 202 via conductive pillars 205. When securing the second chipset 203, the second chip 2031 is offset relative to the first upper chip 2023 in a second offset direction, which is opposite to the first offset direction. In the first offset direction, the first middle chip 2022 is offset relative to the first lower chip 2021, and the first upper chip 2023 is offset relative to the first middle chip 2022. The first middle chip 2022 is offset by a distance d1 relative to the first lower chip 2021, and the first upper chip 2023 is offset by a distance d1 relative to the first middle chip 2022 (offset amount d1). In the second offset direction, the second chip 2031 is offset relative to the first upper chip 2023, and the second chip 2031 has an offset distance d2 (offset d2) relative to the first upper chip 2023. The offset d2 of the second chip 2031 relative to the first upper chip 2023 is greater than the offset d1 of the first upper chip 2023 relative to the first middle chip 2022, thereby preventing the edge of the second chip 2031 from touching the lead 204 on the first upper chip 2023.

[0052] like Figure 2 As shown, the first lower chip 2021 and the first middle chip 2022 are interconnected via leads 204, and the first upper chip 2023 and the second chip 2031 are interconnected via conductive pillars 205. This allows the first upper chip 2023 and the second chip 2031 to belong to the same signal channel and to different ranks within the same signal channel. Similarly, the first lower chip 2021 and the first middle chip 2022 belong to the same signal channel and to different ranks within the same signal channel.

[0053] like Figure 3 As shown, Figure 3 The diagram shows a top view of the first top chip 2023 and the second chip 2031. The edge of the first top chip 2023 has multiple pads, including, for example, first data pads 206 and first control pads 207. The number of first data pads 206 is greater than the number of first control pads 207, and these first data pads 206 and first control pads 207 are arranged along the Y direction. Since the first top chip 2023 and the second chip 2031 are identical, the second chip 2031 also has second data pads 208 and second control pads 209. It should be noted that when the second chip 2031 is fixed, it rotates 180° relative to the first top chip 2023, causing the second data pads 208 on the second chip 2031 to rotate relative to the first data pads 206 on the first top chip 2023, and the second control pads 209 on the second chip 2031 to rotate relative to the first control pads 206 on the first top chip 2023. Because the first data pads 206 and the second data pads 208 carry relatively large amounts of data, even if the second data pads 208 are flipped relative to the first data pads 206, the first data pads 206 can still form a one-to-one correspondence with the second data pads 208. This simplifies the design of the redistribution layer connecting the first data pads 206 on the first top chip 2023. However, since the number of first control pads 207 and second control pads 209 is relatively small, the second control pads 209 are flipped relative to the first control pads 207. This complicates the design of the redistribution layer connecting the first control pads 207 on the first top chip 2023. In this embodiment, the first data pads 206 are used to transmit data (DQ), for example, an 8-bit data width, which can be divided into 4-bit low-order byte data (DQ0-DQ3) and 4-bit high-order byte data (DQ4-DQ7). The first control pads 207 are used to transmit control signals (CMD / ADDR).

[0054] like Figure 3-Figure 4 As shown, Figure 4A simplified top view of the first upper chip 2023 is shown. Because the second chip 2031 is offset relative to the first upper chip 2023, a redistribution layer 210 is required on the first upper chip 2023 to interconnect the redistribution layer 210 and the second chip 2031. The redistribution layer 210 may include a first redistribution layer 211 and a second redistribution layer 212. The first redistribution layer 211 may be connected to the first data pads 206, and the second redistribution layer 212 may be connected to the first control pads 207. Each first data pad 206 is connected to each first redistribution layer 211, and each second redistribution layer 212 is connected to each first control pad 207. Because the second data pads 208 on the second chip 2031 can achieve a one-to-one correspondence with the first data pads 206 on the first top chip 2023, the structure of the first redistribution layer 211 on the first top chip 2023 is relatively simple. For example, the first redistribution layer 211 can be a straight line, and the extension lengths of these first redistribution layers 211 are substantially the same. These first redistribution layers 211 can also be arranged in parallel. Because the second control pads 209 on the second chip 2031 are flipped relative to the first control pads 207 on the first top chip 2023, the structure of the second redistribution layer 212 on the first top chip 2023 is relatively complex. The length (in the X direction) of the second redistribution layer 212 can be greater than the length (in the X direction) of the first redistribution layer 211, thereby facilitating the electrical connection between the first control pads 207 and the second control pads 209.

[0055] like Figure 4As shown, this embodiment focuses on the structure of the second redistribution layer 212. In this embodiment, the first control pad 207 is divided into a first control pad 2071 (for example, a CA0 pad) and a first control pad 2072 (for example, a CA1 pad). The length (X-direction) of the second redistribution layer 212 connected to the first control pad 2071 can be greater than the length of the second redistribution layer 212 connected to the first control pad 2072. The second redistribution layer 212 extends in the X-direction, one end of the second redistribution layer 212 can be connected to the first control pad 2071, and the other end of the second redistribution layer 212 extends in the Y-direction, thereby enabling the positions of the first control pad 2071 and the first control pad 2072 to be flipped. For example, the second redistribution layer 212 connected to the first control pad 2071 extends along the Y-direction, and the second redistribution layer 212 connected to the first control pad 2072 extends along the Y-direction, with the two extending in opposite directions. The end of the second redistribution layer 212 connected to the first control pad 2071 extends longer in the Y direction, so that there is a larger distance between the ends of the two second redistribution layers 212, which is conducive to the flipping of the positions of the first control pad 2071 and the first control pad 2072, and is also conducive to the subsequent electrical connection between the first control pad 2071 and the first control pad 2072 and the second control pad 209 on the second chip 2031.

[0056] like Figure 4 As shown, a plurality of dummy pads 213 are further provided on the first upper chip 2023. The dummy pads 213 are used to connect to the dummy conductive pillars on the second chip 2031. The dummy pads 213 are not connected to the first data pads 206 or the first control pads 207, and thus cannot transmit signals. When the dummy conductive pillars are soldered to the dummy pads 213, they can provide support for the second chip 2031.

[0057] like Figure 5 As shown, Figure 5 A schematic diagram shows a first conductive pillar 214 on the second chip 2031. Because there is a one-to-one correspondence between the first data pad 206 on the first upper chip 2023 and the second data pad 208 on the second chip 2031 (i.e., in the X-direction), and the first redistribution layer 211 is a straight line, the first conductive pillar 214 can be directly disposed on the second chip 2031. The first conductive pillar 214 can be directly disposed on the second data pad 208, meaning that the first conductive pillar 214 does not need to be connected to the second data pad 208 through the redistribution layer. The first conductive pillar 214 can be part of the conductive pillar 205. The first conductive pillar 214 can be a combination of a copper pillar and a solder ball. The first conductive pillar 214 can also be a solder ball.

[0058] like Figure 6-Figure 7 As shown, when the second chip 2031 is secured to the first upper chip 2023 via the conductive pillars 205, the ends of the first conductive pillars 214 are soldered to the first redistribution layer 211, thereby electrically connecting the first conductive pillars 214 to the first redistribution layer 211. Because a large number of first redistribution layers 211 are formed on the first upper chip 2023, the spacing between adjacent first redistribution layers 211 is relatively small. Therefore, when the first conductive pillars 214 are soldered to the first redistribution layer 211, the contact area between the first conductive pillars 214 and the first redistribution layer 211 is smaller than the contact area between the first redistribution layer 211 and the first data pads 206. The first data pads 206 may be formed on the first redistribution layer 211 and used to form wiring pads. Therefore, the area of ​​the first data pads 206 can be larger, thereby increasing the contact area between the first data pads 206 and the first redistribution layer 211, facilitating the wiring process. Of course, since the contact area between the first conductive column 214 and the first redistribution layer 211 is relatively small, it can be ensured that the solder balls on the first conductive column 214 will not overflow outward during soldering, thereby preventing short circuits caused by solder ball overflow. In this embodiment, since the first redistribution layer 211 is a regular rectangular shape, the size of the first conductive column 214 can be smaller than the size of the first data pad 206, thereby ensuring that the first conductive column 214 can have a smaller contact area with the first redistribution layer 211. Of course, in some embodiments, in order to further prevent short circuits caused by solder ball overflow, the first redistribution layer 211 can also be designed to be irregular. Figure 7 As shown, Figure 7 The first redistribution layer 211 is irregularly shaped. The two ends of the first redistribution layer 211 are connected to the first conductive pillar 214 and the first data pad 206, respectively. The end of the first redistribution layer 211 that contacts the first conductive pillar 214 has a smaller width, while the end of the first redistribution layer 211 that contacts the first data pad 206 has a larger width. This allows for a larger spacing between the ends of the first redistribution layer 211, thereby further reducing the short-circuiting problem caused by solder balls conducting electricity sequentially during the soldering process.

[0059] like Figure 7As shown, the first redistribution layer 211 has an irregular shape. In the Y direction, the end in contact with the first conductive pillar 214 has a smaller width, while the end in contact with the first data pad 206 has a larger width. In the X direction, the end in contact with the first conductive pillar 214 has a smaller length, while the end in contact with the first data pad 206 has a larger length. Because the first redistribution layer 211 is used to transmit electrical signals, although the first redistribution layer 211 has smaller ends, it still has a larger area. This allows the impedance of the first redistribution layer 211 to be adjusted, minimizing the impact on signal transmission.

[0060] like Figure 7 As shown, the width of the first redistribution layer 211 in the Y direction at the end in contact with the first conductive pillar 214 is, for example, between 20 and 30 microns, such as 22, 24, 25, 26, or 28 microns. The width of the first redistribution layer 211 in the Y direction at the end in contact with the first data pad 206 is, for example, between 40 and 50 microns, such as 42, 44, 45, 46, or 48 microns. The length of the first redistribution layer 211 in the X direction at the end in contact with the first conductive pillar 214 is, for example, between 40 and 50 microns, such as 42, 44, 45, 46, or 48 microns. The length of the first redistribution layer 211 in the X direction at the end in contact with the first data pad 206 is, for example, between 80 and 150 microns, such as 90, 100, 110, 120, 130, or 140 microns.

[0061] like Figure 8 As shown, since the first control pad 207 and the second control pad 209 are flipped, that is, the first control pad 2071 corresponds to the second control pad 2091, and the first control pad 2072 corresponds to the second control pad 2092. At the same time, the second redistribution layer 212 on the first upper chip 2031 has a longer length, it is necessary to form a third redistribution layer 215 on the second chip 2031. The third redistribution layer 215 is in contact with the second control pad 209, and then a second conductive column 216 is formed on the end of the third redistribution layer 215. The second conductive column 216 is welded to the end of the second redistribution layer 212 to achieve electrical connection with the second redistribution layer 212. One end of the third redistribution layer 215 can be connected to the second control pad 209, and a second conductive column 216 is provided on the other end of the third redistribution layer 215, so that the second conductive column 216 can fall above the end of the second redistribution layer 212, thereby realizing the welding of the second conductive column 216 and the second redistribution layer 212.

[0062] like Figure 9 As shown, Figure 9The diagram shows a second conductive pillar 216 soldered to the second redistribution layer 212. The first upper chip 2023 has the second redistribution layer 212, and a first control pad 2071 on the second redistribution layer 212. The first control pad 2071 is used to electrically connect to a lead, thereby interconnecting with the substrate. The second chip 2031 has a third redistribution layer 215, with a second control pad 2091 on one end and a second conductive pillar 216 on the other end. The end of the second conductive pillar 216 is soldered to the second redistribution layer 212. After the signal is transmitted from the substrate via the lead to the first control pad 2071, it passes through the second redistribution layer 212, the second conductive pillar 216, and the third redistribution layer 215, and then enters the interior of the second chip 2031. Since the second conductive pillar 216 has the same structure as the first conductive pillar 214, that is, the second conductive pillar 216 can also be a combination of a copper pillar and a solder ball, the contact area between the second conductive pillar 216 and the second redistribution layer 212 can be smaller than the contact area between the second redistribution layer 212 and the first control pad 2071, thereby preventing the second conductive pillar 216 from short-circuiting due to solder ball overflow.

[0063] like Figure 10As shown, the second chip 2031 achieves signal interconnection with the first upper chip 2023 via the first conductive pillars 214 and the second conductive pillars 216. However, since the first conductive pillars 214 and the second conductive pillars 216 are both located on the edge of the first upper chip 2023, the second chip 2031 remains unstable after soldering. In this embodiment, a large number of dummy upper pads 217 and dummy conductive pillars 218 are formed on the second chip 2031. One end of the dummy conductive pillar 218 is fixed to the dummy upper pad 217, and the other end of the dummy conductive pillar 218 is fixed to the dummy pad 213 on the first upper chip 2023, thereby securing the second chip 2031. The dummy conductive pillars 218 are not used for signal transmission. In this embodiment, a large number of dummy pads 213 can be designed in the blank area of ​​the first upper chip 2023, and a large number of dummy conductive pillars 218 can be designed on the second chip 2031, thereby improving the soldering stability of the second chip 2031. At the same time, increasing the number of dummy conductive pillars 218 can also improve the heat dissipation efficiency of the second chip 2031. In this embodiment, the size of the dummy pad 213 can be smaller than that of the first data pad 216, and the size of the dummy conductive pillar 218 can also be smaller than that of the first conductive pillar 214. This ensures that the contact area between the dummy conductive pillar 218 and the dummy pad 213 is smaller than the contact area between the first conductive pillar 214 and the first data pad 206. Consequently, more dummy conductive pillars 218 can be provided. The greater the number of dummy conductive pillars 218, the greater the heat dissipation area, and the better the heat dissipation effect of the second chip 2031. In this embodiment, the first conductive pillar 214, the second conductive pillar 216, and the dummy conductive pillar 218 can have the same structure, and the first conductive pillar 214 and the second conductive pillar 216 constitute the conductive pillar 205. In some embodiments, the first conductive pillar 214, the second conductive pillar 216, and the dummy conductive pillar 218 constitute the conductive pillar 205.

[0064] like Figure 11As shown, in this embodiment, the first chipset is first fixed to the substrate 201, and then wire bonding is performed, that is, the first upper chip 2023, the first middle chip 2022, and the first lower chip 2021 are electrically connected to the substrate 201 through the leads 204. Then, the second chip 2031 is fixed to the first upper chip 2023 through the conductive pillars 205. The chip stack structure 200 is then plastic-encapsulated to form a plastic layer 219 covering the first chipset and the second chipset. At the same time, a heat sink 221 is also formed above the plastic layer 219. In this embodiment, the heat sink 221 is first placed on the mold, and then the plastic material 219 is evenly sprinkled on the heat sink 221. Then, the plastic encapsulation process is performed so that the plastic material enters between the first upper chip 2023 and the second chip 2031, thereby covering the first chipset and the second chipset. The molding material contains filler 220. As the molding process progresses, filler 220 also enters the area between the second chip 2031 and the heat sink 221. In this embodiment, the thickness of the molding layer 219 between the second chip 2031 and the heat sink 221 can be adjusted by adjusting the pressure and temperature process. In this embodiment, the thickness of the heat sink 221 can be greater than the maximum diameter of the filler 220 between the second chip 2031 and the heat sink 221. At the same time, part of the filler 220 can also contact the heat sink 221 to enhance heat dissipation. In this embodiment, the filler 220 can be silicon oxide or aluminum oxide, and the heat sink 221 can be a copper sheet. Because the copper sheet has a lower thermal expansion coefficient, and the thickness of the heat sink 221 is equal to the thickness of the molding layer 219 located above the second chip 2031, warpage of the entire package structure can be reduced. In this embodiment, the thickness of the heat sink 221 can be between 10 and 20 microns, for example, 12, 14, 15, 16, or 18 microns.

[0065] like Figure 11 As shown, since the second chip 2031 is fixed to the first upper chip 2023 via conductive pillars 205, there is no need to form leads on the second chip 2031. The arc height of the leads 204 on the first upper chip 2023 is also lower than the upper surface of the second chip 2031. Therefore, during the plastic encapsulation process, the thickness of the plastic encapsulation layer 219 can be reduced, thereby reducing the package height of the chip stack structure 200. After forming the plastic encapsulation layer 219 and the heat sink 221, an electromagnetic shielding layer 222 can be sprayed on the outer surface of the plastic encapsulation layer 219. The electromagnetic shielding layer 222 also covers the heat sink 221. The electromagnetic shielding layer 222 can protect the heat sink 221 and also provide electromagnetic shielding for the chip stack structure 200. The thickness of the electromagnetic shielding layer 222 can be between 3 and 5 microns. Solder balls 223 are also formed on the bottom of the substrate 201. The solder balls 223 can be used for connection to an external substrate. The package height of the chip stacking structure 200 may be between 550 and 570 microns, for example, 560 microns. Figure 11 The package height of the chip stacking structure 200 is relative to Figure 1 The package height of the semiconductor package 100 is greatly improved, and the chip stacking structure 200 can be applied to a variety of miniaturized products.

[0066] like Figure 2 and Figure 11 As shown, the first chipset 202 in the chip stack structure 200 may include three first chips, and the second chipset 203 may include one second chip 2031. When soldering the second chipset 203 to the first chipset 202, the thickness of the second chip 2031 can be greater than that of the first upper chip 2023, thereby ensuring a certain strength for the second chip 2031. In some embodiments, the first chipset 202 may further include five first chips, wherein the topmost first upper chip 2023 in the first chipset 202 may be electrically connected to the second chip 2031. Thus, the first upper chip 2023 and the second chip 2031 may belong to the same signal channel, but may be in different columns within the same signal channel. In some embodiments, two or more chip stack structures 200 may be provided on the same substrate 201. It should be noted that the three first chips in the first chipset 202 may be secured to the substrate 201 via an adhesive layer. The adhesive layer may be made of DAF material. The thickness of the adhesive layer is less than 10 microns, for example, 7-9 microns.

[0067] like Figure 12 As shown, the embodiment of the present disclosure also proposes a packaging structure 300, which includes a motherboard 301 and a chip stacking structure 200. The chip stacking structure 200 is fixed to the motherboard 301 by solder balls, and the motherboard 301 can be a PCB. The packaging structure 300 is also used in electronic devices. The electronic device can include one or more of the following: for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 Audio Layer 3 (MP3) player, a mobile medical device, a camera, a home appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. The wearable device can be an accessory type, a fabric or clothing type, a body attachment type, or an implantable circuit type. The accessory wearable device can be, for example, a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted device (HMD). The electronic device can also be used in large servers, such as data centers, AI computers, and other fields.

[0068] In summary, the embodiments of the present disclosure propose a chip stacking structure and a packaging structure, wherein the chip stacking structure includes a first chip group and a second chip group, wherein the second chip group is arranged on the first chip group. The first chip group includes a plurality of first chips that are stacked and offset in a first offset direction, and the second chip group includes a second chip that is offset in a second offset direction, and the first offset direction and the second offset direction are opposite directions. A redistribution layer is provided on the surface of the first upper chip at the top of the first chip group, and the first upper chip can be electrically connected to the substrate through the redistribution layer and the leads, and the second chip is electrically connected to the redistribution layer through the conductive pillars, and then electrically connected to the first upper chip, thereby eliminating the need for leads to interconnect the first upper chip and the second chip. Since the first upper chip and the second chip are interconnected through the conductive pillars, the overall thickness of the plastic encapsulation layer can be reduced during plastic encapsulation, thereby reducing the packaging height and volume of the chip stacking structure.

[0069] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A chip stacking structure, characterized in that: include: substrate; A first chipset includes first chips stacked on the substrate and offset in a first offset direction, wherein a redistribution layer is provided on a first upper chip at the top of the first chipset, and the first upper chip is electrically connected to the substrate through the redistribution layer; The second chipset includes a second chip disposed on the first upper chip and offset in a second offset direction, the first offset direction being opposite to the second offset direction, and the second chip being electrically connected to the redistribution layer via a conductive column.

2. The chip stacking structure according to claim 1, wherein: An offset amount of the first upper chip in the first offset direction is smaller than an offset amount of the second chip in the second offset direction.

3. The chip stacking structure according to claim 1, wherein: A first data pad and a first control pad are provided on the first upper chip, and the redistribution layer includes a first redistribution layer and a second redistribution layer, wherein the first redistribution layer is connected to the first data pad, and the second redistribution layer is connected to the first control pad. The length of the first redistribution layer is smaller than the length of the second redistribution layer.

4. The chip stacking structure according to claim 3, wherein: There are a plurality of first data pads, a plurality of first redistribution layers, and the plurality of first data pads are parallel to each other.

5. The chip stacking structure according to claim 3, wherein: The first data pad and the first control pad are connected to the substrate through wires, respectively.

6. The chip stacking structure according to any one of claims 3 to 5, characterized in that: A second data pad is provided on the second chip, a first conductive column is provided on the second data pad, and the second data pad is connected to the first redistribution layer through the first conductive column.

7. The chip stacking structure according to claim 6, wherein: A contact area between the first conductive pillar and the first redistribution layer is smaller than a contact area between the first redistribution layer and the first data pad.

8. The chip stacking structure according to claim 6, wherein: The second chip has a second control pad and a third redistribution layer, the second control pad is connected to one end of the third redistribution layer, the other end of the third redistribution layer is provided with a second conductive column, and the second conductive column is connected to the second redistribution layer.

9. The chip stacking structure according to claim 8, wherein: A contact area between the second conductive pillar and the second redistribution layer is smaller than a contact area between the second redistribution layer and the first control pad.

10. The chip stacking structure according to claim 6, wherein: A dummy conductive column is provided on the second chip, and an end portion of the dummy conductive column is welded to the first upper chip.

11. The chip stacking structure according to claim 10, wherein: A contact area between the dummy conductive pillar and the first upper chip is larger than a contact area between the first conductive pillar and the first data pad.

12. The chip stacking structure according to any one of claims 1 to 5, characterized in that: Also includes: a plastic encapsulation layer, the plastic encapsulation layer covering the first chip group and the second chip group, and the plastic encapsulation layer containing fillers; The heat sink is located on the plastic packaging layer.

13. The chip stacking structure according to claim 12, wherein: Part of the filler is located between the heat sink and the second chip, and a maximum diameter of the filler is smaller than a thickness of the heat sink.

14. The chip stacking structure according to claim 12, wherein: The filler located between the heat sink and the second chip contacts the heat sink.

15. The chip stacking structure according to claim 12, wherein: The plastic packaging layer is further provided with an electromagnetic shielding layer, and the electromagnetic shielding layer covers the radiator.

16. The chip stacking structure according to any one of claims 1 to 5 or 7 to 15, characterized in that: The thickness of the second chip is greater than the thickness of the first upper chip.

17. The chip stacking structure according to any one of claims 1 to 5 or 7 to 15, characterized in that: The first upper chip is electrically connected to the second chip. The first upper chip and the second chip belong to the same signal channel and belong to different columns under the same signal channel.

18. A packaging structure, characterized in that: include: A mainboard and at least one chip stacking structure, at least one of the chip stacking structures is arranged on the mainboard, and the chip stacking structure includes the chip stacking structure described in any one of claims 1-17.

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