Fan-out packaging structure and preparation method thereof

Abstract

The invention discloses a fan-out packaging structure and a preparation method thereof. The fan-out packaging structure comprises a power supply substrate; the adapter plate is located on one side of the power supply substrate and electrically connected with the power supply substrate; the redistribution layer is located on the side, away from the power supply substrate, of the adapter plate and electrically connected with the adapter plate; the functional chip layer is located on the side, away from the power supply substrate, of the redistribution layer and electrically connected with the redistribution layer; wherein the adapter plate comprises an organic plastic package layer and a plurality of conductive capacitor chips coated in the organic plastic package layer; the conductive capacitor chip is provided with a silicon through hole, and the silicon through hole in the conductive capacitor chip is used for providing a power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer. According to the technical scheme provided by the invention, the fan-out requirement of a large-size chip is met, the product yield and the effective DTC density are improved, and the problems of packaging warping and internal stress concentration are solved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of chip packaging technology, and in particular to a fan-out packaging structure and a preparation method thereof. Background Art

[0002] As AI chips grow in size, the area of ​​the silicon adapter plate has exceeded 3.3 times the area of ​​the mask plate, and even as high as 5.5 times the area of ​​the mask plate. This makes traditional 2.5D silicon adapter plate technology face multiple challenges such as low yield, insufficient effective DTC (Deep Trench Capacitor) density, excessive package warpage, and internal stress concentration. Summary of the Invention

[0003] The embodiment of the present invention provides a fan-out packaging structure and a preparation method thereof, which can meet the fan-out requirements of large-size chips while improving product yield and effective DTC density, and improving package warping and internal stress concentration problems.

[0004] According to one aspect of the present invention, a fan-out packaging structure is provided, comprising:

[0005] Power supply substrate;

[0006] an adapter plate, located on one side of the power supply substrate and electrically connected to the power supply substrate;

[0007] a redistribution layer, located on a side of the adapter board away from the power supply substrate and electrically connected to the adapter board;

[0008] a functional chip layer, located on a side of the redistribution layer away from the power supply substrate and electrically connected to the redistribution layer;

[0009] Among them, the adapter board includes an organic plastic sealing layer and a plurality of conductive capacitor chips coated in the organic plastic sealing layer; the conductive capacitor chip is provided with a silicon through-hole via, and the silicon through-hole via in the conductive capacitor chip is used to provide the power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer.

[0010] Optionally, the conductive capacitor chip in the adapter plate includes a deep trench capacitor chip provided with through silicon vias, and / or an integrated silicon capacitor chip provided with through silicon vias;

[0011] A plurality of the conductive capacitor chips are distributed in the organic plastic packaging layer in the same layer.

[0012] Optionally, the conductive capacitor chip includes:

[0013] A silicon substrate comprising a first surface and a second surface opposite to each other, wherein the second surface is a surface of the silicon substrate close to the power substrate, the silicon substrate is provided with a through silicon via penetrating the silicon substrate, and the through silicon via is provided with a first conductive pillar;

[0014] A first metal layer is located on the first surface of the silicon substrate; wherein the first metal layer includes a first connecting layer, and the first conductive pillar is integrally provided with the first connecting layer;

[0015] a first insulating layer located on a surface of the first metal layer away from the silicon substrate and on a first surface not covered by the first metal layer; wherein the first insulating layer is provided with a through hole penetrating the first insulating layer, and a second conductive pillar is provided in the through hole penetrating the first insulating layer; an end of the second conductive pillar close to the power supply substrate is electrically connected to the first connection layer;

[0016] a second metal layer located on a surface of the first insulating layer away from the silicon substrate; the second metal layer includes a second connecting layer, and the second connecting layer is integrally provided with the second conductive pillar;

[0017] a second insulating layer located on a surface of the second metal layer away from the silicon substrate and a surface of the first insulating layer not covered by the second metal layer; wherein the second insulating layer is provided with an opening exposing the second connecting layer;

[0018] The third metal layer is located in the opening; the third metal layer located in the opening is used to form a pad connected to the first connection layer.

[0019] Optionally, a vertical projection of the through silicon via on the silicon substrate is located within a vertical projection of the first connection layer on the silicon substrate, and a vertical projection of the through hole penetrating the first insulating layer on the silicon substrate is located within a vertical projection of the first connection layer on the silicon substrate; wherein the vertical projection of the through silicon via on the silicon substrate and the vertical projection of the through hole penetrating the first insulating layer on the silicon substrate at least partially do not overlap;

[0020] and / or, a distance from a surface of the third metal layer located in the opening away from the silicon substrate to the silicon substrate is less than or equal to a distance from a surface of the second insulating layer away from the silicon substrate to the silicon substrate,

[0021] And / or, a backside redistribution layer is provided on the second surface of the silicon substrate, the through silicon vias are electrically connected to micro conductive bumps in the backside redistribution layer, and the conductive capacitor chip is electrically connected to the power supply substrate through the micro conductive bumps.

[0022] Optionally, the adapter board further includes a plurality of plastic-encapsulated conductive through-holes penetrating the organic plastic-encapsulated layer, the plastic-encapsulated conductive through-holes being used to provide the power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer; the plastic-encapsulated conductive through-holes include third conductive posts penetrating the organic plastic-encapsulated layer;

[0023] The power supply voltage transmitted by the plastic-encapsulated conductive vias is greater than the power supply voltage transmitted by the through-silicon vias in the conductive capacitor chip.

[0024] Optionally, the redistribution layer includes multiple organic insulation layers and multiple conductive wiring layers, and the organic insulation layers and the conductive wiring layers are alternately arranged in sequence; wherein the film layer located at the outermost layer of the redistribution layer is the organic insulation layer.

[0025] Optionally, the material of the organic insulating layer in the redistribution layer includes polyimide, and / or the material of the organic molding layer includes epoxy molding compound.

[0026] Optionally, the functional chip layer includes a plurality of functional chips, and two functional chips with signal interaction are electrically connected via the redistribution layer;

[0027] The functional chips in the functional chip layer include at least one of an ASIC chip, an HBM chip, a signal die and a white silicon wafer.

[0028] According to another aspect of the present invention, a method for preparing a fan-out package structure is provided, which is used to prepare the fan-out package structure according to any embodiment of the present invention, comprising:

[0029] Providing a carrier board, wherein a surface of the carrier board is provided with an adhesive layer;

[0030] forming an adapter plate on a side of the adhesive layer away from the carrier plate;

[0031] forming a redistribution layer and a redistribution layer on a side of the adapter board away from the carrier board; wherein the redistribution layer is located on the side of the adapter board away from the carrier board, and the redistribution layer is electrically connected to the adapter board;

[0032] forming a functional chip layer on a side of the redistribution layer away from the carrier board, wherein the functional chip layer is electrically connected to the redistribution layer;

[0033] removing the carrier board and the adhesive layer, and forming a backside redistribution layer on the exposed surface of the adapter board, wherein the backside redistribution layer includes a plurality of micro conductive bumps;

[0034] The side of the adapter board having the back redistribution layer is fixedly connected to the power supply substrate; wherein, the adapter board includes an organic plastic sealing layer and a plurality of conductive capacitor chips coated in the organic plastic sealing layer; silicon-through vias are provided in the conductive capacitor chips, and the silicon-through vias in the conductive capacitor chips are used to provide the power signal of the power supply substrate to the functional chips in the functional chip layer through the redistribution layer.

[0035] Optionally, forming an adapter plate and a redistribution layer on a side of the adhesive layer away from the carrier board includes:

[0036] forming an adapter plate on a side of the adhesive layer away from the carrier plate;

[0037] forming a redistribution layer on a side of the adapter plate away from the carrier plate;

[0038] The step of forming a transfer plate on a side of the adhesive layer away from the carrier plate includes:

[0039] forming a plurality of third conductive pillars on a side of the carrier having the glue layer;

[0040] A plurality of conductive capacitor chips are arranged on the side of the carrier having the adhesive layer; wherein the conductive capacitor chips are electrically isolated from the third conductive pillars;

[0041] forming the mechanical plastic sealing layer, wherein the mechanical plastic sealing layer covers the third conductive pillar and the conductive capacitor chip;

[0042] The mechanical molding layer is thinned from a side of the mechanical molding layer away from the carrier board to expose the surface of the third conductive column and the pad of the conductive capacitor chip.

[0043] Optionally, forming an adapter plate and a redistribution layer on a side of the adhesive layer away from the carrier board includes:

[0044] Providing an auxiliary carrier plate, wherein the surface of the auxiliary carrier plate is provided with an auxiliary adhesive layer;

[0045] forming a redistribution layer on a side of the auxiliary adhesive layer away from the auxiliary carrier;

[0046] forming an adapter plate on a side of the redistribution layer away from the auxiliary carrier;

[0047] removing the auxiliary carrier board and the auxiliary adhesive layer to form an intermediate structure consisting of the redistribution layer and the adapter board;

[0048] Fixing the intermediate structure on a side of the adhesive layer away from the carrier plate; wherein the adapter plate is closer to the adhesive layer;

[0049] The step of forming an adapter plate on a side of the redistribution layer away from the auxiliary carrier includes:

[0050] forming a plurality of third conductive pillars on a side of the redistribution layer away from the auxiliary carrier;

[0051] A plurality of conductive capacitor chips are arranged on a side of the redistribution layer away from the auxiliary carrier; wherein the conductive capacitor chips are electrically isolated from the third conductive pillars;

[0052] forming the mechanical plastic sealing layer, wherein the mechanical plastic sealing layer covers the third conductive pillar and the conductive capacitor chip;

[0053] The mechanical molding layer is thinned from a side of the mechanical molding layer away from the auxiliary carrier to expose the surface of the third conductive column and the pad of the conductive capacitor chip.

[0054] An embodiment of the present invention provides a fan-out packaging structure and a preparation method thereof, wherein the fan-out packaging structure includes: a power supply substrate; an adapter board, located on one side of the power supply substrate and electrically connected to the power supply substrate; a redistribution layer, located on a side of the adapter board away from the power supply substrate and electrically connected to the adapter board; a functional chip layer, located on a side of the redistribution layer away from the power supply substrate and electrically connected to the redistribution layer; wherein the adapter board includes an organic plastic sealing layer and a plurality of conductive capacitor chips coated in the organic plastic sealing layer; silicon-through vias are provided in the conductive capacitor chips, and the silicon-through vias in the conductive capacitor chips are used to provide the power signal of the power supply substrate to the functional chips in the functional chip layer through the redistribution layer. The technical solution provided by the embodiment of the present invention divides a large-size silicon interposer into multiple small-size conductive capacitor chips with DTCs. The multiple small-size conductive capacitor chips are integrated into a package body of multiple conductive capacitor chips through plastic packaging, and a redistribution layer is distributed on this package body to achieve signal interconnection. This replaces the silicon interposer in the current mainstream 2.5D packaging. While meeting the fan-out requirements of large-size chips, it also improves product yield and effective DTC density, and alleviates package warpage and internal stress concentration problems.

[0055] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1is an exploded diagram of a fan-out packaging structure provided by an embodiment of the present invention;

[0058] Figure 2 This is a partial structural cross-sectional view of a conductive capacitor chip provided by an embodiment of the present invention;

[0059] Figure 3 is a partial structural cross-sectional view of a redistribution layer provided by an embodiment of the present invention;

[0060] Figure 4 is a top view of a functional chip layer provided by an embodiment of the present invention;

[0061] Figure 5 This is a flow chart of a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0062] Figure 6 1 is a schematic structural cross-sectional view corresponding to step S10 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0063] Figure 7 1 is a schematic structural cross-sectional view corresponding to step S20 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0064] Figure 8 This is a schematic cross-sectional view of a structure after a plurality of micro-bumps are formed on the surface of a redistribution layer according to an embodiment of the present invention;

[0065] Figure 9 1 is a schematic structural cross-sectional view corresponding to step S30 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0066] Figure 10 1 is a schematic structural cross-sectional view corresponding to step S40 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0067] Figure 11 1 is a schematic structural cross-sectional view corresponding to step S50 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0068] Figure 12 2 is a schematic structural cross-sectional view corresponding to step SA210 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0069] Figure 13 2 is a schematic structural cross-sectional view corresponding to step SA220 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0070] Figure 14 2 is a schematic structural cross-sectional view corresponding to step SA230 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0071] Figure 15 1 is a schematic structural cross-sectional view corresponding to step SB210 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0072] Figure 16 1 is a schematic structural cross-sectional view corresponding to step SB220 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0073] Figures 17 to 19 1 is a schematic structural cross-sectional view corresponding to step SB230 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention;

[0074] Figure 20 It is a structural cross-sectional schematic diagram corresponding to step SB240 in a method for preparing a fan-out packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] An embodiment of the present invention provides a fan-out packaging structure. Figure 1 This is an exploded diagram of a fan-out packaging structure provided by an embodiment of the present invention, refer to Figure 1 , the fan-out packaging structure includes:

[0078] Power supply substrate 10;

[0079] The adapter plate 20 is located on one side of the power supply substrate 10 and is electrically connected to the power supply substrate 10;

[0080] The redistribution layer 30 is located on a side of the adapter board 20 away from the power supply substrate 10 and is electrically connected to the adapter board 20;

[0081] The functional chip layer 40 is located on a side of the redistribution layer 30 away from the power supply substrate 10 and is electrically connected to the redistribution layer 30;

[0082] Among them, the adapter board 20 includes an organic plastic sealing layer 22 and multiple conductive capacitor chips encapsulated in the organic plastic sealing layer; a through silicon via (TSV) is provided in the conductive capacitor chip, and a first conductive column 01 is provided in the through silicon via silicon of the conductive capacitor chip. The first conductive column 01 is used to provide the power signal of the power supply substrate 10 to the functional chip in the functional chip layer 40 through the redistribution layer 30.

[0083] Specifically, the power supply substrate 10 serves as a packaging substrate, which is used to provide a stable power supply signal for the functional chips in the functional chip layer 40 to ensure the normal operation of the functional chips in the functional chip layer 40. The functional chip layer 40 and the power supply substrate 10 are electrically connected through an interposer 20 and a redistribution layer 30 (RDL). In packaging technology, the interposer 20 and the redistribution layer 30 are two key structures, which respectively assume different functions and work together to achieve efficient interconnection between the functional chip and the power supply substrate 10. The interposer 20 is an intermediary layer located between the functional chip and the power supply substrate 10. It plays the role of a "bridge" in 2.5D / 3D packaging, connecting the power supply substrate 10 and the functional chip. Among them, the interposer 20 realizes vertical power signal transmission through silicon vias (TSV); the interposer 20 is also used to provide stable physical support for the stacked chips. The redistribution layer 30 is a wiring layer that redistributes the positions of the chip I / O (input and output) pins, and is used to rearrange the pads of the functional chip to an area suitable for package connection; the redistribution layer 30 is also used to optimize the wiring paths of power, ground and signals, and reduce signal crosstalk.

[0084] The technical solution provided by the embodiment of the present invention divides a large-size silicon interposer into multiple small-size conductive capacitor chips with TSV, and then integrates the multiple small-size conductive capacitor chips into an organic and inorganic hybrid interposer 20 by plastic encapsulation of organic materials. A redistribution layer 30 is distributed on this interposer 20 to achieve signal interconnection, replacing the silicon interposer in the current mainstream 2.5D package. Since the organic material used to plastic encapsulate multiple conductive capacitor chips is softer than the silicon material, it can improve the force buffering effect and reduce the stress burden, thereby improving the package warping and internal stress concentration problems; moreover, the interposer 20 is formed by plastic encapsulating multiple conductive capacitor chips with organic materials. The size of the interposer 20 can be set as needed without being restricted by the size of the mask, which is conducive to the development of large-size AI chips. In addition, the interposer 20 is formed by plastic encapsulating multiple conductive capacitor chips with organic materials. Compared with the large-size silicon interposer in the prior art, the yield of deep trench capacitors can be improved, and the problem of too low density of effective DTC contained in the silicon interposer is improved.

[0085] On the basis of the above embodiments, optionally, the conductive capacitor chip in the adapter plate 20 includes a deep trench capacitor chip (Deep Trench Capacitor DIE, DTC DIE) provided with a through silicon via, and / or an integrated silicon capacitor chip (Integrated Silicon Cap DIE, ISC DIE) provided with a through silicon via. A plurality of conductive capacitor chips are distributed in the same layer in the organic plastic layer 22, so that the power supply signal on the power supply substrate 10 is provided to the chips at different positions above the adapter plate 20 through the through silicon vias in the conductive capacitor chips at different positions. Among them, a plurality of micro conductive bumps C4 Bump are provided on the surface of the adapter plate 20 close to the side of the power supply substrate 10. The micro conductive bumps C4 Bump can achieve high-density and high-performance interconnection between the conductive capacitor chip and the power supply substrate 10.

[0086] Optional, Figure 2 This is a partial structural cross-sectional view of a conductive capacitor chip provided by an embodiment of the present invention. Figure 1 A partial enlarged diagram of the middle area Q1, see Figure 2 , the conductive capacitor chip 21 includes:

[0087] The silicon substrate 201 includes a first surface and a second surface relative to each other, wherein the second surface is the surface of the silicon substrate 201 on the side close to the power supply substrate 10. The silicon substrate 201 is provided with a through-silicon via (TSV) penetrating the silicon substrate 201, and a first conductive pillar 01 is provided in the TSV. The second surface of the silicon substrate 201 is provided with a backside redistribution layer 204. The first conductive pillar 01 provided in the TSV is electrically connected to a micro-conductive bump C4 in the backside redistribution layer 204. The conductive capacitor chip 21 is electrically connected to the power supply substrate 10 via the micro-conductive bump C4.

[0088] The first metal layer M1 is located on the first surface of the silicon substrate 201 ; wherein the first metal layer M1 includes a first connection layer S1 , and the first conductive pillars O1 are integrally provided with the first connection layer S1 ;

[0089] A first insulating layer 202 is located on a surface of the first metal layer M1 away from the silicon substrate 201 and on a first surface not covered by the first metal layer M1. A through hole is provided in the first insulating layer 202, and a second conductive pillar 02 is provided in the through hole. An end of the second conductive pillar 02 that is close to the power supply substrate 10 is electrically connected to the first connection layer S1.

[0090] The second metal layer M2 is located on the surface of the first insulating layer 202 away from the silicon substrate 201; the second metal layer M2 includes a second connection layer S2, and the second connection layer S2 is integrally provided with the second conductive pillar O2;

[0091] A second insulating layer 203 is located on a surface of the second metal layer M2 away from the silicon substrate 201 and a surface of the first insulating layer 202 not covered by the second metal layer M2; wherein the second insulating layer 203 is provided with an opening exposing the second connecting layer S2;

[0092] The third metal layer M3 is located in the opening; the third metal layer M3 located in the opening is used as a pad PAD connected to the second connection layer S2.

[0093] Specifically, the integrated arrangement of the first conductive pillar 01 and the first connection layer S1 can be understood as meaning that the first conductive pillar 01 and the first connection layer S1 are formed in the same fabrication process. The first conductive pillar 01 is formed by filling the through-silicon via with the material of the first metal layer M1, and the first connection layer S1 is formed by depositing the material of the first metal layer M1 on the first surface of the silicon substrate 201. The first insulating layer 202 is located on the surface of the first metal layer M1 facing away from the silicon substrate 201 and on the first surface not covered by the first metal layer M1. The first insulating layer 202 can be a single-layer structure or a multi-layer structure. The first insulating layer 202 can be an inorganic material layer, an organic material layer, or a stack of organic and inorganic material layers. A through hole is provided in the first insulating layer 202, and the second conductive pillar 02 is disposed in the through hole. The end of the second conductive pillar 02 proximal to the power supply substrate 10 is electrically connected to the first connection layer S1, thereby establishing an electrical connection between the first conductive pillar 01 and the second conductive pillar 02.

[0094] The vertical projection of the through-silicon via on the silicon substrate 201 is located within the vertical projection of the first connection layer S1 on the silicon substrate 201, so that the first conductive pillar 01 is in direct contact with the first connection layer S1. The vertical projection of the through-hole penetrating the first insulating layer 202 on the silicon substrate 201 is located within the vertical projection of the first connection layer S1 on the silicon substrate 201, so that the second conductive pillar 02 is in direct contact with the first connection layer S1. The vertical projection of the through-silicon via on the silicon substrate 201 and the vertical projection of the through-hole penetrating the first insulating layer 202 on the silicon substrate 201 at least partially do not overlap, that is, the first conductive pillar 01 and the second conductive pillar 02 can be staggered in the thickness direction of the silicon substrate 201. The first conductive pillar 01 and the second conductive pillar 02 are electrically connected through the first connection layer S1, which reduces the difficulty of electrical connection between the first conductive pillar 01 and the second conductive pillar 02 compared to a method in which the first conductive pillar 01 and the second conductive pillar 02 are in direct contact.

[0095] The second metal layer M2 is located on the surface of the first insulating layer 202 away from the silicon substrate 201. The material of the second metal layer M2 and the first metal layer M1 can be the same or different. The second metal layer M2 includes a second connection layer S2, which is integrally provided with the second conductive pillars 02. It can be understood that the second conductive pillars 02 and the second connection layer S2 are formed in the same preparation process. The second conductive pillars 02 are formed by filling the through holes penetrating the first insulating layer 202 with the material of the second metal layer M2. The second connection layer S2 is formed by depositing the material of the second metal layer M2 on the surface of the first insulating layer 202 away from the silicon substrate 201.

[0096] The second insulating layer 203 is located on the surface of the second metal layer M2 away from the silicon substrate 201 and the surface of the first insulating layer 202 not covered by the second metal layer M2. The second insulating layer 203 can be an inorganic material layer or an organic material layer, or can be formed by stacking an organic material layer and an inorganic material layer. The second insulating layer 203 has an opening that exposes the second connection layer S2. The third metal layer M3 located in the opening is used as a pad PAD connecting the second connection layer S2. The pad PAD is electrically connected to the redistribution layer 30 on the side away from the second connection layer S2, thereby realizing an electrical connection between the conductive capacitor chip and the redistribution layer 30. Optionally, the distance from the surface of the third metal layer M3 located in the opening away from the silicon substrate 201 to the silicon substrate 201 is less than or equal to the distance from the surface of the second insulating layer 203 away from the silicon substrate 201 to the silicon substrate 201, which can prevent the pad PAD located in the opening from protruding from the surface of the second insulating layer 203 and being subjected to external wear.

[0097] The conductive capacitor chip 21 provided in the embodiment of the present invention is only filled with DTC / ISC to maximize the effective capacitor area. Compared with the silicon adapter board with DTC and TSV in CoWoS-L (Local Silicon Interconnect and RDL Interposer) in the related art, which adopts 5 metal layers, the number of metal layers can be reduced, and only three metal layers, namely the first metal layer M1, the second metal layer M2 and the third metal layer M3, are required.

[0098] Based on the above embodiments, Figure 1 Optionally, the adapter board 20 also includes a plurality of through-mold vias (TMVs) penetrating the organic plastic layer 22, and the plastic conductive vias are used to provide the power signal of the power supply substrate 10 to the functional chip in the functional chip layer 40 through the redistribution layer 30; a third conductive column 03 is provided in the plastic conductive via; wherein the power voltage transmitted by the plastic conductive via is greater than the power voltage transmitted by the silicon through via in the conductive capacitor chip.

[0099] TMV is a cost-effective vertical interconnect solution for advanced packaging, achieving high-density electrical connections through conductive channels in the molding compound. Multiple conductive capacitor chips 21, multiple third conductive pillars 03, and a power supply substrate 10 can be integrally encapsulated in organic molding compound. The third conductive pillars 03 penetrate the organic molding compound, automatically forming through-holes to accommodate the third conductive pillars 03 after molding. This eliminates the need for laser drilling to form conductive vias through the organic molding layer 22, simplifying the fabrication of the conductive vias.

[0100] On the basis of the above embodiments, optionally, Figure 3is a partial structural cross-sectional view of a redistribution layer provided by an embodiment of the present invention, which is Figure 1 A partial enlarged diagram of the middle area Q2, see Figure 3 The redistribution layer 30 includes multiple layers of organic insulating layers 301 and multiple layers of conductive trace layers 302, which are arranged alternately. The outermost layer of the redistribution layer 300 is the organic insulating layer 301, which is made of polyimide and / or epoxy molding compound. The use of organic materials in the insulating layer of the redistribution layer 300 provides a better force buffering effect, reduces the stress burden on the flip-chip bumps, and provides high design layout freedom and excellent electrical performance.

[0101] Among them, the multi-layer conductive routing layer 302 can be arranged in a manner that alternates ground lines and signal lines. The GSGSG (Ground / Signal / Ground / Signal / Ground) wiring structure is an efficient layout strategy that alternates ground (GND) and signal (Signal) lines to shield noise and optimize signal integrity. Each signal line (S) is wrapped by ground lines (G) on both sides to form a local shield. The ground line acts as a low-impedance return path, absorbing the electric and magnetic fields generated by the signal line, reducing crosstalk between adjacent signal lines; it can also shorten the signal transmission distance to reduce the parasitic RC value.

[0102] Continue to refer Figure 3 Exemplarily, the redistribution layer 30 may include six conductive trace layers and seven organic insulation layers. The six conductive trace layers are respectively RDL1, RDL2, RDL3, RDL4, RDL5, and RDL6. The seven organic insulation layers are respectively PSV1, PSV2, PSV3, PSV4, PSV5, PSV6, and PSV7. The conductive trace layers may be copper layers with a thickness of 4 μm, and the thickness of the organic insulation layers between the metal layers is 5 μm. In the ubbump area, the line width is 2 μm, and the line spacing is 2 μm. In the non-ubbump area, i.e., the interconnection area between the ASIC chip and the HBM chip, the line width is 2 μm, and the line spacing is up to 4.6 μm. All high-speed signals are distributed on the inner layers, and both the same layer and adjacent layers are shielded by ground planes to maximize noise shielding.

[0103] On the basis of the above embodiments, optionally, Figure 4 This is a top view of a functional chip layer 40 provided in an embodiment of the present invention, referring to Figure 4The functional chip layer 40 includes multiple functional chips, and two functional chips with signal interaction are electrically connected through the redistribution layer 30; wherein, the functional chips in the functional chip layer 40 include at least one of ASIC (Application-Specific Integrated Circuit) chip, HBM (High Bandwidth Memory) chip, signal die (Input / Output Signal Die, IDO) and white silicon wafer (Dummy Die, DD). Figure 4 The functional chips in the functional chip layer 40 exemplarily include ASIC chips, HBM chips, signal dies, and white silicon wafers.

[0104] The embodiment of the present invention further provides a method for preparing a fan-out packaging structure, which is used to prepare the fan-out packaging structure described in any embodiment of the present invention. Figure 5 This is a flow chart of a method for preparing a fan-out packaging structure provided by an embodiment of the present invention, with reference to Figure 5 , a method for preparing a fan-out packaging structure includes:

[0105] S10, providing a carrier board, wherein a glue layer is provided on the surface of the carrier board.

[0106] Specifically, refer to Figure 6 The carrier 501 may be a metal carrier, a silicon wafer, or a glass carrier, etc. A glue layer 502 is provided on one side of the carrier 501 . The provision of the glue layer 502 facilitates subsequent peeling of the carrier 501 .

[0107] S20. Forming an adapter board and a redistribution layer on a side of the adhesive layer away from the carrier board; wherein the redistribution layer is located on a side of the adapter board away from the carrier board, and the redistribution layer is electrically connected to the adapter board; the adapter board includes an organic plastic encapsulation layer and a plurality of conductive capacitor chips coated in the organic plastic encapsulation layer; and silicon through vias are provided in the conductive capacitor chips.

[0108] Specifically, refer to Figure 7, multiple small-sized conductive capacitor chips 21 are integrated into an organic and inorganic hybrid adapter plate 20 by plastic encapsulation of organic materials. Since the organic material used to encapsulate the multiple conductive capacitor chips 21 is softer than silicon material, it can improve the force buffering effect and reduce the stress burden, thereby improving the package warping and internal stress concentration problems; moreover, the method of using organic materials to encapsulate multiple conductive capacitor chips 21 to form the adapter plate 20 can set the size of the adapter plate 20 as required, without being restricted by the size of the mask, which is conducive to the development of large-sized AI chips. In addition, the method of forming the adapter plate 20 by plastic encapsulating multiple conductive capacitor chips 21 with organic materials can improve the yield of DTC compared to the large-sized silicon interposer in the prior art, and improve the problem of too low density of effective DTC contained in the silicon interposer.

[0109] The redistribution layer 30 is a wiring layer that redistributes the position of the chip I / O (input and output) pins, and is used to re-layout the chip's pads to an area suitable for package connection; the redistribution layer 30 is also used to optimize the wiring paths of power, ground, and signals, and reduce signal crosstalk. The redistribution layer 30 includes multiple layers of organic insulating layers and multiple layers of conductive trace layers, and the organic insulating layers and the conductive trace layers are arranged alternately in sequence; the redistribution layer 30 formed on the side of the adapter board 20 away from the carrier board 501 may include alternating organic insulating layers and conductive trace layers, wherein the film layer located on the outermost layer of the redistribution layer 30 is an organic insulating layer. The material of the organic insulating layer includes polyimide and / or epoxy molding compound. The insulating layer material in the redistribution layer 30 is sampled from an organic material, which can provide a better force buffering effect, reduce the stress burden of the flip-chip bump, and has a high degree of freedom in design layout and good electrical performance.

[0110] S30 , forming a functional chip layer on a side of the redistribution layer away from the carrier board, wherein the functional chip layer is electrically connected to the redistribution layer.

[0111] Specifically, refer to Figure 8 Before forming the functional chip layer 40 on the side of the redistribution layer 30 away from the carrier 501, a plurality of micro bumps ubumps may be formed on the side of the redistribution layer 30 away from the carrier 501; Figure 9 A functional chip layer 40 is bonded to the side of the redistribution layer 30 facing away from the carrier 501. The functional chips in the functional chip layer 40 are electrically connected to the redistribution layer 30 via an ubump. The functional chip layer 40 includes multiple functional chips, with two functional chips with signal interaction electrically connected via the redistribution layer 30. The functional chips in the functional chip layer 40 include at least one of an ASIC chip, an HBM chip, a signal die, and a white silicon wafer. Furthermore, the functional chip layer 40 includes multiple functional chips and an organic plastic encapsulation layer for encapsulating the functional chips.

[0112] S40, removing the carrier board and the adhesive layer, and forming a backside redistribution layer on the exposed surface of the adapter board, wherein the backside redistribution layer includes a plurality of micro conductive bumps.

[0113] Specifically, refer to Figure 10 , remove the carrier board 501 and the adhesive layer 502, and form a back redistribution layer on the exposed surface of the adapter board 20. The back redistribution layer includes a plurality of micro conductive bumps C4 Bumps. The micro conductive bumps C4 Bumps are electrical and mechanical connection structures located on the surface of the conductive capacitor chip and formed through a reflow soldering process.

[0114] S50, fixing the side of the adapter board having the back redistribution layer to the power supply substrate; wherein, the through silicon via in the conductive capacitor chip is used to provide the power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer.

[0115] Specifically, refer to Figure 11 The micro-conductive bumps C4 enable high-density, high-performance interconnection between the conductive capacitor chip and the power supply substrate 10. The power supply substrate 10, as a packaging substrate, provides a stable power signal to the chips in the functional chip layer 40, ensuring the normal operation of the chips in the functional chip layer 40.

[0116] The technical solution provided by the embodiment of the present invention divides the large-scale silicon adapter plate into multiple small-scale conductive capacitor chips with TSV, and then integrates the multiple small-scale conductive capacitor chips into an organic and inorganic hybrid adapter plate 20 through plastic encapsulation of organic materials. A redistribution layer 30 is distributed on this adapter plate 20 to achieve signal interconnection, replacing the silicon adapter plate in the current mainstream 2.5D package. Since the organic material used to encapsulate the multiple conductive capacitor chips 21 is softer than the silicon material, it can improve the force buffering effect and reduce the stress burden, thereby improving the package warping and internal stress concentration problems; moreover, the method of using organic materials to encapsulate multiple conductive capacitor chips 21 can set the size of the adapter plate 20 as required, without being restricted by the size of the mask, which is conducive to the development of large-scale AI chips. In addition, the adapter plate 20 is formed by encapsulating multiple conductive capacitor chips with organic materials. Compared with the large-scale silicon interposer in the prior art, it can improve the yield of DTC and improve the problem of too low density of effective DTC contained in the silicon interposer.

[0117] Optionally, in one embodiment of the present invention, step S20 forms an adapter board and a redistribution layer on the side of the adhesive layer away from the carrier board, including: forming an adapter board 20 on the side of the adhesive layer 502 away from the carrier board 501; forming a redistribution layer 30 on the side of the adapter board 20 away from the carrier board 501.

[0118] The step of forming the adapter plate 20 on the side of the adhesive layer 502 away from the carrier plate 501 includes:

[0119] SA210, forming a plurality of third conductive pillars 03 on the side of the carrier 501 having the adhesive layer 502. (Refer to Figure 12 )

[0120] SA220, a plurality of conductive capacitor chips 21 are arranged on one side of the carrier 501 having the adhesive layer 502; wherein the conductive capacitor chips are electrically isolated from the third conductive pillars 03. (Refer to Figure 13 )

[0121] SA230, forming a mechanical plastic sealing layer, which covers the third conductive column 03 and the conductive capacitor chip.

[0122] SA240, thin the machine plastic sealing layer from the side away from the carrier 501 to expose the surface of the third conductive column 03 and the pad of the conductive capacitor chip (refer to Figure 14 ).

[0123] Specifically, the adapter board 20 also includes a plurality of plastic-encapsulated conductive vias that penetrate the organic plastic layer 22. The plastic-encapsulated conductive vias are used to provide the power signal of the power supply substrate 10 to the functional chip in the functional chip layer 40 through the redistribution layer 30. The plastic-encapsulated conductive vias include a third conductive pillar 03 that penetrates the organic plastic layer 22. The power voltage transmitted by the plastic-encapsulated conductive vias is greater than the power voltage transmitted by the silicon-through vias in the conductive capacitor chip. TMV is a cost-effective vertical interconnect solution in advanced packaging, achieving high-density electrical connections through conductive channels in the molding compound. Multiple conductive capacitor chips 21, multiple third conductive pillars 03, and the power supply substrate 10 are encapsulated into a whole using organic molding compound. The third conductive pillars 03 penetrate the organic molding compound. After plastic encapsulation, through holes for accommodating the third conductive pillars 03 are automatically formed. There is no need to form through holes through the organic plastic layer 22 by laser drilling, thereby simplifying the difficulty of preparing the plastic-encapsulated conductive vias.

[0124] Optionally, in one embodiment of the present invention, step S20 of forming an adapter plate and a redistribution layer on a side of the adhesive layer away from the carrier board includes:

[0125] SB210, providing an auxiliary carrier 5010, the surface of the auxiliary carrier 5010 is provided with an auxiliary adhesive layer 5020 (refer to Figure 15 ).

[0126] SB220, forming a redistribution layer 30 on the side of the auxiliary adhesive layer 5020 away from the auxiliary carrier 5010 (refer to Figure 16 ).

[0127] SB230 , forming an adapter board 20 on a side of the redistribution layer 30 away from the auxiliary carrier 5010 .

[0128] Specifically, refer to Figures 17 to 19, forming an adapter board 20 on a side of the redistribution layer 30 away from the auxiliary carrier 5010, including: forming a plurality of third conductive pillars 03 on the side of the redistribution layer 30 away from the auxiliary carrier 5010; disposing a plurality of conductive capacitor chips 21 on the side of the redistribution layer 30 away from the auxiliary carrier 5010; wherein the conductive capacitor chips 21 are electrically isolated from the third conductive pillars 03; forming a mechanical plastic sealing layer 22, the mechanical plastic sealing layer 22 covering the third conductive pillars 03 and the conductive capacitor chips 21; and thinning the mechanical plastic sealing layer 22 from the side of the mechanical plastic sealing layer 22 away from the auxiliary carrier 5010 to expose the surface of the third conductive pillars 03 and the pads 21 of the conductive capacitor chips.

[0129] SB240, remove the auxiliary carrier 5010 and the auxiliary adhesive layer 5020 to form an intermediate structure consisting of the redistribution layer 30 and the adapter plate 20 (refer to Figure 20 ).

[0130] SB250 fixes the intermediate structure on the side of the adhesive layer 502 away from the carrier 501; wherein, the adapter plate 20 is closer to the adhesive layer 502. (Refer to Figure 7 )

[0131] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A fan-out packaging structure, characterized in that: include: Power supply substrate; an adapter plate, located on one side of the power supply substrate and electrically connected to the power supply substrate; a redistribution layer, located on a side of the adapter board away from the power supply substrate and electrically connected to the adapter board; a functional chip layer, located on a side of the redistribution layer away from the power supply substrate and electrically connected to the redistribution layer; Among them, the adapter board includes an organic plastic sealing layer and a plurality of conductive capacitor chips coated in the organic plastic sealing layer; the conductive capacitor chip is provided with a silicon through-hole via, and the silicon through-hole via in the conductive capacitor chip is used to provide the power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer.

2. The fan-out packaging structure according to claim 1, wherein: The conductive capacitor chip in the adapter plate includes a deep trench capacitor chip provided with through silicon vias, and / or an integrated silicon capacitor chip provided with through silicon vias; A plurality of the conductive capacitor chips are distributed in the organic plastic packaging layer in the same layer.

3. The fan-out packaging structure according to claim 1, wherein: The conductive capacitor chip includes: A silicon substrate comprising a first surface and a second surface opposite to each other, wherein the second surface is a surface of the silicon substrate close to the power substrate, the silicon substrate is provided with a through silicon via penetrating the silicon substrate, and the through silicon via is provided with a first conductive pillar; A first metal layer is located on the first surface of the silicon substrate; wherein the first metal layer includes a first connecting layer, and the first conductive pillar is integrally provided with the first connecting layer; a first insulating layer located on a surface of the first metal layer away from the silicon substrate and on a first surface not covered by the first metal layer; wherein the first insulating layer is provided with a through hole penetrating the first insulating layer, and a second conductive pillar is provided in the through hole penetrating the first insulating layer; an end of the second conductive pillar close to the power supply substrate is electrically connected to the first connection layer; a second metal layer located on a surface of the first insulating layer away from the silicon substrate; the second metal layer includes a second connecting layer, and the second connecting layer is integrally provided with the second conductive pillar; a second insulating layer located on a surface of the second metal layer away from the silicon substrate and a surface of the first insulating layer not covered by the second metal layer; wherein the second insulating layer is provided with an opening exposing the second connecting layer; The third metal layer is located in the opening; the third metal layer located in the opening is used to form a pad connected to the first connection layer.

4. The fan-out packaging structure according to claim 3, characterized in that A vertical projection of the through silicon via on the silicon substrate is located within a vertical projection of the first connection layer on the silicon substrate, and a vertical projection of the through hole penetrating the first insulating layer on the silicon substrate is located within a vertical projection of the first connection layer on the silicon substrate; wherein the vertical projection of the through silicon via on the silicon substrate and the vertical projection of the through hole penetrating the first insulating layer on the silicon substrate at least partially do not overlap; and / or, a distance from a surface of the third metal layer located in the opening away from the silicon substrate to the silicon substrate is less than or equal to a distance from a surface of the second insulating layer away from the silicon substrate to the silicon substrate, And / or, a backside redistribution layer is provided on the second surface of the silicon substrate, the through silicon vias are electrically connected to micro conductive bumps in the backside redistribution layer, and the conductive capacitor chip is electrically connected to the power supply substrate through the micro conductive bumps.

5. The fan-out packaging structure according to claim 1, wherein: The adapter board further includes a plurality of plastic-encapsulated conductive through-holes penetrating the organic plastic-encapsulated layer, the plastic-encapsulated conductive through-holes being used to provide the power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer; the plastic-encapsulated conductive through-holes include third conductive posts penetrating the organic plastic-encapsulated layer; The voltage transmitted by the plastic-encapsulated conductive vias is greater than the voltage transmitted by the through-silicon vias in the conductive capacitor chip.

6. The fan-out packaging structure according to claim 1, wherein: The redistribution layer includes multiple organic insulating layers and multiple conductive wiring layers, and the organic insulating layers and the conductive wiring layers are alternately arranged in sequence; wherein the film layer located on the outermost layer of the redistribution layer is the organic insulating layer.

7. The fan-out packaging structure according to claim 6, characterized in that: The material of the organic insulating layer in the redistribution layer includes polyimide, and / or the material of the organic molding layer includes epoxy molding compound.

8. The fan-out packaging structure according to claim 1, wherein: The functional chip layer includes a plurality of functional chips, and two functional chips with signal interaction are electrically connected through the redistribution layer; The functional chips in the functional chip layer include at least one of an ASIC chip, an HBM chip, a signal die and a white silicon wafer.

9. A method for preparing a fan-out packaging structure, characterized in that: Used to prepare the fan-out packaging structure according to any one of claims 1 to 8, comprising: Providing a carrier board, wherein a surface of the carrier board is provided with an adhesive layer; An adapter board and a redistribution layer are formed on a side of the adhesive layer away from the carrier board; wherein the redistribution layer is located on a side of the adapter board away from the carrier board, and the redistribution layer is electrically connected to the adapter board; forming a functional chip layer on a side of the redistribution layer away from the carrier board, wherein the functional chip layer is electrically connected to the redistribution layer; removing the carrier board and the adhesive layer, and forming a backside redistribution layer on the exposed surface of the adapter board, wherein the backside redistribution layer includes a plurality of micro conductive bumps; The side of the adapter board having the back redistribution layer is fixedly connected to the power supply substrate; wherein, the adapter board includes an organic plastic sealing layer and a plurality of conductive capacitor chips coated in the organic plastic sealing layer; silicon-through vias are provided in the conductive capacitor chips, and the silicon-through vias in the conductive capacitor chips are used to provide the power signal of the power supply substrate to the functional chips in the functional chip layer through the redistribution layer.

10. The method for preparing the fan-out packaging structure according to claim 9, wherein: The step of forming an adapter plate and a redistribution layer on a side of the adhesive layer away from the carrier board includes: forming an adapter plate on a side of the adhesive layer away from the carrier plate; forming a redistribution layer on a side of the adapter plate away from the carrier plate; The step of forming a transfer plate on a side of the adhesive layer away from the carrier plate includes: forming a plurality of third conductive pillars on a side of the carrier having the glue layer; A plurality of conductive capacitor chips are arranged on the side of the carrier having the adhesive layer; wherein the conductive capacitor chips are electrically isolated from the third conductive pillars; forming the mechanical plastic sealing layer, wherein the mechanical plastic sealing layer covers the third conductive pillar and the conductive capacitor chip; The mechanical molding layer is thinned from a side of the mechanical molding layer away from the carrier board to expose the surface of the third conductive column and the pad of the conductive capacitor chip.

11. The method for preparing a fan-out packaging structure according to claim 9, wherein: The step of forming an adapter plate and a redistribution layer on a side of the adhesive layer away from the carrier board includes: Providing an auxiliary carrier plate, wherein the surface of the auxiliary carrier plate is provided with an auxiliary adhesive layer; forming a redistribution layer on a side of the auxiliary adhesive layer away from the auxiliary carrier; forming an adapter plate on a side of the redistribution layer away from the auxiliary carrier; removing the auxiliary carrier board and the auxiliary adhesive layer to form an intermediate structure consisting of the redistribution layer and the adapter board; Fixing the intermediate structure on a side of the adhesive layer away from the carrier plate; wherein the adapter plate is closer to the adhesive layer; The step of forming an adapter plate on a side of the redistribution layer away from the auxiliary carrier includes: forming a plurality of third conductive pillars on a side of the redistribution layer away from the auxiliary carrier; A plurality of conductive capacitor chips are arranged on a side of the redistribution layer away from the auxiliary carrier; wherein the conductive capacitor chips are electrically isolated from the third conductive pillars; forming the mechanical plastic sealing layer, wherein the mechanical plastic sealing layer covers the third conductive pillar and the conductive capacitor chip; The mechanical molding layer is thinned from a side of the mechanical molding layer away from the auxiliary carrier to expose the surface of the third conductive column and the pad of the conductive capacitor chip.

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